JPH08307868A - Moving image decoder - Google Patents

Abstract

PURPOSE: To realize the moving image decoder for a storage system medium of a video rate at a low cost. CONSTITUTION: The decoder is made up of a variable length code decoding circuit 1, an inverse quantization circuit 2, an inverse discrete cosine transformation circuit 3, and an inter-frame motion compensation prediction generating circuit 4. A buffer memory 5 is arranged between the inverse quantization circuit 2 and the inverse discrete cosine transformation circuit 3 and a buffer memory 5 is used to realize a matrix transposition function required for inverse zigzag conversion processing and 2-dimension inverse DCT transformation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for decompressing a bit stream compressed by a hybrid structure of inter-frame prediction and discrete cosine transform represented by MPEG system.

[0002]

2. Description of the Related Art Video signals are transmitted to a compact disc (C
A high-efficiency encoding process is performed for the purpose of storing in a relatively narrow band digital storage medium such as D). International standardization organization ISO-IEC JTC1 / SC
2 / WG11 (hereinafter MPEG), 1.5 Mbp
An encoding method compatible with s-equivalent media has been studied.
For an overview of the study method, for example, the explanation is published in Journal of Image Electronics Engineers, Vol. 20, No. 4, pages 306 to 316. According to the contents of the publication, it is a hybrid coding method that combines motion-compensated interframe prediction, discrete cosine transform (DCT), quantization, and variable length coding, and realizes image quality equivalent to VHS video. In addition, the MPEG2 system for maintaining the image quality of the current TV broadcast and compressing it within 15 Mbps (practical 3 to 8 Mbps) is also standardized. All of these methods are for inter-frame prediction method and discrete cosine transform (DCT: Discrete Cos) for video signal compression.
ine Transform) is used. In addition, ITU-TH. Similarly, the H.261 method also uses the inter-frame prediction method and the discrete cosine transform.

In order to decode a video signal compressed based on the MPEG system in real time, a series of processes such as variable length decoding, inverse zigzag conversion, inverse quantization, inverse DCT, and motion compensation are processed at high speed by hardwired logic. I often do it. At this time, since the variable-length code has a different code amount depending on the signal, the processing time required for the variable-length decoding process also largely varies depending on the signal. On the other hand, inverse quantization and inverse DCT
Is constant regardless of the signal. Therefore, it is necessary to temporarily store the variable length decoding result in the memory to absorb the processing time difference before performing the subsequent processing.

As an example of the decoding processing hardware, 19
There is a decoder LSI announced as C-658 of the 1994 IEICE Spring Conference. According to the description, the fixed length code subjected to the variable length decoding and the run length decoding is temporarily stored in the memory circuit. The fixed-length code stored in the memory is read while returning from the zigzag scan order to the block scan order, subjected to inverse quantization and inverse DCT, and stored in another memory. Further, the motion compensation circuit reproduces the inter-frame prediction signal and adds it to the inverse DCT result to obtain a decoded image. Since the inter-frame prediction method differs depending on the block, the processing time also differs in the motion compensation processing. Therefore, a memory for storing the DCT result is arranged to absorb the processing time difference from the processing up to DCT.

In the memory circuit arrangement according to this conventional system, the time adjustment memory for the variable length decoding process is arranged before the dequantization, and the conversion from the zigzag scan order to the block scan order is also realized there. This is to save memory by combining the time adjustment function and the scan conversion function. Furthermore, by arranging the memory before the dynamic range of data is expanded by dequantization, the memory required for storing data is stored. This is because the capacity can be reduced. For example, in the MPEG1 system, the bit width before dequantization is 9
Since the number of bits is increased to 12 bits after dequantization, the memory is saved by 3 bits per data.

Next, problems of the above conventional circuit configuration will be described with reference to FIG. Here, only the decoding processing portion from variable length decoding to inverse discrete cosine transform is extracted and described. The process up to the inverse discrete cosine transform is performed by the variable length decoding circuit 91, the inverse zigzag transform circuit 92, the inverse quantizing circuit 93, the inverse discrete cosine transform circuit 94, the transposing memory 9
It is realized by 5. The inverse zigzag conversion circuit 92 is arranged between the variable length decoding circuit 91 and the inverse quantization circuit 93, and temporarily stores the output of the variable length decoding circuit 91 in the internal memory to perform the inverse zigzag scan conversion and the inverse quantization circuit. Used to supply data to To realize this conversion, the reverse zigzag scan conversion is realized by changing the address generation order of the memory from the zigzag scan order to the intra-block raster scan order at the time of writing or reading to the internal memory.

The inverse discrete cosine transform circuit 94 performs the inverse cosine transform in the row direction when eight pieces of the inversely quantized data are collected, and writes the result in the transposing memory 95.
The inverse discrete cosine transform circuit 94 reads the data from the transposing memory 95 at the time when the row-direction transform is completed on the data supplied from the inverse quantizer circuit 93, and outputs it to the subsequent stage while performing the inverse cosine transform in the column direction. As described above, when the inverse discrete cosine transform circuit 94 is used for both rows / columns in a time division manner, the output of the inverse quantization circuit 93 is not accepted while performing the inverse cosine transform in the column direction, and thus the inverse quantum The conversion circuit 93 enters a waiting state. In other words, the inverse discrete cosine transform circuit 94 has to complete the inverse quantization processing in time with the time when the row-direction transformation is executed, and therefore, the circuit of the inverse quantization circuit 93 is parallelized to achieve high speed. It has become.

If two inverse discrete cosine transform circuits 94 shown in FIG. 8 are prepared and the row transform and the column transform are simultaneously operated with the transposing memory interposed, it is possible to avoid the inverse quantizing circuit 93 from entering a waiting state. However, the circuit scale increases as a result of mounting two sets of the inverse discrete cosine transform circuits 94, which require a larger amount of calculation than the inverse quantization.

[0009]

In the conventional memory arrangement configuration, the inverse quantization and the inverse DCT are stored in the memory for the data read from the time adjustment memory having the inverse zigzag scan conversion function. It is processed continuously without. At this time, in order to balance the inverse quantization and inverse DCT processing times, it was necessary to increase the operation speed by introducing parallel processing. However, both of the inverse quantization and the inverse DCT have a problem in that the cost of the entire decoding device increases because of the large amount of computations that frequently use multiplication. The problem to be solved by the present invention is to avoid the above problems, improve the processing efficiency of the entire video decoding apparatus, and provide a decoding apparatus at a lower cost.

[0010]

In order to achieve the above object, a moving picture decoding apparatus according to the present invention comprises a series of a variable length decoding circuit, an inverse quantization circuit, an inverse discrete cosine transform circuit, and a motion compensation signal generation circuit. In the arithmetic circuit arrangement of, a buffer memory is arranged between the inverse quantization circuit and the inverse discrete cosine transform circuit, and the matrix transposing function required for the inverse zigzag transform and the two-dimensional inverse discrete cosine transform is realized by using this buffer memory. ing. In addition, a method for efficiently controlling the entire moving image decoding apparatus is provided.

[0011]

The memory capacity required by the conventional method and the present invention method is estimated. One-dimensional inverse DCT is used to realize the inverse DCT transform.
Is often divided into two calculations, one in the row direction and one in the column direction.
In either case, a memory circuit is required to transpose the result of the inverse DCT in the row (or column) direction and convert the result in the column (or row) direction. This transposition circuit has an inverse D
A memory of about 16 bits is usually used to maintain the accuracy required for CT calculation. Further, the number of bits required to represent the data before and after the inverse quantization is about 9 bits and 12 bits, respectively. Further, a memory having a double buffer structure is often used in order to simultaneously execute the processing up to writing to the buffer memory and the processing thereafter read from the buffer memory. Here, let's compare under the above assumptions.

In the conventional method, 9 bits × 2 × B = 18 are stored in order to store the data before dequantization in the double buffer.
B [bit] is required. Here, B is the number of pieces of data that make up one block of DCT coefficient, and is the MPEG or H.264 standard.
It becomes 64 in 261. Separately, the transpose memory used for the inverse DCT is 16 bits × 1 × B = 16B [bi
t], and a total capacity of 34 B [bit] is required.

On the other hand, in the present invention, the time adjustment buffer memory for the variable length decoding process is arranged after the inverse quantization, and the inverse scan conversion is performed there. Further, the output of the inverse DCT circuit is stored in the buffer memory to simultaneously realize the function of the transposition memory. Therefore, the required memory capacity is 16 bits x
2 × B = 32 B [bit]. Thus, the memory capacity required for the inverse zigzag conversion is 9 bits to 16 bits.
Considering the entire memory capacity required from the variable length decoding process to the inverse DCT even if the number is increased to t, conversely, it can be seen that the memory arrangement according to the method of the present invention can be realized with a smaller memory capacity. Also, by sharing the transposed memory function, the required number of memories can be reduced from three to two.

In the decoding device in which the buffer memory is arranged according to the present invention, the variable length decoding process and the dequantization are performed first.
It is possible to perform control such that pipeline processing in which the second stage is the inverse DCT calculation and the third stage is the motion compensation process is performed. A feature of this control method is that the inverse DCT operation and the variable length decoding process of the next block are started at the same time when the banks of the buffer memory arranged after the inverse quantization are switched, and the variable length decoding process of the next block is started at the same time. One example is to start the frame addition process of the previous block.

[0015]

1 shows an embodiment of a moving picture coding apparatus according to the present invention. In this embodiment, a variable length decoding circuit 1, an inverse quantization circuit 2, an inverse discrete cosine transform circuit 3, a prediction signal generation circuit 4, buffer memory circuits 5, 6, 7, a frame addition circuit 8, a frame memory 9, timing control. Circuit 10
It is composed of The compressed video stream supplied to the variable length decoding circuit 1 is converted into a fixed length code string and supplied to the inverse quantization circuit 2. The inverse quantization circuit 2 performs an inverse quantization process by multiplying a quantization step size given in advance and a value of a quantization table, and writes it in the buffer memory 5. The order of data to be subjected to inverse quantization is the data order obtained by variable length decoding, that is, the zigzag scan order,
The inverse zigzag scan conversion is performed by generating addresses corresponding to the zigzag scan order when storing in the buffer memory 5. The data written in the buffer memory 5 is later read by the inverse discrete cosine transform 3 and subjected to the one-dimensional inverse discrete cosine transform in the row direction. The data subjected to the inverse discrete cosine transform in the row direction is once written back to the buffer memory 5 and then read again to be subjected to the inverse discrete cosine transform in the column direction. The inter-frame prediction error signal thus obtained by the inverse discrete cosine transform is stored in the buffer memory 6.

The frame memory 9 stores the decoded image signal. The prediction signal generation circuit 4 generates an interframe prediction signal from the image data previously decoded and stored in the frame memory 9, and stores it in the buffer memory 7. The signals respectively stored in the buffer memory 6 and the buffer memory 7 are added by the frame addition circuit 8 to obtain a decoded image signal, which is stored in the frame memory 9. The timing control circuit 10 adjusts the activation timing of the variable length decoding circuit 1, the buffer memory circuit 5, and the frame addition circuit 8 at a timing which will be described in detail later, thereby performing overall control.

FIG. 2 shows an example of the variable length decoding circuit 1. Barrel shifter 2 for shifting from 0 to 7
1. Variable length decoding table 22, determination circuit 23, shift amount calculation circuit 25, 8-bit registers 26, 27, counter 29 for counting zero run length, register 20 for storing the decoded level value, and selector 28. . For the sake of simplicity, a variable length code decoding process for discrete cosine transform coefficients will be described below. Judgment circuit 23
Is a sequencer having an internal state, and decodes one variable length code from the internal state and the output of the barrel shifter 21 to determine a level value representing a cosine transform coefficient and a zero run length preceding this, and respectively register 20 and counter 29. Output to.
According to the contents of the variable length decoding table 22, until the judgment circuit 23 detects one variable length code, the shift of 7 bits or less is repeated by the barrel shifter 21, and the shift of the multiple of 8 bits is repeated by using the registers 27 and 28 to repeat the shift of the input stream. . In general, the number of steps required to finish decoding one code is determined by the number of bits of data referred to at one time as the output of the barrel shifter and the maximum code length of the variable-length code. Here, assuming that the barrel shifter output is 6 bits and the maximum length of the variable length code is 24 bits, in such a circuit, the decoding of one variable length code is completed by calculating at most 4 steps.

When the decoded code has one or more zero runs, the number is stored as the initial value of the counter 29, and the counter 29 is counted down and the output of the selector 28 is set to "0". When the value of the counter 29 becomes 0, the value of the register 20 is output and the countdown of the counter 29 is completed. Further, when the end-of-block code is detected, the counter 29 is set by the determination circuit 23 so that the value “0” is repeatedly output until the number becomes 64 after the immediately preceding level value.

Here, although not shown, the variable length decoding circuit 1 observes the ready signal of the inverse quantization circuit 2 and waits for the next data output if it is not ready. However, even if a wait occurs, the decoding result is stored in the register 20 and the counter 29, so that the decoding process for the next DCT coefficient can be advanced. In this way, 8
As long as the bit stream is continuously supplied from the bit input port, the decoded level signal is output at a rate of one every four clocks.

FIG. 3 shows an example of the inverse quantization circuit 2. The inverse quantization circuit 2 includes a partial product multiplier 301, a register 302 that stores a quantization scale, and a quantization table 30.
3, selectors 304 and 310, shifter 305, clip processing circuit 307, registers 308 and 311, adder 30
9. The selector 312 bypasses the inverse quantization process. The register 302 and the quantization table 303 respectively store the quantization step value and the quantization matrix data supplied in another layer of the bitstream.
All have been set at the time of decoding the DCT coefficient described here. In the inverse quantization operation, the quantization table 30 is applied to each DCT coefficient decoded by the variable length decoding circuit.
This is a process of multiplying the corresponding value in 3 by the quantization step value of the register 302. After this, clip processing circuit 3
At 07, even-odd conversion and clip processing are performed.

First, as a first step, the input DCT coefficient is multiplied by the 8-bit data read from the selector quantization table 303 and the input data. At this time, the selectors 304 and 310 both select the A input. Further, the register 308 is initialized to the value “0”. The value of the quantization table 303 selected by the selector 304 is supplied to the partial product multiplier 301, but the lower 4 bits are selected by the shifter 305, partial multiplication is performed by the partial product multiplier 301, and the result is stored in the register 308. Is stored. Next, in the second step, the upper 4 bits are supplied from the output of the quantization table 303 by the shifter 305, and a partial product is applied between the partial product multiplier 301 and the input. The product of the input data and the value of the quantization table is obtained by adding the partial product of the lower 4 bits stored in the register 308 and the partial product value obtained by the partial product multiplier 301 by the adder 309, and the result is stored in the register 311. Is stored. At this time, the register 308 is initialized to "0".

Next, in the third step, the selector 304,
All 310 select the B input, and the contents of the register 302 and the value of the register 311 are output. In the partial product multiplier 301, the shifter 305 first selects the lower 4 bits of the value of the register 311 and the quantum scale value, and the partial product is stored in the register 308. Next, in the fourth step, the shifter 305 selects the upper 4 bits, and the partial product multiplier 30
The result of multiplication and accumulation by 1 and the adder 309 is stored in the register 308. When the four-step processing required for this multiplication processing is completed, the dequantization circuit 2 sends a ready signal to the variable length decoding circuit 1 to indicate that the next data can be input, although not shown. The value of the register 308 is the clip processing circuit 3
07, and is output via the selector 312.

For the data such as the DC component of the DCT coefficient and the decoding result of the zero run length, which is known to be unnecessary to be inversely quantized by the variable length decoding circuit 1, the input data is converted by using the selector 312. Output as it is in one step. As described above, when each DCT coefficient is realized in 4 steps at most and there are many zero-run codes,
The inverse quantization process is realized in a shorter time.

FIG. 4 shows an example of the buffer memory 5. In the figure, 64-word memories 41a and 41b, a selector 42 for selecting output data of the memory, a read counter 43 to the discrete cosine conversion circuit 3, an inverse zigzag scan address generator 44, selectors 45a and 45b for designating addresses of the memory, Selectors 46a and 46b for selecting write data, write address generator 4
7, high-order 3 bits of the output of the selector 48 and the counter 43
And a row / column switching circuit 49 capable of switching the lower 3 bits. Here, single port RAM
Has a double buffer structure using two surfaces. This double buffer has two states of A and B, and in each state, the data of the input port name corresponding to the selector 42, 45a, 45b, 46a, 46b is selected as the output of each selector. Here, the operation in the state A, that is, the state in which each selector outputs the signal on the side written as A will be described.

The data output from the inverse quantization circuit 3 is written in the memory 41b. The write address is supplied from the inverse zigzag scan address generator 44, and the data input in the zigzag scan order is written in the block raster scan order.

On the other hand, the memory 41a stores the inverse quantization result for the previous block, and the value thereof is read address counter 43 and write address based on the request from the inverse discrete cosine transform circuit 3 described later. It is read out by controlling the generator 47, the selector 48, and the row / column interchange circuit 49, and the two-dimensional inverse discrete cosine transform is realized. Specifically, when the inverse discrete cosine transform circuit 3 executes a row-direction DCT operation, the output of the read address counter 43 is directly read from the memory 41a as a read address without being converted by the row / column interchange circuit 49. Together with the selector 46
The output data of the inverse discrete cosine transform circuit 3 supplied via a is written in the address generated by the write address generator 47. Further, when the inverse discrete cosine transform circuit 3 executes the column direction DCT operation, the output of the read address counter 43 is converted by the row / column interchange circuit 49 to be the read address, and the data is read from the memory 41 a via the selector 42. Read out.

The operation in the state B, that is, the state in which each selector outputs the signal on the side written B, is performed by the memory 41a.
And the functions of the memory 41b are exchanged. In this way, in the double buffer circuit, one memory always realizes the inverse zigzag scan function by dedicating the output of the dequantization circuit 2, and the other memory performs the matrix transposition function by dedicating the input / output of the inverse discrete cosine transform circuit. Has been realized. The switching of the double buffer memory is controlled by the timing control circuit 10 at a timing described later.

FIG. 5 shows an example of the inverse discrete cosine transform circuit 3. Parallel multipliers 51a and 51b, adder 52
a, 52b, registers 53a, 53b, 54a, 54
b, an adder / subtractor 55, coefficient ROMs 56a and 56b storing multipliers for performing inverse DCT calculation, and register files 57a and 57b storing 4-word data.

In the inverse DCT calculation according to this embodiment, the DCT coefficient (y ₀ y ₁ ... y ₇ ) is used to calculate the vector (x ₀ x ₁ ...
· X ₇₎ is calculated according to the following calculation formula for obtaining a.

[0030]

[Equation 1]

Is defined by the coefficient ROM 56a and the coefficient RO
Values corresponding to equations (1) and (2) are written in M56b, respectively. (X ₀ x ₂ x ₄ x ₆ ) is obtained by adding the fourth-order vector that is the result of equations (1) and (2), and (x ₁ x ₃ x ₅ x ₇ ) is obtained by subtracting it. I want it.

One 8th-order vector is read from the buffer memory 5, divided into even-numbered coefficients and odd-numbered coefficients and stored in the register files 57a and 57b. At this time, the vector data of the register files 57a and 57b are sequentially read and stored by directly storing the values of the read address counter of FIG. 4 in the memory without exchanging them by the row / column exchanging circuit 49.

The vector data in the register files 57a and 57b are simultaneously multiplied by the 4 × 4 matrix of the equations (1) and (2) and the quaternary vector by the multipliers 51a and 51b, respectively, and adders 52a and 52b and the register 53a
It is accumulated by 53b. The two data obtained in the registers 3a and 3b at the same time by the calculation of four steps are saved in the registers 54a and 54b at the next clock and added / subtracted by the adder / subtractor 5
Two pieces of data x _i , x _3-i (i = 0 ... 3) obtained after the butterfly operation is performed by 5 are sequentially output. The result of the vector matrix multiplication is registered in the registers 54a and 54b.
By saving to, the multipliers 51a and 51b, the adders 52a and 52b, and the registers 53a and 53b can continuously start calculation of the next vector matrix product. The result is sequentially stored in the buffer memory 5 via the output port. At this time, in the buffer memory 5, the vector data before the inverse DCT operation is already registered in the register file 57a,
Since it has been read by 57b, necessary data is not overwritten.

Since two values are obtained in four steps as described above, the inverse DCT operation in the row direction is applied to 64 pieces of data in 128 steps. The data written in the buffer memory 5 by performing the inverse DCT in the row direction is read again and subjected to the DCT in the column direction. Two-dimensional inverse DCT
Is 128 steps in the row direction and 128 steps in the column direction, for a total of 2
It can be found in 56 steps. Therefore, four steps are required for each DCT coefficient.

FIG. 6 shows an example of the prediction signal generation circuit 4. Register 61 and adder 6 that realize 1-pixel delay
3, a horizontal interpolation unit configured by a selector 66, a vertical interpolation unit configured by a register 62 that realizes 8-pixel delay, an adder 64, and a selector 67, and a time configured by an adder 65 and a selector 68. It is composed of a direction interpolation unit.
Which of the horizontal, vertical, and temporal interpolation units selects H or L as an input to the selectors 66, 67, and 68 that configure each interpolation unit according to the prediction signal generation information of each block obtained by variable-length decoding Is determined. The respective selectors are connected so that when the input H is selected, the interpolated value is output, and when the input L is selected, the interpolation is not performed.

According to the inter-frame prediction information, the data necessary for generating the inter-frame prediction signal is read from the frame memory 9 as block data of 9 pixels × 9 lines,
It is supplied to the horizontal direction interpolation unit and is output to the vertical direction interpolation unit as block data of 8 pixels × 9 lines. The vertical interpolation unit outputs 8 pixels × 8 lines as an output. At this time, since the selector 68 selects the L input, that is, the value 0, the data subjected to the horizontal and vertical interpolation based on the block information is output to the outside. In the case of a bidirectional prediction block, first, the forward prediction block is written in the buffer memory 7 after horizontal / vertical interpolation is performed by the above method. Next, the selector 68 selects the input H, and the backward prediction block is subjected to the interpolation processing by the horizontal / vertical interpolation unit, and at the same time, the forward prediction block read from the buffer memory 7 and the current predicted block are interpolated. The backward prediction block and the backward prediction block are temporally interpolated by the adder 65 and are again written in the buffer memory 7.

In this way, in the case of a unidirectional prediction block only in the forward or backward direction, the time required for the interpolation processing of the data of 9 pixels × 9 lines is calculated by adding the delay time by the registers 61 and 62 (9 × 9). ) +9, which can be estimated as (81 + 9/64 = 1.41) when converted per pixel. The bidirectional prediction block has twice as many 2.9 clocks per pixel. Then, the inter-frame prediction signal can be stored in the buffer memory 7 in a processing time of 2.9 clocks per pixel.

The inter-frame prediction signal stored in the buffer memory 7 is read at the same time as the inverse DCT result stored in the buffer memory 6, and an addition process is performed in the frame adding circuit 8 to reproduce a decoded image, It is written in the memory 9. Although not shown, the processing in the frame addition circuit can be performed with one clock per pixel. Since it takes 2.9 clocks to generate the inter-frame prediction signal stored in the buffer memory 7 and 1 clock to generate the decoded signal read from the buffer memory 7, the inter-frame prediction and the decoded image generation are performed in about 4 clocks in total. Can be finished.

The operation timing of the moving picture decoding apparatus according to the present invention will be described with reference to FIG. The operation of the variable length decoding circuit 1 and the inverse quantization circuit 2 is in the upper stage, the operation of the inverse discrete cosine transform circuit 3 is in the middle stage, the prediction signal generation circuit 4 and the frame addition circuit 8
The operation of is shown in the lower row. As described above, the variable length decoding circuit 1, the inverse quantization circuit 2, the inverse discrete cosine transform circuit 3, and the prediction signal generation circuit 4 and the frame addition circuit 8 in the embodiment each have 4 clocks. The processing is performed at a rate of one. The timing control circuit 10
Upon completion of each of the above three processes, control is performed so as to proceed to the process of the next block at the same time. Therefore, the variable length decoding circuit 1, the inverse discrete cosine transform circuit 3, and the frame addition circuit 8 are simultaneously activated. Has been done.

In the variable length decoding circuit and the inverse quantization circuit in the upper stage, the number of non-zero data differs depending on the input bit stream, so that the processing time differs depending on the block. Particularly, in the period 1, since the block to be subjected to the variable length decoding is not coded, there is no DCT coefficient, so that the processing time is shortened. The inverse discrete cosine transform circuit 3 sequentially performs a row-direction transformation process and a column-direction transformation process. However, in the period 2, the inverse DCT calculation is not necessary for the knot-coded block, so the inverse discrete cosine transform circuit 3 is not activated. The prediction signal generation circuit 4 and the frame addition circuit 8 execute the frame addition process once and the prediction signal generation process up to twice in one cycle. For example, in the period 2, the prediction signal generation for the bidirectional prediction block is performed. On the other hand, in period 3, the inter-frame prediction signal is not generated because the corresponding block is an intra block.

In the figure, the bank switching of the buffer memory 5, the control signal of the selector 68 in the prediction signal generation circuit 4, and the control signal of the row / column interchange conversion circuit 49 in the buffer memory 5 are also shown. Buffer memory 5
The bank switching is performed simultaneously with the activation of the inverse discrete cosine transform circuit 3. Therefore, the activation timing of the inverse DCT calculation for the not coded block, that is, the period 1
No bank switching has occurred at the time of transition from 1 to period 2. Further, it can be seen that the control signal of the selector 68 in the prediction signal generation circuit 4 becomes'H 'only in the bidirectional prediction and only when the second prediction signal is generated, and the interpolation processing in the time direction is realized. Further, while the inverse discrete cosine transform circuit calculates the column direction DCT, the row / column interchange transform circuit 4
The control signal of 9 becomes high level, an address in which rows and columns are interchanged is generated, and it is shown that the transposition function of the matrix is used.

As described above, the inverse DCT process and the variable length decoding process of the next block are started at the same time as the bank switching of the buffer memory 5 arranged after the inverse quantization, and the variable length decoding process of the next block is started at the same time. The start of the frame addition process of the previous block is a feature of this control method. In particular, the inverse discrete cosine transform circuit 3 requires 128 clocks for the conversion in the row direction, whereas the frame addition process takes only 64 clocks. Therefore, the inverse discrete cosine transform circuit 3 includes the delay for realizing the frame adder circuit 8. Starts the conversion process in the column direction and starts the two-dimensional inverse DCT
The frame addition process can be ended before the output of the result is started. Therefore, the buffer memory 6 for storing the inverse DCT result is sufficient for one block, and no special waiting control is required.

As described above, in the embodiment according to the present invention, processing is performed at a rate of one every four clocks for variable length decoding, inverse quantization and inverse DCT. Data 1
The number of processing clocks per piece is determined by the balance between the required processing speed of the entire system and the circuit scale, and this embodiment merely shows an example of implementation every four steps. For example, in a system that requires higher speed processing at the same operating frequency, it is possible to increase the parallel degree of each arithmetic unit and reduce the number of processing clocks per data. In this case, the output of the shifter register is doubled in order to change the number of bits that can be decoded at one time by the variable length decoding circuit 2 from 6 bits to 12 bits, and a large quantization table is adopted. In the inverse quantization circuit 2, the partial product multiplier is used as a parallel multiplier so that multiplication can be performed once with a clock.
In the inverse discrete cosine transform circuit 3, the product-sum calculator including parallel multipliers, adders, registers, etc. may be doubled in four parallels. Conversely, in a system that does not require high-speed processing, in this case, the output of the shifter register is halved and the quantization table is changed in order to reduce the number of bits that can be decoded at one time by the variable length decoding circuit 1 from 6 bits to 3 bits. In the inverse quantization circuit 2, the number of bits of the multiplicand that can be calculated at one time by the partial product multiplier is reduced from 4 bits to 2 bits, and in the inverse discrete cosine transform circuit 3, only one product sum calculator is required. Therefore, the control method according to the timing shown in FIG. 7 does not depend on the configuration method in each arithmetic unit.

[0044]

According to the present invention, the inverse quantization process and the inverse DC are performed.
Pipeline processing can be performed using the buffer memory arranged between the T processings, and efficient design of each arithmetic unit can be performed. Therefore, there is an effect that the entire decoding apparatus can be optimized.

The number of memories required in the method of the present invention can be reduced as compared with the conventional method, and the memory capacity as a whole becomes equal to or less than that of the conventional method. Therefore, there is an effect that it is advantageous for downsizing the device.

Further, according to the present invention, the inverse quantization circuit can be bypassed for the data such as the DC component of the DCT coefficient or the level value 0 which does not require the inverse quantization, and the processing time can be shortened. . Therefore, even if the bit stream supply is delayed due to a factor external to the apparatus, it is possible to reduce the probability of occurrence of processing wait after the inverse DCT by the bypass function of the inverse quantization processing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a moving image decoding apparatus according to the present invention.

FIG. 2 is an example of a variable length decoding circuit 1.

FIG. 3 is an example of an inverse quantization circuit 2.

FIG. 4 is an example of a buffer memory 5.

5 is an example of an inverse discrete cosine transform circuit 3. FIG.

FIG. 6 is an example of a prediction signal generation circuit 4.

FIG. 7 is an explanatory diagram showing operation timing of the embodiment according to the present invention.

FIG. 8 is a block diagram of a conventional decoding device.

[Explanation of symbols]

 1 Variable Length Decoding Circuit 2 Inverse Quantization Circuit 3 Inverse Discrete Cosine Transform Circuit 4 Prediction Signal Generation Circuit 5 Buffer Memory Circuit 6 Buffer Memory Circuit 7 Buffer Memory Circuit 8 Frame Addition Circuit 9 Frame Memory 10 Timing Control Circuit

Claims (5)

[Claims] 1. A variable-length decoding circuit for decoding a variable-length code in a moving picture decoding apparatus for decoding video data compressed by variable-length coding after scan conversion and discrete-cosine transform coefficients, and the variable-length decoding. An inverse quantization circuit connected to the output of the circuit, a first buffer memory connected to the output of the inverse quantization circuit and written with inverse quantized data, and an inverse connection connected to the output of the first buffer memory And a discrete cosine transform circuit, wherein the output of the inverse discrete cosine transform circuit is also connected to the input of the first buffer memory. 2. The moving picture decoding apparatus according to claim 1,
The first buffer memory is composed of two memories,
A moving image decoding apparatus having means for alternately switching between a memory written from the inverse quantization circuit in the reverse scan order at the time of encoding and a memory input / output from the inverse discrete cosine transform circuit. 3. The moving picture decoding apparatus according to claim 1,
The moving picture decoding device, wherein the dequantization circuit has means for switching whether or not to perform dequantization processing for each DCT coefficient, and the variable length decoding circuit controls the switching. 4. The moving picture decoding device according to claim 1, further comprising:
A second buffer memory that stores the output of the inverse discrete cosine transform circuit; a frame memory that stores a decoded image; a prediction signal generation circuit that generates an interframe prediction signal from the decoded image stored in the frame memory; A third buffer memory that stores the output of the prediction signal generation circuit, reads the data stored in the second buffer memory and the third buffer memory, generates a decoded image signal, and stores the decoded image signal in the frame memory. And a frame adder circuit for performing the moving image decoding. 5. The moving picture decoding apparatus according to claim 4,
The variable-length decoding circuit and the inverse quantization circuit have an inverse quantization process of a variable-length code as a first stage, the inverse discrete cosine transform circuit have an inverse discrete cosine transform process as a second stage, and the frame addition circuit performs decoding. The image signal generation process and the inter-frame prediction signal generation process of the next block by the prediction signal generation circuit are set as the third stage, and the process of the next block is performed when all the processes from the first stage to the third stage are completed for one block. A moving picture decoding device characterized in that the moving pictures are simultaneously transferred to.