JP3385866B2 - Inverse quantization and inverse DCT circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DCT (Discrete Cosine Tr) used for encoding or decoding image data.
ansform), quantization, inverse quantization, and inverse DCT.

[0002]

2. Description of the Related Art In recent years, when a digital image is recorded on a recording medium such as an optical disk or the data is transmitted via a cable such as an optical fiber or a communication satellite, it is possible to save the recording medium. , Image data compression and decompression are used to reduce the transmission rate. A method that is often used as a means for compressing image data is a method that combines DCT and quantization, and representative methods include MPEG1 and MPEG2, which are international standards for image compression encoding. A schematic configuration of the decoder of this system is shown in FIG. 2, and its operation will be briefly described below. In FIG. 2, the compressed image coded data is input to the variable length decoding unit 201 to extract the dequantization level value and the motion vector. Next, the dequantization level value is input to the dequantization unit 202, and the motion vector is input to the motion compensation unit 204. The inverse DCT unit 203 generates difference data from the coefficient inversely quantized by the inverse quantization unit 202, and the motion compensation unit 204 reads out reference data corresponding to the motion vector from the frame memory 205. Finally, the adder 206 adds the difference data and the reference data and outputs the result as decoded data. Further, since the decoded data serves as reference data, it is written in the frame data 205. Luminance component 16 x 1
Processing is performed in macroblock units each including 6 pixels and two color difference components 8 × 8 pixels, and inverse quantization and inverse DCT are performed in block units each including 8 × 8 pixels.

The operation of inverse quantization / inverse DCT will be described below. First, an example of the inverse quantization operation used in MPEG2 will be described. The inverse quantization operation can be represented by (Equation 1) except for the correction operation.

[0004]

[Equation 1]

Here, f _ijk is a DCT coefficient, Q _ijk is an inverse quantization level value, W _ijl is a weighting coefficient, and qs is a quantization scale value. Further, i and j are positions of 8 × 8 data in each block (i = 0 to 7, j = 0 to 7), k is a block number (k = 0 to 5), and l is a coefficient group number (l = 0-1).

FIG. 3 shows an explanatory diagram of an inverse quantization operation corresponding to one macroblock. Inverse quantization level value Q _ijk
Is a result of quantizing the DCT coefficient in the encoding process, and 64 pieces are input for every 6 blocks in the macroblock. The weighting coefficient W _{ij l} is a frequency component-dependent quantization table, and is 2 depending on the type of macroblock.
A kind of weighting coefficient group is prepared. Quantization scale q
s is a constant value given for each macroblock and is used for controlling the code amount. In the decoding process, variable length decoding is performed for each macroblock and the inverse quantization level value Q
_The weighting coefficient W _ikl is determined by _ijk , the quantization scale qs, and the extracted macroblock type, and the calculation of ( _Equation 1) is performed.

The DCT coefficient f obtained as a result of (Equation 1)
Two-dimensional inverse DCT is performed on _ijk to obtain the result of inverse quantization / inverse DCT. The DCT coefficient of the kth block is the 8 × 8 matrix F
_Represented by _k , the two-dimensional inverse DCT is DF _k D ^T when represented by an 8 × 8 matrix D of the one-dimensional inverse DCT. The elements of D expressed in d _ij, elements f _ijk of F _k is a value used in the equation (1). The element d _ij of the 8-point inverse DCT is (Equation 2).

[0008]

[Equation 2]

Further, DF _k D ^T = D (F _k D ^T ) is expressed.
F _k D ^T is a one-dimensional inverse D for 8 lines by extracting F _k in the row direction.
This is equivalent to performing CT, and D (F _k D ^T ) is equivalent to performing (F _k D ^T ) in the column direction and performing 1-dimensional inverse DCT for 8 columns. It can be realized by dimensional inverse DCT and transposition.

Next, the calculation of DCT / quantization will be described. The input data of the kth block is the 8 × 8 matrix G _k
The two-dimensional DCT is F _k = CG _k C ^{T when} expressed by the matrix C of 8 × 8 of the one-dimensional DCT. Since DCT is an orthogonal transform, C = D ⁻¹ = D ^T , and i and j are the positions of 8 × 8 data (i = j) in each block with respect to the element g _{ijk of} G _k.
0 to 7, j = 0 to 7), k is a block number (k = 0 to 0)
5). The quantization is _W'ijl = 1 / _Wijl , qs' =
When expressed as 1 / qs, it is expressed as (Equation 3) as in (Equation 1).

[0011]

[Equation 3]

Here, f _ijk is a DCT coefficient, Q _ijk is an inverse quantization level value, _W'ijl is a weighting coefficient, and qs' is a quantization scale value. Also, i and j are 8 × 8 in each block.
Data position (i = 0 to 7, j = 0 to 7), k is block number (k = 0 to 5), l is coefficient group number (l = 0 to 1)
Is.

FIG. 8 shows a conventional inverse quantization / inverse DCT circuit. FIG. 8 is a diagram in which inverse quantization / inverse DCT is realized according to a procedure. In FIG. 8, 801 is a weight coefficient memory,
802 is a first multiplier, 803 is a second multiplier, 804
Is a coefficient buffer memory, 805 is a selector, and 806 is 1
A dimension inverse DCT unit, 807 is a data transposing memory.

The operation of the conventional inverse quantization / inverse DCT circuit will be described below with reference to FIG. In the processing of the first stage, the quantization level Q _ijk of one macroblock is inversely quantized,
The result is written in the coefficient buffer memory 804. L from the weighting factor memory 801 according to the macroblock type
There read the determined weight coefficient W _ijl in the row direction, the first
Of the weighting coefficient W _ijl and the input quantization level Q _ijk by the multiplier 802 of i = 0 to 7, j = 0 to 7, k
= 0 to 5 to obtain Q _ijk × W _ijl , and the second multiplier 803 multiplies the result Q _ijk × W _ijl of the first multiplier 802 by the quantization scale qs at i = 0 to 7, j = 0-7,
Performed for k = 0 to 5 DCT coefficient f _ijk = Q _ijk × W
_ijl × qs, and the DCT coefficient f _ijk is i = 0 to 7, j = 0
.About.7 and k = 0 to 5 are written in the coefficient buffer memory 804.

In the second stage processing, the coefficient buffer memory 8
DCT coefficient f stored in 04_ijkRead out and reverse DC
Realize T. Coefficient buffer memory 804 to DCT
Number f _ijkIs read out in the row direction, and the selector 805
The output of the number buffer memory 804 is selected, and the one-dimensional inverse D is selected.
The DCT coefficient f by the CT unit 806_ijk8 points 1-dimensional inverse D
Number of rows in 1 block for CT in the row direction and 1 macro
Perform 8 x 6 times corresponding to the number of blocks in the block, 1
The output of the three-dimensional inverse DCT unit 806 is used as the data transposing memory 80.
Write to 7 in the row direction. Next, the data transposing memory 807
Data is read in the column direction from the
The output of the storage memory 807 is selected and the one-dimensional inverse DCT unit 8 is selected.
06, and the 1-dimensional inverse DCT unit 806 makes 8 points primary
The number of columns in one block of the original inverse DCT is 8 and 1
8x6 times corresponding to 6 blocks in a macroblock
Inverse quantization / inverse of the output result of the one-dimensional inverse DCT unit 806
This is the output of the DCT circuit.

With this configuration, the number of multiplications per macroblock of the dequantization unit is 8 × 8 × 6 = 38 when the first multiplier multiplies the input quantization level Q _ijk by the weighting coefficient W _ijl.
This is performed four times, and the second multiplier performs multiplication of the result of the first multiplier and the quantization scale value by 8 × 8 × 6 = 384 times, so that a total of 768 times of multiplication are performed.

[0017]

[Problems to be Solved by the Invention] Conventional inverse quantization / inverse D
In the CT circuit, two multipliers, a 384-word coefficient buffer memory, and a 384-word transposing memory are required in the dequantization unit, so that a large area on the chip is occupied in the case of LSI implementation. In addition, since the number of multiplications by the multiplier is 768 times per macroblock, power consumption increases.

In view of the above points, the present invention has an object to provide an inverse quantization / inverse DCT circuit or a DCT / quantization circuit having a small number of arithmetic units and a small number of multiplications.

[0019]

First, as a means for reducing the number of multiplications for dequantization or quantization and reducing the number of multipliers, a weighting coefficient and a quantization scale are multiplied and written in a buffer memory. The multiplication result and the input data are multiplied to perform inverse quantization or quantization.

Second, as means for reducing the coefficient buffer memory of the inverse quantization / inverse DCT circuit, the inverse quantization operation and the first one-dimensional inverse DCT are continuously performed for each data,
The result is written in the transposing memory, the result of the first one-dimensional inverse DCT is read from the transposing memory, and the second one is read.
As a means for reducing the coefficient buffer memory of the DCT / quantization circuit by performing the three-dimensional inverse DCT, the first one-dimensional DCT is performed and the result is written in the transposing memory. The result is read from the transposing memory, and the second one-dimensional DCT and the quantization operation are continuously executed for each data.

Third, an inverse quantization / inverse DCT circuit or D
As a means for reducing the data transposing memory of the CT / quantization circuit, the unit of data to be written in the transposing memory is set to an integral multiple of the block data.

Fourth, as means for reducing the number of times of inverse quantization or quantization on average, a macroblock type which is a signal for selecting a weighting coefficient and a quantization scale value from one macroblock before It is determined whether or not there is a change, and if both values have not changed, the multiplication of the weighting coefficient and the quantization scale value is not performed, and the result of multiplication of the quantization scale value × the weighting coefficient one macroblock before is used. And

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below.

(Embodiment 1) FIG. 1 is a block diagram of an inverse quantization / inverse DCT circuit according to an embodiment of the present invention.
In FIG. 1, 101 is a first selector, 102 is a weight coefficient memory, 103 is a second selector, 104 is a multiplier, 105 is a buffer memory, 106 is a third selector, 107 is a one-dimensional inverse DCT unit, 108 Is a data transposing memory.

In the first stage processing, the quantization scale value qs
And the weighting factor W _ijl are multiplied, and the multiplication result qs × W _ijl is written in the buffer memory 105. In the processing of the first stage, the quantization scale value q
s, and the weighting coefficient W _ijl for which l is determined by the macroblock type from the weighting coefficient memory 102 is i =
0 to 7 and j = 0 to 7 are sequentially read, the weight coefficient W _ijl output from the weight coefficient memory 102 is selected by the second selector 103, and the multiplier 104 then selects the quantization scale value qs and the weight coefficient. Multiply W _ijl sequentially,
The output of the multiplier 104 is written in the buffer memory 105.

In the second stage processing, the buffer memory 105
Qs × W stored in_ijlAnd the inverse quantization level value Q_ijkWith
Multiplies and performs one-dimensional inverse DCT in the row direction and outputs the result.
The data is written in the transposing memory 108. For the second stage processing
And the inverse quantization level value Q _ijkI = 0 to 7, j = 0
7, k = 0 to 5 are sequentially input in the row direction, and the second sec
Inverse quantization level value Q_ijkSelect
Qs obtained from the buffer memory 105 in the first stage processing
× W_ijlAre sequentially read in the row direction, and the first selector 10
1, the output of the buffer memory 105 is qs × W
_ijlAnd the inverse quantization level value Q
_ijkAnd quantization scale value x weighting factor multiplication result qs x W
_ijlI and j corresponding to i and j are i = 0 to 7 and j = 0 to
7, k = 0 to 5, and the selector 106
The output of the calculator 104 is selected and the multiplication result Q_ijkX (qs x
W_ijl) To the one-dimensional inverse DCT unit 107
Input and input 1-dimensional inverse DCT unit 107 to 8 points 1-dimensional inverse D
Number of rows in 1 block for CT in the row direction and 1 macro
Perform 8 x 6 times corresponding to the number of blocks in the block, 1
The output of the three-dimensional inverse DCT unit 107 is used as the data transposing memory 10
Write 8 in the row direction.

In the process of the third stage, the data transposing memory 1
At 08, the one-dimensional inverse DCT in the column direction is performed using the data in which the rows and columns are transposed as input. In the third stage processing, the data is transposed from the data transposing memory 108 in the column direction, and the selector 10
1 selects the output of the data transposing memory 108 by 6
The one-dimensional inverse DCT unit 10 is input to the one-dimensional inverse DCT unit 107.
The 8-point one-dimensional inverse DCT is performed 7 times 8 × 6 times corresponding to the number of columns in one block and the number of blocks in one macroblock of 6 in the column direction, and the output result of the one-dimensional inverse DCT unit 107 is inverted. This is the output of the quantization / inverse DCT circuit.

In the first embodiment, inverse quantization / inverse DC
The process of T is realized by proceeding in the order of the first stage, the second stage, and the third stage.

With the above configuration, the number of multipliers is only one. Further, once qs × W _ijl corresponding to the number of data in the block is calculated, it is not necessary to calculate qs × W _ijl every time the block to which Q _ijk belongs changes, and the number of multiplications can be reduced. . Specifically, qs × W _{ijl in} the first stage
8 × 8 = 64 multiplications for the generation of Q _ijk × 2
For the generation of (qs × W _ijl ), 8 × 8 × 6 = 384 multiplications, that is, 448 multiplications in total. Further, by performing inverse quantization and inverse DCT successively, it is possible to reduce the coefficient buffer memory between them.

If the data transposing memory 108 is a two-port memory and writing of the one-dimensional inverse DCT result in the row direction and data reading into the one-dimensional inverse DCT in the column direction can be performed at the same time, the second step is performed. It is possible to temporally overlap the processing of the third stage, and the number of processing cycles can be reduced.

Further, the quantization scale value which is the input of the first selector 101 and the weighting coefficient which is the input of the second selector 103 may be exchanged.

(Embodiment 2) It is possible to reduce the memory size for data transposition by changing the data processing unit in the second stage and the third stage of the first embodiment.
In the second embodiment, a case will be described in which a macro block composed of 6 blocks has 2 blocks as a data processing unit. The operation will be described with reference to FIG. 1 as in the first embodiment.

In the first stage processing, the quantization scale value qs
And the weighting factor W _ijl are multiplied, and the multiplication result qs × W _ijl is written in the buffer memory 105. In the processing of the first stage, the quantization scale value q
s, and the weighting coefficient W _ijl for which l is determined by the macroblock type from the weighting coefficient memory 102 is i =
0 to 7 and j = 0 to 7 are sequentially read, the weight coefficient W _ijl output from the weight coefficient memory 102 is selected by the second selector 103, and the multiplier 104 then selects the quantization scale value qs and the weight coefficient. Multiply W _ijl sequentially,
The output of the multiplier 104 is written in the buffer memory 105.

In the second stage processing, the buffer memory 105
Qs × W stored in_ijlAnd the inverse quantization level value Q_ijkWith
Multiplies and performs one-dimensional inverse DCT in the row direction and outputs the result.
The data is written in the transposing memory 108. For the second stage processing
And the inverse quantization level value Q _ijkI = 0 to 7, j = 0
7, k = 0 to 1 are sequentially input in the row direction, and the second sec
Inverse quantization level value Q_ijkSelect
Qs obtained from the buffer memory 105 in the first stage processing
× W_ijlAre sequentially read in the row direction, and the first selector 10
1, the output of the buffer memory 105 is qs × W
_ijlAnd the inverse quantization level value Q
_ijkAnd quantization scale value x weighting factor multiplication result qs x W
_ijlI and j corresponding to i and j are i = 0 to 7 and j = 0 to
7, k = 0 to 1, and the selector 106
The output of the calculator 104 is selected and the multiplication result Q_ijkX (qs x
W_ijl) To the one-dimensional inverse DCT unit 107
Input and input 1-dimensional inverse DCT unit 107 to 8 points 1-dimensional inverse D
Number of rows in 1 block for CT in the row direction and 1 macro
Perform 8 × 2 times corresponding to the number of blocks in the block, 1
The output of the three-dimensional inverse DCT unit 107 is used as the data transposing memory 10
Write 8 in the row direction.

In the third stage processing, the data transposing memory 1
At 08, the one-dimensional inverse DCT in the column direction is performed using the data in which the rows and columns are transposed as input. In the third stage processing, the data is transposed from the data transposing memory 108 in the column direction, and the selector 10
1 selects the output of the data transposing memory 108 by 6
The one-dimensional inverse DCT unit 10 is input to the one-dimensional inverse DCT unit 107.
7, the 8-point one-dimensional inverse DCT is performed 8 × 2 times corresponding to the number of columns in one block and the number of blocks in one macroblock of 2 in the column direction, and the output result of the one-dimensional inverse DCT unit 107 is inverted. This is the output of the quantization / inverse DCT circuit.

The second stage process and the third stage process are k = 2.
3 to 3, the second stage process and the third stage process are performed on k = 4 to 5, and the process for one macroblock is completed.

In FIG. 4A, m = 6 and the data processing unit is 6
FIG. 4B shows a processing flow when the block is one macroblock and when the data processing unit is two blocks. When the data processing unit of the second stage and the third stage is one macroblock (m block), the first stage, the second stage, and the third stage of processing are each 1 as in the first embodiment.
Although it is sufficient for each time, the size of the memory for data transposition requires one macroblock (384 words). Meanwhile, the second
When the data processing unit of the stage and the third stage is two blocks, the process of the first stage needs to be performed once, and the processes of the second and third stages need to be performed m / 2 times as described above. Therefore, although the overhead due to the latency in the second and third steps is m / 2 times that of the former method, the number of processing cycles increases, but the capacity of the data transposing memory for two blocks (128
Word).

The data processing unit can be changed corresponding to a divisor of the number m of blocks in one macroblock, and the data transposing memory size can be optimized within a desired number of processing cycles.

(Embodiment 3) FIG. 5 is a block diagram of an inverse quantization / inverse DCT circuit according to an embodiment of the present invention.
In FIG. 5, 501 is a quantization scale value generation unit, 502
Is a first selector, 503 is a determination control unit that receives a macroblock type, a quantized scale code, and a picture switching signal, 504 is a weighting coefficient memory, 505 is a second selector, 506 is a multiplier, and 507 is a buffer. Memory, 508 is third selector, 509 is one-dimensional inverse DCT
Reference numeral 510 denotes a data transposing memory.

In the decision control process, the quantization scale value qs used in the previous macroblock within the same picture.
And whether the multiplication result of the weighting factor W _ijl can be used in the current macroblock as well, and whether or not to perform the first-stage processing described below is controlled. The determination control unit 503 compares the current value and the value one macroblock before with respect to the quantization scale code, which is a factor for determining the quantization scale value, and the macroblock type used to select the two types of weighting coefficient groups. If one of them is different from the one macroblock before, the first stage described below,
The control is performed such that the processes of the second stage and the third stage are performed in order. If neither of the above two values has changed from the previous one macroblock, the result of the quantization scale value of one previous macroblock × weighting coefficient stored in the buffer memory 507 can be used. No, the second described below
The step and the third step are sequentially controlled.

In the first stage processing, the quantization scale value qs
And the weighting factor W _ijl are multiplied, and the multiplication result qs × W _ijl is written in the buffer memory 507. In the processing of the first stage, the quantization scale value generation unit 501 generates a quantization scale value qs from the quantization scale type and the quantization scale code, and the first selector 502 selects the quantization scale value qs and weights it. Weighting coefficient W for which 1 is determined by the macroblock type from the coefficient memory 504
_ijl is sequentially read for i = 0 to 7 and j = 0 to 7,
The second selector 505 selects the weighting factor W _ijl output from the weighting factor memory 504, and then the multiplier 506.
The quantization scale value qs and the weighting coefficient W _ijl are sequentially multiplied by, and the _output of the multiplier 506 is output to the buffer memory 507.
Write in.

In the second stage processing, the buffer memory 507
Stored in qsXW_ijlAnd the inverse quantization level value Q_ijkWith
Multiplies and performs one-dimensional inverse DCT in the row direction and outputs the result.
The data is written in the transposing memory 510. For the second stage processing
And the inverse quantization level value Q _ijkI = 0 to 7, j = 0
7, k = 0 to 5 are sequentially input, and the second selector 5
Dequantization level value Q by 02_ijkSelect the buffer
Qs × W obtained from the memory 507 in the first stage processing_ijl
Are sequentially read out and buffered by the first selector 502.
The output of the memory 507 is qs × W_ijlSelect and multiply
Inverse quantization level value Q_ijkAnd quantization scale
Value x weighting factor multiplication result qs x W_ijlAnd i and j are
The corresponding multiplications are i = 0 to 7, j = 0 to 7, k = 0 to 5
The output of the multiplier 506 by the selector 508.
Select and multiply result Q_ijkX (qs x W_ijl) Is the DCT
The coefficient is input to the one-dimensional inverse DCT unit 509, and the one-dimensional inverse DCT is input.
The 8-point one-dimensional inverse DCT is performed in the row direction by the T unit 509.
Number of rows in 1 block and block in 1 macroblock
Performing 8 × 6 times corresponding to Equation 6, one-dimensional inverse DCT unit 509
Write the output of the data to the data transposing memory 510 in the row direction
Mu.

In the third stage processing, the data transposing memory 5
In step 10, the one-dimensional inverse DCT in the column direction is performed using the data in which the rows and columns are transposed as input. In the process of the third stage, the data transposing memory 510 is read out in the column direction, the output of the data transposing memory 510 is selected by the selector 508 and input to the one-dimensional inverse DCT unit 509. Point 1-dimensional inverse DCT is 8 columns in one block in the column direction and 6 blocks in one macroblock
Is performed 8 × 6 times, and the output result of the one-dimensional inverse DCT unit 509 is used as the output of the inverse quantization / inverse DCT circuit.

In the third embodiment, inverse quantization / inverse DC
The process of T is performed in the order of determination control, first stage (may not be performed by the determination control), second stage, and third stage.

According to the above configuration, 8 × for the generation of qs × W _ijl in the first stage according to the determination control process.
8 = 64 multiplications can be omitted.

(Embodiment 4) FIG. 6 is a block diagram of a DCT / quantization circuit according to an embodiment of the present invention. Figure 6
601 is a first selector, 602 is a weighting coefficient memory, 603 is a second selector, and 604 is a one-dimensional DC.
T section, 605 is a data transposing memory, 606 is a third selector, 607 is a multiplier, and 608 is a buffer memory.

In the first stage processing, the quantization scale value q
s 'is multiplied by the weighting coefficient _W'ijl , and the multiplication result qs'
Write × W ′ _ijl to the buffer memory 608 and perform DCT in the row direction. In the processing of the first stage, the first selector 601 selects the quantization scale value qs ′, and the weighting coefficient W ′ _ijl for which 1 is determined by the macroblock type from the weighting coefficient memory 602 is i = 0 to 7, j =
0 to 7 are sequentially read, and the weighting coefficient W ′ output from the weighting coefficient memory 602 is output by the third selector 606.
_ijl is selected, and then the multiplier 607 sequentially multiplies the quantization scale value qs ′ and the weighting coefficient W ′ _ijl , and writes the output of the multiplier 607 in the buffer memory 608.

In the second stage processing, one-dimensional DCT in the row direction is performed on the input data, and the data transposing memory 605 is used.
Write in. In the processing of the second stage, input data g
_ijk is sequentially input in the row direction for i = 0 to 7, j = 0 to 7, and k = 0 to 5, input data is selected by the second selector 603 and input to the one-dimensional DCT unit 604, and one-dimensional The DCT unit 604 performs 8-point one-dimensional DCT 8 × 6 times corresponding to the number of rows in one block and the number of blocks in one macroblock in the row direction by 8 × 6 times.
Is written in the data transposing memory 605 in the row direction.

In the third stage processing, the data transposing memory 6
In step 05, one-dimensional DCT in the column direction is performed using the data in which the rows and columns are transposed as input to obtain DCT coefficients f _ijk, and qs ′ × W ′ _ijl stored in the buffer memory 608 and the DCT coefficients f _ijk The multiplication is performed, and the result is used as the output of the DCT / quantization circuit. In the process of the third stage, the data is read from the data transposing memory 605 in the column direction, the output of the data transposing memory 605 is selected by the second selector 603, and the selected output is input to the one-dimensional DCT unit 604.
4, the 8-point one-dimensional DCT is performed 8 × 6 times corresponding to the number of columns in one block and the number of blocks in one macroblock of 6 in the column direction, and the DCT coefficient f _ijk is i = 0 to 7, j =
0 to 7 and k = 0 to 5 are sequentially obtained in the row direction, the output of the one-dimensional DCT unit 604 is selected by the third selector 606 to obtain the DCT coefficient f _ijk , and the first stage processing is performed from the buffer memory 608. The obtained qs ′ × W ′ _ijl is sequentially read out in the column direction, the first selector 601 selects qs ′ × W ′ _ijl which is the output of the buffer memory 608, and the multiplier 607 selects the DCT coefficient f _ijk and the quantization scale. Value ×
The multiplication result qs ′ × W ′ _ijl of the weighting factor is multiplied by i and j for i = 0 to 7, j = 0 to 7 and k = 0 to 5, and the multiplication result f _ijk × (qs ′ × DCT of _W'ijl )
-The output of the quantization circuit.

In the fourth embodiment, the DCT / quantization process is realized by proceeding in the order of the first stage, the second stage, and the third stage.

The processing of the first and second steps can be executed simultaneously because the arithmetic units are not shared with each other. Further, as in the second embodiment, the data of the processing of the second and third steps can be executed. The processing unit can be changed. Also,
It is also possible to partially change the configuration as described in the first embodiment.

(Embodiment 5) FIG. 7 is a block diagram of an inverse quantization / inverse DCT / DCT / quantization circuit according to an embodiment of the present invention. In FIG. 7, 701 is a first two-input selector, 702 is a weighting coefficient memory, and 703 is a first three-input selector.
Input selector, 704 is a multiplier, 705 is a buffer memory, 706 is a second three-input selector, 707 is a one-dimensional inverse DCT / DCT unit, 708 is a data transposing memory, 70
Reference numeral 9 is a second 2-input selector. Weighting coefficient memory 70
2 stores a weighting coefficient W _ijl for inverse quantization and a weighting coefficient W ′ _ijl for quantization, and either one is selected by a switching signal. The one-dimensional inverse DCT / DCT unit 707 selects the function of one-dimensional inverse DCT or one-dimensional DCT according to the switching signal. For example, by selecting each input and output of the one-dimensional inverse DCT unit and the one-dimensional DCT unit with a selector. realizable.

First, the operation when performing inverse quantization and inverse DCT
Explain the work. In the first stage processing, the quantization scale value q
s and weighting factor W_ijlAnd the multiplication result qs × W_ijl
Is written in the buffer memory 705. For the first stage processing
Then, the first two-input selector 701 causes the quantization scale
The weight value qs and select from the weighting coefficient memory 702.
Weighting factor W for which l is determined by the block type
_ijlAre sequentially read for i = 0 to 7 and j = 0 to 7,
By the first 3-input selector 703, the weight coefficient memory 7
02 output of weighting factor W_ijlAnd then the multiplier
According to 704, the quantization scale value qs and the weight coefficient W_ijlof
The multiplication is sequentially performed, and the output of the multiplier 704 is stored in the buffer memory.
Write to 705.

In the second stage processing, the buffer memory 705
Qs × W stored in_ijlAnd the inverse quantization level value Q_ijkWith
Multiplies and performs one-dimensional inverse DCT in the row direction and outputs the result.
The data is written in the transposing memory 708. For the second stage processing
And the inverse quantization level value Q _ijkI = 0 to 7, j = 0
7, k = 0 to 5 are sequentially input in the row direction, and the first 3
Inverse quantization level value Q by input selector 703_ijkChoose
Selected from the buffer memory 705 in the first stage processing
Qs × W_ijlAre sequentially read in the row direction, and the first two inputs
The output of the buffer memory 705 is output by the selector 701.
Qs × W_{ij l}, And inverse quantization by the multiplier 704
Level value Q_ijkAnd quantization scale value x weighting factor
Fruit qs × W_ijlAnd i, j correspond to multiplications i = 0 to
7, j = 0 to 7, k = 0 to 5 and the second 3
Select the output of the multiplier 704 with the force selector 706.
Multiplication result Q_ijkX (qs x W_ijl) Is a DCT coefficient of 1
Input to the three-dimensional inverse DCT / DCT unit 707 and input the one-dimensional inverse DC
1-dimensional inverse DCT function by T / DCT switching signal
8 points by the selected one-dimensional inverse DCT / DCT unit 707
Number of rows in one block for one-dimensional inverse DCT in the row direction is 8
And 8 × 6 corresponding to 6 blocks in one macroblock
The output of the one-dimensional inverse DCT / DCT unit 707.
The data is written in the transposing memory 708 in the row direction.

In the third stage processing, the data transposing memory 7
At 08, the one-dimensional inverse DCT in the column direction is performed using the data in which the rows and columns are transposed as input. In the process of the third stage, the data transposing memory 708 is read in the column direction, the output of the data transposing memory 708 is selected by the second three-input selector 706, and is input to the one-dimensional inverse DCT / DCT unit 707.
1-dimensional inverse DCT / DCT switching signal for 1-dimensional inverse D
One-dimensional inverse DCT / DCT unit 70 selected for CT function
7. The 8-point one-dimensional inverse DCT is performed 8 × 6 times by 7 corresponding to the number of columns in one block and the number of blocks in one macroblock of 6 in the column direction, and the one-dimensional inverse DCT is performed by the second 2-input selector. The output result of the / DCT unit 707 is selected and used as the output of the inverse quantization / inverse DCT / DCT / quantization circuit.

The inverse quantization / inverse DCT processing is realized by proceeding in the order of the first step, the second step, and the third step.

Next, the operation when performing DCT / quantization will be described. In the first stage processing, the quantization scale value qs'
And the weighting coefficient W ′ _ijl are multiplied, and the multiplication result qs ′ ×
W ′ _ijl is written in the buffer memory 705, and DCT in the row direction is performed. In the processing of the first stage, the first two-input selector 701 selects the quantization scale value qs ′, and the weighting coefficient W ′ _ijl for which 1 is determined by the macroblock type is selected from the weighting coefficient memory 702 at i = 0 to 0.
7, j = 0 to 7 are sequentially read, the first 3-input selector 703 selects the weighting coefficient W ′ _ijl which is the output of the weighting coefficient memory 702, and the multiplier 704 outputs the quantization scale value qs ′. The weighting factors W ′ _ijl are sequentially multiplied, and the _output of the multiplier 704 is written in the buffer memory 705.

In the second-stage processing, row-direction one-dimensional DCT is performed on the input data, and the data transposing memory 708 is used.
Write in. In the processing of the second stage, input data g
_ijk is sequentially input in the row direction for i = 0 to 7, j = 0 to 7, k = 0 to 5, and input data is selected by the second three-input selector 706 to select the one-dimensional inverse DCT / DCT unit 707.
1-dimensional inverse DCT / DC selected by the 1-dimensional inverse DCT / DCT switching signal for the function of 1-dimensional DCT
Eight-point one-dimensional DCT is set to 1 in the row direction by the T unit 707.
The output of the one-dimensional inverse DCT / DCT unit 707 is written in the row direction in the data transposing memory 708 by performing 8 × 6 times corresponding to the number of rows in a block and the number of blocks in one macroblock.

In the third stage processing, the data transposing memory 7
In step 08, the one-dimensional DCT in the column direction is performed using the data in which the rows and columns are transposed as input to obtain the DCT coefficient f _ijk, and qs ′ × W ′ _ijl stored in the buffer memory 705 and the DCT coefficient f _ijk The multiplication is performed, and the result is used as the output of the DCT / quantization circuit. In the process of the third step, the data is read from the data transposing memory 708 in the column direction, the output of the data transposing memory 708 is selected by the second three-input selector 706, and is input to the one-dimensional inverse DCT / DCT unit 707.
One-dimensional DCT by three-dimensional inverse DCT / DCT switching signal
The one-dimensional inverse DCT / DCT unit 707 selected for the function performs eight-point one-dimensional DCT 8 × 6 times in the column direction corresponding to the number of columns in one block and the number of blocks in one macroblock. The DCT coefficient f _ijk is i = 0 to 7, j = 0
7, k = 0 to 5 are sequentially obtained in the row direction, and the first three-input selector 703 operates the one-dimensional inverse DCT / DCT unit 707.
Output is selected to obtain the DCT coefficient f _ijk, and qs ′ × W ′ _ijl obtained from the buffer memory 705 in the first stage processing.
Are sequentially read out in the column direction, and the first 2-input selector 701
Output qs '× W' of the buffer memory 705
_ijl is selected, and the multiplier 704 multiplies the DCT coefficient f _ijk by the quantization scale value × weighting coefficient qs ′ × W ′ _ijl.
And i, j correspond to multiplications i = 0 to 7, j = 0 to 7,
The second 2-input selector 709 is performed for k = 0 to 5
The output of the multiplier 704 is selected by and the multiplication result f _ijk ×
Inverse quantization / inverse DCT / DCT · (qs ′ × W ′ _ijl )
This is the output of the quantization circuit.

The DCT / quantization processing is realized by advancing the processing in the order of the first step, the second step, and the third step.

In the DCT / quantization processing, the processings of the first and second steps can be executed at the same time because the arithmetic units are not shared. In addition, inverse quantization and inverse DCT
The data processing unit of the processing of the second stage and the processing of the third stage can be changed in the same manner as in the second embodiment for the processing of 1) and the processing of DCT / quantization, and part of the configuration as described in the first embodiment. It can be changed.

[0062]

As described above, according to the present invention, the number of multiplications for inverse quantization or quantization can be reduced and the number of multipliers can be reduced. Also, the coefficient buffer memory of the inverse quantization / inverse DCT circuit or the DCT / quantization circuit is reduced,
Data transposition memory can be reduced. Further, the number of multiplications for inverse quantization or quantization can be reduced on average.
Therefore, in the case of an LSI, the occupied area can be reduced and the current consumption can be reduced, so that this practical effect is great.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an inverse quantization / inverse DCT circuit according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of a decoder for compressed image coded data.

FIG. 3 is an explanatory diagram of an inverse quantization operation.

FIG. 4 is an explanatory diagram of an arithmetic processing flow according to the first and second embodiments of the present invention.

FIG. 5 is a block configuration diagram of an inverse quantization / inverse DCT circuit according to a third embodiment of the present invention.

FIG. 6 is a block configuration diagram of a DCT / quantization circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block configuration diagram of an inverse quantization / inverse DCT circuit / DCT / quantization circuit according to a fifth embodiment of the present invention.

FIG. 8 is a block configuration diagram of a conventional inverse quantization / inverse DCT circuit.

[Explanation of symbols]

101 first selector 102 Weighting coefficient memory 103 second selector 104 multiplier 105 buffer memory 106 third selector 107 one-dimensional inverse DCT section 108 Data transposing memory

Front page continued (72) Inventor Hiromasa Nakajima 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-145765 (JP, A) JP-A-3-140065 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68 H04N 1/41-1/419

Claims (7)

(57) [Claims] 1. A quantization or dequantization circuit for multiplying input data by a weighting coefficient and a quantization scale value, which holds the weighting coefficient, and selects one coefficient group from two kinds of coefficient groups according to a macroblock type. The output of the first memory and the input data are provided with a first memory for selecting and sequentially outputting data, first and second selectors, a multiplier, and a second memory for holding a multiplication result. As the input of the first selector, the quantization scale value and the output of the second memory as the input of the second selector, and the output of the first selector and the output of the second selector as the input of the multiplier. , The output of the multiplier is used as an input of the second memory, the first selector selects the output sequentially read from the first memory in the process of the first step, and the second selector selects the quantization scale value. choose Then, the multiplication result obtained by inputting to the multiplier is stored in the second memory, and in the processing of the second stage, the input data is selected by the first selector and the second memory is selected by the second selector. A quantizing or dequantizing circuit, which selects an output sequentially read from the above and outputs the multiplication result obtained by inputting to the multiplier. 2. A quantizing or inverse quantizing circuit for multiplying input data by a weighting coefficient and a quantization scale value, which holds the weighting coefficient, and selects one coefficient group from two kinds of coefficient groups depending on a macroblock type. A first memory for selecting and sequentially outputting data, a quantization scale value generation unit for obtaining a quantization scale value from a quantization scale code and a quantization scale type, first and second selectors, a multiplier,
A second memory for holding a multiplication result and a comparator having a macroblock type, a quantized scale code, and a picture switching signal as an input are provided, and the output of the first memory and the input data are stored in the first selector. The output of the quantization scale value generation unit and the output of the second memory as the input of the second selector, the output of the first selector and the output of the second selector as the input of the multiplier, The output of the multiplier is used as the input of the second memory, and in the first stage processing, both the macroblock type and the quantized scale code in the same picture are processed by the comparator in the current value and the value one macroblock before. Only when either of them is different as a result of comparison, the first selector selects the output sequentially read from the first memory, and the second selector selects the quantum output. A multiplication result obtained by selecting the scale value input to the multiplier second
In the memory of the second stage, and in the second stage processing, the input data is selected by the first selector, the output sequentially read from the second memory is selected by the second selector, and the selected output is input to the multiplier. A quantization or dequantization circuit, which outputs the multiplication result obtained. 3. An inverse quantization / inverse DCT for multiplying input data by a weighting coefficient and a quantization scale value and performing a two-dimensional inverse DCT.
A first memory for holding a weighting coefficient, selecting one coefficient group from two kinds of coefficient groups according to a macroblock type, and sequentially outputting data; a first memory, a second memory, and a third selector; ,
A multiplier and a second memory for holding the multiplication result,
A one-dimensional inverse DCT unit for performing n-point one-dimensional inverse DCT and a third memory for data transposition are provided, and the output of the first memory and the input data are used as the input of the first selector, and the quantization scale value is used. And an output of the second memory as an input of the second selector, an output of the first selector and an output of the second selector as an input of the multiplier, and an output of the multiplier and an output of the third memory. The output of the multiplier is input to the second memory, the output of the third selector is input to the one-dimensional inverse DCT unit, and the output of the one-dimensional inverse DCT unit is input to the third selector. In the first stage processing, the first selector selects the output sequentially read from the first memory, the second selector selects the quantization scale value, and inputs it to the multiplier. And the output result of the multiplier The input data is stored in the second memory, the input data is selected by the first selector in the second stage processing, the output sequentially read from the second memory is selected by the second selector, and the output is input to the multiplier. ,
The output of the multiplier is selected by the third selector, the result is input to the one-dimensional inverse DCT unit, the obtained result is stored in the third memory, and the third step is performed in the third step. Inverse quantization, characterized in that the output of the third memory read by switching the row direction and the column direction by the selector is selected and the result obtained by inputting to the one-dimensional inverse DCT unit is output. -Inverse DCT circuit. 4. An inverse quantization / inverse DCT which multiplies input data by a weighting coefficient and a quantization scale value and performs a two-dimensional inverse DCT.
A first memory for holding a weighting coefficient, selecting one coefficient group from two kinds of coefficient groups according to a macroblock type, and sequentially outputting data; a first memory, a second memory, and a third selector; ,
A multiplier and a second memory for holding the multiplication result,
A one-dimensional inverse DCT unit for performing n-point one-dimensional inverse DCT and a third memory for data transposition are provided, and the output of the first memory and the input data are used as the input of the first selector, and the quantization scale value is used. And an output of the second memory as an input of the second selector, an output of the first selector and an output of the second selector as an input of the multiplier, and an output of the multiplier and an output of the third memory. The output of the multiplier is input to the second memory, the output of the third selector is input to the one-dimensional inverse DCT unit, and the output of the one-dimensional inverse DCT unit is input to the third selector. In the first stage processing, the first selector selects the output sequentially read from the first memory, the second selector selects the quantization scale value, and inputs it to the multiplier. And the output result of the multiplier The input data stored in the second memory is selected by the first selector for N blocks (N is a natural number equal to or less than the number of blocks included in one macroblock) in the second process, An output sequentially read from the second memory is selected by the selector and input to the multiplier, and an output of the multiplier is selected by the third selector, and the result is selected as the one-dimensional inverse DCT.
The result obtained by inputting to the section is stored in the third memory, and in the processing of the third stage, N blocks of the third memory which are read out by switching the row direction and the column direction by the third selector are stored. An output is selected and the result obtained by inputting it to the one-dimensional inverse DCT unit is set as an output, and the second and third stage processing is performed as N
An inverse quantization / inverse DCT circuit, which is performed for each block. 5. A DCT / quantization circuit that applies two-dimensional DCT to input data and multiplies a weighting coefficient by a quantization scale value, holds a weighting coefficient, and selects from one of two types of coefficient groups depending on a macroblock type. A first memory that selects one coefficient group and sequentially outputs data; first, second, and third selectors;
A multiplier and a second memory for holding the multiplication result,
A one-dimensional DCT unit for performing n-point one-dimensional DCT and a third memory for data transposition are provided, and the output of the first memory and the output of the one-dimensional DCT unit are
The input of the quantization scale value and the output of the second memory as the input of the second selector, and the output of the first selector and the output of the second selector as the input of the multiplier, And the output of the third memory as the input of the third selector, and the output of the third selector as the one-dimensional DC
The input of the T section, the output of the one-dimensional DCT section is the input of the third memory, the output of the multiplier is the input of the second memory, and the first selector selects the first Output sequentially read from the memory, the second selector selects the quantization scale value, inputs it to the multiplier, stores the result in the second memory, and outputs the input data by the third selector. Is selected, the result is input to the one-dimensional DCT unit, the result obtained is stored in the third memory, and in the processing of the second stage, the third selector switches the row direction and the column direction to read. The output of the output third memory is selected and input to the one-dimensional DCT unit, the output of the one-dimensional DCT unit is selected by the first selector, and the output of the second memory is output by the second selector. Select the multiplier D, wherein Accordingly the results obtained to the output
CT / quantization circuit. 6. A DCT / quantization circuit that applies two-dimensional DCT to input data and multiplies a weighting coefficient by a quantization scale value, holds a weighting coefficient, and selects one from two types of coefficient groups depending on a macroblock type. A first memory that selects one coefficient group and sequentially outputs data; first, second, and third selectors;
A multiplier and a second memory for holding the multiplication result,
A one-dimensional DCT unit for performing n-point one-dimensional DCT and a third memory for data transposition are provided, and the output of the first memory and the output of the one-dimensional DCT unit are
The input of the quantization scale value and the output of the second memory as the input of the second selector, and the output of the first selector and the output of the second selector as the input of the multiplier, And the output of the third memory as the input of the third selector, and the output of the third selector as the one-dimensional DC
The input of the T section, the output of the one-dimensional DCT section is the input of the third memory, the output of the multiplier is the input of the second memory, and the first selector selects the first Of the output sequentially read from the memory, the second selector selects the quantization scale value, inputs it to the multiplier, stores the result in the second memory, and in the second-stage processing, The third selector selects N blocks of input data (N is a natural number equal to or less than the number of blocks included in one macroblock), inputs the result to the one-dimensional DCT unit, and outputs the result. No. 3 of the N blocks stored in the memory No. 3 and read in the third step by switching the row direction and the column direction by the third selector.
Output of the memory of 1) is input to the one-dimensional DCT unit, the output of the one-dimensional DCT unit is selected by the first selector, the output of the second memory is selected by the second selector, and the multiplication is performed. A DCT / quantization circuit, wherein the result obtained by the converter is used as an output, and the second and third stage processing is performed every N blocks. 7. An inverse quantization / inverse DCT for multiplying input data by a weighting coefficient and a quantization scale value and performing a two-dimensional inverse DCT.
It is a DCT that performs processing, performs two-dimensional DCT on input data, and multiplies a weighting coefficient by a quantization scale value, an inverse quantization, an inverse DCT / DCT, and a quantization circuit that performs quantization processing, and retains the weighting coefficient. Then, a first memory that selects one coefficient group from four types of coefficient groups according to the macroblock type and the switching signal and sequentially outputs data, a first and a second 2-input selector, and a first and a second 3 An input selector, a multiplier, a second memory for holding a multiplication result, a one-dimensional inverse DCT / DCT unit capable of selecting n-point one-dimensional inverse DCT and n-point one-dimensional DCT processing by a switching signal, and data. A third memory for transposition is provided, and output and input data of the first memory and one-dimensional inverse DCT / D
The output of the CT unit is the input of the first 3-input selector, the quantization scale value and the output of the second memory are the inputs of the first 2-input selector, and the output of the first 3-input selector and the first The output of the 2-input selector is used as the input of the multiplier, the output of the multiplier, the output of the third memory and the input data are used as the input of the second 3-input selector, and the output of the multiplier is used as the output of the second memory. The input of the second three-input selector is the input of the one-dimensional inverse DCT / DCT unit, and the output of the one-dimensional inverse DCT / DCT unit is the input of the third memory,
The output of the multiplier and the output of the one-dimensional inverse DCT / DCT unit are used as the inputs of the second two-input selector, and in the case of inverse quantization / inverse DCT processing, in the first stage processing, from the first memory The dequantization weighting factors determined by the macroblock type and the switching signal are sequentially read, the output of the first memory is selected by the first 3-input selector, and the quantization scale value is selected by the first 2-input selector. Is input to the multiplier, the output result of the multiplier is stored in the second memory, and the input data is selected by the first 3-input selector in the second stage processing, and the first 2 Second by input selector
The output sequentially read out from the memory is selected and input to the multiplier, the output of the multiplier is selected by the second 3-input selector, and the result is selected as the one-dimensional inverse DCT function by the switching signal. The one-dimensional inverse DCT / DCT
The result obtained by inputting to the section is stored in the third memory, and in the processing of the third stage, the output of the third memory read by the second three-input selector with the row direction and the column direction switched. Is selected and the function of the one-dimensional inverse DCT is input to the selected one-dimensional inverse DCT / DCT unit by the switching signal, and the second two-input selector selects the one-dimensional inverse DCT /
The output obtained by selecting the output of the DCT section is used as the output. In the case of the DCT / quantization processing, the quantization for the quantization determined by the macroblock type and the switching signal from the first memory in the first stage processing. Sequentially read out the weighting factors of, the first 3-input selector selects the output of the first memory, the first 2-input selector selects the quantization scale value, and inputs the result to the multiplier. The data is stored in the second memory, the input data is selected by the second 3-input selector, and the result is input to the selected one-dimensional inverse DCT / DCT unit by the switching signal. The result is stored in the third memory, and in the second stage processing, the output of the third memory read by switching the row direction and the column direction by the second 3-input selector is selected and switched. 1D the function is selected the DCT type to the one-dimensional inverse DCT / DCT unit, the first 3 wherein the input selector one-dimensional inverse DCT by No. /
Selecting the output of the DCT section, selecting the output of the second memory by the first two-input selector, and selecting the output of the multiplier by the second two-input selector, and using the result obtained as the output. An inverse quantization / inverse DCT / DCT / quantization circuit characterized by: