JPH04211575A - Orthogonal convertion operation device - Google Patents

Abstract

PURPOSE:To reduce the number of multiplication circuits and addition circuit so that the size of the circuit can be reduced by performing the addition and subtraction of input data so that a part of a DCT coefficient used in a DCT processing is set to zero. CONSTITUTION:The number of addition and subtraction circuits 100 and 101 may be four, for four kinds of addition and subtraction are performed for eight input data. The subtraction circuits 100 are connected to multipliers 80. The number of the multipliers 80 is 32 in total, as comparing with 64 at the conventional unit, for there exists a section having 0 (zero) in the DCT processing coefficient and the multiplication operation may be performed for two sections consisting of 4 lines by 4 trains. The multipliers 80 are connected to an addition circuits 81, and the number of the addition circuits 80 is 24, as comparing with 56 at the conventional unit, for the addition operation is performed for data consisting of 4 line by 4 trains in the section other than that having 0 (zero) in the DCT processing coefficient. The adders are connected to a transposition RAM82.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is used in digital still cameras, facsimile machines, color copying machines, video telephones, etc., and is used to compress and expand color images. The present invention relates to an arithmetic device that performs orthogonal transforms such as DST (hereinafter referred to as DST) and discrete sine transform (hereinafter referred to as DST or DST transform).

0002

[Prior art and its problems] Several methods have been developed and researched as coding methods for color still images.
Joint Photography in October 1989
c Export Group (hereinafter referred to as JPEG) uses adaptive discrete cosine transform (hereinafter referred to as ADCT or simply DCT) as an international standard for the above encoding method.
) was decided to be adopted. This AD below
An outline of CT processing will be explained.

When recording a color photographed image as a still image, for example, a charge coupled device (hereinafter referred to as C) is used as shown in FIG.
After the photographed image information is converted into an electrical signal by the A/D converter 2 (referred to as CD) 1, the image data obtained by digitally converting the electrical signal is sent to the DCT processing section 3, which will be described in detail later. DC for each block that divides one image into a certain size
T processing is performed. Image data A that has been subjected to DCT processing
ij is quantized by the following equation in the quantization processing unit 4 based on the α value, which is a quantization coefficient, and the quantization transformation coefficient Qij defined in JPEG. Note that Bij indicates image component data after quantization. Quantization processing formula: Bij=Aij/α/Qij

00
The quantized image component data Bij is subjected to Huffman encoding processing in the Huffman encoding processing section 5 to compress the image component data, and the compressed image data is stored in the storage section 6. The above is the operation of compressing the captured image information and storing it in the storage section 6. On the other hand, a case where the compressed image data stored in the storage unit 6 is reproduced into the original photographed image will be described below. The compressed image data read out from the storage section 6 is decoded in the Huffman decoding processing section 7, and the compressed image data is converted into image component data Bij. This image component data is subjected to inverse quantization processing in the inverse quantization processing section 8 and converted into image data. This converted image data is processed by an inverse DCT processing unit 9, which will be described in detail later.
CT processing is performed to reproduce almost the original captured image information. Incidentally, among the above-mentioned constituent parts, constituent parts 3 to 5 and 7 to 9 constitute an ADCT processing part.

[0005] In a series of data compression and expansion,
The quantization processing section 4, Huffman encoding processing section 5, Huffman decoding processing section 7, and dequantization processing section 8 are described, for example, in "Journal of Image Electronics Engineers," Vol. 18, No. 6, pp. 398-407 (1989). The configuration is as described.

To explain in more detail, when recording a color photographed image as a still image, as shown in FIG.
0 and processed into a luminance (Y) signal and a color difference (RY, B-Y) signal in the signal processing circuit 11. Each of these Y signal, R-Y signal, and B-Y signal is converted into a digital signal by the A/D converter 2, and then sent to the corresponding Y component page buffer 12 and R-Y component page buffer 13, respectively. , B-Y component page buffer 14. Each data is temporarily stored in the B-Y component page buffer 14. Note that the Y, R-Y, and B-Y component data stored in the component parts 12 to 14 are, for example, when one photographed image consists of only one sheet of A4 size paper. This is all the image information drawn on the paper. As shown in FIG. 21, one captured image consists of a total of 5,400 blocks divided into, for example, 60 blocks in the vertical direction and 90 blocks in the horizontal direction.
It is composed of a total of 64 pixels, 8 pixels on each side. The component data sent out from each of the component parts 12 to 14 is compressed in order to be stored in the memory 6, or conversely, the compressed data stored in the memory 6 is decoded into the original component data. The above-mentioned pixel data for each block is supplied to the ADCT processing unit 15, which performs the processing.

The ADCT processing section 15 has a circuit configuration as shown in FIG. The multiplier 80 is sequentially supplied from each of the constituent parts 12 to 14 with data in pixels constituting the block and DCT processing coefficients for each block. The multiplier 80 then multiplies the pixel data by the DCT processing coefficient and sends the resulting data to the adder 81. The adder 81 adds the supplied result data and sends the addition result data to the transposition RAM 82 which can store the data in 8 vertical by 8 horizontal sections. In addition, in order to perform ADCT processing on a photographed image, which is two-dimensional information, two-dimensional Achieve DCT processing. Therefore, in the processing in the multiplier 80 and adder 80 described above, one-dimensional DCT processing is first performed.

Note that the two-dimensional DCT operation can be expressed as the following equation (a).

[0009]

[Math 1]

f(i,j) is pixel data.

The addition result data read from the transposition RAM 82 is sent to a multiplier 8 that operates in the same manner as the multiplier 80 described above in order to further perform one-dimensional DCT processing.
3 to perform multiplication, and the multiplication result data is sent to adder 84 to perform addition. Two-dimensional DCT processing has now been executed. Then, the ADCT processing is completed through the quantization circuit 85 and the encoding circuit 86.

The above-mentioned operation will be explained in more detail below. For example, among the data of one captured image stored in the Y component page buffer 12, one block of data is shown in FIG.
Assume that The first in this block
Component data X00 to X70 stored in columns are supplied to the multiplier 80 in that order. The multiplier 80 is supplied with DCT processing coefficients arranged in 8 rows and 8 columns as shown below. Incidentally, in the DCT processing coefficients below, a portion indicated by ... indicates that a coefficient exists like the others, but its description is omitted.

[0013]

[Math 2]

Therefore, the multiplier 80 multiplies the data X00 to X70 by the DCT processing coefficients A00 to A70. Assuming that the resulting data are Z00 to Z70, for example, data Z00 is shown as follows. Z00=A00・X00+A01・X10+A02・X
20+A03・X30+A04・X40+A05・X5
0+A06・X60+A07・X70... Equation A As is clear from the above Equation A, the addition part in the data value calculated as above is calculated by the adder 81 at the next stage of the multiplier 80, Finally, the value of Z00 is found. Data Z10 to Z70 are calculated in the same way. The above calculation can be expressed using the determinant c as shown on the next page.

[0015]

[Math 3]

The data Z00 to Z70 obtained in this manner are sent to the transposition RAM 82. Similarly, data X01 in the second column shown in FIG.
Data Z01 to Z7 after DCT processing of
1 is found, and the data up to Z77 are found in the same way and sequentially sent to the transposition RAM 82. Note that the one-dimensional DCT processing is now complete. In addition, each of the above data Z is stored in the transposition RAM 82.
As shown in FIG. 20, the data are stored in the order of 1st column, 2nd column, 3rd column, and so on. At the time when all the data subjected to one-dimensional DCT processing are stored in the transposition RAM 82 in this way, the transposition RAM 82 stores data Z70 to Z77 stored in row I, which is the bottom row shown in FIG. is read out and sent to the multiplier 83.

The multiplier 83 and the adder 84 perform the same operation as the multiplier 80 and the adder 81 described above.
Perform dimensional DCT processing. and transposition R
Data Z60 stored in the next row II from AM82
to Z67 are sent to the multiplier 83. Similarly below,
Data Z00 to Z07 stored in row VIII
are sent to the multiplier 83. In this way, the order in which stored data Z is read from the transposition RAM 82 is different from the order in which it is written into the transposition RAM 82, so until the writing of one block of data to the transposition RAM 82 is completed, data Z is read from the transposition RAM 82. Unable to read data.

Data Z sent out from the adder 84 is compressed by performing predetermined quantization in a quantization circuit 85, and the quantized data is stored in the memory 6 in an encoding circuit 86. Predetermined encoding is performed on the data stored in the . Then, encoded data is sent out from the encoding circuit 86, and this encoded data is stored in the memory 6.

Although the above description has been made regarding Y component data, the same operation applies to other RY component data and BY component data. Further, the above-mentioned ADCT processing operation is about data compression for storing captured image data in memory, but conversely, when reproducing original captured image data from compressed data stored in memory,
The data read from the memory is decoded by a decoding circuit, and then dequantized by a dequantization circuit. The dequantized data is reproduced as captured image data through a multiplier, an adder, a transposition RAM, a multiplier, and an adder.

Note that the IDCT operation (Inverse DCT operation), which is the inverse operation of the DCT operation, can be expressed as the following equation (E).

[0021]

[Math 4]

As mentioned above, DCT processing and IDCT
In processing, all of the input data must be multiplied 64 times by DCT processing coefficients consisting of 8 rows and 8 columns, and the multiplication results must be added 56 times.
Y component page buffer 12 from CCD 1 shown in 7-A
, or R-Y, B-Y component page buffers 13, 1
The time required for the ADCT processing including the storage operation in the memory 6 shown at A in FIG. 17 is longer than the processing time required for the processing up to step 4. Therefore, a memory for temporarily storing color information and brightness information for one screen of captured images, a memory corresponding to each page buffer 12 to 14 shown in FIG. 17, and a frame memory are required. For example, a still video camera requires a memory having a storage capacity of 7.5 Mbits for one screen. Therefore, there is a problem in that the circuit scale of the entire orthogonal transform calculation device becomes large.

The present invention has been made to solve these problems, and its first object is to provide an orthogonal transform arithmetic device with a small circuit scale.

[0024] Furthermore, when conventionally encoding an image and reproducing the original image, the image is sometimes reduced or enlarged from the original image. In reduction processing and enlargement processing, orthogonally transformed data is subjected to inverse orthogonal transformation processing to reproduce the original image, and then processing for reduction and enlargement is performed. If further reduction or enlargement processing is performed after the image is reproduced, a separate processing unit for reduction or enlargement processing is required. Furthermore, there is a problem in that providing separate reduction and enlargement processing increases the processing time accordingly.

[0025] The present invention was made to solve these problems, and instead of processing image reduction and enlargement as separate units, it reproduces the orthogonally transformed data into the original image. An orthogonal transform arithmetic device that simultaneously executes reduction processing and enlargement processing in an inverse orthogonal transform circuit to eliminate the need for a reduction/enlargement unit and shorten the processing time for reduction processing and enlargement processing. The second purpose is to provide the following.

Furthermore, as described above, the conventional apparatus for performing DCT processing and inverse DCT processing is provided with a DCT processing section 3 and an inverse DCT processing section 9, respectively.
These processing units are provided with main arithmetic circuits and the like that perform the same operations. In addition, in the semiconductor circuit chip that constitutes the DCT processing/inverse DCT processing device, this main arithmetic circuit occupies approximately 90% of the circuit chip area, and the fact that two main arithmetic circuits are provided reduces the circuit scale. It is becoming larger. As described above, the conventional orthogonal transform computing device that performs DCT processing/inverse DCT processing also has a problem in that the circuit scale is large.

Furthermore, the present invention has been made to solve these problems, and is a small circuit scale DC
A third object of the present invention is to provide an orthogonal transform calculation device that performs T processing or DCT processing/inverse DCT processing.

Furthermore, the conventional orthogonal transform arithmetic device has the following problems. FIG. 22 shows a data group after the two-dimensional DCT processing has been performed on the data of each pixel in the block shown in FIG. 21A, for example, which has been subjected to the DCT processing. Of course, the image data after DCT processing is also composed of 8 pixels in both the vertical and horizontal directions, as shown in FIG. 22, and a total of 64 data forms one block of data. In the image data after DCT processing, the image data shown in the vertical direction in FIG. 22 has higher frequency components toward the bottom of the diagram, and the image data shown in the horizontal direction has higher frequency components toward the right in the diagram. This results in high image data. Therefore, as is clear from FIG. 22, and also a feature of DCT processing, when DCT processing is performed on image data, the image data value is small in the high frequency component region where frequency components are high in both the vertical and horizontal directions. On the other hand, the image data value in the low frequency region where the frequency component is low is large. Note that the image data group after DCT processing is referred to as Aij for the sake of explanation.

The image data subjected to the DCT processing in this manner is quantized as shown in FIG. When the image data group after quantization is denoted by Bij, Bij is calculated using the following formula (o). Bij=Aij/(α・Qij)...(Formula O) Here, Q
ij is a data group defined by JPEG and consisting of a total of 64 values arranged in 8 rows and 8 columns as shown in FIG. Further, α is a quantization coefficient consisting of a numerical value of 1 or less.

Specifically, each image data value in each row and column of Aij shown in FIG. 22 is divided by the value in the corresponding row and column of Qij, and further divided by the α value. Then, the value of Bij in the corresponding row and column is calculated. For example, in the case of the DC component (also referred to as DC component) 272.2 shown in A in FIG. 22, where both the vertical spatial frequency and the horizontal spatial frequency are the smallest in Aij, the diagram corresponding to that row and column is The value of Qij shown in 23c is 1
6, and the division result value is further divided by the α value. If the α value is now 0.125, then 272.2/1
6/0.125=136. In this way Aij
The calculations are performed on all 64 image data components, and as a result, a quantized image data group Bij shown in FIG. 24 is obtained.

[0031] In Bij, in the above-mentioned high frequency component domain, since the value of Aij serving as the denominator is small, the value after quantization is 0, while in the low frequency component domain, Aij
Since the value of is large, it becomes a value other than 0 even after quantization. If the value after quantization is 0, it means that there is no data as an image, so even if the image data whose value after quantization is 0 is demodulated, the original video will not be reproduced. Become. Therefore, among the 64 pieces of data in the Bij image data after quantization, the greater the number of data that is 0, the worse the quality of the reproduced image will be, and conversely, if the number of data that is 0 is small, The image quality of the reproduced image is good.

Also, paying attention to FIG. 24, in the Bij data group, the area after a certain boundary has only 0 values after quantization, a "zero boundary area" as shown by the dotted line in FIG.
It turns out that there is. Further, this zero boundary area moves depending on the amount of data that is 0 after quantization. In other words, when there is a large amount of data that is 0, that is, when the image quality after playback is poor, the zero boundary area moves in the direction of arrow E shown in FIG. When the image quality is good, the zero boundary area moves in the direction indicated by arrow O. Furthermore, as mentioned above, the value of Aij is due to the photographed image, and Qij is based on JPE
Since these two elements are predetermined values determined by G, these two elements cannot be changed. Therefore, as mentioned above, in order to move the zero boundary region in the direction of arrow E or arrow O, it is understood that the α value should be changed, as is clear from the above-mentioned equation O. In other words, since the α value is a value less than 1, if the α value is set to a value close to 0, each value of Bij will all increase, so the number of data that is 0 after quantization will decrease, and the zero boundary area will be indicated by the arrow Move in the direction of O. Conversely, if the α value is set to a value close to 1, all the values of Bij become small, so the number of data that is 0 increases after quantization, and the zero boundary area moves in the direction of arrow D. In this way, image quality can be changed by appropriately selecting the α value when performing quantization.

After quantization, the quantized image data group Bij is subjected to Huffman encoding, and data compression of the quantized image component data is performed, as shown in FIG. Huffman encoding is an encoding method that changes the bit length of a code word according to the frequency of occurrence of each data. Data that occurs frequently is used as a short code word, for example, 1 bit long, and data that occurs frequently The data is a long code word, for example 7 bits long. Each value of the quantized image data Bij is recorded on a recording medium by adding additional bit data to a Huffman code predetermined in JPEG according to each value of the quantized image data Bij. encoded into data. For example, Table 1 shows the amount of compressed data obtained by Huffman encoding each value of the quantized image component data Bij shown in FIG. In Table 1, the AC component is also called an AC component, and is the DC component mentioned above.
Refers to all image component data other than components. In addition, the AC component is the image component data Bi, as shown by the arrow in FIG.
j, a so-called zigzag scan is performed starting from the AC component adjacent to the DC component in the horizontal direction of the spatial frequency, and all AC component data are extracted. By performing zigzag scanning in this way, the zero boundary area can be easily found because the scanning is performed in parallel to the zero boundary area mentioned above, and after scanning the zero boundary area, the remaining image component data is Since all are 0, Huffman encoding can be easily highly compressed.

[0034]

[Table 1]

To explain data compression in detail based on Table 1, component data 136, which is a DC component, is
The number of additional bits is 8 due to EG, and the Huffman code is 11.
It is uniquely defined as 6-bit length of 1110. Since the compressed data amount consists of the additional bits and the Huffman code as described above, the compressed data amount of the component data 136 consists of 14 bits, which is the sum of the additional bit length and the Huffman code length. Similarly, the amount of compressed data for the AC component extracted by zigzag scanning is determined as shown in Table 1. Then, the total number of constituent bits of all compressed data amounts in the DC component and AC component can be obtained. In this example, it is 73 bits as shown in Table 1. Therefore, in this example, one block has a data amount of 73 bits, while, as mentioned above, one block has 64 bits (
If one pixel is made up of, for example, 8 bits, then one block has a data amount of 512 bits, so in this example, the data is compressed to about 1/7 (=73/512). It means that it was done. That is, if the α value is 0.125 as described above, the compression ratio is 1/7. or,
A compression ratio of 1/7 means that a storage medium with a storage capacity of 512 bits per block will have a compression ratio of 7
This means that it is possible to store multiple images.

From the above explanation, in order to change the compression ratio, it is sufficient to change the number of non-zero values in the quantized pixel component data Bij, and this means moving the zero boundary area mentioned above. In other words, it is sufficient to change the α value. That is, if the α value is set to a value close to 0, the image quality after reproduction will improve, but the amount of image data will increase accordingly, and the compression ratio will decrease. Note that a decrease in the compression rate means that the compression rate is bad, and that the compression rate approaches 1. Conversely, if the α value is set to a value close to 1, the image quality after reproduction will deteriorate, but the compression ratio will improve. By changing the α value in this way, it is possible to determine the quality of the image after reproduction. Also, a low compression rate will result in a decrease in the number of still images that can be stored on a single storage medium, although the image quality will be good, and a high compression rate will result in an increase in the number of still images that can be stored, although the image quality will be poor. I can do it.

[0037] The above explanation is for one block in one image, and in order to process one image, the above-mentioned operation will be performed for the 5400 blocks that make up one image. . Furthermore, although the above explanation has been about the process of storing a photographed image in a storage medium, the image stored in this way can be reproduced as a reproduced image by going through a process completely opposite to that described above, as shown in FIG. be able to.

However, among conventional color image compression/expansion devices using DCT processing, there is no orthogonal transformation calculation device that focuses on the relationship between the α value, image quality, and number of stored images as described above. The present invention focuses on the above points, and provides an orthogonal transformation calculation device that makes it possible to change the α value by making it possible to set the number of images stored in a storage medium, thereby changing the quality of the stored images. This is the fourth purpose.

[0039]

[Means for Solving the Problems and Their Effects] The present invention performs discrete cosine transform on a digital signal, and then compresses the data by quantizing and Huffman encoding the transformed data.
The luminance and chrominance signals converted to digital signals are processed by the orthogonal transform processing device, which performs Huffman decoding on the compressed data and demodulates the data into digital signals by performing inverse quantization and inverse discrete cosine transform. A storage unit that stores image data for one line block and addition and subtraction between the image data read from the storage unit so that some values of the discrete cosine transform coefficients used in the discrete cosine transform become 0. and a discrete cosine transform processing section having a preprocessing circuit for performing the processing.

With this configuration, the discrete cosine transform processing section performs addition and subtraction between the digitally converted luminance signal data and color signal data supplied from the storage section, and performs discrete cosine transformation using the data obtained. By performing cosine transformation, some values of the discrete cosine transform coefficients used in the discrete cosine transform can be set to zero. Therefore, the discrete cosine transform processing section can reduce the number of calculations required for the discrete cosine transform, and acts to shorten the time required for the discrete cosine transform. On the other hand, by shortening the time required for discrete cosine transformation processing, the storage unit no longer needs to store all the information of one photographed image, and the storage unit does not need to store all the information of one photographed image, and the storage unit does not have to store all the information of one photographed image, and the storage unit does not have to store all the information of one photographed image. The storage unit only needs to store image data for the existing 90 blocks, ie, a total of 180 blocks. That is, it suffices to provide two storage units that store one line block worth of image data, and the circuit scale of the storage unit becomes smaller. In this way, the discrete cosine transform processing section and the storage section function to reduce the circuit scale of the entire orthogonal transform arithmetic device.

More specifically, in the present invention, input data
0, X1, ...
7) , (X2+X5), (X1+X6), (
X3+X4), (X0-X7), (X2-X5
), (X1-X6), (X3-X4). The data converted by the preprocessing circuit is used as a variable, and the DCT
Expressing the conversion formula, it becomes the determinant.

[0042]

[Math 5]

According to determinant F, some of the coefficients are zero. Since there is no need to perform multiplication for the part where the coefficient is 0, in the end, only 32 multiplications and 24 additions are required. In the decompression process, the calculation formula for the IDCT operation becomes the following determinant.

[0044]

[Math 6]

After the IDCT operation using the determinant Ki, (X
0+X7) , (X2+X5) , (X1+X6)
, (X3+X4) , (X0-X7) , (X2
Post-processing is performed to return X5), (X1-X6), (X3-X4) to X0, X1,...X7. DCT
In the processing circuit, the number of multipliers for a block of (8×8) pixels has been reduced from 64 to 32, and the number of adders has been reduced from 5 to 5
The number will be reduced from 6 to 24. As a result, the processing speed of the DCT calculation becomes faster in proportion to the circuit reduction, for example, in this case, it becomes more than twice as fast, so that the processing speed of the DCT processing circuit becomes faster than the reading speed of the CCD reading element. In addition, the memory capacity of the memory device that relays between the CCD reading element and the DCT processing circuit becomes sufficient in line units.

Further, in the present invention, the inverse orthogonal transform circuit that returns the orthogonally transformed data to the original image data has a variable processing block size, and performs the inverse orthogonal transform corresponding to the specified processing block size. The feature is that coefficients are selected and inverse orthogonal transformation processing of a specified size is performed.

The operation of the orthogonal transform arithmetic device constructed in this way will be explained below. FIG. 5 shows a case where DCT processing is performed as orthogonal transform encoding and IDCT processing is performed as inverse orthogonal transform processing to reproduce the encoded data into the original image. FIG. 5(A) shows an encoding circuit in which the image 20
0 is subjected to DCT processing in blocks of m pixels×n pixels. 204 is a block to which DCT processing is applied, 20
6 is a DCT processing circuit, 208 is a quantization circuit, and 210 is a Huffman encoding circuit. Huffman encoded data is stored in memory. This process is the same as before.

FIG. 5B shows a decoding circuit that reproduces encoded data into the original image, 212 is a Huffman decoding circuit, and 214 is a dequantization circuit. IDCT that performs IDCT processing on inverse quantized DCT transform data
The processing circuit 216 has a function of freely selecting the size of the image to be reproduced, and can specify the block size of the reproduced image as m'pixels×n' pixels. If m', n' is larger than the number of pixels m, n of the block of the original image, the reproduced image is enlarged, and if it is smaller, it is reduced. 218 is a block of a reproduced image, and 220 is a reproduced image. The reproduced image 220 can be reduced in size, enlarged in size, or the same size as the original image 200.

As shown in FIG. 6, two blocks of converted data are subjected to IDCT operation in the IDCT processing circuit 216.
04a, in the case of reduction, the high frequency part (shaded part) of the converted data is discarded, and only the low frequency part 216a is used as the ID.
CT processing is performed to create a reduced image block. When the reproduced image is enlarged, as shown in FIG. 6(B), 0 is added to the higher frequency part (the shaded part) of the converted data block 204a, and this enlarged block 216a is subjected to IDCT transformation and becomes a block of a reproduced image.

Furthermore, the present invention performs DCT processing on a digital signal, then compresses the data by quantizing the converted data and Huffman encoding, and performs Huffman decoding on the compressed data. An orthogonal transform calculation device that performs inverse quantization and inverse DCT processing to demodulate digital signals, stores the coefficients necessary for DCT processing and the coefficients necessary for inverse DCT processing, and instructs DCT processing or inverse DCT processing. a coefficient storage unit that sends out one of the above coefficients selected in response to a control signal, and the supplied coefficients enable both DCT processing and inverse DCT processing;
a set of main arithmetic circuits commonly used for both processes;
A DCT/DCT/Selector having a selection section that selects data subjected to DCT processing or inverse DCT processing in accordance with the control signal.
It is characterized by being equipped with an inverse DCT processing section.

With this configuration, DCT/inverse D
The CT processing section performs DCT processing and inverse DC in one set of the same circuit.
Both the T process and the T process can be executed in common, and the selection unit selects any one of the converted data according to the supplied control signal. In this way, DCT/inverse DC
The T processing section is a DCT and an inverse D, which were conventionally provided separately.
By integrating the CT processing circuits, the circuit scale of the entire device is reduced.

Further, the present invention provides an orthogonal transform calculation device for color still image information using the ADCT encoding method, which includes an image number changeover switch that allows setting the number of photographed images that can be stored in a storage section having a certain storage capacity. , automatically sets a quantization coefficient used for compressing the amount of captured image information to a predetermined amount of image information according to the number of images signal sent by the number of images changeover switch, and also sets the compression rate of the amount of information. A compression ratio detection unit that predicts the image quality level of the captured image to be determined and stored based on the compression ratio, and a display unit that visually displays the image quality level signal sent by the compression ratio detection unit. Features.

With this configuration, the compression rate detection section arbitrarily sets the α value so that the captured image information for the number of images set by the operator using the image number changeover switch can be stored in the storage section. In this way, the α value changes depending on the number of images set by the operator. When the α value changes, the zero boundary area moves as described above, and the image quality of the captured image to be stored can be changed. Also, the compression ratio detection section is α
A compression rate is determined based on the value, an image quality level is predicted based on this compression rate, and the display section visually displays this predicted image quality level. Therefore, the operator can check the image quality of the captured images for the set number of images. In this way, the number of images selection switch, compression rate detection section, and display section indirectly change the α value by setting the number of images to be stored, so that the image quality of the captured images to be stored can be set. It's working.

[0054]

【Example】

The DCT processing of the first embodiment can be expressed by the determinant U as described above, but in the calculation formula processing, Z00 to Z70, which are examples of data after DCT processing, are expressed as Z00, Z20,
It divides into even numbers and odd numbers like Z40, Z60, Z10, Z30, Z50, and Z70, and further divides X00 to X70, which is an example of input data, into (X00+X70), (X2
0+X50), (X10+X60), (X30+X40
), (X00-X70), (X20-X50), (X1
0 - X60), (X30 - Only 0s consisting of 4 rows and 4 columns will exist in partitions O and F. This embodiment takes advantage of this fact.

In FIG. 2 showing an example of the configuration of the ADCT processing section 104 constituting the orthogonal transform calculation device using DCT processing in this embodiment, the same components as in FIG. 18 are given the same reference numerals. The adder/subtractor 100 performs the above-described predetermined addition/subtraction on input data X00 to X70, for example, (X00+X70), (X20+X50),
(X10+X60), (X30+X40), (X00-
X70), (X20-X50), (X10-X60),
(X30-X40), and an example of its configuration is shown in FIG.

In FIG. 4, 110 to 117 respectively clock input data X00 to X70.
This is a shift register and latch circuit that advances and holds at a timing of 1. Addition/subtraction circuits 121 to 124 take in two predetermined pieces of data held in the shift register and latch circuits 110 to 117, and perform addition or subtraction according to a select signal. That is, taking the above data X00 to X70 as an example, the output sides of the latch circuit 110 that latches data X00 and the latch circuit 117 that latches data X70 are connected to the addition/subtraction circuit 121, and the output sides of the latch circuit 110 that latches data X00 and the latch circuit 117 that latches data X70 are connected to the addition/subtraction circuit 121, and the latch circuit that latches data X20. 112
The output sides of the latch circuit 115 that latches the data , the output sides of the latch circuit 116 that latches the data X60 and the latch circuit 111 that latches the data X10 are connected to the addition/subtraction circuit 124. 131 to 134
, 141 to 144 are addition/subtraction circuits 121 to 1
This is a shift register and a latch circuit that increments and holds the data calculated in step 24 at the timing of clock CLOCK2.

The multiplier 80 shown in FIG. 2 uses coefficients a , b ,
Hold d, e, f, g, and h and perform 32 multiplications. The arithmetic device that performs the IDCT calculation also has a similar configuration. The arithmetic device that performs DST calculation and IDST calculation also has a similar configuration.

As is clear from FIG. 4, the addition/subtraction circuit 12
The number from 1 to 124 is 4 for 8 input data.
It is better to use four than to perform different types of addition and subtraction. Such an adder/subtractor 100 is connected to the multiplier 80 described above. The operation of the multiplier 80 is as described above and will not be described here. However, in the conventional example, the number of multipliers 80 is
Since the processing coefficients are composed of 8 rows and 8 columns and the input data is 8, a total of 64 are required, but in this example, as mentioned above, in the DCT processing coefficients, the partition o and the exists, so it is sufficient to perform the multiplication operation on two sections consisting of 4 rows and 4 columns in which values other than 0 exist, resulting in a total of 32 sections. Such a multiplier 80 is connected to an adder 81 which performs the same operation as described above, but with D
Due to the presence of sections O and F in the CT processing coefficients, the addition operation is performed on data in 4 rows and 4 columns in two sections other than sections O and F, and the number of adders 81 is increased from the conventional 56. There will be 24 pieces. Adder 8 like this
1 is connected to a transposition RAM 82 which has the same configuration as described above and performs the same operation.

The above is the circuit configuration related to one-dimensional DCT processing.
M82 is connected to an adder/subtractor 101 having the same configuration and the same operation as described above. Like the multiplier 80, the adder/subtractor 101 is connected to a multiplier 83 which is supplied with DCT processing coefficients having the above partitions O and F and has the same configuration as the multiplier 80 and performs the same operation. Adder 84 has the same configuration as adder 81 and performs the same operation.
connected to. The above is the circuit configuration related to two-dimensional DCT processing. As before, the output side of the adder 84 is connected to a quantization circuit 85, the output side of the quantization circuit 85 is connected to an encoding circuit 86, and the encoding circuit 86 is connected to a memory (not shown). .

On the other hand, as shown in FIG. 3, the circuit that reads out the compressed data stored in the memory and reproduces the original photographed image performs inverse quantization on the decoding circuit 102 that decodes the compressed data read out from the memory. The dequantization circuit 103 is connected to a multiplier 83' which is supplied with dequantization coefficients and performs the same operation as the multiplier 83. The multiplier 83' is connected to the transposition RAM 82 via the adder 84 and the adder/subtracter 101. The transposition RAM 82 includes a multiplier 80 that is supplied with inverse DCT processing coefficients and performs the same operation as the multiplier 80 described above.
', the multiplier 80' is connected to the adder 81, the adder/subtracter 1
It is connected to an image display device (not shown) via 00.

The data compression operation in the orthogonal transform arithmetic device configured as described above is performed in the conventional manner, except that the predetermined addition/subtraction processing as described above is performed on the input data X00 to X70 in the adders/subtractors 100 and 101. The operation is the same as that explained in the orthogonal transform calculation device, so the explanation will be omitted. Also, regarding the data expansion operation, the data added by the adders 84 and 81 is added to the adder/subtractor 10.
Since the operation is the same as the conventional data decompression operation except that the above-mentioned addition and subtraction operations are executed at 1 and 100, the explanation will be omitted.

By performing predetermined addition and subtraction on the supplied data in the adders/subtractors 100 and 101 in this way, the DC supplied to the multipliers 80, 83, 80', 83'
Since some values of the T processing coefficients can be set to 0, and there is no need to perform multiplication when the DCT processing coefficient value is 0, the number of multipliers can be reduced compared to the conventional one in a circuit related to one-dimensional DCT processing. The number of adders can be reduced from 64 to 32, and the number of adders can be reduced to 2 from the conventional 56.
It can be reduced to 4. Since the number of processing operations is reduced in this way, the time required for ADCT processing can be significantly shortened compared to the conventional processing time.

Therefore, conventionally, the processing time in the ADCT processing unit is longer than the processing time from the operation in the CCD 1 to the A/D conversion operation, and therefore, as shown in FIG. It was a page buffer that stored all images in the captured image. However, for the reasons mentioned above, the time required for ADCT processing can be made the same as or shorter than the processing time from the operation in CCD 1 to the A/D conversion operation. The buffers 105 to 107 that store the Y component data, R-Y component data, and B-Y component data do not need to be page buffers that store all images in one captured image, and It can be configured with a line buffer that can store information equivalent to two block lines. Note that one block line refers to a row of blocks extending in the horizontal direction of the photographed image in one of the 60 blocks forming the vertical direction of the photographed image. Further, the reason why a buffer for two lines is required is that when data is being input to one buffer, data can be read from the other buffer. or,
Components in FIG. 1 that are the same as those in FIG. 17 are designated by the same reference numerals and their explanations will be omitted.

Furthermore, as mentioned above, the Y component line buffer 1
05. The data stored in the R-Y component line buffer 106 and the B-Y component line buffer 107 is only data for two lines and cannot store data related to one photographed image, so in order to perform DCT processing continuously. ADCT processing section 1
Selector 10 that controls data supplied and sent to 04
8a and 8b are connected to the input and output sides of the component parts 105 to 107, and the output side of the selector 108b is connected to the ADCT.
It is connected to the processing unit 104.

The operations of the constituent parts 105 to 108a, b in the orthogonal transform arithmetic device constructed as described above will be explained below. In addition, other constituent parts 1 in FIG.
The operations of 2, 6, 10, and 11 are the same as those described in the conventional example, and the ADCT processing unit 104 has been described above, so its description will be omitted here. Y component line buffer 105, RY component line buffer 106, B-Y
The component line buffer 107 stores Y component data, RY component data, and BY component data corresponding to two line blocks of the captured image supplied from the A/D converter 2. That is, each of the line buffers 105 to 107 has a buffer that stores two lines of data.
The brightness and color information supplied from the A/D converter 2 are supplied to either one of the two line buffers under the control of the selector 108a. In addition, each line buffer 105
1 to 107 store one line block's worth of data, while the other one line block's worth of data stored therein is read out under the control of the selectors 108a and 108b. The data read out from each line buffer alternately is
It is sent to the ADCT processing unit 104 from the selector 108b. Note that the method of sending the signal from the selector 108b to the ADCT processing unit 104 is performed for each pixel in each block as in the conventional case. Then, the ADCT processing unit 104 performs ADCT processing on the supplied type of component data, and upon completion of this processing, performs ADCT processing on the next component data. Further, the selector 108b is the ADCT processing section 10.
The component data is sent in accordance with the process of step 4.

It should be noted that each of the line buffers 105 to 107 and the selectors 108a and 108b described above operate only in the case of data compression, and are not related to the operation during reproduction processing of compressed data. A description of the operation during data expansion will be omitted since it is the same as the operation of the orthogonal transform arithmetic device in the conventional example described above. As described above, in the orthogonal transform calculation device of this embodiment, the time required for ADCT processing can be shortened as described above, and as the ADCT processing time is shortened, Y component data,
Since the buffer that stores R-Y component data and B-Y component data can be changed from a page buffer to a line buffer, the total memory capacity of the line buffer and transposition RAM 82 is 0.2 Mbits, which is about 1/40 of the conventional one. can be reduced to therefore,
The circuit scale can be significantly reduced.

Although the above embodiment has described DCT processing, the arithmetic unit that performs DST processing and IDCT processing also has a similar configuration.

Second Embodiment The reduction or enlargement of image data to be reproduced is performed using two-dimensional IDC.
This is done when executing the T process. In addition, two-dimensional IDCT processing is
This can be achieved by successively performing one-dimensional IDCT processing on rows and columns, similar to the two-dimensional DCT processing described in the first embodiment. In FIG. 7, 222 and 226 are one-dimensional IDCT processing circuits,
A one-dimensional IDCT processing circuit 222 performs one-dimensional IDCT processing in the row direction (or column direction), the processing result is temporarily held in the data transfer RAM 224, and then the one-dimensional IDCT processing circuit 222 performs one-dimensional IDCT processing in the row direction (or column direction).
The DCT processing circuit 226 performs one-dimensional IDCT processing in the column direction (or row direction).

For the two-dimensional DCT operation, after performing the one-dimensional DCT operation on j using the above-mentioned equation A, the one-dimensional DCT operation can also be performed on i. As described above, when one block is composed of (8×8) pixels and N=8, when the one-dimensional DCT calculation formula is converted into a vector calculation formula, the following determinant is obtained.

[0070]

[Math 7]

[0071] Here, α=cos(2/8)π β=cos(1/8)π δ=sin(1/8)π λ=cos(1/16)π μ=sin(3/16)π γ=cos(3/16)π ν=sin(1/16)π It is.

Similarly, in the two-dimensional IDCT operation, after performing the one-dimensional IDCT operation on V using the above equation E,
It is sufficient to perform one-dimensional IDCT operation for N=8.
In the case of , the one-dimensional IDCT operation can be expressed as a vector calculation formula as shown in the following determinant.

[0073]

[Math. 8]

FIG. 8 shows an example of an IDCT processing circuit for calculating one piece of data in the one-dimensional IDCT processing circuit 222 or 226 shown in FIG. This example is an example of one-dimensional IDCT processing when the original image data has been subjected to DCT processing in blocks of 8 pixels x 8 pixels, and the data is reduced or expanded to N pixels x N pixels, or left at the same size. be. When N>8, enlarge; when N<8, reduce;
When N=8, they are the same size.

Reference numeral 230 is a shift register into which one line of data including eight pieces of data expressed in 8 bits is shifted, and this input data is Huffman decoded and dequantized in the one-dimensional IDCT processing circuit 222. The one-dimensional IDCT processing circuit 226 performs one-dimensional IDCT conversion in the row direction (or example direction) in the one-dimensional IDCT processing circuit 222, and the data is stored in the RAM 224. 232 is a latch that holds data shifted by the shift register 230;

234 is a coefficient RO holding IDCT transform coefficients corresponding to the size N of the block of the image to be reproduced.
M, 236 is a register for specifying the size N of the reproduced image block. 238 is a multiplier, and ID selected from the coefficient ROM 234 according to the specified size N.
The CT transform coefficient and the data in latch 232 are multiplied. The outputs of each multiplier 238 are added together in an adder 242 via an AND gate 240, which is a gate circuit, and then stored in the RAM 22.
Sent to 4. AND gate 240 has each multiplier 238
Signals C0 to C7 are applied to enable or disable the multiplication results. C0 to C7 are designated by the screen size N to be reproduced.

Next, the operation of the embodiment shown in FIG. 8 will be explained. Data N of the reproduced image size is input to the register 236. When the input data is shifted by the shift register 230 and eight pieces of data are shifted, the latch 2
32 at a time. In the coefficient ROM 234, IDCT conversion coefficients are selected according to the data N of the reproduced image size. A multiplier 238 multiplies the data held in the latch 232 by the IDCT conversion coefficient selected from the coefficient ROM 234.

In the AND gate 240, when N≧8, all C0 to C7 are set to high level and all the products of the multiplier 238 are output, and the adder 242 adds them to calculate one piece of data. . On the other hand, in the case of reduction, N<8,
For example, when N=7, the valid/invalid switching signal C0 becomes low level, and the product of seven pieces of data on the low frequency component side is sent to the adder 242 and added.

For the data held in the latch 232, the IDCT transform coefficients of the image size data N are sequentially sent to the multiplier 238, and a number of products corresponding to the data N are added and sent to the RAM 224. repeated times.

Next, the input data is changed and the process is repeated N times for each piece of input data. This repetition continues until there is no more input data. In this way, according to the orthogonal transform calculation device according to this embodiment, the inverse DCT
During processing, reduction processing and enlargement processing can be performed simultaneously.

Third Embodiment In FIG. 9 showing an embodiment of an orthogonal transform calculation device that performs DCT processing/inverse DCT processing, the same components as those shown in FIG. 16 are given the same reference numerals. As can be seen by comparing FIG. 9 and FIG. 16, this DCT processing/inverse DCT processing device integrates the DCT processing section and the inverse DCT processing section in the conventional DCT processing/inverse DCT processing device shown in FIG. 16 into one circuit. A DCT/inverse DCT processing section 300 is provided. The DCT/inverse DCT processing unit 300 executes either DCT processing or inverse DCT processing based on the DCT transform coefficients or inverse DCT transform coefficients selected and sent out by the coefficient ROM 306 in response to a selection signal supplied from the outside. This is a circuit that can do this. Note that the other components are the same as the configuration shown in FIG. 16, so the explanation will be omitted.

As explained in the first embodiment above, as shown in FIG. 11, image data X00, X10,
The image data is sequentially converted into digital data in the order of X20,...X70 and serial/parallel (hereinafter S
/P) is sent to the converter 331. When the first column of digital image data shown in FIG. 19 is stored, the S/P converter 331 sends these eight pieces of digital image data to the register 332 in parallel. Note that the digital image data stored in the register 332 is
Set it to 7.

The digital image data X0 to X7 stored in the register 332 are processed by the A circuit 333 as (X0+X
7), (X1+X6), (X2+X5), (X3+X4
), (X3-X4), (X2-X5), (X1-X6)
, (X0 -
a, respectively. Each multiplier 334a multiplies the DCT transform coefficient supplied to each multiplier 334a by the calculation result value, and the multiplication result value is applied to the adder group 334b.
The adder group 334b adds the multiplication result values and adds the addition result values Z0, Z2, Z4, Z6, Z1, Z.
3, Z5, and Z7 are sent to the B circuit 335.

The B circuit 335 rearranges the above addition result values in order from Z0 to Z7, sends the values to the register 336, and the register 336 stores them. Note that the data X0 to X7 stored in the register 332 are the data Z
The determinant to be converted into 0 to Z7 is shown in the above-mentioned determinant (f). In this determinant, the DCT transform coefficients are a, -a, etc. expressed in a matrix.

The above explanation relates to the first one-dimensional DCT processing of two-dimensional processing; in order to perform the DCT processing of the entire image, the same one-dimensional It is necessary to perform DCT processing. Therefore, the above data Z0 to Z7 are further subjected to DCT processing, and data Y
Converted to 0 to Y7. The inverse DCT processing unit 9 also performs one-dimensional inverse DC similarly to the DCT processing unit 3 described above.
Two-dimensional inverse DCT processing is achieved by performing T processing twice, and FIG. 12 shows a circuit configuration for performing the one-dimensional inverse DCT processing. Note that the same components as those shown in FIG. 11 are given the same reference numerals.

A register 392 that stores, for example, data Y00 to Y70 sent from the S/P converter 391 as data Y0 to Y7 sends the data Y0 to Y7 to a multiplier 334a constituting the main arithmetic circuit 334 and a C circuit 3.
93. The C circuit 393 has a register 39
Seven multipliers 33 constituting the main arithmetic circuit 334 each send data Y0 to Y7 in parallel from
This is a circuit that controls which of 4a the signal is sent to. still,
The main arithmetic circuit 334 performs the same operation as in the case of the DCT processing described above. Data sent from the main arithmetic circuit 334 is sent to the register 336 via the above-mentioned A circuit 333. With the above, the first inverse DCT process is completed, and the same operation is performed again to complete the two-dimensional inverse DCT process.

FIG. 10, which shows an example of the configuration of the DCT/inverse DCT processing section 300, shows constituent parts that perform DCT processing and inverse DCT processing corresponding to FIGS. 11 and 12. Components that are the same as those shown in FIG. 12 are designated by the same reference numerals. As defined in JPEG, one unit of a block constituting an image is composed of 8 x 8 pixels, so in Fig. 10,
When performing DCT processing, the image data digitally converted by the A/D converter 2 is serially supplied to the S/P converter 301 that processes 8-bit input data, and the inverse DCT
When CT processing is being performed, the image data Aij is serially supplied from the inverse quantization processing section 8 and sent to the S/P converter 3.
01 sends the stored data to the input register 302 in parallel when 8 bits of data is stored.

The output side of the input register 302 is connected to the A selector 303 and the C circuit 393 described with reference to FIG.
connected to. The input side of the A selector 303 is connected to the output side of a main arithmetic circuit 334, which will be described later.
During CT processing, the contact is switched to the input register 302 side, and during inverse DCT processing, the contact is switched to the main arithmetic circuit 334 side.

The output side of the A selector 303 is connected to the B selector 304 via the A circuit 333 described with reference to FIGS. 11 and 12. On the other hand, the output side of the C circuit 393 is also connected to the B selector 304. Further, the output side of the A circuit 333 is connected to the C selector 305.

The B selector 304 is supplied with the above select signal in the same way as the A selector 303 described above, and the B selector 304 switches the contact to the A circuit 333 side during DCT processing, and switches the contact to the C circuit 393 side during reverse DCT processing. Switch to The output side of such B selector 304 is
As described above, it is connected to the main arithmetic circuit 334, which is composed of a multiplier 334a and an adder group 334b. Further, the output side of the coefficient ROM block 306 is connected to the main arithmetic circuit 334 . This coefficient ROM block 306 is
The T transform coefficients and the inverse DCT transform coefficients are stored, and when the above select signal is supplied, the T transform coefficients and the inverse DCT transform coefficients are
DCT transform coefficients or inverse D selected according to T processing
The CT transform coefficients are sent to the multiplier 334a.

The output side of the main arithmetic circuit 334 is as follows:
It is connected to the A selector 303 and the B circuit 335 described with reference to FIG. 11, and the output side of the B circuit 335 is connected to the C selector 305. Note that the C selector 305 switches its contacts to the B circuit 335 side during DCT processing, and switches its contacts to the A circuit 333 side during inverse DCT processing, using a select signal supplied similarly to the A selector 303 and B selector 304 described above. C selector 3 like this
The output side of 05 is an output register 307 consisting of 8 bits.
connected to.

Note that the circuit configuration related to the DCT/inverse DCT processing shown in FIG. 10 is also the same as the DCT processing section 3 shown in FIGS.
Similarly to the inverse DCT processing section 9, it performs one-dimensional processing. A DCT equipped with such a DCT/inverse DCT processing section 300
/The operation of the inverse DCT processing device will be explained below. Furthermore, Figure 1
0, white arrows indicate the flow of information during DCT processing, hatched arrows indicate the flow of information during inverse DCT processing, and black arrows indicate the flow of information during both DCT processing and inverse DCT processing. It shows the flow. When performing DCT processing, image information converted into an electrical signal by the CCD 1 and digitally converted by the A/D converter 2 is sent to the S/DCT processing section 300 configuring the DCT/inverse DCT processing section
When the image information for 8 bits is supplied to the P converter 301 and stored in the S/P converter 301, this image information is sent from the S/P converter 301 to the input register 302.

The input register 302 sends the stored input data DI0 to DI7 to the A selector 303 and the C circuit 3.
Send to 93. Since the A selector 303 is currently executing DCT processing, its contacts are connected to the input register 302 side by the select signal, so the A selector 303 sends the supplied input data DI0 to DI7 to the A circuit 333. The A circuit 333 performs predetermined addition and subtraction on the supplied input data DI0 to DI7 and sends the added and subtracted data to the B selector 304.

On the other hand, the input data DI0 to DI7 supplied to the C circuit 393 are supplied to the B selector 304 after the data order to be supplied to the next stage circuit is converted into a predetermined order. Since the B selector 304 is supplied with a select signal instructing DCT processing, the B selector 304
switches the contact to the A circuit 333 side, and sends the addition/subtraction data supplied from the A circuit 333 to the main arithmetic circuit 334. Further, the main arithmetic circuit 334 is supplied with coefficients for performing DCT processing from the coefficient ROM block 306 in response to a select signal, and the main arithmetic circuit 334 performs the same operation as the conventional one, and sends the resulting data to the B circuit 335. and sends it to the A selector 303. Furthermore, as mentioned above, the A selector 30
3 is supplied with a select signal instructing DCT processing, and its contact is switched to the input register 302 side, so that the result data sent out by the main arithmetic circuit 334 is not selected.

The B circuit 335 changes the order of the supplied result data and sends it to the C selector 305. Since the C selector 305 is supplied with a select signal instructing DCT processing, the C selector 305 switches the contact to the B circuit 335 side and sends the supplied data to the output register 307.

[0096] The output register 307 sends the stored data to the next stage quantization processing unit 4, and the quantization processing unit 4 performs the above-described predetermined quantization on the supplied data, and converts the quantized data into The data is sent to the Huffman encoding processing section 5. Then, the Huffman encoding processing unit 5 performs predetermined Huffman encoding on the supplied data and performs data compression.

Next, the case of performing inverse DCT processing will be explained. The compressed data is decoded by a Huffman decoding processor 7, and subjected to dequantization processing by a dequantization processor 8. Then, the dequantized data is subjected to DCT/inverse DCT
The signal is supplied to the S/P converter 301 constituting the processing section 300, and sent from the S/P converter 301 to the input register 302. Input register 302 sends the stored data to A selector and C circuit 393. Since the A selector 303 is supplied with a select signal instructing inverse DCT processing, the A selector 303 connects the contact point to the main arithmetic circuit 33.
Switch to side 4. However, at present, the main arithmetic circuit 3
No data is supplied from 34. On the other hand, C circuit 39
3 performs the same operation as described above and sends the processed data to the B selector 304. B selector 304 is an inverse DCT
The contact is connected to the C circuit 393 by a select signal that instructs processing.
Since the switching is made to the side, the data sent by the C circuit 393 is sent to the main processing circuit 334.

The main arithmetic circuit 334 is supplied with coefficients necessary for inverse DCT processing from the coefficient ROM block 306 in response to a select signal instructing inverse DCT processing, and the main arithmetic circuit 334
34 performs a predetermined calculation and outputs the image information as A.
It is sent to the selector 303 and the B circuit 335.

At this point, the A selector 303 sends the supplied image information to the A circuit 333;
performs predetermined addition/subtraction processing and sends the processed data to C selector 305. Note that the C selector 305 is supplied with the above-mentioned image information sent by the main arithmetic circuit 334 via the B circuit 335.
The contact is switched to A circuit 3 by a select signal that instructs processing.
33 side, the image information supplied from the A circuit 333 is sent to the output register 307.

As explained above, regarding the main arithmetic circuit portions provided in the conventional DCT processing unit 3 and inverse DCT processing unit 9, the coefficients supplied to the multipliers are subjected to DCT processing and inverse DCT processing.
Although the processing is different, the circuit configuration is the same, so in the orthogonal conversion arithmetic device according to this embodiment, the selectors 10 from A to C are
By providing 3 to 105, the main arithmetic circuit portion that occupies about 90% of the semiconductor circuit in the DCT/inverse DCT processing device is reduced to one, and one main arithmetic circuit 334 performs both DCT processing and inverse DCT processing. So, DC
The circuit scale of the entire T/inverse DCT processing device can be significantly reduced, and the area of the semiconductor circuit chip constituting the device can be reduced. As shown in Figure 13, the relationship between the area ratio and chip price for two semiconductor circuits with different chip areas is that if the area ratio is within 1, there will not be much difference in price, but if it exceeds 1. and the price will rise exponentially. The size of the semiconductor circuit chip in conventional DCT/inverse DCT processing equipment is approximately 1 in both height and width.
3 mm, and in the DCT/inverse DCT processing apparatus of this embodiment, the length and width are approximately 9 mm. Therefore, the area ratio is approximately 2,
The price of the DCT/inverse DCT processing device of this embodiment can be significantly reduced compared to the price of a conventional DCT/inverse DCT processing device.

Fourth Embodiment The color still image orthogonal transformation calculation device using DCT in this embodiment allows the operator to first set the number of pieces of color still image information to be stored. The α value is automatically determined to match the storage capacity per image, and the image is compressed based on the α value. Furthermore, the image quality of the image information to be stored is predicted based on the compression ratio calculated based on the α value, and the predicted result is visually displayed. The orthogonal transform calculation device of this embodiment can be added to a conventional orthogonal transform calculation device, or can be added to a third orthogonal transform calculation device.
It is also possible to add the present invention to an orthogonal transform arithmetic device having a faster orthogonal transform arithmetic processing time as shown in the embodiments.

In FIG. 14 showing the configuration of the orthogonal transform calculation device in this embodiment, the DCT processing section 3 performs DCT processing on image information converted into an electric signal by the CCD 1 and amplified by the amplifier 402. Changeover switch 41
The image data Ai sent out by the DCT processing section 3 is based on the α value calculated and sent out by the compression ratio detection section 411 based on the number of stored images set in 0 and the storage capacity of the storage section 6.
It is connected to a quantization processing unit 4 that performs quantization of j. The storage image number changeover switch 410 is provided with several types of switching contacts, each of which has a predetermined number of stored images set, for example, and when the operator selects these switching contacts, the switch 410 is installed in the color still image orthogonal transformation calculation device. This is a switch that allows changing the number of images that can be stored in the storage unit 6. The output side of such a storage image number changeover switch 410 is connected to a compression ratio detection section 411.

The output side of the quantization processing section 4 is connected to the above-mentioned Huffman encoding processing section 5, and the Huffman encoding processing section 5 has a storage section 6 for storing compressed image data, and a compression ratio detection section 411. connected to.

As described above, the Huffman encoding processing unit 5
Then, Huffman encoding is performed and the total amount of compressed data in one block within the photographed image is calculated. Compression ratio detection unit 4
11 is supplied with a signal instructing the number n of images selected by the operator with the storage image number changeover switch 410, and the compression ratio detection unit 411 uses the storage capacity M of the storage unit 6 stored in advance as the number of images stored in the storage unit 6. By dividing by the number of images n, the storage capacity P (=M/n) required for each image to be stored is calculated. Note that in order to determine whether the total amount of compressed data per image falls within the storage capacity P, it is necessary to change the α value appropriately and perform trial and error. Therefore, the compression ratio detection section 41
1 sends a control signal to the DCT processing unit 3 so as to send out only one block of image data in the center of the image before quantizing the entire image. Therefore, the compression rate detection unit 411 is supplied from the Huffman encoding processing unit 5.
Since one image consists of 5400 blocks, the total amount of compressed data in one block in a photographed image is 54.
00, and the α value is changed as appropriate so that this value is equal to the storage capacity P or closest to the P value within a range smaller than the storage capacity P, and the optimum α value is determined. The compression ratio detection unit 411 then sends the determined α value to the quantization processing unit 4.

[0105] Furthermore, the compression ratio detection unit 411 has the
Function information indicating the relationship between the compression rate value and image quality as shown in 5 is stored, and the compression rate detection unit 411 determines the image quality based on the function information for the compression rate value calculated based on the determined α value. The information signal is sent to the image quality display section 412. The image quality display section 412 indicates the image quality based on the image quality information signal, for example, EXCELLENT, GOOD, FAIR, POOR, BAD.
(Defective) and the corresponding rank is visually displayed to the operator on a liquid crystal display or LED display.

[0106] The constituent parts described above relate to the case where photographed images are stored. The output side of the storage unit 6 is connected to a Huffman decoding unit 7 that decodes compressed data representing pixel information for each pixel into uncompressed pixel component data, and the Huffman decoding unit 7 is connected to a compression ratio detection unit. 411
It is connected to an inverse quantization processing section 8 that performs inverse quantization using the α value sent by. The inverse quantization processing unit 8 is connected to an inverse DCT processing unit 9 that reproduces the original captured image by performing inverse DCT processing on the supplied quantized pixel data. Incidentally, the above-mentioned components 1, 402, 3 to 9 have the same circuit configuration as the conventional orthogonal transform calculation device described above.

The operation of the orthogonal transformation calculation device for color still image information configured as described above will be explained below. It should be noted that the operations of the constituent parts 1, 402, 3 to 9 are similar to those in the conventional orthogonal transform arithmetic device described above, and therefore the explanation will be omitted except for necessary parts.

First, the operator sets how many captured images he wants to record in the storage section 6 using the storage image number changeover switch 410. A signal regarding the set number of stored images is supplied to the compression ratio detection section 411, and the compression ratio detection section 411 calculates the storage capacity P required for each stored image. Further, the compression ratio detection unit 411 sends an appropriate α value to the quantization processing unit 4.

On the other hand, the image information converted into electrical signals by the CCD 1 is sequentially sent to the DCT processing section 3. The DCT processing unit 3 receives only the image information in one block located in the center of one image from the compression rate detection unit 411 and performs DCT processing on it.
A control signal to be processed is supplied, and the DCT processing unit 3 performs DCT processing on the image information of one block in the center. Note that the reason why a block in the center of the image is selected as the block to be subjected to the DCT processing is that focusing in a photographed image is normally performed at the center of the image.

The one block of image data Aij that has been subjected to DCT processing in the DCT processing section 3 is sent to the quantization processing section 4. The quantization processing unit 4 performs quantization using the α value supplied from the compression ratio detection unit 411 according to the above-mentioned formula (E), and sends the image component data Bij for one block to the Huffman encoding processing unit 5. The Huffman encoding processing unit 5 performs Huffman encoding on one block of image information and sends the compressed data amount to the compression rate detection unit 411.

The compression ratio detection unit 411 determines whether the value obtained by multiplying the supplied compressed data amount by 5400 is the largest value within the above-mentioned storage capacity P per image, or
If the above conditions are not met, the α value is set again and sent to the quantization processing section 4. Therefore, the quantization processing unit 4 again performs quantization processing on one block in the center of the image using the reset α value, and sends the image component data Bij to the Huffman encoding processing unit 5. The Huffman encoding processing unit 5 then performs the Huffman encoding process again and sends the compressed data amount to the compression ratio detection unit 411, which again performs the same operation as described above. In this way, the compression ratio detection unit 411 determines the optimal α value, and when the optimal α value is determined, sends the optimal α value to the quantization processing unit 4, and also sends the optimal α value for one sheet to the DCT processing unit 3. A control signal is sent to perform DCT processing on all image data. Further, the compression ratio detection section 411 determines the compression ratio using the above-mentioned optimum α value and sends an image quality information signal to the image quality display section 412. For example, if the compression ratio is 1/7, Figure 1
5, the image quality information signal corresponding to EXCELLENT is sent out.

Accordingly, the image quality display section 412 visually displays, for example, the characters "EXCELLENT" based on the image quality information signal. Therefore, the operator can use this display as a guideline for determining the image quality of the next photographed image. For example, if it is acceptable to lower the image quality, the operator can switch the number of stored images changeover switch 410 to the one that has a larger number of stored images. On the other hand, the quantization processing unit 4 sequentially performs quantization processing on the image data in all blocks of one captured image based on the above-mentioned optimal α value, block by block, and converts the image component data Bij of each block into a Huffman encoding processing unit. Send to 5. The Huffman encoding processing section 5 performs Huffman encoding processing for each block as in the case described above, and sequentially sends the compressed data to the storage section 6, which stores it.

[0113] When reproducing the image stored in the storage unit 6, the compressed data read out from the storage unit 6 is decoded in the Huffman decoding processing unit 7, and then dequantized in the dequantization processing unit. Inverse quantization is performed at 8. Note that the α value supplied to the inverse quantization processing unit 8 at this time is the α value when the image being reproduced is subjected to the quantization process. The image data sent from the inverse quantization processing unit 8 is reproduced into the original captured image information by the inverse DCT processing unit 9, and then displayed on an appropriate display device (not shown).
By supplying this reproduced photographed image information to the camera, the photographed image can be visually displayed.

As described above, the operator can select the number of images to be stored in the storage section, and the quality of the stored images can be changed depending on the number of images. Furthermore, it is possible to display the superiority or inferiority of the image quality. In this way, this orthogonal transformation calculation device for color still image information can indirectly change the α value by making it possible to variably set the number of captured images to be stored, which has not received attention in the past. This makes it possible to change the quality of captured images that are stored. Furthermore, since the image quality of the memorized captured image is displayed, the operator can know the image quality of the memorized captured image in advance without having to play back the memorized captured image.For example, if a clear image is desired, the operator can This can be made possible by setting the number of images to be small.

[0115]

Effects of the Invention As detailed above, according to the present invention, addition and subtraction are performed between input data and the resulting data is used to perform the discrete cosine transform. The value of can be set to zero, and the number of operations required for discrete cosine transform processing can be reduced. Therefore, the time required for discrete cosine transformation can be shortened to the same or shorter time than the time required for the pre-stage from the time of photographing to before the photographed image is subjected to discrete cosine transformation processing. Therefore, the storage unit that sends data to the discrete cosine transform processing unit does not need to store all the image data of one captured image, but only needs to store image data for two line blocks. Therefore, the circuit scale of the storage section can be reduced, the circuit scale of the entire data compression/expansion circuit device can be reduced, and there is no need to use an expensive page buffer. can be provided. Further, according to the present invention, in an apparatus using image encoding and decoding that performs orthogonal transform such as DCT and its inverse orthogonal transform, reduction processing and enlargement processing are performed simultaneously during inverse orthogonal transform processing. Therefore, an orthogonal transformation arithmetic device having a reduction function and an enlargement function can be realized with a simple configuration, and can be processed at high speed. Further according to the invention, DCT
Since the processing and the inverse DCT processing are executed in the same circuit, the circuit scale of the DCT/inverse DCT processing device can be reduced. Furthermore, according to the present invention, the number of captured images that can be stored in a storage unit with a certain storage capacity can be set, and the quantization coefficient can be changed according to the set number of images. In other words, the image quality of the captured images to be stored can be changed depending on the number of images to be set. Furthermore, by predicting and displaying the image quality level corresponding to the compression rate determined according to the quantization coefficient, the operator can estimate the image quality of the captured image to be stored according to the set number of memorized images before playback. can be confirmed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of an orthogonal transform calculation device using DCT processing of the present invention.

FIG. 2 is a block diagram showing an example of a circuit configuration related to data compression in the ADCT processing section shown in FIG. 1;

3 is a block diagram showing an example of a circuit configuration related to data expansion in the ADCT processing section shown in FIG. 1. FIG.

4 is a block diagram showing a configuration example of an adder/subtractor shown in FIG. 2. FIG.

FIG. 5 is a block diagram showing a data compression/decompression system in a second embodiment of the present invention.

FIG. 6 is a diagram showing the operation, where (A) shows the case of reduction and (B) shows the case of enlargement.

FIG. 7 is a block diagram showing IDCT processing in a second embodiment of the present invention.

FIG. 8 is a block diagram showing an example of a one-dimensional IDCT processing circuit.

FIG. 9 is a block diagram showing the configuration of a third embodiment of the present invention.

10 is a block diagram showing an example of the configuration of a DCT/inverse DCT processing section shown in FIG. 9. FIG.

11 is a block diagram showing the configuration of the DCT processing section shown in FIG. 16. FIG.

12 is a block diagram showing the configuration of the inverse DCT processing section shown in FIG. 16. FIG.

FIG. 13 is a graph showing the relationship between circuit chip area ratio and circuit chip price.

FIG. 14 is a block diagram showing the configuration of a fourth embodiment of the present invention.

15 is a graph showing a function for determining the quality of an image after compression in the apparatus shown in FIG. 14. FIG.

FIG. 16 is a block diagram showing the configuration of a conventional DCT/inverse DCT processing device.

FIG. 17 is a block diagram showing the configuration of an orthogonal transform calculation device in conventional DCT processing.

18 is a block diagram showing a circuit configuration related to data compression in the ADCT processing section shown in FIG. 17. FIG.

FIG. 19 is a diagram showing one block of data before DCT processing.

FIG. 20 is a diagram showing one block of data after DCT processing.

FIG. 21 is a diagram showing the division of blocks in one image.

FIG. 22 is a diagram showing a specific example of image data after DCT processing.

[Figure 23] Quantization coefficients used when performing quantization (
[alpha] value).

FIG. 24 is a diagram showing a specific example of image component data after quantization.

FIG. 25 is a diagram showing the scanning direction of zigzag scanning when performing Huffman encoding processing.

[Explanation of symbols]

100 and 101...addition/subtraction unit, 104...ADCT processing unit, 105...Y component line buffer, 106...R
-Y component line buffer, 107...B-Y component line buffer, 108...Selector, 110 to 117...
Shift registers and latch circuits, 121 to 124...
Addition and subtraction circuits, 131 to 134, 141 to 14
4...Shift register and latch circuit, 202...Original image, 204...Original image block, 206...DC
T processing circuit, 208...Quantization circuit, 210...Huffman encoding circuit, 212...Huffman decoding circuit, 214...Dequantization circuit, 216...IDCT processing circuit, 218...Regenerated image block , 22
0...Reproduction image, 230...Shift register, 23
2...Latch, 234...Coefficient ROM, 236...
Screen size data register, 238...multiplier,
240...AND gate, 242...Adder, 33
4... Main arithmetic circuit, 303... A selector, 304... B selector, 305... C selector, 306... Coefficient ROM block, 410... Storage image number changeover switch, 41
1... Compression rate detection section, 412... Image quality display section.

Claims (5)

[Claims] Claim 1: After performing discrete cosine transform on a digital signal, compressing the data through quantization and Huffman encoding of the transformed data, and performing Huffman decoding on the compressed data, and then inverting the data. an orthogonal transform calculation device that demodulates digital signals by performing quantization and inverse discrete cosine transform;
a discrete cosine transform processing unit having a preprocessing circuit that performs addition and subtraction between the image data read from the storage unit so that some values of the discrete cosine transform coefficients used in the discrete cosine transform become 0; An orthogonal transformation calculation device comprising: 2. In an orthogonal transformation calculation device equipped with an orthogonal transformation circuit that divides one image into blocks each including a plurality of pixels and performs orthogonal transformation processing on each block, the orthogonally transformed data is converted into original data. The inverse orthogonal transform circuit that returns image data has variable processing block sizes, selects inverse orthogonal transform coefficients that correspond to the specified processing block size, and performs inverse orthogonal transform processing of the specified size. An orthogonal transformation calculation device characterized by the following. 3. The inverse orthogonal transform circuit includes a multiplier that multiplies input data by an inverse orthogonal transform coefficient corresponding to the size of the designated processing block, and a multiplier that multiplies the input data by an inverse orthogonal transform coefficient corresponding to the size of the designated processing block, and 3. The multiplier according to claim 2, further comprising: a gate circuit that determines whether the product of the multiplier is valid or invalid; and an adder that adds the products of the multiplier that are determined to be valid by the gate circuit to obtain one piece of data. Orthogonal transformation calculation device. Claim 4: After performing discrete cosine transform on the digital signal, compressing the data by quantizing the transformed data and Huffman encoding, and performing Huffman decoding on the compressed data, and then inverting the data. An orthogonal transform calculation device that demodulates digital signals by performing quantization and inverse discrete cosine transform, stores the coefficients necessary for discrete cosine transform and the coefficients necessary for inverse discrete cosine transform, and performs discrete cosine transform or inverse discrete cosine transform. a coefficient storage section that sends out one of the coefficients selected above in response to a control signal instructing conversion;
Both discrete cosine transform and inverse discrete cosine transform can be performed by the supplied coefficients, and a set of main arithmetic circuits is used in common for both processes, and the discrete cosine transform or inverse transform is performed according to the control signal. An orthogonal transform calculation device comprising: a selection section that selects data that has been subjected to a discrete cosine transform; and a discrete cosine transform/inverse discrete cosine transform processing section. 5. A color still image information orthogonal transform calculation device using an adaptive discrete cosine transform encoding method, comprising:
An image number changeover switch that allows setting the number of photographed images that can be stored in a storage unit with a certain storage capacity; and an image number changeover switch that allows setting the number of photographed images that can be stored in a storage unit with a certain storage capacity; a compression rate detection unit that automatically sets a quantization coefficient used for compressing the amount of information, calculates the compression rate of the information amount, and predicts the image quality level of the captured image to be stored based on the compression rate; A color still image information orthogonal transformation calculation device using discrete cosine transformation, comprising: a display section that visually displays the image quality level signal sent out by the compression ratio detection section.