JPH09212484A - Discrete cosine transformation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design economical DCT for adaption to the MPEG standards by performing a quantization step for a DCT coefficient together with the execution of the DCT when a video signal is encoded. SOLUTION: An image processor 10 inputs input image information consisting of (8 pixels) × (8 lines) blocks to an FDCT transformation/quantization part 14 through a subtracter 12. The FDCT transformation/quantization part 14 transforms the input image information into a signal represented in a frequency space according to a discrete cosine transforming method to generate image data showing 64 DCT coefficients corresponding to the number of pixels, and then generates a quantization coefficient through a quantizing process. At this time, even and odd function blocks are decomposed by different methods and the transformation output is scaled and integrated with a following quantizing process. The step of the decomposition of the odd function blocks in this DCT is carried out according to equations I-IV. In the equations, x0 -x7 are inputs and cn is cos(nπ/16).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine transform, and more particularly to a high speed discrete cosine transform method useful in processing a video compression signal.

[0002]

2. Description of the Related Art Discrete Cosine Transform (Discrete Cosine Transform) is a central component of video compression signal processing.
ransform) (hereinafter referred to as DCT). There have been many papers on this DCT in the past and now it is a two-dimensional DCT.
There is also interest in the direct computation of. But,
The complexity of the hardware in the direct implementation has become a problem, and in general, one-dimensional D
Tandem connection in which CT is transposed and repeated twice is accepted as the most effective method in LSI design. In this method, 20 multiplication Rs are used.
OM and 4 clocks of pipeline processing time are required, including a special 48-bit latch for synchronization between partial block outputs corresponding to even and odd functions. Further, since there are many coefficients for multiplication, a circuit that equivalently realizes this becomes large. Therefore, there is a greater need for an economical DCT design for application to the growing MPEG standard as the core technology of video compression for future business communications and home entertainment.

[0003]

The present invention provides a new discrete cosine transform method. High speed D according to the invention
CT evenly and evenly decomposes the odd function block by scaling and transforming its transform output (adjusting the size by the multiplication coefficient) and integrating it with the subsequent quantization process (performing simultaneous processing). , Can reduce the amount of hardware. The steps of decomposition of the odd function block in this DCT include the following equations:

[Equation 2]

This new DCT has 10 multiplication ROMs.
Therefore, pipeline processing time for 3 clocks is required. When the present invention is applied to the coding of a video signal, the step of quantizing DCT coefficients can be performed in combination with the execution of DCT. That is, the execution of DCT,
Video coding can be made more economically than separately treating the quantization of the DCT coefficients resulting from its execution.

[0005]

An embodiment of the present invention will be described with reference to the drawings. The DCT has a forward transform and an inverse transform, but since only the direction of the signal flow is different, the forward transform will be mainly described here. The positive one-dimensional DCT is defined by the following equation.

(Equation 3)

The cosine term of equation (5) is expressed in matrix form as follows.

(Equation 4) Where X is the coefficient and input data vector, c
_n means cos (nπ / 16). The number of each element of the matrix of Expression (6) is caused by the modulo 32 as shown in Expression (2).

(Equation 5) The matrix may be decomposed into even and odd function sub-blocks.

(Equation 6)

The upper left sub-matrix can be further decomposed as follows.

(Equation 7) Here, s _n and t _n are sine and tangent, respectively. Most conventional implementations of even function blocks of the DCT use equation (9a). However, removing the common scaling factor as shown in equation (9b) may reduce the hardware complexity as well. According to the equations (9a) and (9b), two butterflys are used to perform conversion of an even number of function blocks except for coefficient re-encoding.
Steps required. Conversely, the transformation of odd function blocks does not have such a clear advantage. However, the equations (1) to (4), which are the characteristic portions in the embodiment of the present invention, are used.
When you decompose an odd functional sub-block like
There is a relationship of (10) and (11).

[0008]

(Equation 8)

Using these relationships, the odd function blocks can be further decomposed as follows.

[Equation 9]

Equation (12) allows a two-step butterfly implementation with a three-input adder in the second stage, and by removing the common scaling factor from the operation, the total number of multiply ROMs can be significantly reduced. FIG. 1 shows a DCT butterfly structure according to the present invention. FIG.
In, butterfly for every two pairs for 8 inputs (x (0) to x (7)) (symmetrical operation for two inputs)
Each coefficient and two pairs of input values at the time of performing are shown. What is finally generated at the right end of 8 inputs x (0) to x (7) corresponds to the DCT coefficient value. Output

[Outside 1] Becomes

To execute a butterfly having three stages, 10
Only multiplication ROMs are required and even function and odd function blocks are processed in the third stage. This saves the 4x10 bit latches required to perform a traditional butterfly. With respect to the total number of 2D DCT multiplications of 8 × 8 pixels, this new approach
2D, 37.5% less than the (chen) algorithm
Only 2 than the very complex direct implementation of CT butterfly
Only 160 multiplications, which is 0% more, are needed, whereas the latter implementation requires 120 ROMs.
Only 20 similar ROMs are needed.

How the scaling works in practice will be described. The output from the butterfly structure shown in FIG. 1 is scaled and the one-dimensional DCT coefficients are stored in the transpose FIFO for the two-dimensional DCT. The second pass one-dimensional DCT is applied to these transposed coefficients so that the input data to the second DCT is uniformly scaled. Thus, the scaling in the one-dimensional DCT is further scaled through the second pass one-dimensional DCT.
The result of the two-dimensional DCT coefficient is expressed as follows.

(10) B = ADA (13) where D is a true two-dimensional D defined by C (CX) ^t.
It is a CT coefficient and A is a scaling matrix defined as follows.

[Equation 11]

However, merge with subsequent quantization
Scaling to a two-dimensional DCT output is not necessary as it can be done. In quantization, the result of the two-dimensional DCT is read in a zigzag pattern and divided by the quantization step size (or processed similarly by accessing ROM). The partition may be scaled according to the scaling factor defined in equations (13), (14). The inverse DCT is simply the opposite operation of the forward transform, as described above. That is, all input data is supplied from the right side of FIG. 1 and the result is available on the left side. The matrices are all transposed and the butterfly connections are shown exactly in the figure. Due to the transpose property of matrix inversion (Hermitian property), the same set of ROMs can be used for the inverse DCT. The three-input adder of equation (12) also has the following Hermitian characteristics.

(Equation 12) The scaling factor is the same as for the forward DCT. This coefficient can be incorporated into the inverse quantization process again after the tunable code decoding of the encoded bit stream.

Although the DCT circuit can be made smaller by using the method according to the present invention described above, this is more advantageous when a two-dimensional DCT is used, such as a process for an image signal. Since the image signal is two-dimensional,
This is because the DCT also acts on the 8 × 8 portion two-dimensionally, so that the circuit itself becomes large. In the method according to the present invention, “If 8-input DCT can be completed in 4 clocks, which is half the number of input data, the input signal is converted in the row direction in the first 4 clocks, and after this is completed,
In the latter four clocks, the transposition result can be converted in the column direction. That is, the conversion can be performed with 8 clocks by a single DCT circuit without doubling the clock rate for 8 inputs. It is based on the idea.

FIG. 2 is a block diagram showing an example of a moving image compression image processing apparatus to which the discrete cosine transform of the present invention is applied. The image processing apparatus 10 includes an FDCT transform / quantization unit 14 that inputs input image information composed of blocks of (8 pixels) × (8 lines) via a subtractor 12. F
The DCT transform / quantization unit 14 transforms the input image information into a signal representing in a frequency space based on the discrete cosine transform method of the present invention, and generates image data showing 64 DCT coefficients (frequency coefficients) corresponding to the number of pixels. The quantized coefficient value is generated by the post-quantization processing. The inverse quantization / IDCT unit 16 returns the quantized coefficient value to a signal value. Inverse quantization / IDCT
The unit 16 performs inverse DCT on the image data after the inverse quantization based on the discrete cosine transform method of the present invention, and writes the result to the memory 20 via the adder 18. Although not shown,
Externally displayed as an image is an input of the memory 20. The image processing apparatus 1 further includes a memory 20 for performing motion compensation and a moving compensator 22. The present invention has been described with reference to one embodiment, but the present invention is not limited to this.

[0016]

The fast and economical discrete cosine transform can be performed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a discrete cosine transform according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of an image processing apparatus to which the discrete cosine transform of the present invention is applied.

[Explanation of symbols]

 14 FDCT / quantization unit 16 Inverse quantization / IDCT unit

Claims (1)

[Claims] 1. The steps of decomposition of an odd function block are as follows: A discrete cosine transform method characterized by being based on the equation of.