JPH10207735A - Cpu diagnostic method for computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect failure by diagnosing a computer by an exclusive testing device by removing it from a moving object in a state close to an operating state in which the computer is loaded on the moving object. SOLUTION: A first CPU sets a branch address at the time of each interruption generation (a step 7), switches an address space (a step 8), executes an instruction test after inter-CPU interruption to the other CPU (a step 9), and reads and judges an input and output test result (a step 10). A second CPU sets the branch address at the time of each interruption generation, operates the initialization and activation of an input and output board, operates the inter-CPU interruption after the writing of the input and output test result in the main memory of the other CPU, and operates the inter-CPU interruption after the writing of error information in the main memory of the other CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of diagnosing a CPU of a computer for diagnosing a computer mounted on a mobile body and operating the mobile body for inspection and maintenance.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing the relationship between a mobile unit equipped with radar and the like and a control center, and FIG. FIG. 7 is a block diagram of the operation control computer,
FIG. 8 is a block diagram of an operation control computer for controlling each device of the operation control computer system, and FIG. 9 is a flowchart showing a conventional CPU diagnosis method of the computer.

[0005] As shown in FIG. 5, a moving body 1 is alerted to the front by radar and, at the same time, communicates with a control center 2, and an operation manager determines the operation direction and the like.
For this purpose, the mobile unit 1 is equipped with a radar 3, an antenna 4, a radar signal processor 5, a communication control processor 6, an operation control computer 7, a display device 8, and an operation panel 9 as shown in FIG. The radar 3, the antenna 4, the radar signal processor 5, the communication control processor 6, the operation control computer 7, the display device 8, and the operation panel 9 are connected to each other as shown in FIG. In FIG. 7, reference numeral 10 denotes an external bus for connecting each device.

[0004] That is, the radar 3 detects an obstacle in front, converts the signal by the radar signal processor 5, and the operation control computer 7 displays it on the display device 8 by an operational program. By operating the operation panel 9, the operational program is transmitted to the communication control processor 6.
The message converted by the communication control processor 6 is transmitted to the control center 2 via the antenna 4. Conversely, a message from the control center 2 is received by the antenna 4 and converted into a communication message by the communication control processor 6. The operation control computer 7 displays the communication message on the display device 8 by an operational program.

[0005] The operation control computer 7, which is the center of the operation described above, has the configuration shown in FIG. In FIG.
Reference numeral 11 denotes a CPU board (hereinafter, referred to as a first CPU board) mainly for operating an operation program for performing operation calculation, and reference numeral 12 denotes an operation program for mainly controlling input / output of data with another computer. CPU board (hereinafter referred to as a second CPU board),
Reference numeral 13 denotes an input / output board for inputting / outputting data between the operation control computer 7 and the outside through the external bus 10;
Reference numeral 5 denotes an internal bus, 16 denotes a power supply, 17 denotes a CPU of the first CPU board 11 (hereinafter, referred to as a first CPU), and 18 denotes a boot ROM of the first CPU board 11 (hereinafter, referred to as a first boot ROM). ), 19 is the main memory of the first CPU board 11 (hereinafter referred to as the first main memory), and 20 is the second main memory.
(Hereinafter, referred to as a second CPU) of the CPU board 12, and 21 is a boot ROM of the second CPU board 12.
(Hereinafter referred to as a second boot ROM), 22 is a second C
The main memory of the PU board 12 (hereinafter, referred to as a second main memory). When operating the operation control computer 7 mounted on the mobile unit 1, the operational program stored in the auxiliary memory 14 is loaded onto the first main memory 19 and the second main memory 22, and the first It is executed by the CPU 17 and the second CPU 20 at the same time.

[0006] The operation control computer 7 which operates as described above.
The first CPU board 11 or the second CPU board 11 may be removed from the mobile unit 1 for maintenance and diagnosed with a dedicated test device.
The CPU diagnosis is individually performed on the CPU board 12 according to the procedure shown in FIG. That is, the first CPU 1
It is tested whether all the registers of the CPU 7 or the second CPU 20 operate normally (S1), and it is tested whether switching access is possible to all the virtual address spaces of the first CPU 17 or the second CPU 20 (S1). S2), first
It is tested whether all the instructions of the CPU 17 or the second CPU 20 operate normally (S17).
3) It is tested whether all the interrupts of the first CPU 17 or the second CPU 20 operate normally (S4), and the first C
PU 17 to first main memory 19, first boot ROM
18 and the auxiliary memory 14 or the second CPU 20 to the second
Test whether the access to the main memory 22, the second boot ROM 21, and the auxiliary memory 14 normally operates (S
5) Test whether the control of the input / output board 13 from the first CPU 17 or the control of the input / output board 13 from the second CPU 20 operates normally (S6).

[0007]

When the operation control computer 7 is mounted on the mobile unit 1 and is operated by the operational program, both the first CPU 17 and the second CPU 20 are operating at the same time. Various interrupts such as direct memory access from the operating individual CPUs to the main memories 19 and 22 on the other CPU boards, interrupts between CPUs, etc., occur in conflict with each other, or data input / output occurs. The internal bus 15 operates in a state where an overload occurs. However, in the conventional computer CPU diagnosis method, two CPUs are operated independently and, for example, when the instruction function is tested, only the instruction function is tested. A test to confirm that the above-mentioned instructions operate without being affected by the above-mentioned interrupt when an interrupt that is not directly related to the execution of the above-mentioned instruction. The above test is performed without being affected by the overload of the internal bus 15 due to the confirmation test of the operation without being affected by the interrupt or the other CPU performing input / output with the device such as the radar signal processor 5. There is a problem that a confirmation test that the instruction operates cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. When a computer is detached from a moving body and diagnosed by a dedicated test device, the computer is mounted on the moving body and is close to an operating state. The purpose is to diagnose and detect failures in the state.

[0009]

According to a first aspect of the present invention, there is provided a method for diagnosing a CPU of a computer, wherein a first CPU tests an instruction function of the CPU, and a second CPU tests a data input / output function. By cross-checking both test results, diagnosis is performed by operating two CPUs simultaneously.

Further, a CPU of a computer according to the second invention
The diagnosis method notifies the timing at which the second CPU starts the data input / output test by an interrupt between CPUs from the first CPU, and notifies the second CPU of the timing at which the input / output test ends.
The test is performed while synchronizing between the two CPUs by notifying the first CPU from the CPU.

Further, a CPU of the computer according to the third invention
In the diagnosis method, the test timing of each instruction function is made variable by controlling the test interval of the instruction function performed by the first CPU by a timer interrupt.

Also, a computer CPU according to a fourth aspect of the present invention.
The diagnosis method adjusts the amount of input / output data flowing through the internal bus by selecting and specifying a channel to be tested in a data input / output test controlled by the second CPU, and makes the load state of the internal bus variable. Things.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 and 2 show a computer C according to the present invention.
FIG. 3 is a flowchart showing a PU diagnosis method, and FIG. 3 is a diagram showing a first CPU 17 and a second C when the CPU diagnosis method of the computer operates.
FIG. 4 is a timing chart showing the flow of data between the first CPU board 11, the second CPU board 12, and the input / output board 13 during operation of the computer diagnostic method of the computer. is there.

In the computer CPU diagnosis method according to the present invention, an instruction test of the CPU is performed by a program (hereinafter, referred to as a first program) operating on the first CPU board 11, and the program is executed on the second CPU board 12. A data input / output function test is performed by a program (hereinafter, referred to as a second program) that operates in the above. That is, the first
In the program of FIG. 1, the first main memory 1 is stored in advance as shown in FIG.
The timer interrupt is started using the set value of the timer interrupt generation interval time written in the specific area on the step 9; if a timer interrupt occurs, the process branches to step 8 (S8); Branching to 10 (S10), when an error interrupt such as a machine error occurs, a branch address is set to define branching to CPU board abnormality determination (S7), and the interrupt waits until an interrupt occurs. The timer interrupt occurrence interval time in the above step can be freely set by rewriting the set value of the first main memory 19 in advance. If a timer interrupt has occurred, the address space is switched to an address for performing an instruction test (S8), and then an inter-CPU interrupt is generated for the second CPU 20 as shown in FIG. Perform the test. If the result of the instruction test is normal, it waits until the next interrupt occurs. When the test result is normal and the test is performed for the preset number of times, it is determined that the CPU board is normal. Conversely, if the test result is abnormal, it is determined that the CPU board is abnormal (S9). CPU from second CPU 20
When an interrupt occurs, the second main memory 22
Read the test result of the input / output test executed by the CPU 20 and read the test result for the second CPU 20 by the second program recorded on the first main memory 19, and when the test result is normal, the following Wait until an interrupt occurs. Conversely, when the test result is abnormal, it is determined that the CPU board is abnormal (S10).
Also, when an error interrupt occurs, it is determined that the CPU board is abnormal.

In the second program, as shown in FIG.
If an inter-U interrupt occurs, branch to step 12 (S12),
When an O completion interrupt occurs, the process branches to step 13 (S13). When an error interrupt such as a machine error occurs, step 14 (S1) occurs.
A branch address is defined to define branching to 4) (S11), and an interrupt is waited until an interrupt occurs. First
When the CPU 17 interrupts from the CPU 17, the input / output board 13 is initialized, the input / output data is set using the set values in the second main memory 22, and the designated channel is started. , And waits until the next interrupt occurs (S
12). In the above step, the data area of the input / output data that the input / output board 13 performs input / output is stored in the first main memory 19.
By setting the input / output command in the second main memory 22, the first CPU board 11 and the second CPU board 1
A data flow as shown in FIG. By changing the selection information set on the second main memory 22 for selecting a channel to be tested, a channel to be subjected to an input / output test can be selected. The input / output board 13 activated by the second CPU 20
Performs input and output of external data with each device other than the operation control computer 7 through the external bus 10 as shown in FIGS.
When the input / output is completed, an I / O completion interrupt is sent to the second CPU 20. Here, by changing the selection information for selecting the channel to be tested from, for example, selection of only one channel to selection of two channels, the first CPU board 11,
Since the amount of input / output data flowing between the second CPU board 12 and the input / output board 13 can be increased, the load on the internal bus 15 can be increased. Conversely, by changing the selection information for selecting the channel to be tested from, for example, selection of three channels to selection of two channels, the first CPU board 11 and the second CP
Since the amount of input / output data flowing between the U board 12 and the input / output board 13 can be reduced, the internal bus 1
5 can be reduced. When the I / O completion interrupt has occurred, the result of the input / output test is written to the first main memory 19, and then an inter-CPU interrupt is sent to the first CPU 17 to wait until the next interrupt occurs ( S13). If an error interrupt has occurred, after writing the error information to the first main memory 19, an inter-CPU interrupt is sent to the first CPU 17 to terminate the program (S14).

Although the first CPU 17 executes the first program and the second CPU 20 executes the second program, the computer CPU diagnosis method has been described. The second program may be executed by the second CPU 20.

[0017]

As described above, according to the first invention, 2
One CPU runs the test program at the same time, and performs cross-checks by direct memory access that writes and reads each test result to and from the main memory of another CPU board. There is an advantage that a test in a form close to the operation in a mounted state can be performed, as compared with the case where the test is performed by using.

Further, according to the second aspect of the present invention, the timing of the start of the program and the end of the test are notified by an interrupt between CPUs, so that an interrupt function that cannot be tested when the test is performed by only one CPU can be performed. There is an advantage.

According to a third aspect of the present invention, the test of the instruction function is controlled by a timer interrupt capable of arbitrarily rewriting the interval time between occurrences of interrupts. Is generated and the test timing is changed, there is an advantage that a test can be performed when an interrupt unrelated to the function of the instruction occurs in conflict.

According to the fourth aspect of the present invention, since the channel to be activated at the time of the input / output function test can be set arbitrarily, the amount of input / output data flowing through the internal bus between the main memory and the input / output board can be changed. There is an advantage that a test capable of changing the load of the internal bus can be performed.

[Brief description of the drawings]

FIG. 1 is a computer CPU according to an embodiment of the present invention;
6 is a flowchart of a first program illustrating a diagnosis method.

FIG. 2 is a computer CPU according to an embodiment of the present invention;
It is a flowchart of the 2nd program which shows a diagnostic method.

FIG. 3 is a computer CPU according to an embodiment of the present invention;
5 is a timing chart illustrating a diagnosis method.

FIG. 4 is a computer CPU according to an embodiment of the present invention;
FIG. 4 is a diagram showing a flow of data between a CPU board and an input / output board at the time of diagnosis by a diagnosis method.

FIG. 5 is a diagram showing a relationship between a moving object and a control center.

FIG. 6 is a schematic diagram of an operation control computer system.

FIG. 7 is a configuration diagram of an operation control computer system.

FIG. 8 is a configuration diagram of an operation control computer to which the present invention is applied.

FIG. 9 is a flowchart showing a conventional computer CPU diagnosis method.

[Explanation of symbols]

1 mobile unit, 2 control center, 3 radar, 4 antenna, 5 radar signal processor, 6 communication control processor, 7
Operation control computer, 8 display device, 9 operation panel, 10
External bus, 11 CPU board, 12 CPU board,
13 input / output board, 14 auxiliary memory, 15 internal bus, 16 power supply, 17 CPU, 18 boot ROM, 1
9 main memory, 20 CPU, 21 boot ROM, 2
2 Main memory.

Claims (4)

[Claims] 1. A computer which has a first CPU for performing operation calculation and a second CPU for controlling input / output of data to / from another computer, and which is mounted on a mobile body and operates. ,
In the computer CPU diagnosis method of diagnosing the CPU by removing the CPU of the computer from the moving body for inspection and maintenance, the first CPU performs a test of an instruction function of the CPU and performs a test of the second CPU. CPU
A method for performing a test of a data input / output function and cross-checking test results of both CPUs by using direct memory access. 2. The timing at which the second CPU starts a data input / output function test is determined by the first CPU
The timing at which the data input / output function test is completed is designated from the second CPU to the CPU
2. The computer diagnostic method according to claim 1, wherein the notification is made by using an interval interrupt. 3. The computer according to claim 1, wherein a test interval of an instruction function executed by said first CPU is controlled by a timer interrupt so that a test timing of each instruction function is made variable. CPU diagnosis method. 4. The computer diagnostic method according to claim 1, wherein in the test of the data input / output function performed by the second CPU, a channel as an input / output test target is selected and activated. .