JP2014229208A - Multi-core system - Google Patents

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JP2014229208A
JP2014229208A JP2013110259A JP2013110259A JP2014229208A JP 2014229208 A JP2014229208 A JP 2014229208A JP 2013110259 A JP2013110259 A JP 2013110259A JP 2013110259 A JP2013110259 A JP 2013110259A JP 2014229208 A JP2014229208 A JP 2014229208A
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浩太朗 中山
Kotaro Nakayama
浩太朗 中山
小野　雅人
Masato Ono
雅人 小野
佐藤　裕
Yutaka Sato
佐藤　　裕
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Keihin Corp
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Abstract

PROBLEM TO BE SOLVED: To prevent from waiting at the time of confirmation request by a CPU for an arithmetic result of a test arithmetic processing.SOLUTION: A multi-core system includes a plurality of CPUs (Central Processing Unit), and the plurality of CPUs execute test arithmetic processing at a predetermined interval and confirm an arithmetic result of the test arithmetic processing with each other. Each of the plurality of CPUs interrupts the present processing and executes confirmation processing for the arithmetic result when receiving a confirmation request for the arithmetic result of the test arithmetic processing from another CPU, and restarts the interrupted processing after completing the confirmation processing for the arithmetic result.

Description

本発明は、マルチコアシステムに関する。   The present invention relates to a multi-core system.

下記特許文献１には、ＣＰＵを比較検査用に多重化し信頼性の向上を図った車両制御用コンピュータシステムにおいて、ノイズ等の影響による瞬間的な演算誤差を小さく抑えることで異常検出精度を向上させる演算同期方法が開示されている。第１の発明に係る演算同期方法は、各ＣＰＵに、自ＣＰＵが割り込み処理を実行中であることを他ＣＰＵに報知する手段を設け、各ＣＰＵが、特定の演算処理の開始前に、他ＣＰＵが割り込み処理を実行中でないことを確認してから該演算処理を実行するものである。また、第２の発明に係る演算同期方法は、各ＣＰＵが、特定の演算処理の開始前に、保留中の割り込み要求がないことを確認してから該演算処理を実行するものである。   In Patent Document 1 below, in a computer system for vehicle control in which CPUs are multiplexed for comparative inspection to improve reliability, abnormality detection accuracy is improved by minimizing instantaneous calculation errors due to the influence of noise and the like. An operation synchronization method is disclosed. In the arithmetic synchronization method according to the first aspect of the present invention, each CPU is provided with means for notifying other CPUs that the CPU is executing interrupt processing, and before each CPU starts the specific arithmetic processing, The arithmetic processing is executed after confirming that the CPU is not executing the interrupt processing. In the calculation synchronization method according to the second invention, each CPU executes the calculation process after confirming that there is no pending interrupt request before the start of the specific calculation process.

特開平０６−３２１０７６号公報Japanese Patent Laid-Open No. 06-321076

ところで、上記従来技術では、各ＣＰＵは、ノイズ等の影響による瞬間的な処理異常を検出するために、所定の間隔でテスト演算処理（上述した演算処理に相当）を実行し、各ＣＰＵお互いにテスト演算処理の演算結果を確認するが、演算結果を確認してもらうために他のＣＰＵに要求しても、何らかの処理を実行している場合、割り込むことができないため、処理が終了するまで待機しなければならないという問題があった。   By the way, in the above prior art, each CPU executes test arithmetic processing (corresponding to the arithmetic processing described above) at a predetermined interval in order to detect instantaneous processing abnormality due to the influence of noise or the like. Check the calculation result of the test calculation process, but even if you request another CPU to check the calculation result, if some process is being executed, you cannot interrupt and wait until the process ends There was a problem that had to be done.

本発明は、上述した事情に鑑みてなされたものであり、ＣＰＵによるテスト演算処理の演算結果の確認要求時に待機しないようにすることを目的とする。   The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to avoid waiting when a calculation result check result of a test calculation process by a CPU is requested.

上記目的を達成するために、本発明では、複数のＣＰＵ（Central Processing Unit）を具備し、前記複数のＣＰＵは、所定の間隔でテスト演算処理を実行し、お互いに前記テスト演算処理の演算結果を確認するマルチコアシステムであって、前記複数のＣＰＵ各々は、他のＣＰＵから前記テスト演算処理の演算結果の確認要求を受信すると、現在の処理を中断して演算結果の確認処理を実行し、演算結果の確認処理の完了後、中断した処理を再開する、という手段を採用する。   In order to achieve the above object, in the present invention, a plurality of CPUs (Central Processing Units) are provided, and the plurality of CPUs execute a test operation process at a predetermined interval, and result from each other in the test operation process. Each of the plurality of CPUs, when receiving a confirmation request for the test result of the test computation process from another CPU, interrupts the current process and executes a confirmation process of the computation result, A method of restarting the interrupted process after completion of the calculation result confirmation process is adopted.

本発明では、第２の解決手段として、上記第１の解決手段において、前記演算結果の期待値が予め記憶されたデータ記憶部をさらに具備し、前記ＣＰＵ各々は、前記テスト演算処理を実行し、該テスト演算処理の演算結果を前記データ記憶部に記憶させると共に、演算結果の確認要求を送信し、前記演算結果の確認要求を受信したＣＰＵは、前記データ記憶部に記憶される前記テスト演算処理の演算結果と、演算結果の期待値とを比較することによって演算結果を確認する、という手段を採用する。   According to the present invention, as the second solving means, in the first solving means, the data processing unit further stores an expected value of the calculation result in advance, and each of the CPUs executes the test calculation processing. The CPU stores the calculation result of the test calculation process in the data storage unit, transmits the calculation result confirmation request, and receives the calculation result confirmation request, the CPU calculates the test calculation stored in the data storage unit. A means is adopted in which the calculation result is confirmed by comparing the calculation result of the process with the expected value of the calculation result.

本発明によれば、ＣＰＵ各々は、他のＣＰＵからテスト演算処理の演算結果の確認要求を受信すると、現在の処理を中断して演算結果の確認処理を実行し、演算結果の確認処理の完了後、中断した処理を再開するので、テスト演算処理の演算結果の確認要求を送信したＣＰＵは待機する必要がない。   According to the present invention, when each CPU receives a calculation result confirmation request for a test computation process from another CPU, the CPU interrupts the current process and executes the computation result confirmation process, thereby completing the computation result confirmation process. Thereafter, since the interrupted process is resumed, the CPU that has transmitted the request for confirming the calculation result of the test calculation process does not need to wait.

本発明の一実施形態に係るマルチコアシステムＡの概略構成図である。It is a schematic block diagram of the multi-core system A which concerns on one Embodiment of this invention. 本発明の一実施形態に係るマルチコアシステムＡの動作を示すタイミングチャートである。It is a timing chart which shows operation | movement of the multi-core system A which concerns on one Embodiment of this invention.

以下、図面を参照して、本発明の実施形態について説明する。
本実施形態に係るマルチコアシステムＡは、電気自動車（ＥＶ：Electric Vehicle）あるいはハイブリッド自動車（ＨＶ：Hybrid Vehicle）等の移動車両に搭載され、
共に移動車両に搭載されている周辺機器Ｄ１〜Ｄｎを制御するものであり、図１に示すように、第１演算制御部Ｅ１、第２演算制御部Ｅ２及び通信バスＢを備える。 Embodiments of the present invention will be described below with reference to the drawings.
The multi-core system A according to the present embodiment is mounted on a moving vehicle such as an electric vehicle (EV: Electric Vehicle) or a hybrid vehicle (HV: Hybrid Vehicle),
Both control peripheral devices D1 to Dn mounted on the moving vehicle, and include a first calculation control unit E1, a second calculation control unit E2, and a communication bus B as shown in FIG.

第１演算制御部Ｅ１は、図１に示すように、第１ＲＯＭ（Read Only Memory）１１、第１ＲＡＭ（Random Access Memory）１２及び第１ＣＰＵ（Central Processing Unit）１３を備えている。なお、第１ＲＯＭ１１及び第１ＲＡＭ１２は、本実施形態におけるデータ記憶部である。   As shown in FIG. 1, the first arithmetic control unit E1 includes a first ROM (Read Only Memory) 11, a first RAM (Random Access Memory) 12, and a first CPU (Central Processing Unit) 13. The first ROM 11 and the first RAM 12 are data storage units in the present embodiment.

第１ＲＯＭ１１は、第１ＣＰＵ１３で実行される各種演算制御プログラム及びその他データを記憶する不揮発性メモリである。
第１ＲＡＭ１２は、第１ＣＰＵ１３が演算制御プログラムを実行して各種動作を行う際に、データの一時保存先となるワーキングエリアとして用いられる揮発性メモリである。 The first ROM 11 is a non-volatile memory that stores various arithmetic control programs executed by the first CPU 13 and other data.
The first RAM 12 is a volatile memory that is used as a working area that is a temporary storage destination of data when the first CPU 13 executes a calculation control program and performs various operations.

第１ＣＰＵ１３は、第１ＲＯＭ１１及び第１ＲＡＭ１２と電気的に接続されると共に、周辺機器Ｄ１〜Ｄｎと通信バスＢを介して電気的に接続され、上記第１ＲＯＭ１１に記憶された各種演算制御プログラムに基づいて各種の演算処理を行うと共に各部と通信を行うことにより周辺機器Ｄ１〜Ｄｎの動作を制御する。詳細については後述するが、第１ＣＰＵ１３は、所定の間隔でテスト演算処理を実行し、後述する第２演算制御部Ｅ２の第２ＣＰＵ２３とお互いにテスト演算処理の演算結果を確認する。なお、テスト演算処理とは、ノイズ等の影響による瞬間的な処理異常を検出するために、所定の間隔で第１ＣＰＵ１３や第２ＣＰＵ２３によって実行される処理である。   The first CPU 13 is electrically connected to the first ROM 11 and the first RAM 12, and is electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is based on various arithmetic control programs stored in the first ROM 11. The operation of the peripheral devices D1 to Dn is controlled by performing various arithmetic processes and communicating with each unit. Although details will be described later, the first CPU 13 executes test calculation processing at predetermined intervals, and mutually confirms the calculation result of the test calculation processing with a second CPU 23 of the second calculation control unit E2 described later. The test calculation process is a process executed by the first CPU 13 or the second CPU 23 at a predetermined interval in order to detect an instantaneous process abnormality due to the influence of noise or the like.

第２演算制御部Ｅ２は、図１に示すように、第２ＲＯＭ２１、第２ＲＡＭ２２及び第２ＣＰＵ２３を備えている。なお、第２ＲＯＭ２１及び第２ＲＡＭ２２は、本実施形態におけるデータ記憶部である。   As shown in FIG. 1, the second arithmetic control unit E <b> 2 includes a second ROM 21, a second RAM 22, and a second CPU 23. The second ROM 21 and the second RAM 22 are data storage units in the present embodiment.

第２ＲＯＭ２１は、第２ＣＰＵ２３で実行される各種演算制御プログラム及びその他データを記憶する不揮発性メモリである。
第２ＲＡＭ２２は、第２ＣＰＵ２３が制御プログラムを実行して各種動作を行う際に、データの一時保存先となるワーキングエリアとして用いられる揮発性メモリである。 The second ROM 21 is a non-volatile memory that stores various arithmetic control programs executed by the second CPU 23 and other data.
The second RAM 22 is a volatile memory used as a working area that is a temporary storage destination of data when the second CPU 23 executes a control program and performs various operations.

第２ＣＰＵ２３は、第２ＲＯＭ２１及び第２ＲＡＭ２２と電気的に接続されると共に、周辺機器Ｄ１〜Ｄｎと通信バスＢを介して電気的に接続され、上記第２ＲＯＭ２１に記憶された各種演算制御プログラムに基づいて各種の演算処理を行うと共に各部と通信を行うことにより周辺機器Ｄ１〜Ｄｎの動作を制御する。詳細については後述するが、第２ＣＰＵ２３は、所定の間隔でテスト演算処理を実行し、第１ＣＰＵ１３とお互いにテスト演算処理の演算結果を確認する。   The second CPU 23 is electrically connected to the second ROM 21 and the second RAM 22 and is electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is based on various arithmetic control programs stored in the second ROM 21. The operation of the peripheral devices D1 to Dn is controlled by performing various arithmetic processes and communicating with each unit. Although the details will be described later, the second CPU 23 executes test calculation processing at a predetermined interval, and mutually confirms the calculation result of the test calculation processing with the first CPU 13.

通信バスＢは、第１ＣＰＵ１３、第２ＣＰＵ２３及び周辺機器Ｄ１〜Ｄｎを電気的に相互接続するための通信線である。第１ＣＰＵ１３、第２ＣＰＵ２３及び周辺機器Ｄ１〜Ｄｎは、通信バスＢを介してデータを送受信する。   The communication bus B is a communication line for electrically connecting the first CPU 13, the second CPU 23 and the peripheral devices D1 to Dn. The first CPU 13, the second CPU 23, and the peripheral devices D 1 to Dn transmit and receive data via the communication bus B.

一方、周辺機器Ｄ１〜Ｄｎは、移動車両に搭載されている走行モータ、発電機及び昇圧回路等を制御するためのコントローラ等であり、通信バスＢを介して第１ＣＰＵ１３や第２ＣＰＵ２３とデータを送受信する。また、各周辺機器Ｄ１〜Ｄｎは、第１ＣＰＵ１３や第２ＣＰＵ２３による書き込み及び読み取りの可否が予め設定されている。例えば、図１には、周辺機器Ｄ１に、「ＣＰＵ１３：Ｒ/Ｗ」「ＣＰＵ２３：Ｒ/―」と記載されている。これは、第１ＣＰＵ１３は、周辺機器Ｄ１に対してデータの書き込み及び読み取りが可能であり、一方、第２ＣＰＵ２３は、周辺機器Ｄ１に対してデータの書き込みが不可であり、読み取りのみが可能であることを示している。   On the other hand, the peripheral devices D1 to Dn are controllers for controlling a travel motor, a generator, a booster circuit, and the like mounted on the moving vehicle, and transmit / receive data to / from the first CPU 13 and the second CPU 23 via the communication bus B. To do. In each peripheral device D1 to Dn, whether or not writing and reading by the first CPU 13 and the second CPU 23 is set in advance. For example, in FIG. 1, “CPU13: R / W” and “CPU23: R / −” are described in the peripheral device D1. This is because the first CPU 13 can write and read data to the peripheral device D1, while the second CPU 23 cannot write data to the peripheral device D1 and can only read it. Is shown.

次に、このように構成されたマルチコアシステムＡの動作について図２を参照して説明する。
例えば、第１ＣＰＵ１３は、テスト演算処理を実行し、該テスト演算処理を完了すると、図２に示すように、テスト演算処理の演算結果の確認要求を通信バスＢを介して第２ＣＰＵ２３に送信する。また、第１ＣＰＵ１３は、同時に、テスト演算処理の演算結果を、第２ＲＡＭ２２に書き込む。 Next, the operation of the multi-core system A configured as described above will be described with reference to FIG.
For example, the first CPU 13 executes the test calculation process, and when the test calculation process is completed, the first CPU 13 transmits a confirmation request for the calculation result of the test calculation process to the second CPU 23 via the communication bus B as shown in FIG. At the same time, the first CPU 13 writes the calculation result of the test calculation process in the second RAM 22.

一方、第２ＣＰＵ２３は、第１ＣＰＵ１３からテスト演算処理の演算結果の確認要求を受信すると、現在の処理を中断して演算結果の確認処理を実行し、確認結果を通信バスＢを介して第１ＣＰＵ１３に送信する。そして、第２ＣＰＵ２３は、演算結果の確認処理の完了後、中断した処理を再開する。   On the other hand, when the second CPU 23 receives the confirmation request for the calculation result of the test calculation process from the first CPU 13, the second CPU 23 interrupts the current process and executes the check process of the calculation result, and sends the check result to the first CPU 13 via the communication bus B. Send. Then, the second CPU 23 resumes the interrupted process after the calculation result confirmation process is completed.

例えば、第２ＣＰＵ２３も、図２に示すように、テスト演算処理を実行している場合には、テスト演算処理を中断して、演算結果の確認処理を実行し、確認処理によって得た確認結果を第１ＣＰＵ１３に送信し、その後、中断したテスト演算処理を再開する。   For example, as shown in FIG. 2, when the second CPU 23 is also executing the test calculation process, the test calculation process is interrupted, the calculation result confirmation process is performed, and the confirmation result obtained by the confirmation process is displayed. Then, the interrupted test computation process is resumed.

ここで、第２ＣＰＵ２３は、第２ＲＯＭ２１に予め記憶される演算結果の期待値と、第２ＲＡＭ２２に記憶されるテスト演算処理の演算結果とを比較することによって、演算結果を確認する。つまり、第２ＣＰＵ２３は、演算結果の期待値と、テスト演算処理の演算結果とが異なる場合には、演算結果に問題があると判断し、同じである場合には、演算結果に問題がないと判断する。   Here, the second CPU 23 confirms the calculation result by comparing the expected value of the calculation result stored in advance in the second ROM 21 with the calculation result of the test calculation process stored in the second RAM 22. That is, the second CPU 23 determines that there is a problem with the calculation result when the expected value of the calculation result is different from the calculation result of the test calculation process, and there is no problem with the calculation result when they are the same. to decide.

図２に戻り、第２ＣＰＵ２３は、中断したテスト演算処理を再開し、該テスト演算処理を完了すると、テスト演算処理の演算結果の確認要求を通信バスＢを介して第１ＣＰＵ１３に送信する。また、第２ＣＰＵ２３は、同時に、テスト演算処理の演算結果を、第１ＲＡＭ１２に書き込む。   Returning to FIG. 2, the second CPU 23 resumes the interrupted test calculation process, and when the test calculation process is completed, transmits a request for confirming the calculation result of the test calculation process to the first CPU 13 via the communication bus B. At the same time, the second CPU 23 writes the calculation result of the test calculation process in the first RAM 12.

一方、第１ＣＰＵ１３は、第２ＣＰＵ２３からテスト演算処理の演算結果の確認要求を受信すると、現在の処理を中断して演算結果の確認処理を実行し、演算結果の確認処理の完了後、中断した処理を再開する。   On the other hand, when the first CPU 13 receives the calculation result confirmation request of the test computation process from the second CPU 23, the first CPU 13 interrupts the current process and executes the computation result confirmation process. To resume.

ここで、第１ＣＰＵ１３は、第１ＲＯＭ１１に予め記憶される演算結果の期待値と、第１ＲＡＭ１２に記憶されるテスト演算処理の演算結果とを比較することによって、演算結果を確認する。つまり、第１ＣＰＵ１３は、演算結果の期待値と、テスト演算処理の演算結果とが異なる場合には、演算結果に問題があると判断し、同じである場合には、演算結果に問題がないと判断する。   Here, the first CPU 13 confirms the calculation result by comparing the expected value of the calculation result stored in advance in the first ROM 11 with the calculation result of the test calculation process stored in the first RAM 12. That is, the first CPU 13 determines that there is a problem with the calculation result when the expected value of the calculation result is different from the calculation result of the test calculation process, and there is no problem with the calculation result when they are the same. to decide.

このような本実施形態によれば、第１ＣＰＵ１３及び第２ＣＰＵ２３各々は、他のＣＰＵからテスト演算処理の演算結果の確認要求を受信すると、現在の処理を中断して演算結果の確認処理を実行し、演算結果の確認処理の完了後、中断した処理を再開するので、テスト演算処理の演算結果の確認要求を送信したＣＰＵは待機する必要がない。   According to this embodiment, when each of the first CPU 13 and the second CPU 23 receives an operation result confirmation request from the other CPU, it interrupts the current process and executes the operation result confirmation process. Since the interrupted process is resumed after the completion of the computation result confirmation process, the CPU that has transmitted the computation result confirmation request for the test computation process does not need to wait.

以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されることなく、例えば以下のような変形が考えられる。
（１）上記実施形態は、２つの第１ＣＰＵ１３及び第２ＣＰＵ２３を備えたものであるが、２つに限定されず、２つ以上であってもよい。
（２）上記実施形態は、移動車両に搭載されているが、移動車両以外に、家電製品等の電子機器に搭載されていてもよい。 As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, For example, the following modifications can be considered.
(1) Although the said embodiment is provided with two 1st CPU13 and 2nd CPU23, it is not limited to two, Two or more may be sufficient.
(2) Although the said embodiment is mounted in the moving vehicle, you may mount in electronic devices, such as household appliances, other than a moving vehicle.

Ａ…マルチコアシステム、Ｄ１〜Ｄｎ…周辺機器、Ｅ１…第１演算制御部、Ｅ２…第２演算制御部、Ｂ…通信バス、１１…第１ＲＯＭ（データ記憶部）、１２…第１ＲＡＭ（データ記憶部）、１３…第１ＣＰＵ、２１…第２のＲＯＭ（データ記憶部）、２２…第２ＲＡＭ（データ記憶部）、２３…第２ＣＰＵ   A ... multi-core system, D1-Dn ... peripheral devices, E1 ... first calculation control unit, E2 ... second calculation control unit, B ... communication bus, 11 ... first ROM (data storage unit), 12 ... first RAM (data storage) Part), 13 ... 1st CPU, 21 ... 2nd ROM (data storage part), 22 ... 2nd RAM (data storage part), 23 ... 2nd CPU

Claims (2)

複数のＣＰＵ（Central Processing Unit）を具備し、
前記複数のＣＰＵは、所定の間隔でテスト演算処理を実行し、お互いに前記テスト演算処理の演算結果を確認するマルチコアシステムであって、
前記複数のＣＰＵ各々は、他のＣＰＵから前記テスト演算処理の演算結果の確認要求を受信すると、現在の処理を中断して演算結果の確認処理を実行し、演算結果の確認処理の完了後、中断した処理を再開することを特徴とするマルチコアシステム。 A plurality of CPUs (Central Processing Units)
The plurality of CPUs is a multi-core system that executes a test calculation process at a predetermined interval and confirms a calculation result of the test calculation process with each other,
When each of the plurality of CPUs receives a calculation result confirmation request for the test calculation process from another CPU, the current process is interrupted and the calculation result confirmation process is performed. After completion of the calculation result confirmation process, A multi-core system characterized by resuming suspended processing. 前記演算結果の期待値が予め記憶されたデータ記憶部をさらに具備し、
前記ＣＰＵ各々は、前記テスト演算処理を実行し、該テスト演算処理の演算結果を前記データ記憶部に記憶させると共に、演算結果の確認要求を送信し、
前記演算結果の確認要求を受信したＣＰＵは、前記データ記憶部に記憶される前記テスト演算処理の演算結果と、演算結果の期待値とを比較することによって演算結果を確認することを特徴とする請求項１に記載のマルチコアシステム。 A data storage unit in which the expected value of the operation result is stored in advance;
Each of the CPUs executes the test calculation process, stores the calculation result of the test calculation process in the data storage unit, and transmits a check request for the calculation result.
The CPU that has received the calculation result confirmation request confirms the calculation result by comparing the calculation result of the test calculation processing stored in the data storage unit with an expected value of the calculation result. The multi-core system according to claim 1.
JP2013110259A 2013-05-24 2013-05-24 Multi-core system Pending JP2014229208A (en)

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Citations (4)

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JPH10207735A (en) * 1997-01-22 1998-08-07 Mitsubishi Electric Corp Cpu diagnostic method for computer
WO2008062511A1 (en) * 2006-11-21 2008-05-29 Fujitsu Limited Multiprocessor system
JP2012160033A (en) * 2011-02-01 2012-08-23 Keihin Corp Electronic controller for moving object

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119451A (en) * 1982-12-27 1984-07-10 Panafacom Ltd Diagnosing system of electronic computer system
JPH10207735A (en) * 1997-01-22 1998-08-07 Mitsubishi Electric Corp Cpu diagnostic method for computer
WO2008062511A1 (en) * 2006-11-21 2008-05-29 Fujitsu Limited Multiprocessor system
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