JPH10200086A - Solid state pickup device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in a charge read-out efficiency, afterimage characteristic and light shielding property in a solid state pickup device. SOLUTION: This device has a charge read-out electrode 110 formed on a P well formed on the surface of a silicon substrate 101 through a gate insulating film 106. The edge of the charge read-out electrode 110 is tapered only by an isotropic plasma dry etching process and a patterning process. By implanting ions into a region just under the charge read-out electrode 110 through the tapered part of the electrode 110, the region has a concentration gradient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A solid-state image pickup device accumulates information input such as incident light in the form of electric charges, sequentially transfers the electric charges by a large number of transfer electrodes, and extracts the electric signals as electric signals. Widely used for etc.

FIG. 5 is a plan view of a line sensor as an example of a conventional solid-state imaging device, and FIG. 6 is a sectional view taken along line XX of FIG. In this conventional example, a first region selectively formed on the surface of a P-type region (P well 202) on the surface of a silicon substrate is formed.
Including a first N-type region 205 and a first N-type region 205.
A buried channel 203 for charge transfer, which is a second N-type region selectively formed on the surface of the P-well 202 at a predetermined distance from the mold region 205, and provided on the surface of the silicon substrate and the buried channel 203; A CCD register including a first transfer electrode 208-1 intersecting via a gate oxide film 206; and a gate connected to the first charge transfer electrode 208-1 and extending from the above-described predetermined interval to the first N-type region 205. A charge readout electrode 210 for selectively covering oxide film 206 and an opening on first n-type region 205 with interlayer insulating film 211 interposed therebetween, the first n-type from the edge of charge readout electrode 210 Area 2
And a light-shielding film 212 covering a part of the upper part of the light-transmitting part 05.

Next, a description will be given of a manufacturing method of this conventional example. First, as shown in FIG. 8A, after a P well 202 is formed on the surface of an N-type silicon substrate 201, an N-type region (buried channel 203) of a charge transfer portion (hereinafter referred to as a CCD portion) and a P ⁺ -type A channel stopper 204, a gate oxide film 206, and a first charge transfer electrode 208-1, which is a first-layer polysilicon film, are formed.
A barrier layer is formed by implanting boron into the buried channel 203 which is not covered with 8-1, and a second charge transfer electrode 208-2 and a charge readout electrode 210, which are the second polysilicon film, are formed.

Next, as shown in FIG. 8B, as a countermeasure against dark current, an acceleration voltage of 50 is applied to the surface of the N-type region 205.
A P-type impurity is ion-implanted at a low energy of about keV using the resist film 215 as a mask, and an ion implantation region 207 is formed.
After forming a, the resist film 215 is removed,
The annealing process is performed to the extent that the P-type region 2 shown in FIG.
07 is formed. Here, the P-type region 207 is also formed below the charge transfer electrode 208-1 by thermal diffusion during the annealing process. Finally, as shown in FIG. 8D, an interlayer insulating film 211, a light shielding film 212 made of an aluminum film, and the like are formed.

[0006]

The first problem is that, in the conventional solid-state imaging device, since the impurity in the P-type region 207 on the surface of the photodiode immediately below the charge readout electrode 210 is dense, the potential well just below the charge readout electrode 210 is high. W is formed, and only some of the charges Q2 = Q-Q1 are read. Due to this, the conventional solid-state imaging device has a drawback that the readout efficiency and the afterimage characteristics are reduced.

The second problem is that the edge side surface of the charge readout electrode has a shape perpendicular to the semiconductor substrate.
The step coverage is large and the step coverage of the aluminum film of the light-shielding film 212 is deteriorated, so that the film thickness is locally reduced as shown in FIG. .

A first object of the present invention is to provide a fixed imaging device with improved readout efficiency and a method of manufacturing the same. A second object of the present invention is to provide a solid-state imaging device with improved light-shielding properties and a method of manufacturing the same.

[0009]

According to the present invention, there is provided a solid-state imaging device comprising: a first N-type region selectively formed on a surface portion of a P-type region on a surface portion of a semiconductor substrate; A photodiode including a P-type region selectively formed on the surface of the P-type region; and a second N-type selectively formed on the surface of the P-type region at a predetermined distance from the first N-type region. A buried channel for charge transfer comprising a mold region and a register including a charge transfer electrode intersecting therewith via a gate insulating film provided on the surface of the semiconductor substrate; and A charge readout electrode that selectively covers the gate insulating film over the first N-type region, and an edge of the charge readout electrode having an opening on the first N-type region via an interlayer insulating film Shielding part of the first N-type region from above. In the solid-state imaging device having a film, during a period in which electric charges are accumulated in the photodiode, a potential minimum surface at which a potential with respect to electrons in a depth direction from an arbitrary point on the surface of the first N-type region is minimized. The P-type impurity concentration on the surface of the first N-type region has a gradient that decreases below the charge readout electrode toward the second N-type region. By doing so, it becomes possible to make the potential well that reduces the readout efficiency shallow. Here, the thickness of the conductive film constituting the charge readout electrode may be increased as the distance from the end on the first N-type region increases. Then, a step in a region where the light shielding portion is formed is reduced.

According to the method of manufacturing a solid-state imaging device of the present invention, the surface of a semiconductor substrate having a P-type region on the surface is selectively N-type.
Forming a buried channel to be a second N-type region by introducing a N-type impurity, and then selectively introducing an N-type impurity to a surface portion of a semiconductor substrate having a P-type region to form a first N-type impurity; Forming a photodiode serving as a region, forming a gate insulating film on the surface, depositing a conductive film, performing anisotropic etching, and forming a charge readout electrode having a tapered peripheral region whose thickness decreases toward an end; Forming and forming P on the surface of the first N-type region.
Forming a P-type region having a gradient whose thickness decreases toward the second N-type region by ion-implanting using the tapered peripheral region when selectively forming the mold region; It is to have. Here, a step of depositing an interlayer insulating film after forming the N-type region of the photodiode and forming a light-shielding film covering a part of the N-type region from the insulating portion of the charge readout electrode can be added. .

[0011]

FIG. 1 is a plan view showing an embodiment of a solid-state imaging device according to the present invention, and FIG. 2 is a sectional view taken along line XX of FIG. In this embodiment, the first N-type region 105 selectively formed on the surface of the P-type region (P-well 102) on the surface of the N-type silicon substrate 101 and the surface of the first N-type region are formed. It has a photodiode including the P-type region 107 formed. Also, a buried channel 1 for charge transfer comprising a second N-type region selectively formed on the surface of the P-well 102 at a predetermined distance from the first N-type region 105.
03 and the first charge transfer electrode 10 intersecting therewith via a gate oxide film 106 provided on the surface of the silicon substrate.
8-1. Further, the charge readout electrode 11 which is coupled to the first charge transfer electrode 108-1 and selectively covers the gate oxide film 106 from the above-mentioned predetermined interval (readout region 102a) to the first N-type region 105
0 and the first N-type region 105 via the interlayer insulating film 111.
A light-shielding film 11 having an opening above and covering a part of the first N-type region 105 from the edge of the charge readout electrode 110
2 Then, during a period in which electric charges are accumulated in the photodiode, the potential of the first N-type region 105 on the surface of the first N-type region 105 at a potential minimum surface where the potential for electrons in the depth direction is minimized from any point on the surface of the first N-type region 105 A feature is that the P-type impurity concentration forming the P-type region 107 has a gradient that decreases below the charge readout electrode 110 toward the buried channel 103 that is the second N-type region.

Next, an embodiment of a method of manufacturing a solid-state imaging device according to the present invention will be described. First, as shown in FIG. 4A, a P-well 102 is formed on the surface of an N-type silicon substrate 101, and a buried channel 103 (second N-type region) is formed on the surface of the P-well 102. A P ⁺ type channel stopper 104 is formed, and the first
Is formed, and a gate oxide film 106 having a thickness of 80 nm is formed. Next, a second polysilicon film having a thickness of about 500 nm is deposited, and is patterned using the resist film 113 as a mask, thereby forming the buried channel 10.
A first charge transfer electrode 108-1 intersecting with No. 3 is formed. Next, boron ions for forming a barrier layer are implanted into a buried channel that is not covered with the first charge transfer electrode 108-1, and the gate oxide film 106 is formed using the first charge transfer electrode 108-1 as a mask. After removal, thermal oxidation is performed to form a gate oxide film 109. Next, a thickness of about 500 nm
A second polysilicon film is deposited, and a resist film 113 is formed.
The second charge readout electrode (108-2 in FIG. 1) and the charge readout electrode 11 are patterned by using
0 is formed. This patterning, by isotropic plasma etching using a gas such as SF _6. The edges of these electrodes are tapered at about 45 °.

Next, using the resist film 115 as a mask,
Boron ions are implanted at an acceleration voltage of about 50 to 100 keV. This is to reduce the dark current of the photodiode. The resist film 115 has a shape that exposes an upper part of the first N-type region 105 among the tapered edges of the charge readout electrode 110. Then, the charge readout electrode 1
It is possible to form the P-type region 107 in which the P-type region immediately below the edge of the P-type region 10 is shallow. Next, the resist film 11
5 is removed, and an annealing process at about 900 ° C. is performed. Next, as shown in FIG. 4C, FIG. 1 and FIG.
Forming an interlayer insulating film 111 made of a 2 μm BPSG film;
By depositing and patterning an aluminum film, clock pulses φ1 and φ2 are applied to the light shielding film 112 and the transfer electrode.
Is formed to supply the electrodes. Next, a cover film (not shown) is formed to cover the CCD register section.
Is formed.

Since the edge of the charge readout electrode 110 is tapered, the step coverage of the aluminum film is improved, the uniformity of the light-shielding film 112 is good, and no disconnection occurs.

FIG. 3 is a potential diagram of a transfer region (a potential minimum surface schematically shown by a two-dot chain line in FIG. 2) in one embodiment of the solid-state imaging device of the present invention. The potential に お け る during the period of accumulating charges in the photodiode (when 0 volt is applied to the charge readout electrode 110, φ1 is 5 volts, and φ2 is 0 volt) is shown in FIG.
It is shown as follows. The minimum potential surface of the first N-type region 105 is such that the P-type region 107 formed on the surface of the first N-type region is shallower toward the charge readout region 102a. P formed on the surface of the first N-type region
Since the mold region 107 is inclined below the charge readout electrode,
The N-type impurity concentration near the surface immediately below the charge readout electrode is lower than in the conventional example, and the potential well as in the conventional example becomes shallower.

Next, when a voltage of 5 volts is applied to the charge readout electrode 110, the charge Q stored in the first N-type region 105 is read out to the buried channel 103 except for a part Q1a. Since the potential well is shallow, Q1a is smaller than Q1 of the conventional example. The read charge amount Q2a = Q-Q1a is larger than Q2 (improvement in readout efficiency). As a result, the afterimage, which was conventionally about 80 mV in output voltage, could be reduced to at least half.

As described above, the edge of the charge transfer electrode is tapered by performing isotropic dry etching, and the ion implantation using the tapered edge is used to improve the readout efficiency and the readout efficiency. The light-shielding property could be improved.

Although a line sensor has been described as an example, it will be apparent that the present invention can be applied to a two-dimensional sensor without further detailed explanation.

[0019]

The first effect is that, in the solid-state imaging device of the present invention, a charge readout electrode having a tapered edge is formed using isotropic etching, and the charge readout electrode corresponding to the tapered edge is formed. By forming the P-type region of the impurity concentration distribution as a countermeasure against dark current of the photodiode by using ion implantation, the depth of the P-type region from an arbitrary point on the surface of the N-type region of the photodiode below the charge readout electrode is reduced. The potential well in the N-type region of the photodiode can be made shallow because the N-type impurity concentration on the potential minimum surface where the potential for electrons in the direction becomes minimal can be reduced toward the charge readout electrode. Thus, the charge readout efficiency can be improved and the afterimage can be reduced.

The second effect is that, since the edge of the charge readout electrode is tapered, a light-shielding film covering this insulating film can be formed with good step coverage via an interlayer insulating film, so that the light-shielding property is improved. Step breakage can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a sectional view taken along line XX of FIG.

FIG. 3 is a potential diagram (FIG. 3A) during a charge accumulation period and a potential diagram at the time of charge transfer reading (FIG. 3B) for describing a charge reading operation in one embodiment of the solid-state imaging device of the present invention. )).

FIGS. 4A to 4C are cross-sectional views illustrating a manufacturing process of the solid-state imaging device of the present invention.

FIG. 5 is a plan view illustrating an example of a conventional solid-state imaging device.

FIG. 6 is a sectional view taken along line XX of FIG. 5;

7A and 7B are a potential diagram (FIG. 7A) during a charge accumulation period and a potential diagram at the time of charge reading (FIG. 7B) for describing a charge reading operation in an example of a conventional solid-state imaging device.

FIGS. 8A to 8D are cross-sectional views illustrating a manufacturing process of a conventional solid-state imaging device.

[Explanation of symbols]

101, 201 N-type silicon substrate 102a, 202a, 3 Charge readout region 102, 202 P well 103, 203 Buried channel 104, 204 P ⁺ type channel stopper 105, 205 First N-type region 106, 206 Gate insulating film 107, 207 P-type region 108-1, 208-1 First charge transfer electrode 108-2, 208-2 Second charge transfer electrode 109, 209 Gate insulating film 110, 210 Charge readout electrode 111, 211 Interlayer insulating film 112, 212 light shielding film 113 resist film 114 resist film 115,215 resist film 116,216 potential minimum surface

Claims (4)

[Claims] A first N-type region selectively formed on a surface portion of a P-type region on a surface portion of the semiconductor substrate;
A photodiode including a P-type region selectively formed on the surface of the P-type region; and a second photodiode selectively formed on the surface of the P-type region at a predetermined distance from the first N-type region. A buried channel for charge transfer comprising an N-type region and a register including a charge transfer electrode intersecting therewith via a gate insulating film provided on the surface of the semiconductor substrate; A charge readout electrode for selectively covering the gate insulating film from a portion to the first N-type region; and an opening on the first N-type region through an interlayer insulating film, the charge readout electrode having a hole. The first N from the edge
A solid-state imaging device having a light-shielding film that covers a part of the upper part of the type region, wherein a charge is accumulated in the photodiode in a depth direction from an arbitrary point on the surface of the first N-type region. The P-type impurity concentration on the surface of the first N-type region on the potential minimum surface where the potential for electrons is minimized is lower than the charge read-out electrode.
A solid-state imaging device having a gradient that decreases toward the N-type region. 2. The solid-state imaging device according to claim 1, wherein the thickness of the conductive film forming the charge readout electrode increases as the distance from the end on the first N-type region increases. 3. A buried channel serving as a second N-type region is formed by selectively introducing an N-type impurity into a surface portion of a semiconductor substrate having a P-type region on a surface portion. An N-type impurity is selectively introduced into a surface portion of a semiconductor substrate having a GaN layer, a photodiode serving as a first N-type region is formed, a gate insulating film is formed on the surface, a conductive film is deposited, and anisotropic etching is performed. Forming a charge readout electrode having a tapered peripheral region whose thickness decreases toward an end portion, and selectively forming a P-type region on the surface of the first N-type region. Forming a P-type region having a gradient that decreases in thickness near the second N-type region by ion-implanting using the tapered peripheral region. Method. 4. A step of forming an N-type region of the photodiode, depositing an interlayer insulating film, and forming a light-shielding film covering a part of the N-type region from the edge of the charge readout electrode to the N-type region. Item 4. A method for manufacturing a solid-state imaging device according to Item 3.