JPH10200014A - Ceramic multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the wiring capacitance of a ceramic multilayer wiring board, without lowering the insulation between the through-holes and signal lines. SOLUTION: The wiring board uses a ceramic material formed into a multilayer board and has a laminate structure composed of power source layers, ground layers and wiring layers. Each wiring layer has a wiring pattern involving signal lines each running the shortest path between two through-holes to be connected. The wiring pattern of the wiring layer for connecting the through- holes arranged in the diagonal directions (at 45 deg. to axis X) of e.g. an orthogonal grid includes signal lines 106 running in the diagonal directions of this grid. The signal lines 106 are laid to route the shortest path along regions defined by the proximity limit lines set round the through-holes 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a ceramic multilayer wiring board mainly used for mounting an LSI chip.

[0002]

2. Description of the Related Art Conventionally, ceramic multilayer wiring boards have been used exclusively as small substrates in IC packages. However, attention has been paid to their features such as high thermal conductivity suitable for high-density mounting. As a result, it has come to be used frequently as a substrate for mounting an LSI chip, particularly a large substrate for mounting a CPU of a super-large computer. The ceramic multilayer wiring board is formed by performing conductor printing and multilayering at the stage of a green sheet before firing alumina, and thereafter firing alumina and the conductor wiring integrally. It is known that the performance is greatly improved depending on the firing conditions and other processing conditions.
For example, Japanese Patent Publication No. 2-49550 discloses that processing conditions (conductor material, composition of a slurry for forming a green sheet, firing conditions after multilayering) useful for manufacturing a ceramic multilayer wiring board with higher reliability. Is disclosed.

Attempts have also been made to increase the mounting density by using a thin film technique in combination with this. For example, NIKKEI
MICRODEVICE, June 1989 (p50), describes a fine wiring pattern (wiring width 20 μm,
A technique for forming a wiring thickness of about 5 μm) is described.

[0004]

The wiring layout of the conventional multilayer ceramic wiring board has two directions orthogonal to each other.
(X direction, Y direction) is selected in principle. Therefore, depending on the arrangement of the devices on the ceramic multilayer wiring board, the signal lines may have to be extended. For example, in accordance with this principle (hereinafter referred to as a wiring layout rule), when connecting two devices arranged on a diagonal line of a ceramic multilayer wiring board, at least about 少 な く と も 2 times the actual device interval is required. A signal line is required.

The extension of the signal line due to the restriction on the wiring layout design, together with the extension of the signal line accompanying the increase in the scale of integration, affects the performance of the electronic device (as the signal transmission delay increases remarkably). ) To increase the wiring capacitance. For example, even a ceramic multilayer wiring board formed of copper having a small electric resistance and glass ceramic having a low dielectric constant (relative dielectric constant of 5.2) has a length of 140 m.
When 25 LSI chips are mounted in a mounting area of m × 140 mm in a 5 × 5 array, the signal transmission delay time from the LSI chip in the first row and the first column to the LSI chip in the fifth row and the fifth column located farthest ( Maximum signal transmission delay time)
It is known to reach 2.13 ns.

Therefore, in accordance with the wiring layout rules of the multilayer printed wiring board, the signal lines are not only in the X direction and the Y direction but also in an oblique direction (a direction not orthogonal to the X direction, for example, a diagonal direction of the ceramic multilayer wiring board). It has become necessary to shorten the signal lines by increasing the degree of freedom of the path selection.

However, when the multilayer ceramic wiring board is mounted at a high density and the through-hole interval is further reduced, the wiring layout rule of the multilayer printed wiring board cannot be applied as it is. As shown in FIG. 13, when the signal line 106 is wired in the radiation direction (a), compared with the case where the signal line 106 is wired in the Y direction (b), the distance between the through hole 104 and the signal line 106 is smaller. This is because the gap t becomes narrower, and the through hole 104 and the signal line 106 may approach beyond the proximity limit. That is, the insulation resistance between the through hole and the signal line decreases,
This is because there is a high possibility that adverse effects such as migration will occur.

Accordingly, an object of the present invention is to reduce the wiring capacitance of a ceramic multilayer wiring board without lowering the insulation resistance between a through hole and a signal line.

[0009]

In order to solve the above-mentioned problems, according to the present invention, at least one pair of signal lines connecting between two connection points among the connection points located on the intersection of the basic lattice are formed. A ceramic multi-layer wiring board including a wiring layer, wherein at least one set of signal lines of the one or more sets of signal lines has at least a part of the signal lines that are not in the same row of the basic lattice. Provided is a ceramic multilayer wiring board which is wired along a shortest path connecting connection points located at lattice points.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, the basic structure of the ceramic multilayer wiring board according to the present embodiment will be described with reference to FIG.

The ceramic multilayer wiring board 100 uses ceramics as a substrate material and has a multilayer structure as shown in FIG. 1 (a). Specifically, a power supply layer (not shown) and ground layers 102a ₁ ,. . . , The wiring layer 103b _1, 102a _m. . . , 103b _n, and through holes 104 are formed in each layer at predetermined lattice point positions of an imaginary orthogonal basic lattice. Then, each of the wiring layers 103b ₁ ,. . . , 103
The wiring pattern of the b _n, contains signal lines running along the shortest route connecting between the two through holes to be connected. For example, the wiring pattern of the wiring layer 103b ₁ that connects between the two through holes arranged in (a direction parallel to one of the parallel straight lines 101a defining an orthogonal lattice element) X direction, the signal lines running in the X direction 106a. Further, the wiring pattern of the wiring layer 103b ₂ which connects between the two through holes aligned in the Y direction (direction parallel to the other parallel line group 101b defining an orthogonal lattice element), Y
A signal line 106b running in the direction is included. The wiring patterns of the wiring layers 103b ₃ and 103b ₄ connecting the through holes arranged in the diagonal direction of the orthogonal basic lattice include signal lines 106c ₁ and 10 running in the diagonal direction of the orthogonal basic lattice.
6c ₂ is included.

Next, with reference to FIGS. 2, 3 and 4, a method of manufacturing the ceramic multilayer wiring board 100 including the wiring layers of such a wiring pattern will be described.

First, as shown in FIG. 2A, a ceramic raw material powder 200 and a filler 201 are mixed at an appropriate mixing ratio, and an organic binder 202, a solvent 203, and a plasticizer (not shown) are added thereto. The mixture is sufficiently wet-mixed in a ball mill 204 to prepare a mixed slurry. For example, using the _{SiO 2 -B 2 O 3 -K 2} O-Al 2 O 3 based borosilicate glass as the ceramic raw material powder 200, when using the mullite powder as a filler 201, the mixing ratio between the two (the weight ratio )
Is preferably about 7: 3. Then, this is left under reduced pressure for an appropriate time to perform viscosity adjustment and defoaming. Thereafter, the mixed slurry is poured into a carrier film having a good surface condition, and is spread with a doctor blade to a uniform thickness (typically, about 0.2 mm). Then, when this is dried, the solvent is volatilized, and a flexible green sheet 205 is completed.

Next, as shown in FIG. 2B, after fixing the green sheet 205 with the support frame 206, the position of the lattice point of the orthogonal basic lattice (usually, Through hole 205 at every 0.3mm pitch)
punch out a. In the present embodiment, the machining efficiency is improved by introducing an NC machine tool having a plurality of carbide tools 207 in the drilling.

Next, as shown in FIG. 2C, the conductive powder is applied to the vehicle inside the through holes 205a punched in the green sheet 205 by screen printing.
(For example, Cu powder, Au powder, or the like) is filled with a conductive paste 208 suspended therein. Specifically, Green Sheet 2
After the stencil screen 209a is positioned with respect to the stencil screen 209, the squeegee 210 is moved on the stencil screen 209a so that the conductive paste 208
From the through-hole pattern portion A of the stencil screen 209a. Thereby, the green sheet 2
The inside of the through hole 205a punched in 05 is filled with the conductor paste 208.

Similarly, as shown in FIG. 2D, predetermined wiring patterns 211 are printed on a plurality of green sheets 205, respectively. Specifically, after the stencil screen 209b is positioned with respect to the green sheet 205, the squeegee 210 of the stencil screen 209b is moved so that the conductive paste 208 is applied to the wiring pattern portion B of the stencil screen 209b.
Through. Thereby, the stencil screen 20
The wiring pattern drawn in 9b is a green sheet 20
5 is transferred. Note that the wiring pattern drawn on the stencil screen 209b used at this time includes any one of the linear patterns having different inclinations from each other, or a combined pattern obtained by combining these linear patterns. . For example, as a representative straight line pattern, as shown in FIG. 3, a straight line pattern (A) parallel to the X direction, a positive angle with the X direction (in the present embodiment, +
45 °), a straight line pattern (C) oblique at a negative angle to the X direction (−45 ° in the present embodiment), and a straight line pattern (D) parallel to the Y direction. And the like. Also, as a bonding pattern that combines them,
For example, an oblique pattern in which two linear patterns are oblique
(E).

In this manner, a plurality of green sheets 2
After printing the required wiring patterns 208 on the respective layers 05, they are stacked with the ground layer 102 interposed every predetermined number as shown in FIG. 4A. At this time, it is necessary that the through holes 104 of each layer be accurately positioned. In addition, each green sheet 2
During the period of 05, the organic binder 203 mixed in the mixed slurry was used.
Adhere with adhesive strength.

Thereafter, as shown in FIG. 4 (B), the outer shape thereof is punched into a predetermined shape, and then the atmosphere is sintered in an electric furnace according to a predetermined firing schedule. In this embodiment, the atmosphere in the electric furnace is controlled so that about 55
Organic binder 203 in humidified nitrogen gas at 0 ° C. to 650 ° C.
, Alumina sintering is performed in nitrogen gas at about 900 ° C.

In this sintering process, the green sheet 2
Since a flux component (such as SiO ₂ ) contained in the substrate 05 diffuses into the wiring pattern 208 to form an intermediate layer, a very strong adhesive strength can be obtained.

Next, the present ceramic multilayer wiring board 100
The degree of improvement of the wiring capacity in the above is examined based on the signal transmission delay time between LSI chips. However, here, 1
It is assumed that a 50 mm square ceramic multilayer wiring board 100 is used.

In the mounting area (140 mm × 140 mm) of the ceramic multilayer wiring board 100, 25 LSI chips are mounted in a 5 × 5 array by the TAB method, and are located at the farthest distance from the LSI chips in the first row and first column. The signal transmission delay time (maximum signal transmission delay time) up to the 5th row and 5th column LSI chip was measured.

By increasing the degree of freedom in selecting signal lines in the radiation direction in addition to the XY directions, the length of the signal lines connecting two LSI chips arranged diagonally to the mounting area can be reduced. √2) / 2 (that is, about 7/10), theoretically, the wiring capacity between the two LSI chips is reduced to about 7/10 of the conventional one, thereby maximizing signal transmission. The delay time should be about 7/10 of the conventional one.

In practice, the present ceramic multilayer wiring board 1
00 is approximately 0.90 to 1.50.
ns, which is almost the same as the theoretical maximum transmission delay time of the conventional ceramic multilayer wiring board (about 1.28 to 2.13).
(ns) was confirmed to be reduced to about 7/10. That is, it was confirmed that the wiring capacitance, which is the cause of the signal transmission delay, was suppressed to about 7/10 of the related art.

LS which will be further promoted in the future
In order to cope with the high-density mounting of the I chip, it is not sufficient to simply configure the wiring patterns to be transferred onto the green sheet by linear patterns having different inclinations from each other (see FIG. 3). A device as shown in Fig. 1 is required. That is, as shown in FIG. 5, the orthogonal basic grating 101a,
A proximity limit 500 of the signal line with respect to the through hole is set around each lattice point 101c of 101b, and a straight line initially determined so that the signal line is not routed in an area 500A surrounded by the proximity limit 500. The pattern 501 is corrected, and a new wiring pattern 502 that bypasses the outer periphery of the area 500A surrounded by the proximity limit 500 by the shortest distance is created. By making such a modification, as shown in FIG. 6B, the gap t between the through hole 104 and the signal line 106 can be secured to a certain distance or more. The insulation resistance during the period is not extremely reduced. In such a case, the signal line is extended by an amount that bypasses the outer periphery of the area 500A surrounded by the proximity limit 500. However, with such a slight extension, the performance of the electronic device is reduced. It has been confirmed that no extreme signal transmission delay is induced.

By changing the setting of the proximity limit 500 of the signal line to the through hole, a wiring layout different from the wiring layout shown in FIG. 6B can be completed. For example, if a hexagonal proximity limit 500 is set, a wiring layout as shown in FIG. 6A can be obtained.

It has already been mentioned in the section of the prior art that attempts have been made to increase the mounting density of LSI chips by forming a thin film wiring layer on the surface of a ceramic multilayer wiring board. Even if the above-described wiring layout rule is adopted as the wiring layout rule of the layer, the above-described effect can be achieved. Less than,
The laminated structure of the thin film wiring layer will be described.

As shown in FIG. 7, the thin-film wiring layer 901 formed on the surface of the ceramic multilayer wiring board 900 includes interlayer insulating film layers 905a ₁ ,. . . , 905a ₅ and the wiring layer 90
It has a laminated structure in which 3a, 903b or a power supply layer 902 are alternately stacked, and a device mounting pattern 906 is further formed on a surface layer thereof. And
Each of the wiring layers 903a and 903b has a signal line wired in accordance with the above-described wiring layout rule, for example, a signal line 1000 running in the X direction (see FIG. 8A) and a signal line 1003 running in the Y direction (see FIG. E)), a signal line 1001 running in a direction at an angle of -45 ° with the X direction (see FIG. 8B),
A signal line 1002 (see FIG. 8C) running in a direction forming 5 ° is formed. Then, of course, a modification for securing the gap between the signal line and the through-hole 104 to a certain distance or more is also added. Note that signal lines 1004, 100 running in two different directions are added to the wiring patterns of the wiring layers 903a, 903b.
Needless to say, there may be a case where 5 are mixed (see FIG. 8D).

[0029] Then, the wiring layers 903a, between 903b are connected via a through hole 905A formed in the interlayer insulating film layer 905a _3. Similarly, between the terminal pattern 907 formed on the surface layer of the ceramic multilayer wiring board 900 and each of the wiring layers 903a and 903b, through holes 905A formed in the interlayer insulating film layers 905a ₁ , 905a ₂ and 905a ₃ respectively. Through the device mounting pattern 906 and each wiring layer 903a,
903b, an interlayer insulating film layer 905, respectively.
a _3, 905a _4, are connected via a through hole 905A formed in the 905a _5.

Next, referring to FIG. 9, this thin film wiring layer 901
Will be described. Here, as the ceramic multilayer wiring substrate 900 for forming the thin film wiring layer 901, the ceramic multilayer wiring substrate 100 having the laminated structure described with reference to FIG. 1 is used.

First, as shown in FIG. 9 (A), the surface layer of
(Or in the order of Cr, Cu, Cr) to form a terminal pattern 907 on the surface layer of the ceramic multilayer wiring board 900.

Next, a photosensitive polyimide is applied to the surface layer of the ceramic multilayer wiring board 900, and is then pre-dried for an appropriate time. And the photolithography process
(Exposure, development, cured) by, after forming an interlayer insulating film 905a _1, as shown in FIG. 9 (B), by a sputtering method,
An Al thin film 908 as shown in FIG.
To form Then, an Al thin film 9 is formed using a spin coater.
After applying the resist on the substrate 08, it is pre-dried for an appropriate time. Then, as shown in FIG. 9D, a resist mask 909 for forming a wiring pattern designed in accordance with the wiring layout rules described above is formed by exposure and development. Then, this resist mask 90
After the Al thin film 908 is etched by using the resist mask 9, the unnecessary resist mask 909 is removed. As a result, as shown in FIG.
Is formed. By repeating the above process as many times as necessary, the thin film wiring layer 901 shown in FIG. 7 can be formed.

When it is necessary to form a thin film wiring layer having a smaller wiring resistance, a laminating method using electroplating described below is used rather than a laminating method using the sputtering method described above. We recommend that you adopt it. This is because the stress remaining in the wiring pattern is small.

Also in this case, first, as shown in FIG. 10A, the ceramic multilayer wiring board 90 is formed by sputtering.
By depositing Al (or in the order of Cr, Cu, Cr) on the surface layer of the ceramic multilayer wiring substrate 90,
A terminal pattern 907 is formed on the surface layer of No. 0. Then, as shown in FIG. 10B, a power supply film 911 for electroplating is formed by depositing chromium and copper on the surface layer of the ceramic multilayer wiring substrate 900 by a sputtering method.
Then, using a spin coater, resist (about 20 μm thick)
After application of m), it is pre-dried for a suitable time.
Then, as shown in FIG. 10C, a plating resist mask 912 for forming a through hole is formed by exposure and development. Then, as shown in FIG. 10D, by using the power supply film 911 as a cathode and selectively performing electroplating with a Cu plating solution, a conductor portion 913 to be a through hole is formed. Then, as shown in FIG.
Then, as shown in FIG. 10F, the unnecessary power supply film 911 is etched. Then, a polyimide having a low dielectric constant is applied thereon, and is cured to form an interlayer insulating film 9 as shown in FIG.
14 is formed. Then, the surface of the interlayer insulating film 914 is polished, and when the terminal surface of the through hole 913 is exposed, as shown in FIG.
A power supply film 915 for electroplating is formed by depositing chromium and copper thereon. Then, using a spin coater, put a resist on top of it (about 20 μm thick)
After the application, it is pre-dried for an appropriate time. Then, as shown in FIG. 11 (I), a plating resist mask 916 for forming a wiring pattern designed according to the above wiring layout rules by exposure and development.
To form Then, as shown in FIG. 11J, by using the power supply film 915 as a cathode and selectively performing electroplating with a Cu plating solution, a conductor portion 917 to be a wiring pattern is formed. Then, using a spin coater,
After a resist (approximately 20 μm thick) is applied thereon, it is pre-dried for an appropriate time. And FIG.
As shown in (K), a plating resist mask 918 for forming a through hole is formed by exposure and development. Then, as shown in FIG. 12 (L), by selectively performing electroplating with a Cu plating solution using the power supply film 915 as a cathode, the conductor portion 919 to be a through hole is formed.
To form Then, as shown in FIG. 12 (M), after the unnecessary plating resist masks 916 and 918 are removed, as shown in FIG.
5 is etched. Then, using a spin coater,
Polyimide is applied on top of this, and cured, whereby an interlayer insulating film 92 as shown in FIG.
0 is formed. Then, the surface of the interlayer insulating film 920 is polished to expose the terminal surface of the through hole 919. By repeating the above process as many times as necessary, the thin film wiring layer 901 shown in FIG. 7 can be formed.

[0035]

According to the ceramic multilayer wiring board of the present embodiment, it is possible to reduce the wiring capacitance that causes signal transmission delay without lowering the insulation resistance between the through hole and the signal line. it can.

It is needless to say that the same effect can be obtained even if the design conditions such as the composition of the ceramic raw material powder, the conductor material, and the mounting density of the LSI chip are changed.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a basic structure of a ceramic multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a view for explaining a method of manufacturing the ceramic multilayer wiring board of FIG. 1;

FIG. 3 is a diagram showing an example of a wiring layout of the ceramic multilayer wiring board of FIG. 1;

FIG. 4 is a view for explaining a method of manufacturing the ceramic multilayer wiring board of FIG. 1;

FIG. 5 is a diagram for explaining correction of the wiring layout of FIG. 3;

FIG. 6 is a diagram illustrating an example of a corrected wiring layout.

FIG. 7 is a diagram showing an example of a structure of a ceramic multilayer wiring board according to an embodiment of the present invention.

FIG. 8 is a diagram showing an example of a wiring layout of a thin film wiring layer of FIG. 7;

FIG. 9 is a view for explaining a method of forming the thin film wiring layer of FIG. 7;

FIG. 10 is a view for explaining a method of forming the thin film wiring layer of FIG. 7;

FIG. 11 is a view for explaining a method of forming the thin film wiring layer of FIG. 7;

FIG. 12 is a view for explaining a method of forming the thin film wiring layer of FIG. 7;

FIG. 13 is a diagram showing an example of a wiring layout of a conventional ceramic multilayer wiring board.

[Explanation of symbols]

100 ... multilayer ceramic wiring board 101a, 101b ... orthogonal grid points 102a ₁ parallel straight lines 101c ... orthogonal lattice element defining a primitive lattice. . . , 102a _m ... ground layer 103b _1,. . . , 103b _n ... wiring layer 104 ... through hole 106a, 106b, 106c ₁ , 106c ₂ ... signal line 200 ... ceramic raw material powder 201 ... filler 202 ... organic binder 203 ... solvent 204 ... ball mill 205 ... green sheet 206 ... support frame 207 ... Carbide tool (punch) 208 ... Conductor paste 209a, 209b ... Stencil screen 210 ... Squeegee 211 ... Wiring pattern 500 ... Proximity limit of signal line to through hole 900 ... Ceramic multilayer wiring board 901 ... Thin film wiring layer 902 ... Power supply layer 903a, 903b ... wiring layer _{905a 1, 905a 2, 905a 3} , 905a 4, 905a 5
... interlayer insulating film layer 906 ... device mounting pattern 907 ... terminal pattern 908 ... Al thin film 909 ... resist mask 910 ... wiring pattern 911 ... feeding film 912 ... plating resist mask 913 ... conductor part 915 ... feeding film 916 ... plating resist mask 917 ... Conductor 918 ... Plating resist mask 919 ... Conductor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masahide Okamoto 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Production Technology Laboratory (72) Inventor Tetsuya Yamazaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd. Production Technology Research Laboratories (72) Inventor Hidetaka Shigi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Ltd. Production Technology Research Laboratories (72) Ryohei Sato Totsuka-ku, Yokohama-shi, Kanagawa Prefecture 292 Yoshidacho Inside Hitachi, Ltd. Production Engineering Laboratory

Claims (6)

[Claims] 1. A ceramic multilayer wiring board including a wiring layer in which at least one set of signal lines connecting between two connection points among connection points located on intersections of a basic lattice is formed, At least one signal line of the one or more signal lines is formed along a shortest straight path connecting at least a part of the signal lines between connection points located at two grid points that are not in the same column of the basic grid. A ceramic multilayer wiring board characterized by being wired. 2. A ceramic multilayer wiring board including a wiring layer in which one or more pairs of signal lines connecting between two connection points among connection points located on intersections of a basic lattice are formed, At least one signal line of the one or more signal lines may be configured such that at least a portion of the signal lines detours at a shortest distance around a perimeter of each intersection of the basic lattice and a predetermined perimeter of a no-entry area. A ceramic multilayer wiring board, which is wired along a shortest straight path connecting between connection points located at two grid points that are not in the same row of the basic grid. 3. A thin film wiring layer including at least one set of signal lines connecting between two connection points among the connection points located on the intersection of the basic lattice is formed on the surface. 3. The ceramic multilayer wiring board according to claim 1, wherein at least one set of signal lines among one or more sets of signal lines included in the thin film wiring layer has at least a part of the signal lines not in the same row of the basic lattice. A ceramic multilayer wiring board, which is wired along a shortest straight path connecting between connection points located at two lattice points. 4. A thin-film wiring layer including at least one set of signal lines connecting between two connection points among the connection points located on the intersection of the basic lattice is formed on the surface. 4. The ceramic multilayer wiring board according to claim 1, wherein at least one part of the signal lines of the one or more signal lines included in the thin film wiring layer is formed around each intersection of the basic lattice. Ceramics characterized in that the ceramics are wired along a shortest straight path connecting between connection points located at two grid points that are not in the same row of the basic grid while bypassing the outer circumference of a predetermined prohibited area by a shortest distance. Multilayer wiring board. 5. An electronic circuit device comprising a plurality of devices mounted on the ceramic multilayer wiring board according to claim 1, 2, 3 or 4. 6. Electronic equipment on which the electronic circuit device according to claim 5 is mounted.