JPH02246299A - Multilayer ceramic circuit board and its manufacture - Google Patents

Multilayer ceramic circuit board and its manufacture

Info

Publication number
JPH02246299A
JPH02246299A JP6606089A JP6606089A JPH02246299A JP H02246299 A JPH02246299 A JP H02246299A JP 6606089 A JP6606089 A JP 6606089A JP 6606089 A JP6606089 A JP 6606089A JP H02246299 A JPH02246299 A JP H02246299A
Authority
JP
Japan
Prior art keywords
circuit board
resistors
resistor
multilayer ceramic
ceramic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6606089A
Other languages
Japanese (ja)
Inventor
Shigenori Aoki
重憲 青木
Mineharu Tsukada
峰春 塚田
Kishio Yokouchi
貴志男 横内
Etsuro Udagawa
悦郎 宇田川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6606089A priority Critical patent/JPH02246299A/en
Publication of JPH02246299A publication Critical patent/JPH02246299A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make small the mounting areas of resistors and to make possible an adjustment of the resistance value subsequent to firing of a circuit board by a method wherein the resistors are formed on the circuit board vertically to the element mounting surface of an LSI and extraction lines, which are connected to other electrode parts provided on the board surface from each layer of green sheets, are provided. CONSTITUTION:A multilayer ceramic circuit board is provided with electrode parts 15 formed at the upper and lower parts of a hole 12 for resistor use, resistors 13 provided in the hole 12, extraction lines 14, which are provided on the surface of the board from each layer of green sheets 11 and are independently formed so as to reach other electrode parts 16, and the like. The lines 14 are respectively connected to one of the resistors 13, one other electrode part is selected from among the other electrode parts 16 and at least one of the resistors 13 is incorporated between the electrode parts 15 and the other electrode part 16 to contrive to adjust the resistance value of the board. Moreover, the resistors 13 are formed vertically to an element mounting surface of a large-scale integrated circuit (an LSI). Thereby, the mounting areas of the resistors 13 can be made small and the resistance value subsequent to firing of the board can be adjusted.

Description

【発明の詳細な説明】 〔概要〕 大規模集積回路(LSI)素子を搭載するための多層セ
ラミック回路基板の製造方法に関し、抵抗器の実装面積
が小さく、また基板の焼成後で抵抗値の調節が可能な抵
抗内蔵の多層セラミック回路基板を提供することを目的
とし、三次元配線を有するた多層セラミック回路基板で
あって、抵抗体から成り該基板を上下方向に貫通する抵
抗器用穴の上下にはそれぞれ電極部が設けられ、該基板
の各層から基板表面の他の電極部に接続する引き出し線
路は該抵抗体のいずれか1つに接続され、他の電極部の
選定により抵抗体の少なくとも1つを電極部と他の電極
部との間に組み入れて該基板の抵抗値を調整する構成と
したことを特徴とする多層セラミック回路基板、および
三次元配線を有する多層セラミック回路基板の製造方法
において、予め複数枚のグリーンシートの所定位置に抵
抗器用穴を形成し、この穴に抵抗体を設ける工程と、前
記グリーンシートの各層から表面に設けた電極部に達す
る独立した引き出し線路を形成する工程と、前記グリー
ンシートを位置合わせして積層したのち焼成する工程と
を含むことを特徴とする多層セラミック回路基板の製造
方法を含み構成する。
[Detailed Description of the Invention] [Summary] A method for manufacturing a multilayer ceramic circuit board for mounting large-scale integrated circuit (LSI) elements, which requires a small mounting area for resistors and adjusts the resistance value after baking the board. The purpose of the present invention is to provide a multilayer ceramic circuit board with a built-in resistor that is capable of providing three-dimensional wiring. are each provided with an electrode portion, and a lead line connecting each layer of the substrate to another electrode portion on the surface of the substrate is connected to any one of the resistors, and at least one of the resistors is connected by selecting the other electrode portion. A multilayer ceramic circuit board, and a method for manufacturing a multilayer ceramic circuit board having three-dimensional wiring, characterized in that one is incorporated between an electrode part and another electrode part to adjust the resistance value of the board. , a step of forming holes for resistors in advance at predetermined positions in a plurality of green sheets, and providing resistors in these holes; and a step of forming independent lead-out lines from each layer of the green sheets to the electrode portions provided on the surface. and a step of aligning and stacking the green sheets and then firing them.

〔産業上の利用分野〕[Industrial application field]

本発明は、大規模集積回路(LSI)素子を搭載するた
めの多層セラミック回路基板の製造方法に関する。
The present invention relates to a method of manufacturing a multilayer ceramic circuit board for mounting large scale integrated circuit (LSI) elements.

C従来の技術〕 近年の情報処理装置の大容量化と高速化に対応して、L
SIやVLS Iを高密度に実装することの可能な回路
基板が要求されている。このため、回路基板の内部には
銅などを材料とする電気抵抗の低い配線を三次元的に張
り巡らせ多層構造とする必要がある。さらには、外部回
路とのインピーダンスマツチングなどをとるために抵抗
器などを内蔵した、よりコンパクトな回路基板が望まれ
ている。
C. Conventional technology] In response to the increased capacity and speed of information processing devices in recent years,
There is a need for a circuit board that can mount SI and VLSI at high density. For this reason, it is necessary to have a multilayer structure in which wiring with low electrical resistance made of copper or the like is spread three-dimensionally inside the circuit board. Furthermore, there is a demand for a more compact circuit board that includes built-in resistors for impedance matching with external circuits.

第7図は従来の抵抗器を内蔵する多層セラミック回路基
板の構成図である。同図において、グリーンシート1上
に酸化ルテニウム(RuO*)などの導電性ペーストを
厚膜印刷して抵抗器2を形成し、また基板表面に形成し
た電極部3に達する引き出し線路4を形成したものを、
多数枚積層したのち焼成するものが知られている。
FIG. 7 is a block diagram of a multilayer ceramic circuit board incorporating a conventional resistor. In the figure, a resistor 2 is formed by printing a thick film of conductive paste such as ruthenium oxide (RuO*) on a green sheet 1, and an extraction line 4 reaching an electrode part 3 formed on the surface of the substrate is formed. Things,
It is known that many sheets are laminated and then fired.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来の抵抗器2を内蔵する多層セラミック回路
基板では、抵抗器2の数が多くなると総印刷面積も大き
くなってしまい、層数の増加など基板の大型化につなが
る。また、抵抗器2が基板の内部に封入されてしまうた
め、焼成後の抵抗値の調節が極めて困難である。
However, in a conventional multilayer ceramic circuit board with built-in resistors 2, as the number of resistors 2 increases, the total printing area also increases, leading to an increase in the number of layers and an increase in the size of the board. Furthermore, since the resistor 2 is sealed inside the substrate, it is extremely difficult to adjust the resistance value after firing.

そこで本発明は、抵抗器の実装面積が小さく、また基板
の焼成後で抵抗値の調節が可能な抵抗内蔵の多層セラミ
ック回路基板を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multilayer ceramic circuit board with built-in resistors, which has a small mounting area and whose resistance value can be adjusted after firing the board.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、三次元配線を有するた多層セラミック回路
基板であって、抵抗体から成り該基板を上下方向に貫通
する抵抗器用穴の上下にはそれぞれ電極部が設けられ、
該基板の各層から基板表面の他の電極部に接続する引き
出し線路は該抵抗体のいずれか1つに接続され、他の電
極部の選定により抵抗体の少なくとも1つを電極部と他
の電極部との間に組み入れて該基板の抵抗値を調整する
構成としたことを特徴とする多層セラミツ夛回路基板、
および三次元配線を有する多層セラミック回路基板の製
造方法において、予め複数枚のグリーンシートの所定位
置に抵抗器用穴を形成し、この穴に抵抗体を設ける工程
と、前記グリーンシートの各層から表面に設けた電極部
に達する独立した引き出し線路を形成する工程と、前記
グリーンシートを位置合わせして積層したのち焼成する
工程とを含むことを特徴とする多層セラミック回路基板
の製造方法によって解決される。
The above-mentioned problem is a multilayer ceramic circuit board having three-dimensional wiring, in which electrode portions are respectively provided above and below a resistor hole made of a resistor and passing through the board in the vertical direction,
An extraction line connecting each layer of the substrate to another electrode section on the surface of the substrate is connected to one of the resistors, and by selecting another electrode section, at least one of the resistors is connected to the electrode section and the other electrode. A multilayer ceramic circuit board, characterized in that it is incorporated between a circuit board and a circuit board to adjust the resistance value of the board.
and a method for manufacturing a multilayer ceramic circuit board having three-dimensional wiring, which includes the steps of forming holes for resistors in advance at predetermined positions in a plurality of green sheets, and providing resistors in the holes; The present invention is solved by a method for manufacturing a multilayer ceramic circuit board characterized by including a step of forming an independent lead-out line that reaches a provided electrode portion, and a step of aligning and stacking the green sheets and then firing them.

第1図は本発明の原理説明図である。同図において、1
1は複数枚の積層されるグリーンシート、12は各グリ
ーンシート11のそれぞれに穿孔された抵抗器形成用穴
、13は前記抵抗器形成用穴12に設けた抵抗体、14
はグリーンシート11の各層から基板表面に設けた他の
電極部16に達するよう独立して形成した引き出し線路
であり、グリーンシート11を位置合わせして積層した
のち焼成することにより三次元配線を有する多層セラミ
ック回路基板が製造される。なお、工5は抵抗器用大工
2の上下に形成された電極部である。第2図は第1図の
多層セラミック回路基板の等価回路図であり、グリーン
シート11の厚さ方向に抵抗体13が直列に接続され、
また各抵抗体13間から表面の他の電極部16に引き出
し線路14が形成され、かつ内部の引き出し線路14の
一部と電極部15はLS117に接続されている。なお
、抵抗体13は、抵抗穴12に導電性ペースト21を充
填すること、抵抗器穴12にグリーンシート11の焼成
温度より低い温度で焼成し、グリーンシート11と同等
の厚さを有する導電性チップ31を充填すること、また
は抵抗穴12に導電性を有する抵抗粉末41を充填する
ことによっても形成される。
FIG. 1 is a diagram explaining the principle of the present invention. In the same figure, 1
Reference numeral 1 denotes a plurality of stacked green sheets, 12 a hole for forming a resistor formed in each green sheet 11, 13 a resistor provided in the hole 12 for forming a resistor, 14
are lead lines formed independently from each layer of the green sheet 11 to reach another electrode section 16 provided on the surface of the substrate, and are formed by aligning and laminating the green sheets 11 and then firing them to form a three-dimensional wiring. A multilayer ceramic circuit board is manufactured. Note that the parts 5 are electrode parts formed above and below the resistor carpenter 2. FIG. 2 is an equivalent circuit diagram of the multilayer ceramic circuit board of FIG. 1, in which resistors 13 are connected in series in the thickness direction of the green sheet 11.
Further, a lead line 14 is formed between each resistor 13 and another electrode part 16 on the surface, and a part of the internal lead line 14 and the electrode part 15 are connected to the LS 117. The resistor 13 is made by filling the resistor hole 12 with a conductive paste 21, firing the resistor hole 12 at a temperature lower than the firing temperature of the green sheet 11, and applying a conductive paste 21 having the same thickness as the green sheet 11. It can also be formed by filling the chip 31 or by filling the resistance hole 12 with conductive resistance powder 41.

〔作用〕[Effect]

本発明によれば、抵抗体13がLSI素子実装面に対し
て垂直に形成されるため、抵抗体13の実装面積を小さ
くできる。さらに各層から基板表面に設けた他の電極部
16に引き出し線路14を設けることによって、焼成後
に基板表面の他の電極部16を選択することによって抵
抗値を調節することができる。
According to the present invention, since the resistor 13 is formed perpendicularly to the LSI element mounting surface, the mounting area of the resistor 13 can be reduced. Furthermore, by providing lead lines 14 from each layer to other electrode portions 16 provided on the substrate surface, the resistance value can be adjusted by selecting other electrode portions 16 on the substrate surface after firing.

〔実施例〕〔Example〕

以下、本発明を図示の一実施例により具体的に説明する
Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.

第3図は本発明第一実施例の多層セラミック回路基板の
構成図である。なお1.第1図に対応する部分は同一の
符号を記す(以下の実施例も同様とする)。
FIG. 3 is a configuration diagram of a multilayer ceramic circuit board according to a first embodiment of the present invention. Note 1. Portions corresponding to those in FIG. 1 are denoted by the same reference numerals (the same applies to the following embodiments).

同図において、アルミナ、はうけい酸ガラス、バインダ
ー、溶剤を混合してスラリーを作製し、ドクターブレー
ド法によって厚さ500 μm程度のグリンシート11
を作製した。これを100mm角に打ち抜き、0.3a
+m φのドリルでスルーホールを形成した。そして抵
抗器用穴12として0.2mn+ φ程度のスルーホー
ルに抵抗体として抵抗ペースト21を、引き出し線用の
スルーホールに銅ペーストを充填したのち、表面(基板
の両面)の他の電極部16に達するための引き出し線路
14をスクリーン印刷した。抵抗ペースト21は、それ
ぞれ粒径3μmのLaB、粉末とはうけい酸ガラス粉末
とを2:1の割合で混合し、混練して作製した。次にこ
れらのグリーンシート11を位置合わせして10枚重ね
て加圧積層した。続いて1000°Cの窒素中で焼成し
、全体の厚さが4IllIm程度の多層セラミック基板
を得た。
In the figure, a slurry is prepared by mixing alumina, silicate glass, a binder, and a solvent, and a green sheet 11 with a thickness of about 500 μm is prepared using a doctor blade method.
was created. Punch this out into a 100mm square, 0.3a
A through hole was formed using a +mφ drill. Then, fill the through hole of about 0.2 mm + φ as the resistor hole 12 with resistance paste 21 as a resistor, and fill the through hole for the lead wire with copper paste. The lead-out line 14 for reaching was screen printed. The resistance paste 21 was prepared by mixing and kneading LaB powder and silicate glass powder each having a particle size of 3 μm at a ratio of 2:1. Next, these green sheets 11 were aligned and 10 sheets were stacked and laminated under pressure. Subsequently, it was fired in nitrogen at 1000°C to obtain a multilayer ceramic substrate having a total thickness of about 4IllIm.

上記製造方法によれば、得られた抵抗器の抵抗値をデジ
タルマルチメータを用い、四端子法によって測定したと
ころ、10層の抵抗体の抵抗値はそれぞれ4.8〜6.
0Ωであり、これを直列につなぐことによって0〜54
Ωの抵抗値が約5.4Ω刻みで得られた。
According to the above manufacturing method, when the resistance values of the obtained resistors were measured using a digital multimeter by the four-terminal method, the resistance values of the 10 layers of resistors were 4.8 to 6.
0Ω, and by connecting them in series, the resistance between 0 and 54
Resistance values in Ω were obtained in steps of approximately 5.4 Ω.

また、得られた抵抗器の寸法は、0.2 Xo、2 X
4Il1113であった。同様の抵抗器を従来法(スク
リーン印刷法など)で作製するためには、膜厚0.02
5m−1線幅0.5a+mと仮定すると、線長は1.2
Ωm必要(計算による)である。すなわち、本実施例で
は抵抗値の実装面積を小さくすることが可能である。
Also, the dimensions of the obtained resistor are 0.2 Xo, 2 X
It was 4Il1113. In order to produce a similar resistor using a conventional method (screen printing method, etc.), a film thickness of 0.02
Assuming 5m-1 line width 0.5a+m, line length is 1.2
Ωm is required (according to calculation). That is, in this embodiment, it is possible to reduce the mounting area of the resistance value.

この例では、(0,2X0.2)八〇、5 Xl、2)
=1/15となる。
In this example, (0,2X0.2)80,5Xl,2)
=1/15.

第4図は本発明第二実施例の多層セラミック回路基板の
構成図である。
FIG. 4 is a structural diagram of a multilayer ceramic circuit board according to a second embodiment of the present invention.

同図において、第1実施例と同様の方法により厚さ50
0 μ鋼程度のグリンシートを作製した。これを100
mm角に打ち抜き、0.3mm φのドリルでスルーホ
ールを形成し、ここに銅ペーストを充填した。続いて所
定の位置に抵抗器用穴12として0.2mmφ程度のス
ルーホールをグリーンシート11を貫通するように形成
し、導電性チップ31を充填したのち、表面(基板の両
面)の他の電極部16に達するための引き出し線14を
スクリーン印刷した。次に、これらのグリーンシート1
1を位置合わせして10枚重ねて加圧積層した。続いて
1000°Cの窒素中で焼成し、全体の厚さが4mm程
度の多層セラミック基板を得た。
In the same figure, a thickness of 50 mm was obtained by the same method as in the first embodiment.
A green sheet of approximately 0μ steel was produced. This is 100
It was punched into a square mm square, a through hole was formed with a 0.3 mm φ drill, and the hole was filled with copper paste. Next, a through hole of about 0.2 mmφ is formed as a resistor hole 12 at a predetermined position so as to penetrate through the green sheet 11, and after filling it with a conductive chip 31, other electrode parts on the surface (both sides of the substrate) are formed. A leader line 14 to reach 16 was screen printed. Next, these green sheets 1
1 were aligned and 10 sheets were laminated under pressure. Subsequently, it was fired in nitrogen at 1000°C to obtain a multilayer ceramic substrate with a total thickness of about 4 mm.

導電性チップ31は次のように作製した。まず、それぞ
れ粒径3μmのLaBb粉末とはうけい酸ガラス粉末と
を2:lの割合で混合しこれを加圧成形したのち100
0°Cで熱処理した。得られた焼成体をめのう乳鉢で粉
砕したのちふるいがけし、粒径が400〜500μmの
球状のチップを得た。
The conductive chip 31 was manufactured as follows. First, LaBb powder, each having a particle size of 3 μm, and silicate glass powder were mixed at a ratio of 2:1, and this was pressure-molded.
Heat treated at 0°C. The obtained fired body was crushed in an agate mortar and then sieved to obtain spherical chips with a particle size of 400 to 500 μm.

上記製造方法によれば、得られた抵抗器の抵抗値をデジ
タルマルチメータを用い、四端子法によって測定したと
ころ、10層の抵抗値の抵抗値はそれぞれ4.0〜5.
6Ωであり、これを直列につなぐことによって0〜48
Ωの抵抗値が約4.8Ω刻みで得られた。
According to the above manufacturing method, when the resistance values of the obtained resistors were measured using a digital multimeter using the four-terminal method, the resistance values of the 10 layers were 4.0 to 5.0, respectively.
6Ω, and by connecting them in series, the resistance between 0 and 48
Resistance values in Ω were obtained in steps of approximately 4.8 Ω.

また、得られた抵抗器の寸法は0.2X0.2X4ms
″であった。同様の抵抗器を従来法(スクリーン印刷法
など)で作製するためには、膜厚0.025mm、線幅
0.5+*mと仮定すると、線長は1.2mm必要(計
算による)である。すなわち、本実施例によると抵抗値
の実装面積を小さくすることが可能である。
Also, the dimensions of the obtained resistor are 0.2X0.2X4ms
''. To make a similar resistor using a conventional method (such as screen printing), assuming a film thickness of 0.025 mm and a line width of 0.5+*m, the line length would need to be 1.2 mm ( According to this embodiment, it is possible to reduce the mounting area of the resistance value.

この例では、(0,2x0.2)/(0,5xl、2)
=1/15となる。
In this example, (0,2x0.2)/(0,5xl,2)
=1/15.

第5図は本発明第三実施例の多層セラミック回路基板の
構成図である。
FIG. 5 is a block diagram of a multilayer ceramic circuit board according to a third embodiment of the present invention.

同図において、第1実施例と同様の方法により厚さ50
0μm程度のグリンシートを作製した。これを100+
+us角に打ち抜き、0.3+am φのドリルでスル
ーホールを形成した。そして抵抗器用穴12として0.
2mm φ程度のスルーホールに抵抗粉末41を、引き
出し線用のスルーホールに銅ペーストを充填したのち、
表面(基板の両面)の他の電極部16に達するための引
き出し線14をスクリーン印刷した。
In the same figure, a thickness of 50 mm was obtained by the same method as in the first embodiment.
A green sheet with a thickness of about 0 μm was produced. This is 100+
It was punched out at +us angle and a through hole was formed with a 0.3+am φ drill. And 0.0 as the resistor hole 12.
After filling the through hole of about 2 mm φ with resistance powder 41 and the through hole for the lead wire with copper paste,
Lead lines 14 for reaching other electrode portions 16 on the front surface (both sides of the substrate) were screen printed.

抵抗粉末には、それぞれ粒径3μ慣のLaB、粉末とは
うけい酸ガラス粉末とを2:1の割合で混合したものを
用いた0次にこれらのグリーンシート11を位置合わせ
して10枚重ねて加圧積層した。続いて1000℃の窒
素中で焼成し、全体の厚さが4IllII+程度の多層
セラミック基板を得た。
The resistance powder used was a mixture of LaB powder and silicate glass powder at a ratio of 2:1, each having a particle size of 3 μm. These green sheets 11 were aligned to form 10 sheets. They were laminated under pressure. Subsequently, it was fired in nitrogen at 1000° C. to obtain a multilayer ceramic substrate having a total thickness of about 4IllII+.

上記製造方法によれば、得られた抵抗器の抵抗値をデジ
タルマルチメータを用い、四端子法によって測定した。
According to the above manufacturing method, the resistance value of the obtained resistor was measured using a digital multimeter by the four-terminal method.

10層の抵抗値の抵抗値はそれぞれ4.5〜6.4Ωで
あり、これを直列につなぐことによって0〜55Ωの抵
抗値が約5.5Ω刻みで得られた。なお、第二と第三の
実施例においても、第一の実施例と同様に、抵抗器用穴
12の上下には電極部15を形成する。
The resistance values of each of the 10 layers were 4.5 to 6.4 Ω, and by connecting them in series, resistance values of 0 to 55 Ω were obtained in approximately 5.5 Ω increments. In addition, in the second and third embodiments, electrode portions 15 are formed above and below the resistor hole 12, similarly to the first embodiment.

また、得られた抵抗器の寸法は0.2X0.2X4ms
+″であった。同様の抵抗器を従来法(スクリーン印刷
法)で作製するためには、膜厚0.025mm 、線幅
0.5mmと仮定すると、線長は1 、2mm必要(計
算による)である。すなわち、本発明によると抵抗値の
実装面積を小さくすることが可能である。この例では、
(0,2xO,2)/(0,5xl、2)=1/15と
なる。
Also, the dimensions of the obtained resistor are 0.2X0.2X4ms
+''. To make a similar resistor using the conventional method (screen printing method), assuming a film thickness of 0.025 mm and a line width of 0.5 mm, the line length would need to be 1 to 2 mm (according to calculations). ).In other words, according to the present invention, it is possible to reduce the mounting area of the resistance value.In this example,
(0,2xO,2)/(0,5xl,2)=1/15.

なお、上記各実施例では、基板表面の他の電極部16を
一直線上配置されるように形成しているが、例えば、第
6図に示すように、抵抗体13の電極部15を中心とす
る円周上に他の電極部16が位置するように形成すれば
、さらにコンパクトにすることが可能になる。
In each of the above embodiments, the other electrode portions 16 on the surface of the substrate are formed so as to be arranged in a straight line, but for example, as shown in FIG. If the other electrode portions 16 are formed so as to be located on the circumference, further compactness can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明によれば、セラミック回路基板
に抵抗体をLSI素子実装面に対して垂直に形成するこ
とで、抵抗器の実装面積が小さく、また焼成後の抵抗値
の調節が可能な抵抗内蔵多層セラミック回路基板が得ら
れ、装置の小型化および高性能化に寄与するところが大
きい。
As explained above, according to the present invention, by forming the resistor on the ceramic circuit board perpendicular to the LSI element mounting surface, the mounting area of the resistor is small and the resistance value can be adjusted after firing. A multilayer ceramic circuit board with a built-in resistor can be obtained, which greatly contributes to miniaturization and higher performance of devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理説明図、 第2図は第1図の多層セラミ回路基板の等価回路図、 第3図は本発明第一実施例の多層セラミック回路基板の
構成図、 第4図は本発明第二実施例の多層セラミック回路基板の
構成図、 第5図は本発明第三実施例の多層セラミック回路基板の
構成図、 第6図は本発明実施例の電極部の配置を示す図、第7図
は従来の抵抗器を内蔵する多層セラミック回路基板の構
成図である。 図中、 11はグリーンシート、 12は抵抗器用穴、 13は抵抗体、 14は引き出し線路、 15は電極部、 16は他の電極部、 17はLS I。 21は抵抗ペースト、 31は導電性チップ、 41は抵抗粉末 を示す。
Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an equivalent circuit diagram of the multilayer ceramic circuit board of Fig. 1, Fig. 3 is a configuration diagram of the multilayer ceramic circuit board of the first embodiment of the invention, Fig. 4 is a block diagram of a multilayer ceramic circuit board according to a second embodiment of the present invention, FIG. 5 is a block diagram of a multilayer ceramic circuit board according to a third embodiment of the present invention, and FIG. 6 is a diagram showing the arrangement of electrode parts according to a third embodiment of the present invention. 7 are configuration diagrams of a conventional multilayer ceramic circuit board incorporating a resistor. In the figure, 11 is a green sheet, 12 is a resistor hole, 13 is a resistor, 14 is an extraction line, 15 is an electrode part, 16 is another electrode part, and 17 is an LSI. 21 is a resistive paste, 31 is a conductive chip, and 41 is a resistive powder.

Claims (2)

【特許請求の範囲】[Claims] (1) 三次元配線を有する多層セラミック回路基板で
あって、 抵抗体(13)から成り該基板を上下方向に貫通する抵
抗器用穴(12)の上下にはそれぞれ電極部(15)が
設けられ、 該基板の各層から基板表面の他の電極部(16)に接続
する引き出し線路(14)は該抵抗体(13)のいずれ
か1つに接続され、 他の電極部(16)の選定により抵抗体(13)の少な
くとも1つを電極部(15)と他の電極部(16)との
間に組み入れて該基板の抵抗値を調整する構成としたこ
とを特徴とする多層セラミック回路基板。
(1) A multilayer ceramic circuit board having three-dimensional wiring, in which electrode portions (15) are provided above and below a resistor hole (12) consisting of a resistor (13) and penetrating the board in the vertical direction. , The extraction line (14) connecting each layer of the substrate to another electrode section (16) on the surface of the substrate is connected to any one of the resistors (13), and depending on the selection of the other electrode section (16), A multilayer ceramic circuit board characterized in that at least one resistor (13) is incorporated between an electrode part (15) and another electrode part (16) to adjust the resistance value of the board.
(2) 三次元配線を有する多層セラミック回路基板の
製造方法において、 予め複数枚のグリーンシート(11)の所定位置に抵抗
器用穴(12)を形成し、この穴(12)に抵抗体(1
3)を設ける工程と、 前記グリーンシート(11)の各層から表面に設けた他
の電極部(16)に達する独立した引き出し線路(14
)を形成する工程と、 前記グリーンシート(11)を位置合わせして積層した
のち焼成する工程とを含むことを特徴とする多層セラミ
ック回路基板の製造方法。
(2) In a method for manufacturing a multilayer ceramic circuit board having three-dimensional wiring, resistor holes (12) are formed in advance at predetermined positions in a plurality of green sheets (11), and resistors (1) are inserted into the holes (12).
3), and an independent extraction line (14) reaching from each layer of the green sheet (11) to another electrode part (16) provided on the surface.
); and a step of aligning and stacking the green sheets (11) and then firing them.
JP6606089A 1989-03-20 1989-03-20 Multilayer ceramic circuit board and its manufacture Pending JPH02246299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6606089A JPH02246299A (en) 1989-03-20 1989-03-20 Multilayer ceramic circuit board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6606089A JPH02246299A (en) 1989-03-20 1989-03-20 Multilayer ceramic circuit board and its manufacture

Publications (1)

Publication Number Publication Date
JPH02246299A true JPH02246299A (en) 1990-10-02

Family

ID=13304941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6606089A Pending JPH02246299A (en) 1989-03-20 1989-03-20 Multilayer ceramic circuit board and its manufacture

Country Status (1)

Country Link
JP (1) JPH02246299A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994022281A1 (en) * 1993-03-19 1994-09-29 Fujitsu Limited Laminated circuit board
US5910755A (en) * 1993-03-19 1999-06-08 Fujitsu Limited Laminate circuit board with selectable connections between wiring layers
JP2006269692A (en) * 2005-03-23 2006-10-05 Tdk Corp Multilayer ceramic substrate and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994022281A1 (en) * 1993-03-19 1994-09-29 Fujitsu Limited Laminated circuit board
US5910755A (en) * 1993-03-19 1999-06-08 Fujitsu Limited Laminate circuit board with selectable connections between wiring layers
JP2006269692A (en) * 2005-03-23 2006-10-05 Tdk Corp Multilayer ceramic substrate and manufacturing method thereof
JP4683269B2 (en) * 2005-03-23 2011-05-18 Tdk株式会社 Manufacturing method of multilayer ceramic substrate

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