JPH10198410A - Pulse generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load of a system controlling CPU without preparing a CPU only for pulse generation and to increase operation speed. SOLUTION: The pulse generation circuit is provided with a CPU 1 for controlling the whole system, a pulse generation part 2 for counting up the pulse generation frequency of an original clock signal and generating a pulse every when its count value reaches a set point, and a pulse counter part 3 for counting the pulse generation frequency from the pulse generation part 2 and generating an interruption for changing the frequency of a pulse to the CPU 1 at every time when its count value reaches a set point. Since the frequency of a pulse and the generation timing of an interruption to the CPU 1 can be changed by changing those set points, the load of the CPU 1 can be sharply reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generating circuit for driving and controlling a motor of a driving mechanism requiring high-precision operation control such as a copying machine or an image reader.

[0002]

2. Description of the Related Art A pulse drive type motor is used as an actuator of a drive mechanism such as an image scanning mechanism provided in a copying machine or an image reader. This type of motor drive pulse acceleration / deceleration control is performed using a timer interrupt process of a CPU that controls the entire system such as a copying machine. That is, a pulse (Hig
h or Low) and sequentially changing the time interval at which the interrupt processing occurs, thereby changing the time from the generation of a pulse to the generation of the next pulse, and consequently changing the pulse width to change the drive pulse. Perform acceleration / deceleration control.

[0003]

However, in the above-described control method using the conventional interrupt processing, if the frequency of the pulse to be generated is very high, the interrupt processing occurs frequently, and the processing other than the interrupt processing is performed. However, there is a problem that the operation speed of the device is lowered, and a so-called heavy condition is caused. This poses a serious problem when a single CPU performs acceleration / deceleration control for a plurality of actuators. Further, if smoother acceleration / deceleration control is performed, interrupts are more frequently generated. In order to solve such a problem, for example, Japanese Patent Laid-Open No. 2-159
The image scanning apparatus described in Japanese Patent No. 879 has a CPU dedicated to generating pulses for driving a motor, in addition to a CPU for system control. Using a CPU dedicated to pulse generation in this way enables fine control of the motor without affecting the operating speed of the CPU for system control, but the cost is reduced by mounting the CPU dedicated to pulse generation. And C for system control
Control may be complicated due to data exchange between the PU and the CPU dedicated to pulse generation. An object of the present invention is to provide a pulse generation circuit which can reduce the load on a system control CPU and improve the operation speed without providing a CPU dedicated to pulse generation.

[0004]

In order to solve the above-mentioned problems, a pulse generating circuit according to the first aspect of the present invention includes a CPU for controlling an entire system including, for example, a pulse drive type motor and a source clock signal. A pulse generator that generates a pulse for driving the motor or the like each time the count reaches a set value, and counts the number of pulses generated from the pulse generator, and the count is A pulse counter for generating an interrupt for changing a frequency of a pulse for driving the motor or the like to the CPU each time the set value is reached. According to a second aspect of the present invention, based on the first aspect, the set value held in the pulse generator is changed by the CPU. . Also,
According to a third aspect of the present invention, there is provided a pulse generation circuit.
On the premise that the set value held in the pulse counter unit is changed by the CPU. A pulse generating circuit according to a fourth aspect of the present invention is characterized in that, based on the second or third aspect, the change of the set value is performed within an interrupt process of the CPU. Claim 5
The pulse generation circuit according to the invention described above is characterized in that, on the premise of claim 1, the pulse generation section includes first and second setting holding circuits for holding the set value. And According to a sixth aspect of the present invention, in the pulse generation circuit according to the first aspect, the pulse counter unit includes a first and a second circuit for holding the set value.
Is provided.
In the pulse generation circuit according to the present invention, the setting value held in the first setting holding circuit can be changed by the CPU and the second value can be changed by the CPU. The setting values held in the setting holding circuit are transferred from the first holding circuit at the time of startup and when an interrupt to the CPU occurs.
The pulse generating circuit according to the invention of claim 8 is characterized in that it operates based on the setting value held in the second setting holding circuit based on claim 7.

[0005]

Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram showing an example of an embodiment of a pulse generating circuit according to the present invention. In the drawing, reference numeral 1 denotes a CPU that controls the entire system of an electrophotographic copying machine;
A pulse generator 2 counts the number of pulse generations of the source clock signal generated by the CPU 1, and generates a driving pulse for a driving motor of an image scanning mechanism of a copying machine every time the counted number reaches a set value. A pulse counter unit that counts the number of pulse generations from the unit 2 and generates an interrupt for changing the frequency of the motor drive pulse to the CPU 1 each time the counted number reaches a set value. The pulse generator 2 includes a first register 4 that stores and holds a set value given by the CPU 1, a second register 5 that stores and holds a set value that determines an actual operation during operation of the pulse generator 2, A clock counter 6 that counts the number of clock signal pulse generations, a comparator 7 that compares a set value N1 held in the second register 5 with a count value n1 of the clock counter 6, and a signal from the comparator 7. And a pulse generator 8 for generating a motor drive pulse.

The clock counter 6 counts up each time a pulse of the source clock signal is received, and constantly outputs the count value to the comparator 7. Comparator 7
Always compares the set value N1 held in the second register 5 with the count value n1 of the clock counter 6, and outputs a signal every time the set value N1 becomes equal to the count value n1. The output signal of the comparator 7 is input to a clear terminal of the clock counter 6 and the pulse generator 8, whereby the clock counter 6 is cleared (reset), and at the same time, a pulse is output by the pulse generator 8. The pulse counter unit 3 has a first register 9 for storing and holding a set value given from the CPU 1, a second register 10 for storing and holding a set value for determining an actual operation of the pulse counter unit 3 during operation, a pulse generation. Part 2
A pulse counter 11 for counting the number of occurrences of the pulse
The comparator 12 includes a comparator 12 that compares the set value N2 held in the second register 10 with the count value n2 of the pulse counter 11, and an interrupt controller 13 that outputs an interrupt generation signal in accordance with a signal from the comparator 12. You.

The pulse counter 11 generates an extraction signal every time a pulse is input from the pulse generator 8,
Using the signal as an enable, the number of times of pulse generation is counted (see FIG. 6). The count value of the pulse counter 11 and the set value of the second register 10 are always input to the comparator 12. The comparator 12 constantly compares the set value N2 held in the second register 10 with the count value n2 of the pulse counter 11, and sets the set value N2
And outputs a signal to the interrupt controller 13 each time the count value n2 becomes equal. Interrupt controller 13
Outputs an interrupt generation signal to the CPU 1 upon receiving a signal from the comparator 12. In the above configuration, when the set values of the first and second registers 4 and 5 of the pulse generator 2 are changed, the timing at which the comparator 7 outputs a signal changes. The frequency (or width) can be made variable. If the set values of the first and second registers 9 and 10 of the pulse counter unit 3 are changed, the comparator 12
Since the timing at which the signal is output changes, the timing at which the interrupt controller 13 generates the interrupt generation signal can be made variable.

FIG. 2 shows an example of a circuit configuration for storing a set value in each register of the pulse generator 2 and the pulse counter 3. The CPU 1 outputs control signals (/ WR in the figure) such as an address bus, a data bus, read, and write. Each register is CPU1
When the CPU 1 accesses the address, one of the outputs of the decoder 14 that is connected to the enable terminal of the register becomes active, and
The WR signal is transmitted to the output side as a clock. The set value is held until the next access to the same address. As described above, the pulse counter unit 3
The set value N2 held in the second register 10 and the count value n2 of the pulse counter 11
2 and a signal is output to the interrupt controller 13 every time the set value N2 becomes equal to the count value n2. Therefore, by using this signal, it is possible to notify the CPU 1 in the form of an interrupt that the pulse generation circuit has generated a pulse having a certain set width a predetermined number of times, and to execute the next pulse frequency (or pulse Width) and a set value for determining the pulse count number can be set in each register.

FIG. 3 shows a flow of the interrupt processing operation in the CPU 1. When the CPU 1 is notified of the interrupt,
The normal flow is interrupted and interrupt processing is started (S
1). When actually generating a drive pulse of a motor or the like, particularly when controlling acceleration / deceleration of a motor, it is necessary to sequentially change the pulse width set value and the pulse count set value each time an interrupt is executed. . Therefore, a table for determining these set values is prepared in advance in a ROM (not shown) in which a program is stored as data, and is implemented by software to control a reference location of the table. The table reference counter is incremented each time interrupt processing is executed (S2). Each time, the value of the table reference counter is checked to determine whether or not the table has been referenced to the end (S3). If the table has been referenced (Yes in S3), the register (pulse width register) of the pulse generator 2 and The register (pulse count register) of the pulse counter unit 3 is cleared (S4), and the motor stop control and the interrupt prohibition process (S4) are performed.
Perform 5). Otherwise (No in S3), the value is set in the register by referring to the value in the next table.

As an example, FIG. 5 shows an example of creating table data when performing acceleration / deceleration control of a pulse frequency indicated by a curve as shown in FIG. In the acceleration / deceleration control of FIG. 4, the pulse frequency is changed in eight stages of 1 to 8. FIG. 5 shows the values arranged on the memory, where PCn is a pulse count data table and fn is a frequency table. The frequency is a value set in a pulse width register, that is, a register of the pulse generation unit 2, and the pulse count is a pulse count register, that is, a pulse counter unit 3.
Is the value to be set in the register. The table values are stored continuously on the memory. The head addresses of the tables are a and b, respectively, and these addresses are stored, and the set value is obtained from these addresses when the pulse generation circuit starts. Then, each time an interrupt occurs, the table reference counter is incremented (corresponding to the above step S2), and the set value is obtained from the address obtained by adding the addresses a and b and the counter value. In this way, the set values can be sequentially obtained, and the value of each register can be changed.

Next, the functions of the first and second registers of the pulse generator 2 and the pulse counter 3 will be described in more detail. FIG. 7 is a partial circuit diagram showing the first and second registers of the pulse generation unit 2 and the pulse counter unit 3 and a peripheral circuit for making both registers function in combination. A first register 4, 9 and a second register 5,
Reference numeral 10 denotes a D flip-flop, between which an AND
A logic circuit including a gate 16 and two OR gates 17 and 18 is inserted. CL of flip-flop
Since the system clock is input to the K terminal, the 1-pulse extraction signal of the signal for turning on the motor is ON1P, and the CPU
An IRQ1P is a 1-pulse extraction signal of an interrupt signal for notifying an interrupt to 1, and a logical sum of these two signals is obtained.
The output and the set value signal are ANDed with each other, and the output and an MTON signal indicating that the circuit is operating (CPU 1
Is turned ON / OFF by OR)
The set values of the first registers 4 and 9 can be transferred to the second registers 5 and 10 when the circuit is started and each time an interrupt occurs.

FIG. 8 shows a timing chart of the above circuit. As shown, when the circuit is started, that is, when the MTON signal changes from low to high, and when an interrupt occurs, the data of the first register is transferred to the second register. Since the data setting in the first register is performed by software after the occurrence of the interrupt, the data is set later than the second register to which the data is transferred by hardware simultaneously with the occurrence of the interrupt. As is apparent from this figure, there is a difference between a set value set by software (a program executed by the CPU) and a set value that actually determines the operation of the hardware (circuit). FIG. 9 shows the correlation. FIG. 10 shows an operation flow of a process of changing the setting value at the time of starting the circuit and at the time of interrupt processing.

Before activating the circuits of the pulse generator 2 and the pulse counter 3, the CPU 1 executes step S in FIG.
As shown in FIG. 11, the first value is stored in the first register.

[0] is written, and then the MTON signal is started to start the motor (S12). As a result, the first value set in the first register

[0] is the timing tm shown in FIG.
At 0, it is transferred to the second register. After the MTON signal is activated, the value [1] to be set when the next interrupt occurs is written to the first register (S13). And the first value

When the operation at [0] is completed, the hardware generates an interrupt (S14), and transfers the value [1] set in the first register to the second register at timing tm1 shown in FIG. The operation according to the changed value [1] is started. When the interrupt occurs, an interrupt flow is executed, and the next value [2] is set in the first register at timing tm2 shown in FIG. 8 (S1).
5).

FIG. 9 shows the correlation between the set value set by software in the above operation and the set value that actually determines the operation of the hardware.
When the value to be set reaches the end according to software, that is, the program, the MTON signal is set to L when the next interrupt occurs (in a state indicated by P in FIG. 9).
Set to ow to disable acceptance of interrupts. The hardware, that is, the circuit of the pulse generator 2 and the pulse counter 3 operates at the last set value [n] set and held in the second register, and generates an interrupt when a pulse is output a predetermined number of times. At this time, the interrupt flow is not executed because the acceptance of the interrupt is prohibited on the CPU 1 side operating according to the program. As mentioned above, after the hardware generates an interrupt, the software recognizes it,
Since the next value can be set irrespective of the time up to the start of the interrupt routine, it is possible to avoid a problem that a hazard is generated in the pulse waveform or the number of waveforms does not match.

In the above, between the pulse generator 8 and the motor, for example, as shown in FIG. 11, a circuit 20 for utilizing the interrupt signal IRQ1P and the MTON signal to output the state of the MTON signal when an interrupt occurs.
By inserting a circuit 21 that controls the pulse output from the output state of the circuit 20 and the pulse from the pulse generator 8, the pulse to the motor can be stopped. If the circuit as shown in FIG. 12 is used, the CPU 1 outputs the MTON signal to Lo according to a program.
When w is set, pulse output to the motor can be stopped irrespective of interruption or the like. Therefore, the pulse generating circuit can be used in a case where a predetermined pulse is output as shown in FIG. 4 or a case where the pulse is immediately interrupted by an input of a sensor or the like as a trigger. In the above embodiment, a circuit configuration for generating one kind of pulse has been described as an example. However, a counter linked to the clock counter 6 is added to the pulse generator 8 and the number of generated pulses is increased to perform stepping. It is also possible to perform acceleration / deceleration control of the motor.

[0016]

As described above, the present invention has the following effects. According to the pulse generation circuit of the first aspect, by changing the set value in the pulse generation unit, the frequency of the generated pulse can be changed,
Also, by changing the set value in the pulse counter section, the timing of the interrupt to the CPU can be made variable, and furthermore, the interrupt to the CPU can be generated only when the pulse frequency changes. The operation speed can be improved by reducing the load on the CPU, and the cost can be reduced because it is not necessary to add a CPU dedicated to pulse generation. Claims 2 and 3
According to the pulse generation circuit, in addition to the above effects, the set value can be changed by the CPU, so that the circuit scale of the pulse generation unit and the pulse counter unit can be reduced, and the cost can be further reduced. According to the pulse generation circuit of the fourth aspect, the operation speed can be further improved in the second and third aspects. According to the pulse generation circuit of the fifth, sixth, seventh, and eighth aspects, the following operation is performed regardless of the time from when the hardware generates an interrupt to when the CPU operating according to the program recognizes the interrupt and enters the interrupt routine. Since the value can be set, it is possible to avoid a problem that a hazard occurs in the pulse waveform or the number of waveforms does not match.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a pulse generation circuit showing an example of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of the pulse generation circuit of FIG. 1;

FIG. 3 is a flowchart of an interrupt processing operation of a CPU of the pulse generation circuit of FIG. 1;

FIG. 4 is an explanatory diagram of an acceleration / deceleration control curve of a pulse frequency in the pulse generation circuit of FIG. 1;

5 is an explanatory diagram showing an example of creating table data corresponding to the acceleration / deceleration control curve in FIG.

FIG. 6 is a timing chart showing a counting operation of the number of times of pulse generation by the pulse counter of the pulse generation circuit of FIG. 1;

FIG. 7 is a partial circuit diagram of a pulse generator and a pulse counter of the pulse generator of FIG. 1;

FIG. 8 is a timing chart showing the operation of the circuit of FIG. 7;

FIG. 9 is an explanatory diagram showing a correlation between a set value set by software and a set value that actually determines the operation of hardware.

FIG. 10 is a flowchart of a processing operation of the pulse generation circuit in FIG. 1 at the time of circuit startup and at the time of interrupt processing.

FIG. 11 is a circuit diagram illustrating an example of a pulse output control circuit.

FIG. 12 is a circuit diagram showing another example of the pulse output control circuit.

[Explanation of symbols]

1 CPU, 2 pulse generators, 3 pulse counters, 4 first registers, 5 second registers, 6 clock counters, 7 comparators, 8 pulse generators, 9 first registers, 10 second registers,
11 pulse counters 11, 12 comparators, 13
Interrupt controller.

Claims (8)

[Claims] 1. A CPU for controlling the entire system, a pulse generator for counting the number of pulse generations of a source clock signal, and generating a pulse each time the count reaches a set value, and a pulse from the pulse generator. The number of occurrences is counted, and each time the counted number reaches a set value, the CPU
And a pulse counter for generating an interrupt for changing the frequency of the pulse. 2. The pulse generation circuit according to claim 1, wherein said set value held in said pulse generation section is changed by said CPU. 3. The pulse generating circuit according to claim 1, wherein said set value held in said pulse counter section is changed by said CPU. 4. The apparatus according to claim 2, wherein the change of the set value is performed in an interrupt process of the CPU.
A pulse generation circuit as described. 5. The pulse generation circuit according to claim 1, wherein the pulse generation unit includes first and second setting holding circuits for holding the set value. 6. The pulse generation circuit according to claim 1, wherein said pulse counter section includes first and second setting holding circuits for holding said set value. 7. The setting value held in the first setting holding circuit can be changed by the CPU, and the setting value held in the second setting holding circuit can be changed at the time of startup and in the CPU.
7. The pulse generating circuit according to claim 5, wherein the signal is transferred from the first holding circuit when an interrupt occurs to the pulse generator. 8. The pulse generating circuit according to claim 7, wherein the pulse generating circuit operates based on the set value held in the second setting holding circuit.