JPH10190063A - Semiconductor light emitting element and semiconductor light emitting device - Google Patents

Semiconductor light emitting element and semiconductor light emitting device

Info

Publication number
JPH10190063A
JPH10190063A JP34488896A JP34488896A JPH10190063A JP H10190063 A JPH10190063 A JP H10190063A JP 34488896 A JP34488896 A JP 34488896A JP 34488896 A JP34488896 A JP 34488896A JP H10190063 A JPH10190063 A JP H10190063A
Authority
JP
Japan
Prior art keywords
light emitting
wire bonding
semiconductor light
emitting device
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34488896A
Other languages
Japanese (ja)
Inventor
Taiji Morimoto
泰司 森本
Shigetoshi Ito
茂稔 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP34488896A priority Critical patent/JPH10190063A/en
Publication of JPH10190063A publication Critical patent/JPH10190063A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which is free of irregular luminance and irregular color and has a small size. SOLUTION: A semiconductor light emitting element formed on an insulating substrate 10 has at least a light emitting section 18, a wire bonding pad 15 for positive electrode, and a wire bonding pad 17 for negative electrode. The wire bonding pads 17 and 15 are arranged closely to each other and the light emitting section 18 is disposed closely to the long sides of the rectangular pads 17 and 15.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光素子の
電極構造に係り、特に、絶縁性基板上に形成された半導
体発光素子の電極パッドの形状、及びそれを用いて実装
した半導体発光装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure of a semiconductor light emitting device, and more particularly, to a shape of an electrode pad of a semiconductor light emitting device formed on an insulating substrate and a semiconductor light emitting device mounted using the same. .

【0002】[0002]

【従来の技術】GaN、AlN、InN、またはこれら
の混晶に代表される窒化物系半導体材料により、可視か
ら紫外領域まで発光する発光素子(LED素子)等の半
導体発光素子が実現されている。これらのLED素子で
は、成長基板としてサファイア基板等の基板が用いられ
るが、これらの基板は絶縁性基板であるため、成長面側
から正電極及び負電極を取り出す必要があり、種々の構
造が提案されている。
2. Description of the Related Art A semiconductor light emitting device such as a light emitting device (LED device) that emits light from the visible to the ultraviolet region has been realized by using a nitride semiconductor material represented by GaN, AlN, InN, or a mixed crystal thereof. . In these LED elements, a substrate such as a sapphire substrate is used as a growth substrate, but since these substrates are insulating substrates, it is necessary to take out a positive electrode and a negative electrode from the growth surface side, and various structures have been proposed. Have been.

【0003】図8は窒化物系半導体材料を用いた従来例
であり、特開平7−94782号公報、発明の名称:窒
化ガリウム系化合物半導体発光素子、出願人:日亜化学
工業株式会社である。
FIG. 8 shows a conventional example using a nitride-based semiconductor material, which is disclosed in Japanese Patent Application Laid-Open No. 7-94782, the title of which is: a gallium nitride-based compound semiconductor light-emitting device, and the applicant: Nichia Corporation. .

【0004】図8(a)は従来例の窒化ガリウム系化合
物半導体発光素子の平面図であり、図8(b)は図8
(a)の平面図のF−F′線で切断した模式断面図であ
る。図8(b)において、サファイア基板等の絶縁性基
板70の上にn型窒化ガリウム系化合物半導体層71と
p型窒化ガリウム系化合物半導体層73とが順に積層さ
れており、n型窒化ガリウム系化合物半導体層71には
負電極72が形成され、p型窒化ガリウム系化合物半導
体層73には正電極74が形成されている。75はp型
窒化ガリウム系化合物半導体層73表面のほぼ全面に形
成された電流拡散用の透光性電極であり、76は前記透
光性電極73に設けられた正電極74を取り出すための
窓部である。
FIG. 8A is a plan view of a conventional gallium nitride-based compound semiconductor light emitting device, and FIG.
It is the schematic cross section cut | disconnected by the FF 'line | wire of the top view of (a). In FIG. 8B, an n-type gallium nitride-based compound semiconductor layer 71 and a p-type gallium nitride-based compound semiconductor layer 73 are sequentially stacked on an insulating substrate 70 such as a sapphire substrate. A negative electrode 72 is formed on the compound semiconductor layer 71, and a positive electrode 74 is formed on the p-type gallium nitride-based compound semiconductor layer 73. Reference numeral 75 denotes a current-diffusing translucent electrode formed on substantially the entire surface of the p-type gallium nitride-based compound semiconductor layer 73, and 76 denotes a window for taking out the positive electrode 74 provided on the translucent electrode 73. Department.

【0005】図8(a)の平面図において、70はサフ
ァイア基板等の絶縁性基板、71はn型窒化ガリウム系
化合物半導体層、72はn側の負電極用ワイヤボンディ
ングパッド(以下、負電極という)、73はp型窒化ガ
リウム系化合物半導体層、74はp側の正電極用ワイヤ
ボンディングパッド(以下、正電極という)、75はp
型窒化ガリウム系化合物半導体層73表面のほぼ全面に
形成された電流拡散用の透光性電極、76は前記透光性
電極73に設けられた正電極74の取り出しのための窓
部である。同図に示されるように、p側の正電極74と
n側の負電極72は対角位置隅部に形成されている。
In the plan view of FIG. 8A, reference numeral 70 denotes an insulating substrate such as a sapphire substrate, 71 denotes an n-type gallium nitride-based compound semiconductor layer, and 72 denotes an n-side negative electrode wire bonding pad (hereinafter referred to as a negative electrode). , 73 is a p-type gallium nitride compound semiconductor layer, 74 is a p-side positive electrode wire bonding pad (hereinafter, referred to as a positive electrode), and 75 is p
A current-transmitting light-transmitting electrode 76 formed on almost the entire surface of the type gallium nitride-based compound semiconductor layer 73 is a window for taking out the positive electrode 74 provided on the light-transmitting electrode 73. As shown in the figure, the p-side positive electrode 74 and the n-side negative electrode 72 are formed at diagonal corners.

【0006】また、同じような正負の電極配置を取った
他の従来例に、特開平8−274377号公報、発明の
名称:LEDランプ、出願人:日亜化学工業株式会社が
ある。
Another conventional example having the same positive and negative electrode arrangement is disclosed in Japanese Patent Application Laid-Open No. 8-274377, the title of which is LED lamp, and the applicant is Nichia Corporation.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上述の
電極用ワイヤボンディングパッド74及び75は光を透
過する厚さ以上膜厚の金属層を使用した非透光性電極で
あり、さらに、その大きさは通常約100μm角以上の
大きさを必要とするため、正負両電極を素子の対角位置
の隅部に形成する構造の発光素子の発光パターンは中心
部でくびれ、両側に略正方形の暗黒部のある複雑な発光
パターン形状となる。
However, the above-mentioned wire bonding pads 74 and 75 for electrodes are non-light-transmitting electrodes using a metal layer having a thickness greater than the thickness of transmitting light. Usually requires a size of about 100 μm square or more. Therefore, the light emitting pattern of a light emitting device having a structure in which both positive and negative electrodes are formed at diagonal corners of the device is constricted at the center and a substantially square dark portion is formed on both sides. It has a complicated light emitting pattern shape.

【0008】図9はこのような正負両電極の配置を持つ
発光素子77をレンズ付き樹脂モールドの半導体装置
(LEDランプ)として組み立てた場合の発光パターン
を説明する図であり、レンズ付き樹脂モールドLEDラ
ンプ78を見る方向、例えば79の方向及び80の方向
によって、発光パターンは非対称な形81、82とな
る。従って、このような指向特性を持つLEDランプ
を、他のランプと組み合わせて、例えばフルカラーディ
スプレーパネルを組み立てた場合には、見る角度によ
り、他のLEDとの混合、混色割合が変化し、輝度ム
ラ、色ムラと認識されていた。
FIG. 9 is a view for explaining a light emitting pattern when the light emitting element 77 having such an arrangement of the positive and negative electrodes is assembled as a resin-molded semiconductor device (LED lamp) with a lens. Depending on the direction in which the lamp 78 is viewed, for example, the directions of 79 and 80, the light emission pattern has asymmetric shapes 81 and. Therefore, when an LED lamp having such directional characteristics is combined with another lamp, for example, when a full-color display panel is assembled, the ratio of mixing and color mixing with the other LEDs changes depending on the viewing angle, resulting in uneven brightness. Was recognized as color unevenness.

【0009】また、電極が発光素子の対角位置に在るこ
とから、図10に示すような表面実装型のランプ83へ
の発光素子77を取付の際に、電極84、85にワイヤ
ボンディングされたワイヤ86、87が出射光を遮らな
いように発光素子77の発光部88の前面を横切らない
ように引き回すためには、図10(a)のように、ワイ
ヤがリードフレーム等に接続する電極端子89、90が
発光素子の両側、あるいは同図(b)に示すように、2
辺の側に形成する必要があり、発光素子を組み込んだラ
ンプ等の小型化を阻んでいた。また、図10(c)は図
10(a)または図10(b)の略断面図であり、表面
実装型の半導体発光装置83のモールドケース91の底
面92には、電極端子89、90及び半導体発光素子7
7の電極84、85と電極端子89、90とをワイヤボ
ンディングするワイヤ86、87がある。
Further, since the electrodes are located at diagonal positions of the light emitting element, when the light emitting element 77 is mounted on a surface mount type lamp 83 as shown in FIG. In order to route the wires 86 and 87 so as not to cross the front surface of the light emitting portion 88 of the light emitting element 77 so as not to block the emitted light, as shown in FIG. The terminals 89 and 90 are connected to both sides of the light emitting element or as shown in FIG.
It must be formed on the side of the side, which hinders miniaturization of a lamp or the like incorporating a light emitting element. FIG. 10C is a schematic sectional view of FIG. 10A or FIG. 10B. The electrode terminals 89 and 90 and the electrode terminals 89 and 90 are provided on the bottom surface 92 of the mold case 91 of the surface-mounted semiconductor light emitting device 83. Semiconductor light emitting element 7
There are wires 86 and 87 for wire bonding between the electrodes 84 and 85 and the electrode terminals 89 and 90.

【0010】また、図11は、発光素子を複数個用いて
アレイ状の表面実装型の半導体発光装置に組み立てた場
合の構成を示す図であり、図11(a)は給電用の共通
配線95、96に対して、発光素子の辺を平行に配列し
た場合の平面図であり、図11(b)は給電用の共通配
線に対して、発光素子の辺を菱形に配列した場合の平面
図である。
FIG. 11 is a diagram showing a configuration in which a plurality of light emitting elements are assembled into a surface-mounted semiconductor light emitting device in an array, and FIG. , 96 are arranged in parallel with the sides of the light emitting elements, and FIG. 11B is a plan view in which the sides of the light emitting elements are arranged in a rhombus shape with respect to the common wiring for power supply. It is.

【0011】図11(a)において、切片g−g′とh
−h′における光強度分布は93、94にそれぞれ示さ
れるように最高となる位置がズレるため、例えば原稿読
み取り光源に使った場合、読み取り精度の低下を来す原
因となっていた。この読み取り精度を維持するためには
図11(b)の配置とすることが必要であり、発光素子
は平行軸に対して45度に傾けて(発光素子の辺を菱形
に配列して)配列する必要があり、アレイ状の表面実装
型の半導体発光装置光源の外形サイズが大きくなるとい
う問題点があった。図11(a)及び図11(b)にお
いて、77は発光素子、84、85は半導体発光素子7
7の電極、86、87はワイヤボンディングのワイヤ、
88は発光素子77の発光部、89、90は電極端子、
95、96は給電用の共通配線である。
In FIG. 11 (a), sections gg 'and h
Since the light intensity distribution at -h 'is shifted from the highest position as shown by 93 and 94, for example, when it is used as a document reading light source, it causes a decrease in reading accuracy. In order to maintain this reading accuracy, the arrangement shown in FIG. 11B is necessary. The light emitting elements are arranged at an angle of 45 degrees with respect to the parallel axis (the sides of the light emitting elements are arranged in a rhombus). Therefore, there is a problem that the outer size of the light source of the surface-mount type semiconductor light emitting device in the form of an array becomes large. 11A and 11B, 77 is a light emitting element, and 84 and 85 are semiconductor light emitting elements 7
7, electrodes 86 and 87 are wires for wire bonding,
88 is a light emitting portion of the light emitting element 77, 89 and 90 are electrode terminals,
Reference numerals 95 and 96 are common wirings for power supply.

【0012】[0012]

【課題を解決するための手段】本発明の請求項1記載の
半導体発光素子は、絶縁性基板上に形成されたものであ
り、該半導体発光素子は少なくとも発光部及び正電極用
ワイヤボンディングパッド及び負電極用ワイヤボンディ
ングパッドを有し、該正電極用ワイヤボンディングパッ
ド及び該負電極用ワイヤボンディングパッドを近接して
配設し、且つ該正電極用ワイヤボンディングパッド及び
該負電極用ワイヤボンディングパッドの外形が形作る長
辺部側に近接して該半導体発光素子の発光部を配設する
ことを特徴とするものである。
According to a first aspect of the present invention, there is provided a semiconductor light emitting device formed on an insulating substrate, wherein the semiconductor light emitting device includes at least a light emitting portion, a wire bonding pad for a positive electrode, and A wire bonding pad for the negative electrode, the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode are disposed in close proximity to each other, and the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode; The light-emitting portion of the semiconductor light-emitting element is disposed close to a long side portion formed by an outer shape.

【0013】また、本発明の請求項2記載の半導体発光
素子は、前記絶縁性基板の面積をS1、発光部の面積を
2、正電極用ワイヤボンディングパッドと負電極用ワ
イヤボンディングパッドとの面積の和をS3とする時、
1≧S2+S3であり、且つ、S2≧S3であることを特
徴とするものである。
According to a second aspect of the present invention, in the semiconductor light emitting device, the area of the insulating substrate is S 1 , the area of the light emitting section is S 2 , and a positive electrode wire bonding pad and a negative electrode wire bonding pad are provided. the sum of the area when the S 3,
S 1 ≧ S 2 + S 3 , and S 2 ≧ S 3 .

【0014】また、本発明の請求項3記載の半導体発光
素子は、該発光素子の発光部の形状がほぼ正方形または
ほぼ長方形であることを特徴とするものである。
According to a third aspect of the present invention, there is provided the semiconductor light emitting device, wherein the shape of the light emitting portion of the light emitting device is substantially square or substantially rectangular.

【0015】また、本発明の請求項4記載の半導体発光
素子は、該発光素子の発光部の形状がほぼ円形またはほ
ぼ多角形であることを特徴とするものである。
According to a fourth aspect of the present invention, in the semiconductor light emitting device, the light emitting portion of the light emitting device has a substantially circular or substantially polygonal shape.

【0016】さらに、本発明の請求項5記載の半導体発
光装置は、請求項1記載の半導体発光素子を用いて実装
したことを特徴とするものである。
Furthermore, a semiconductor light emitting device according to a fifth aspect of the present invention is characterized by being mounted using the semiconductor light emitting element according to the first aspect.

【0017】[0017]

【発明の実施の形態】図1乃至図7は本発明の一実施の
形態に関する図である。以下に、本発明の実施の形態に
ついて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 7 relate to an embodiment of the present invention. Hereinafter, embodiments of the present invention will be described.

【0018】[実施の形態1]図1は、本発明の第1の
実施の形態よりなる発光素子の構成を示す図であり、図
1(a)は平面図であり、図1(b)は模式断面図であ
る。
[Embodiment 1] FIG. 1 is a diagram showing a configuration of a light emitting device according to a first embodiment of the present invention, FIG. 1 (a) is a plan view, and FIG. Is a schematic sectional view.

【0019】図1(a)において、10はサファイア基
板(約350μmの正方形)であり、18は発光部(約
300μm×170μmの長方形)であり、15は正電
極用ワイヤボンディングパッド、17は負電極用ワイヤ
ボンディングパッドであり、正負の電極用ワイヤボンデ
ィングパッド(各約130μmの正方形)15及び17
はサファイア基板上で近接して配設されており、且つ該
正電極用ワイヤボンディングパッド及び該負電極用ワイ
ヤボンディングパッドの外形が形作る長辺部側に近接し
て該半導体発光素子の発光部が配設されている。図1
(a)のA−A′線で切断した略断面図を図1(b)に
示す。
In FIG. 1A, 10 is a sapphire substrate (square of about 350 μm), 18 is a light emitting portion (rectangular of about 300 μm × 170 μm), 15 is a wire bonding pad for a positive electrode, and 17 is a negative electrode. Wire bonding pads for electrodes, and wire bonding pads for positive and negative electrodes (squares of about 130 μm each) 15 and 17
Are disposed close to each other on the sapphire substrate, and the light emitting portion of the semiconductor light emitting element is disposed close to the long side formed by the outer shape of the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode. It is arranged. FIG.
FIG. 1B is a schematic sectional view taken along the line AA ′ of FIG.

【0020】さらに、図1(a)において、絶縁性基板
の面積のS1は約350μmの正方形であり、S1=約
0.123mm2であり、発光部の面積のS2は約300
μm×170μmの長方形であり、S2=約0.051
mm2であり、正電極用ワイヤボンディングパッドと負
電極用ワイヤボンディングパッドとの面積の和のS
3は、各約130μmの正方形の約2倍であり、S3=約
0.034mm2である。この時、S1〜3.6×S3
2〜1.5×S3となっている。また、正負の正電極用
ワイヤボンディングパッドは各約100μm角〜約16
0μm角程度の大きさが必要であり、この時は、S2
>1.0×S3となっている。従って、各面積の関係
は、S1≧S2+S3であり、且つ、S2≧S3の関係にあ
る。
Further, in FIG. 1A, the area S 1 of the insulating substrate is a square of about 350 μm, S 1 = about 0.123 mm 2 , and the area S 2 of the light emitting section is about 300
μm × 170 μm, S 2 = about 0.051
mm 2 and the sum of the areas of the positive electrode wire bonding pad and the negative electrode wire bonding pad is S
3 is about twice as large as each about 130 μm square, S 3 = about 0.034 mm 2 . At this time, S 1 to 3.6 × S 3 ,
S 2 to 1.5 × S 3 . The wire bonding pads for the positive and negative positive electrodes are each about 100 μm square to about 16 μm square.
It is necessary to 0μm angle about the size, at this time, S 2 ~
> 1.0 × S 3 . Therefore, the relationship between the areas is S 1 ≧ S 2 + S 3 and S 2 ≧ S 3 .

【0021】図1(b)において、サファイア基板10
上に、基板と略平行の面が−部露出したn型AlXGaY
In1-X-YN層(0≦X≦1、0≦Y≦1)11が形成
され、その上には、発光層であるAlZGaTIn1-Z-T
N層(0≦Z≦1、0≦T≦1)層12、p型AlU
VIn1-U-VN層(0≦U≦1、0≦V≦1)13が積
層されている。正電極14は、p型AlUGaVIn
1-U-VN層13に形成され、その上に正電極用ワイヤボ
ンディングパッド(以下、正電極パッドと呼ぶ)15を
形成する。負電極16はn型AlXGaYIn1-X-YN層
11の一部露出した面上に形成され、その上に負電極用
ワイヤボンディングパッド(以下、負電極パッドと呼
ぶ)17を形成する。図1(a)で示した発光部18
は、n型AlXGaYIn1-X-YN層11、AlZGaT
1-Z-TN層12、p型AlUGaVIn1-U-VN層13よ
り構成されている。
In FIG. 1B, a sapphire substrate 10
An n-type Al X Ga Y with a surface substantially parallel to the substrate exposed at the − side
In 1-XY N layer (0 ≦ X ≦ 1,0 ≦ Y ≦ 1) 11 is formed, on the same, and a light emitting layer Al Z Ga T In 1-ZT
N layer (0 ≦ Z ≦ 1, 0 ≦ T ≦ 1) layer 12, p-type Al U G
a V In 1-UV N layers (0 ≦ U ≦ 1, 0 ≦ V ≦ 1) 13 are laminated. The positive electrode 14 is made of p-type Al U Ga V In
A 1-UV N layer 13 is formed on which a wire bonding pad for a positive electrode (hereinafter, referred to as a positive electrode pad) 15 is formed. The negative electrode 16 is formed on a partly exposed surface of the n-type Al X Ga Y In 1-XY N layer 11, and a negative electrode wire bonding pad (hereinafter, referred to as a negative electrode pad) 17 is formed thereon. . The light emitting unit 18 shown in FIG.
Are n-type Al X Ga Y In 1-XY N layers 11, Al Z Ga T I
It comprises an n 1 -ZTN layer 12 and a p-type Al U Ga V In 1 -UV N layer 13.

【0022】図2は、図1の発光素子をレンズ付き樹脂
モールドの発光ダイオードランプにしたところ、垂直軸
上方向(19)は勿論のこと右方向(20)及び左方向
(21)においてもほぼ滑らかな指向特性を得ることが
できた。
FIG. 2 shows that the light emitting element of FIG. 1 is a resin-molded light emitting diode lamp with a lens. The light emitting element is substantially not only in the vertical direction (19) but also in the right direction (20) and the left direction (21). Smooth directional characteristics could be obtained.

【0023】図3は、本発明の第1の実施の形態よりな
る発光素子を用いて表面実装型の半導体発光装置に組み
立てた場合の構成を示す図であり、図3(a)は平面図
であり、図3(b)はB−B′線で切断した略断面図で
ある。
FIG. 3 is a diagram showing a configuration in a case where the light emitting device according to the first embodiment of the present invention is used to assemble a surface-mounted semiconductor light emitting device. FIG. 3 (a) is a plan view. FIG. 3B is a schematic sectional view taken along the line BB '.

【0024】図3(a)において、10はサファイア基
板(約350μmの正方形)であり、18は発光部(約
300μm×170μmの長方形)であり、15は正電
極用ワイヤボンディングパッド、17は負電極用ワイヤ
ボンディングパッドであり、正負の電極用ワイヤボンデ
ィングパッド(各約130μmの正方形)15及び17
はサファイア基板上で近接して配設されており、且つ該
正電極用ワイヤボンディングパッド及び該負電極用ワイ
ヤボンディングパッドの外形が形作る長辺部側に近接し
て該半導体発光素子の発光部が配設されている。22及
び23は表面実装型の半導体発光装置のモールドケース
26の底面にメッキ等の手法により形成された電極端子
であり、金線24及び25によりそれぞれ22及び23
は正負の電極用ワイヤボンディングパッド15及び17
と電気的にワイヤボンディングされている。
In FIG. 3A, reference numeral 10 denotes a sapphire substrate (square of about 350 μm), 18 denotes a light emitting portion (rectangle of about 300 μm × 170 μm), 15 denotes a wire bonding pad for a positive electrode, and 17 denotes a negative electrode. Wire bonding pads for electrodes, and wire bonding pads for positive and negative electrodes (squares of about 130 μm each) 15 and 17
Are disposed close to each other on the sapphire substrate, and the light emitting portion of the semiconductor light emitting element is disposed close to the long side formed by the outer shape of the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode. It is arranged. Reference numerals 22 and 23 denote electrode terminals formed on the bottom surface of the mold case 26 of the surface-mount type semiconductor light emitting device by plating or the like.
Are wire bonding pads 15 and 17 for positive and negative electrodes
And is electrically wire-bonded.

【0025】図3(b)において、表面実装型の半導体
発光装置のモールドケース26の底面27には、電極端
子23及びサファイア基板10が配設されており、サフ
ァイア基板10上には発光部18があり、電極端子23
と負電極用ワイヤボンディングパッド17とを金線25
により電気的にワイヤボンディングされている。また2
8は透明なモールド樹脂である。電極端子22及び23
を発光素子の片側に集めることが出来て、発光素子を組
み込んだ表面実装型の半導体発光装置の小型化が図れ
た。具体的には、図3(a)及び図3(b)に示された
表面実装型の半導体発光装置の外形サイズは、縦約1.
2mm×横約1.8mm×高さ約1.2mm程度とな
り、従来例の外形サイズ縦約1.2mm×横約2.0〜
2.3mm×高さ約1.2mm程度より小型することが
出来た。
In FIG. 3B, an electrode terminal 23 and a sapphire substrate 10 are provided on a bottom surface 27 of a mold case 26 of the surface-mount type semiconductor light emitting device. And electrode terminals 23
And the wire bonding pad 17 for the negative electrode
Are electrically wire-bonded. Also 2
8 is a transparent mold resin. Electrode terminals 22 and 23
Can be collected on one side of the light emitting element, and the size of the surface mount type semiconductor light emitting device incorporating the light emitting element can be reduced. Specifically, the external size of the surface-mount type semiconductor light emitting device shown in FIGS.
It is about 2mm x about 1.8mm x about 1.2mm in height.
It was possible to reduce the size to about 2.3 mm × about 1.2 mm in height.

【0026】図4は、本発明の第1の実施の形態よりな
る発光素子を複数個用いて表面実装型の半導体発光装置
に組み立てた場合の構成を示す図であり、1個の発光素
子を用いて表面実装型の半導体発光装置に組み立てた図
3と異なり、表面実装型の半導体発光装置のモールドケ
ース29の底面にメッキ等の手法により形成されたそれ
ぞれの電極端子30及び31は共通ライン32及び33
により電気的に結線されている。24、25は電極端子
30及び31と正負の電極パッド15及び17とを結線
する金線ワイヤである。この結果、正負の電極は近接し
て配設されており、且つ該正電極用ワイヤボンディング
パッド及び該負電極用ワイヤボンディングパッドの外形
が形作る長辺部側に近接して該半導体発光素子の発光部
を配設さすることにより、発光素子からの金線ワイヤを
同−辺側に引き出すことが出来て、また、従来例の図1
1(a)で問題になった光強度の軸上のズレの問題を、
図11(b)の斜め配置を使わずとも解決することが出
来た。
FIG. 4 is a diagram showing a configuration in which a plurality of light emitting elements according to the first embodiment of the present invention are used to assemble them into a surface-mounted semiconductor light emitting device. 3, the electrode terminals 30 and 31 formed on the bottom surface of the mold case 29 of the surface-mounted semiconductor light emitting device by plating or the like are different from those in FIG. And 33
Are electrically connected to each other. Reference numerals 24 and 25 are gold wires connecting the electrode terminals 30 and 31 and the positive and negative electrode pads 15 and 17, respectively. As a result, the positive and negative electrodes are arranged close to each other, and the semiconductor light emitting element emits light in the vicinity of the long side formed by the outer shape of the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode. By disposing the portion, the gold wire from the light emitting element can be pulled out to the same side, and the conventional example shown in FIG.
The problem of the deviation of the light intensity on the axis, which was a problem in 1 (a),
The problem could be solved without using the oblique arrangement shown in FIG.

【0027】[実施の形態2]図5は、本発明の第2の
実施の形態よりなる発光素子の構成を示す図であり、発
光部34はほぼ正方形に形作られたものであり、図5
(a)は平面図であり、図5(b)は模式断面図であ
る。
[Embodiment 2] FIG. 5 is a diagram showing a configuration of a light emitting device according to a second embodiment of the present invention. The light emitting section 34 is formed in a substantially square shape.
5A is a plan view, and FIG. 5B is a schematic sectional view.

【0028】図5(a)において、35はサファイア基
板(約350μm×約480μmの長方形)であり、3
4は発光部(約300μm×約300μmの正方形)で
あり、15は正電極用ワイヤボンディングパッド、17
は負電極用ワイヤボンディングパッドである。正負の電
極用ワイヤボンディングパッド(各約130μmの正方
形)15及び17はサファイア基板上で近接して配設さ
れており、且つ該正電極用ワイヤボンディングパッド及
び該負電極用ワイヤボンディングパッドの外形が形作る
長辺部側に近接して該半導体発光素子の発光部が配設さ
れている。図5(a)のC−C′線で切断した略断面図
を図5(b)に示す。
In FIG. 5A, reference numeral 35 denotes a sapphire substrate (about 350 μm × about 480 μm rectangle).
Reference numeral 4 denotes a light-emitting portion (a square of about 300 μm × about 300 μm), 15 denotes a wire bonding pad for a positive electrode,
Denotes a wire bonding pad for a negative electrode. The positive and negative electrode wire bonding pads (each about 130 μm square) 15 and 17 are arranged close to each other on the sapphire substrate, and the outer shape of the positive electrode wire bonding pad and the negative electrode wire bonding pad is A light-emitting portion of the semiconductor light-emitting element is disposed near the long side portion to be formed. FIG. 5B is a schematic sectional view taken along the line CC ′ of FIG.

【0029】さらに、図5(a)において、絶縁性基板
の面積のS1は約350μm×約480μmの長方形で
あり、S1=約0.168mm2であり、発光部の面積の
2は約300μm×約300μmの正方形であり、S2
=約0.09mm2であり、正電極用ワイヤボンディン
グパッドと負電極用ワイヤボンディングパッドとの面積
の和のS3は、各約130μmの正方形の約2倍であ
り、S3=約0.034mm2である。この時、S1
4.9×S3、S2〜2.7×S3となっている。また、
正負の正電極用ワイヤボンディングパッドは各約100
μm角〜約160μm角程度の大きさが必要であり、こ
の時は、S2〜>1.8×S3となっている。従って、各
面積の関係は、S1≧S2+S3であり、且つ、S2≧S3
の関係にある。
Further, in FIG. 5A, the area S 1 of the insulating substrate is a rectangle of about 350 μm × about 480 μm, S 1 = about 0.168 mm 2 , and the area S 2 of the light emitting portion is It is a square of about 300 μm × about 300 μm, and S 2
= 0.09 mm 2 , the sum of the area of the positive electrode wire bonding pad and the area of the negative electrode wire bonding pad, S 3, is about twice the square of about 130 μm each, and S 3 = about 0.03 mm. 034 mm 2 . At this time, S 1 ~
4.9 × S 3 and S 2 to 2.7 × S 3 . Also,
Each wire bonding pad for positive and negative electrodes is about 100
It requires μm square to about 160μm square about the size, when this has a S 2 ~> 1.8 × S 3 . Accordingly, the relationship between the areas is S 1 ≧ S 2 + S 3 , and S 2 ≧ S 3
In a relationship.

【0030】図5(b)において、サファイア基板35
上に、基板と略平行の面が−部露出したn型AlXGaY
In1-X-YN層(0≦X≦1、0≦Y≦1)11が形成
され、その上には、発光層であるAlZGaTIn1-Z-T
N層(0≦Z≦1、0≦T≦1)層12、p型AlU
VIn1-U-VN層(0≦U≦1、0≦V≦1)13が積
層されている。正電極14は、p型AlUGaVIn
1-U-VN層13に形成され、その上に正電極用ワイヤボ
ンディングパッド15を形成する。負電極16はn型A
XGaYIn1-X-YN層11の一部露出した面上に形成
され、その上に負電極用ワイヤボンディングパッド17
を形成する。図5(a)の発光部34は、n型AlX
YIn1-X-YN層11、AlZGaTIn1-Z-TN層1
2、p型AlUGaVIn1-U-VN層13より構成されて
いる。
In FIG. 5B, the sapphire substrate 35
An n-type Al X Ga Y with a surface substantially parallel to the substrate exposed at the − side
In 1-XY N layer (0 ≦ X ≦ 1,0 ≦ Y ≦ 1) 11 is formed, on the same, and a light emitting layer Al Z Ga T In 1-ZT
N layer (0 ≦ Z ≦ 1, 0 ≦ T ≦ 1) layer 12, p-type Al U G
a V In 1-UV N layers (0 ≦ U ≦ 1, 0 ≦ V ≦ 1) 13 are laminated. The positive electrode 14 is made of p-type Al U Ga V In
A 1-UV N layer 13 is formed on which a wire bonding pad 15 for a positive electrode is formed. Negative electrode 16 is n-type A
l X Ga Y In 1-XY N layer 11 is formed on a part exposed on the surface of the wire bonding pads 17 for the negative electrode is formed thereon
To form The light emitting section 34 in FIG. 5A is an n-type Al X G
a Y In 1-XY N layer 11, Al Z Ga T In 1 -ZT N layer 1
2, and it is composed of p-type Al U Ga V In 1-UV N layer 13.

【0031】正負の電極用ワイヤボンディングパッド
(各約130μmの正方形)15及び17はサファイア
基板35上で近接して配設されている。この電極配置に
より、正方形の発光部34を得ることが出来た。この発
光素子により、図2で示したような左右対称な発光パタ
ーンを実現出来た。
The wire bonding pads for positive and negative electrodes (squares of about 130 μm each) 15 and 17 are arranged close to each other on the sapphire substrate 35. With this electrode arrangement, a square light emitting section 34 could be obtained. With this light emitting element, a symmetrical light emitting pattern as shown in FIG. 2 was realized.

【0032】[実施の形態3]図6は、本発明の第3の
実施の形態よりなる発光素子の構成を示す図であり、発
光部36はほぼ円形に形作られたものであり、図6
(a)は平面図であり、図6(b)は模式断面図であ
る。
[Embodiment 3] FIG. 6 is a view showing a structure of a light emitting device according to a third embodiment of the present invention. The light emitting section 36 is formed in a substantially circular shape.
FIG. 6A is a plan view, and FIG. 6B is a schematic sectional view.

【0033】図6(a)において、35はサファイア基
板(約350μm×約480μmの長方形)であり、3
6は発光部(直径約300μmの円形)であり、15は
正電極用ワイヤボンディングパッド、17は負電極用ワ
イヤボンディングパッドである。正負の電極用ワイヤボ
ンディングパッド(各約130μmの正方形)15及び
17はサファイア基板上で近接して配設されており、且
つ該正電極用ワイヤボンディングパッド及び該負電極用
ワイヤボンディングパッドの外形が形作る長辺部側に近
接して該半導体発光素子の発光部が配設されている。図
6(a)のD−D′線で切断した略断面図を図6(b)
に示す。
In FIG. 6A, reference numeral 35 denotes a sapphire substrate (a rectangle of about 350 μm × about 480 μm),
Reference numeral 6 denotes a light emitting portion (circle having a diameter of about 300 μm), reference numeral 15 denotes a positive electrode wire bonding pad, and reference numeral 17 denotes a negative electrode wire bonding pad. The positive and negative electrode wire bonding pads (each about 130 μm square) 15 and 17 are arranged close to each other on the sapphire substrate, and the outer shape of the positive electrode wire bonding pad and the negative electrode wire bonding pad is A light-emitting portion of the semiconductor light-emitting element is disposed near the long side portion to be formed. FIG. 6B is a schematic sectional view taken along line DD ′ of FIG.
Shown in

【0034】さらに、図6(a)において、絶縁性基板
の面積のS1は約350μm×約480μmの長方形で
あり、S1=約0.168mm2であり、発光部の面積の
2は直径約300μmの円形であり、S2=約0.07
1mm2であり、正電極用ワイヤボンディングパッドと
負電極用ワイヤボンディングパッドとの面積の和のS3
は、各約130μmの正方形の約2倍であり、S3=約
0.034mm2である。この時、S1〜4.9×S3
2〜2.1×S3となっている。また、正負の正電極用
ワイヤボンディングパッドは各約100μm角〜約16
0μm角程度の大きさが必要であり、この時は、S2
>1.4×S3となっている。従って、各面積の関係
は、S1≧S2+S3であり、且つ、S2≧S3の関係にあ
る。
Further, in FIG. 6A, the area S 1 of the insulating substrate is a rectangle of about 350 μm × about 480 μm, S 1 = about 0.168 mm 2 , and the area S 2 of the light emitting portion is It is a circle having a diameter of about 300 μm, and S 2 = about 0.07
1 mm 2 , the sum of the area of the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode, S 3
Is about twice as large as each 130 μm square, and S 3 = about 0.034 mm 2 . At this time, S 1 to 4.9 × S 3 ,
S 2 to 2.1 × S 3 . The wire bonding pads for the positive and negative positive electrodes are each about 100 μm square to about 16 μm square.
It is necessary to 0μm angle about the size, at this time, S 2 ~
> 1.4 × S 3 . Therefore, the relationship between the areas is S 1 ≧ S 2 + S 3 and S 2 ≧ S 3 .

【0035】図6(b)において、サファイア基板35
上に、基板と略平行の面が−部露出したn型AlXGaY
In1-X-YN層(0≦X≦1、0≦Y≦1)11が形成
され、その上には、発光層であるAlZGaTIn1-Z-T
N層(0≦Z≦1、0≦T≦1)層12、p型AlU
VIn1-U-VN層(0≦U≦1、0≦V≦1)13が積
層されている。正電極14は、p型AlUGaVIn
1-U-VN層13に形成され、その上に正電極用ワイヤボ
ンディングパッド15を形成する。負電極16はn型A
XGaYIn1-X-YN層11の一部露出した面上に形成
され、その上に負電極用ワイヤボンディングパッド17
を形成する。図6(a)の発光部36は、n型AlX
YIn1-X-YN層11、AlZGaTIn1-Z-TN層1
2、p型AlUGaVIn1-U-VN層13より構成されて
いる。
In FIG. 6B, the sapphire substrate 35
An n-type Al X Ga Y with a surface substantially parallel to the substrate exposed at the − side
In 1-XY N layer (0 ≦ X ≦ 1,0 ≦ Y ≦ 1) 11 is formed, on the same, and a light emitting layer Al Z Ga T In 1-ZT
N layer (0 ≦ Z ≦ 1, 0 ≦ T ≦ 1) layer 12, p-type Al U G
a V In 1-UV N layers (0 ≦ U ≦ 1, 0 ≦ V ≦ 1) 13 are laminated. The positive electrode 14 is made of p-type Al U Ga V In
A 1-UV N layer 13 is formed on which a wire bonding pad 15 for a positive electrode is formed. Negative electrode 16 is n-type A
l X Ga Y In 1-XY N layer 11 is formed on a part exposed on the surface of the wire bonding pads 17 for the negative electrode is formed thereon
To form The light emitting section 36 in FIG. 6A is an n-type Al X G
a Y In 1-XY N layer 11, Al Z Ga T In 1 -ZT N layer 1
2, and it is composed of p-type Al U Ga V In 1-UV N layer 13.

【0036】正負の電極用ワイヤボンディングパッド
(各約130μmの正方形)15及び17はサファイア
基板35上で近接して配設されており、且つ該正電極用
ワイヤボンディングパッド及び該負電極用ワイヤボンデ
ィングパッドの外形が形作る長辺部側に近接して該半導
体発光素子の発光部が配設されている。この電極配置に
より、正方形の発光部34を得ることが出来た。この発
光素子により、図2で示したような左右対称な発光パタ
ーンを実現出来た。
The wire bonding pads for positive and negative electrodes (squares of about 130 μm each) 15 and 17 are arranged close to each other on the sapphire substrate 35, and the wire bonding pads for positive electrode and the wire bonding for negative electrode are provided. A light-emitting portion of the semiconductor light-emitting element is disposed close to a long side formed by the outer shape of the pad. With this electrode arrangement, a square light emitting section 34 could be obtained. With this light emitting element, a symmetrical light emitting pattern as shown in FIG. 2 was realized.

【0037】特に本発明の円形の発光部の形は、発光素
子のリードフレーム等への実装時に、取付角度を選ばな
いという利点がある。すなわち、点対称でない発光部の
形の発光素子を軸対称形のリードフレームに取り付ける
場合には、取付角度によりリードフレームの方向に対す
る発光の指向パターンが異なっていたが、本実施例で
は、この問題を回避することができる。
In particular, the shape of the circular light emitting portion of the present invention has an advantage that the mounting angle can be selected when the light emitting element is mounted on a lead frame or the like. That is, when a light emitting element in the form of a light emitting portion that is not point-symmetrical is mounted on an axially symmetrical lead frame, the directional pattern of light emission with respect to the direction of the lead frame differs depending on the mounting angle. Can be avoided.

【0038】[実施の形態4]図7は、本発明の第4の
実施の形態よりなる発光素子の構成を示す図であり、発
光部37はほぼ多角形に形作られたものであり、図7
(a)は平面図であり、図7(b)は模式断面図であ
る。
[Embodiment 4] FIG. 7 is a view showing a structure of a light emitting device according to a fourth embodiment of the present invention, in which a light emitting section 37 is formed in a substantially polygonal shape. 7
7A is a plan view, and FIG. 7B is a schematic sectional view.

【0039】図7(a)において、35はサファイア基
板(約350μm×約480μmの長方形)であり、3
7は発光部(外径が約300μmの多角形)であり、1
5は正電極用ワイヤボンディングパッド、17は負電極
用ワイヤボンディングパッドである。正負の電極用ワイ
ヤボンディングパッド(各約130μmの正方形)15
及び17はサファイア基板上で近接して配設されてお
り、且つ該正電極用ワイヤボンディングパッド及び該負
電極用ワイヤボンディングパッドの外形が形作る長辺部
側に近接して該半導体発光素子の発光部が配設されてい
る。図7(a)のE−E′線で切断した略断面図を図7
(b)に示す。
In FIG. 7A, reference numeral 35 denotes a sapphire substrate (a rectangle of about 350 μm × about 480 μm).
Reference numeral 7 denotes a light emitting portion (polygon having an outer diameter of about 300 μm),
5 is a wire bonding pad for a positive electrode, and 17 is a wire bonding pad for a negative electrode. Wire bonding pads for positive and negative electrodes (square of about 130 μm each) 15
And 17 are disposed close to each other on the sapphire substrate, and emit light of the semiconductor light emitting element in the vicinity of a long side formed by the outer shape of the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode. Department is arranged. FIG. 7A is a schematic sectional view taken along the line EE ′ of FIG.
(B).

【0040】図7(b)において、サファイア基板35
上に、基板と略平行の面が−部露出したn型AlXGaY
In1-X-YN層(0≦X≦1、0≦Y≦1)11が形成
され、その上には、発光層であるAlZGaTIn1-Z-T
N層(0≦Z≦1、0≦T≦1)層12、p型AlU
VIn1-U-VN層(0≦U≦1、0≦V≦1)13が積
層されている。正電極14は、p型AlUGaVIn
1-U-VN層13に形成され、その上に正電極用ワイヤボ
ンディングパッド15を形成する。負電極16はn型A
XGaYIn1-X-YN層11の一部露出した面上に形成
され、その上に負電極用ワイヤボンディングパッド17
を形成する。図7(a)の発光部37は、n型AlX
YIn1-X-YN層11、AlZGaTIn1-Z-TN層1
2、p型AlUGaVIn1-U-VN層13より構成されて
いる。正負の電極用ワイヤボンディングパッド(各約1
30μmの正方形)15及び17はサファイア基板35
上で近接して配設されており、且つ該正電極用ワイヤボ
ンディングパッド及び該負電極用ワイヤボンディングパ
ッドの外形が形作る長辺部側に近接して該半導体発光素
子の発光部が配設されている。この電極配置により、多
角形の発光部37を得ることが出来た。この発光素子に
より、図2で示したような左右対称な発光パターンを実
現出来た。
In FIG. 7B, the sapphire substrate 35
An n-type Al X Ga Y with a surface substantially parallel to the substrate exposed at the − side
In 1-XY N layer (0 ≦ X ≦ 1,0 ≦ Y ≦ 1) 11 is formed, on the same, and a light emitting layer Al Z Ga T In 1-ZT
N layer (0 ≦ Z ≦ 1, 0 ≦ T ≦ 1) layer 12, p-type Al U G
a V In 1-UV N layers (0 ≦ U ≦ 1, 0 ≦ V ≦ 1) 13 are laminated. The positive electrode 14 is made of p-type Al U Ga V In
A 1-UV N layer 13 is formed on which a wire bonding pad 15 for a positive electrode is formed. Negative electrode 16 is n-type A
l X Ga Y In 1-XY N layer 11 is formed on a part exposed on the surface of the wire bonding pads 17 for the negative electrode is formed thereon
To form The light emitting section 37 in FIG. 7A is an n-type Al X G
a Y In 1-XY N layer 11, Al Z Ga T In 1 -ZT N layer 1
2, and it is composed of p-type Al U Ga V In 1-UV N layer 13. Wire bonding pads for positive and negative electrodes (each about 1
30 μm squares) 15 and 17 are sapphire substrates 35
A light-emitting portion of the semiconductor light-emitting element, which is disposed close to the top of the semiconductor light-emitting element, and is disposed close to a long side formed by the outer shape of the positive electrode wire bonding pad and the negative electrode wire bonding pad. ing. With this electrode arrangement, a polygonal light emitting portion 37 could be obtained. With this light emitting element, a symmetrical light emitting pattern as shown in FIG. 2 was realized.

【0041】特に本発明の多角形の発光部の形は、その
形が円形に近付くほどリードフレーム等への実装時に、
取付角度を選ばないという利点が発生する。すなわち、
点対称でない発光パターンの場合には、軸対称形のリー
ドフレームに取り付ける場合には、取付角度によりリー
ドフレームの方向に対する発光の指向パターンが異なっ
ていたが、本実施例では、この問題を無視できるほど低
減できた。
In particular, the shape of the polygonal light emitting portion of the present invention is such that the closer the shape becomes to a circular shape, the more the light emitting portion is mounted on a lead frame or the like.
There is an advantage that the mounting angle is not selected. That is,
In the case of a light-emitting pattern that is not point-symmetric, when the light-emitting pattern is mounted on an axially symmetrical lead frame, the directional pattern of light emission with respect to the direction of the lead frame differs depending on the mounting angle. In the present embodiment, this problem can be ignored. Could be reduced.

【0042】[0042]

【発明の効果】以上のように、本発明の請求項1記載の
半導体発光素子によれば、絶縁性基板上に形成された半
導体発光素子であり、該半導体発光素子は少なくとも発
光部及び正電極用ワイヤボンディングパッド及び負電極
用ワイヤボンディングパッドを有し、該正電極用ワイヤ
ボンディングパッド及び該負電極用ワイヤボンディング
パッドを近接して配設し、且つ該正電極用ワイヤボンデ
ィングパッド及び該負電極用ワイヤボンディングパッド
の外形が形作る長辺部側に近接して該半導体発光素子の
発光部を配設することを特徴とするものであり、外部よ
り半導体発光素子に電流を流すための2本のリードワイ
ヤを一方向に引き出すことが可能となり、半導体発光素
子の小型化を図ることが出来た。また、発光部の形状が
単純な形状となったことで、半導体製造装置に組み立て
た場合、左右対称な発光パターン(放射特性)を得るこ
とが出来る。さらに、本発明の複数個の半導体発光素子
をアレイ状に並べた場合、明るさ(輝度)のむらを低減
することが出来た。
As described above, according to the semiconductor light emitting device of the first aspect of the present invention, the semiconductor light emitting device is formed on an insulating substrate, and the semiconductor light emitting device includes at least a light emitting portion and a positive electrode. A wire bonding pad for the positive electrode and a wire bonding pad for the negative electrode, the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode are disposed in close proximity to each other, and the wire bonding pad for the positive electrode and the negative electrode A light emitting portion of the semiconductor light emitting device is disposed close to a long side portion formed by an outer shape of a wire bonding pad for forming a wire. The lead wire can be pulled out in one direction, and the size of the semiconductor light emitting device can be reduced. Further, since the light emitting portion has a simple shape, a symmetrical light emitting pattern (radiation characteristic) can be obtained when the light emitting portion is assembled in a semiconductor manufacturing apparatus. Furthermore, when a plurality of semiconductor light emitting devices of the present invention are arranged in an array, unevenness in brightness (brightness) can be reduced.

【0043】また、本発明の請求項2記載の半導体発光
素子によれば、前記絶縁性基板の面積をS1、発光部の
面積をS2、正電極用ワイヤボンディングパッドと負電
極用ワイヤボンディングパッドとの面積の和をS3とす
る時、S1≧S2+S3であり、且つ、S2≧S3であるこ
とを特徴とするものであり、正負の正電極用ワイヤボン
ディングパッドは各約100μm角〜約160μm角程
度の大きさが必要であり、所定の絶縁性基板の面積に対
して、発光部の面積を多く設定することができ、半導体
発光素子の小型化を図ることができる。
According to the semiconductor light emitting device of the second aspect of the present invention, the area of the insulating substrate is S 1 , the area of the light emitting portion is S 2 , the positive electrode wire bonding pad and the negative electrode wire bonding. When the sum of the area of the pad and the pad is S 3 , S 1 ≧ S 2 + S 3 and S 2 ≧ S 3 , and the wire bonding pad for positive and negative positive electrodes is A size of about 100 μm square to about 160 μm square is required, and the area of the light emitting portion can be set to be larger than the area of the predetermined insulating substrate, so that the size of the semiconductor light emitting element can be reduced. it can.

【0044】また、本発明の請求項3記載の半導体発光
素子によれば、該発光素子の発光部の形状がほぼ正方形
またはほぼ長方形であることを特徴とするものであり、
発光部の形状が単純な形状となったことで、半導体製造
装置に組み立てた場合、左右対称な発光パターン(放射
特性)を得ることが出来る。
According to a third aspect of the present invention, there is provided the semiconductor light emitting device, wherein the shape of the light emitting portion of the light emitting device is substantially square or substantially rectangular.
Since the light emitting portion has a simple shape, a symmetrical light emitting pattern (radiation characteristic) can be obtained when the light emitting portion is assembled in a semiconductor manufacturing apparatus.

【0045】また、本発明の請求項4記載の半導体発光
素子によれば、該発光素子の発光部の形状がほぼ円形ま
たはほぼ多角形であることを特徴とするものであり、発
光部の形状が単純な形状となったことで、半導体製造装
置に組み立てた場合、左右対称な発光パターン(放射特
性)を得ることが出来る。また、発光部の形状が正方
形、多角形、円形など特に点対称に近い場合、中心軸対
象の放射特性を得やすくなり、これを応用した半導体発
光装置、例えば、発光パネルの性能向上を図ることが出
来た。
According to the semiconductor light emitting device of the present invention, the shape of the light emitting portion of the light emitting device is substantially circular or substantially polygonal. Has a simple shape, so that when assembled in a semiconductor manufacturing apparatus, a symmetrical light-emitting pattern (radiation characteristic) can be obtained. In addition, when the shape of the light-emitting portion is particularly close to point symmetry, such as a square, a polygon, and a circle, it becomes easier to obtain the radiation characteristics of the center axis, and to improve the performance of a semiconductor light-emitting device, for example, a light-emitting panel to which this is applied. Was completed.

【0046】さらに、本発明の請求項5記載の半導体発
光装置によれば、請求項1記載の半導体発光素子を用い
て実装したものであり、滑らかな発光パターンを持つこ
とにより、特に集合ランプ型ディスプレー用として優れ
た指向特性を持つ半導体装置(LEDランプ)を得るこ
とができる。
Further, according to the semiconductor light emitting device of the fifth aspect of the present invention, the semiconductor light emitting device is mounted using the semiconductor light emitting element of the first aspect, and has a smooth light emitting pattern, and particularly has a collective lamp type. A semiconductor device (LED lamp) having excellent directivity for display can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態よりなる発光素子の
構成を示す図であり、(a)は平面図であり、(b)は
(a)のA−A′線で切断した略断面図である。
FIGS. 1A and 1B are diagrams showing a configuration of a light emitting device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line AA ′ of FIG. It is a schematic sectional drawing.

【図2】本発明の第1の実施の形態よりなる発光素子を
レンズ付き樹脂モールドした発光ダイオードランプの模
式図である。
FIG. 2 is a schematic diagram of a light emitting diode lamp in which a light emitting element according to the first embodiment of the present invention is resin-molded with a lens.

【図3】本発明の第1の実施の形態よりなる発光素子を
用いて表面実装型の半導体発光装置に組み立てた場合の
構成を示す図であり、(a)は平面図であり、(b)は
(a)のB−B′線で切断した略断面図である。
FIGS. 3A and 3B are diagrams showing a configuration when a light emitting element according to the first embodiment of the present invention is used to assemble a surface-mount type semiconductor light emitting device, wherein FIG. 3A is a plan view and FIG. () Is a schematic sectional view taken along the line BB 'of (a).

【図4】本発明の第1の実施の形態よりなる発光素子を
複数個用いて表面実装型の半導体発光装置に組み立てた
場合の構成を示す図である。
FIG. 4 is a diagram showing a configuration when a plurality of light emitting elements according to the first embodiment of the present invention are used to assemble a surface-mounted semiconductor light emitting device.

【図5】本発明の第2の実施の形態よりなる発光素子の
構成を示す図であり、発光部はほぼ正方形に形作られた
ものであり、(a)は平面図であり、(b)は(a)の
C−C′線で切断した略断面図である。
FIG. 5 is a diagram showing a configuration of a light emitting device according to a second embodiment of the present invention, in which a light emitting portion is formed in a substantially square shape, (a) is a plan view, and (b) FIG. 3 is a schematic sectional view taken along line CC ′ of FIG.

【図6】本発明の第3の実施の形態よりなる発光素子の
構成を示す図であり、発光部はほぼ円形に形作られたも
のであり、(a)は平面図であり、(b)は(a)のD
−D′線で切断した略断面図である。
FIG. 6 is a diagram showing a configuration of a light emitting device according to a third embodiment of the present invention, in which a light emitting portion is formed in a substantially circular shape, (a) is a plan view, and (b) Is D in (a)
It is the schematic sectional drawing cut | disconnected by the -D 'line.

【図7】本発明の第4の実施の形態よりなる発光素子の
構成を示す図であり、発光部はほぼ多角形に形作られた
ものであり、(a)は平面図であり、(b)は(a)の
E−E′線で切断した略断面図である。
FIG. 7 is a diagram showing a configuration of a light emitting device according to a fourth embodiment of the present invention, in which a light emitting portion is formed in a substantially polygonal shape, (a) is a plan view, and (b) is a plan view. () Is a schematic sectional view taken along line EE 'of (a).

【図8】従来例の窒化物系半導体材料を用いた窒化ガリ
ウム系化合物半導体発光素子の説明図であり、(a)は
平面図であり、(b)は(a)のF−F′線で切断した
略断面図である。
8A and 8B are explanatory views of a gallium nitride-based compound semiconductor light emitting device using a conventional nitride-based semiconductor material, wherein FIG. 8A is a plan view and FIG. 8B is an FF ′ line of FIG. It is the schematic sectional drawing cut | disconnected by.

【図9】従来例の窒化物系半導体材料を用いた窒化ガリ
ウム系化合物半導体発光素子をレンズ付き樹脂モールド
の半導体装置(LEDランプ)に組み立てた場合の発光
パターンを説明する図である。
FIG. 9 is a diagram illustrating a light emitting pattern when a gallium nitride based compound semiconductor light emitting element using a conventional nitride based semiconductor material is assembled into a resin molded semiconductor device (LED lamp) with a lens.

【図10】従来例の窒化物系半導体材料を用いた窒化ガ
リウム系化合物半導体発光素子を表面実装型のランプへ
実装した説明図であり、(a)及び(b)は平面図であ
り、(c)は(a)または(b)の略断面図である。
FIGS. 10A and 10B are explanatory views in which a gallium nitride-based compound semiconductor light-emitting device using a conventional nitride-based semiconductor material is mounted on a surface-mounted lamp; FIGS. 10A and 10B are plan views; (c) is a schematic sectional view of (a) or (b).

【図11】従来例の窒化物系半導体材料を用いた窒化ガ
リウム系化合物半導体発光素子を複数個用いてアレイ状
の表面実装型の半導体発光装置へ実装した説明図であ
り、(a)は給電用の共通配線95、96に対して、発
光素子の辺を平行に配列した場合の平面図であり、
(b)は給電用の共通配線に対して、発光素子の辺を菱
形に配列した場合の平面図である。
FIG. 11 is an explanatory view in which a plurality of gallium nitride-based compound semiconductor light-emitting elements using a conventional nitride-based semiconductor material are mounted on an array-type surface-mounted semiconductor light-emitting device using a plurality of light-emitting elements. FIG. 9 is a plan view when the sides of the light emitting element are arranged in parallel with the common wirings 95 and 96 for
(B) is a plan view in the case where the sides of the light emitting elements are arranged in a diamond shape with respect to the common wiring for power supply.

【符号の説明】[Explanation of symbols]

10 絶縁性基板であるサファイア基板 11 n型AlXGaYIn1-X-YN層(0≦X≦1、0
≦Y≦1) 12 発光層であるAlZGaTIn1-Z-TN層(0≦Z
≦1、0≦T≦1) 13 p型AlUGaVIn1-U-VN層(0≦U≦1、0
≦V≦1) 14 正電極 15 正電極用ワイヤボンディングパッド(以下、正電
極パッドと呼ぶ) 16 負電極 17 負電極用ワイヤボンディングパッド(以下、負電
極パッドと呼ぶ) 18 長方形の発光部 19 垂直軸上方向の発光パターン 20 右方向の発光パターン 21 左方向の発光パターン 22、23 電極端子 24、25 金線 26 表面実装型の半導体発光装置のモールドケース 27 モールドケース26の底面 28 透明なモールド樹脂 29 表面実装型の半導体発光装置のモールドケース 30、31 電極端子 32、33 共通ライン 34 正方形の発光部 35 長方形のサファイア基板 36 円形の発光部 37 多角形の発光部
Reference Signs List 10 sapphire substrate as an insulating substrate 11 n-type Al X Ga Y In 1-XY N layer (0 ≦ X ≦ 1, 0
≦ Y ≦ 1) is a 12-emitting layer Al Z Ga T In 1-ZT N layer (0 ≦ Z
≦ 1,0 ≦ T ≦ 1) 13 p -type Al U Ga V In 1-UV N layer (0 ≦ U ≦ 1,0
≦ V ≦ 1) 14 Positive electrode 15 Wire bonding pad for positive electrode (hereinafter referred to as positive electrode pad) 16 Negative electrode 17 Wire bonding pad for negative electrode (hereinafter referred to as negative electrode pad) 18 Rectangular light emitting portion 19 Vertical On-axis light-emitting pattern 20 Right-side light-emitting pattern 21 Left-side light-emitting pattern 22, 23 Electrode terminal 24, 25 Gold wire 26 Mold case of surface-mounted semiconductor light emitting device 27 Bottom surface of mold case 26 28 Transparent mold resin 29 Mold case for surface mounted semiconductor light emitting device 30, 31 Electrode terminal 32, 33 Common line 34 Square light emitting part 35 Rectangular sapphire substrate 36 Circular light emitting part 37 Polygonal light emitting part

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上に形成された半導体発光素
子において、該半導体発光素子は少なくとも発光部及び
正電極用ワイヤボンディングパッド及び負電極用ワイヤ
ボンディングパッドを有し、該正電極用ワイヤボンディ
ングパッド及び該負電極用ワイヤボンディングパッドを
近接して配設し、且つ該正電極用ワイヤボンディングパ
ッド及び該負電極用ワイヤボンディングパッドの外形が
形作る長辺部側に近接して該半導体発光素子の発光部を
配設することを特徴とする半導体発光素子。
1. A semiconductor light emitting device formed on an insulating substrate, said semiconductor light emitting device having at least a light emitting portion, a wire bonding pad for a positive electrode, and a wire bonding pad for a negative electrode. A pad and the wire bonding pad for the negative electrode are disposed in close proximity to each other, and the semiconductor light emitting element is disposed close to a long side formed by the outer shape of the wire bonding pad for the positive electrode and the wire bonding pad for the negative electrode. A semiconductor light emitting device comprising a light emitting unit.
【請求項2】 請求項1記載の半導体発光素子におい
て、前記絶縁性基板の面積をS1、発光部の面積をS2
正電極用ワイヤボンディングパッドと負電極用ワイヤボ
ンディングパッドとの面積の和をS3とする時、S1≧S
2+S3であり、且つ、S2≧S3であることを特徴とする
半導体発光素子。
2. The semiconductor light emitting device according to claim 1, wherein the area of the insulating substrate is S 1 , the area of the light emitting section is S 2 ,
When the sum of the areas of the positive electrode wire bonding pad and the negative electrode wire bonding pad is S 3 , S 1 ≧ S
2. A semiconductor light emitting device, wherein 2 + S 3 and S 2 ≧ S 3 .
【請求項3】 請求項1記載の半導体発光素子におい
て、該発光素子の発光部の形状がほぼ正方形またはほぼ
長方形であることを特徴とする半導体発光素子。
3. The semiconductor light emitting device according to claim 1, wherein the shape of the light emitting portion of the light emitting device is substantially square or substantially rectangular.
【請求項4】 請求項1記載の半導体発光素子におい
て、該発光素子の発光部の形状がほぼ円形またはほぼ多
角形であることを特徴とする半導体発光素子。
4. The semiconductor light emitting device according to claim 1, wherein a shape of a light emitting portion of said light emitting device is substantially circular or substantially polygonal.
【請求項5】 請求項1記載の半導体発光素子を用いて
実装したことを特徴とする半導体発光装置。
5. A semiconductor light-emitting device mounted using the semiconductor light-emitting element according to claim 1.
JP34488896A 1996-12-25 1996-12-25 Semiconductor light emitting element and semiconductor light emitting device Pending JPH10190063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34488896A JPH10190063A (en) 1996-12-25 1996-12-25 Semiconductor light emitting element and semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34488896A JPH10190063A (en) 1996-12-25 1996-12-25 Semiconductor light emitting element and semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPH10190063A true JPH10190063A (en) 1998-07-21

Family

ID=18372777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34488896A Pending JPH10190063A (en) 1996-12-25 1996-12-25 Semiconductor light emitting element and semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPH10190063A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002103811A1 (en) * 2001-06-15 2002-12-27 Nichia Corporation Nitride semiconductor light emitting device
JP2015195349A (en) * 2014-03-28 2015-11-05 日亜化学工業株式会社 Light emitting device
CN108323004A (en) * 2018-02-02 2018-07-24 江门黑氪光电科技有限公司 A kind of wiring board with symmetrical pad

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002103811A1 (en) * 2001-06-15 2002-12-27 Nichia Corporation Nitride semiconductor light emitting device
JP2015195349A (en) * 2014-03-28 2015-11-05 日亜化学工業株式会社 Light emitting device
CN108323004A (en) * 2018-02-02 2018-07-24 江门黑氪光电科技有限公司 A kind of wiring board with symmetrical pad

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