JPH10189801A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10189801A
JPH10189801A JP34730096A JP34730096A JPH10189801A JP H10189801 A JPH10189801 A JP H10189801A JP 34730096 A JP34730096 A JP 34730096A JP 34730096 A JP34730096 A JP 34730096A JP H10189801 A JPH10189801 A JP H10189801A
Authority
JP
Japan
Prior art keywords
semiconductor device
solder
wiring board
temperature solder
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34730096A
Other languages
Japanese (ja)
Inventor
Takeo Anpo
武雄 安保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP34730096A priority Critical patent/JPH10189801A/en
Publication of JPH10189801A publication Critical patent/JPH10189801A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, having superior heat dissipating property, which can be used for the consumer appliances such as electronic appliances, electric appliances, communication appliances and measurement control appliances. SOLUTION: A connecting conductor 2b is embedded in a via hole where the surface, on which the semiconductor device 4 of wiring substrate 1 is mounted, and the surface opposite to this surface and metal balls 3 made of high temperature solder will be arranged, are electrically connected. By forming the metal balls 3, consisting of high temperature solder, on the part directly below the connecting conductor 12b, heat is sufficiently dissipated from the semiconductor device, the bonding strength of the solder balls 3, consisting of high temperature solder, can be increased, and a semiconductor with superior reliability device can be provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子機器、電気機
器、通信機器および計測制御機器などの電気機器に用い
られる半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for electric equipment such as electronic equipment, electric equipment, communication equipment and measurement control equipment.

【0002】[0002]

【従来の技術】以下に従来の半導体装置について説明す
る。
2. Description of the Related Art A conventional semiconductor device will be described below.

【0003】従来の半導体装置は、ポリイミド・ポリエ
ステル等の樹脂材料からなる配線基板で構成されてお
り、この配線基板の第一の面に半導体ディバイスを機械
的に搭載し、この半導体ディバイスの各々の電極を上記
配線基板の第一の面に形成した複数の配線電極にそれぞ
れ金属線をもって電気的に接続している。
A conventional semiconductor device is composed of a wiring board made of a resin material such as polyimide or polyester. A semiconductor device is mechanically mounted on a first surface of the wiring board, and each of the semiconductor devices is mounted. The electrodes are electrically connected to a plurality of wiring electrodes formed on the first surface of the wiring board by metal wires.

【0004】一方、上記配線基板の第二の面にその第二
の面に対し所定の寸法をもって平面的になるように複数
のハンダボールが配列されており、上記配線基板の第一
の面に設けた半導体ディバイスが上記配線基板の第一の
面と第二の面とを導通接続する複数のビアホールを介し
て上記複数のハンダボールのそれぞれと電気的に接続さ
れている。
On the other hand, a plurality of solder balls are arranged on the second surface of the wiring board so as to be planar with a predetermined dimension with respect to the second surface. The provided semiconductor device is electrically connected to each of the plurality of solder balls via a plurality of via holes for electrically connecting the first surface and the second surface of the wiring substrate.

【0005】そして、上記複数のハンダボールのそれぞ
れは上記ビアホールのそれぞれと離れた箇所に形成さ
れ、上記配線基板の第二の面に形成した配線導体をもっ
て電気的に接続されている。
[0005] Each of the plurality of solder balls is formed at a location apart from each of the via holes, and is electrically connected to a wiring conductor formed on the second surface of the wiring board.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、従来の
半導体装置の構成は、配線基板として樹脂基板を用い、
半導体ディバイスをハンダボールにビアホールと配線導
体を介して電気的に接続する構成であるため、半導体装
置自体としての熱伝導が悪く高電力の半導体ディバイス
を用いることができず、用途が著しく限られてしまうと
いう課題を有していた。
However, the configuration of the conventional semiconductor device uses a resin substrate as a wiring substrate,
Because the semiconductor device is electrically connected to the solder balls via via holes and wiring conductors, the heat conduction of the semiconductor device itself is poor, and high-power semiconductor devices cannot be used. Had the problem of getting lost.

【0007】本発明は、放熱性の優れた半導体装置を提
供することを目的としている。
An object of the present invention is to provide a semiconductor device having excellent heat dissipation.

【0008】[0008]

【課題を解決するための手段】上記の課題を解決するた
めに、本発明の半導体装置は、配線基板の材料として放
熱性の優れた配線基板上の半導体ディバイスがマウント
される面と、この面と対面するハンダボールが配列され
る面を電気的に接続しているビアホールにハンダを埋め
込み、さらにこのビアホールの直下にハンダボールを形
成するという構成を有している。
In order to solve the above-mentioned problems, a semiconductor device according to the present invention comprises a surface on which a semiconductor device on a wiring board having excellent heat dissipation as a material of the wiring board is mounted; Solder is buried in a via hole that electrically connects the surface on which the solder balls facing each other are arranged, and a solder ball is formed immediately below the via hole.

【0009】この構成により、半導体装置の十分な放熱
が図れると共に、ハンダボールの接合強度をアップする
ことができる。
With this configuration, sufficient heat radiation from the semiconductor device can be achieved, and the bonding strength of the solder ball can be increased.

【0010】[0010]

【発明の実施の形態】本発明の請求項1に記載の発明
は、第一の面と第二の面とを有する配線基板と、この配
線基板の第一の面に搭載され、上記配線基板の第一の面
に形成した回路パターンに電気的に接続された半導体デ
ィバイスと、上記配線基板の第一の面と第二の面とを導
通接続する複数のビアホールと、上記ビアホールのそれ
ぞれに埋め込まれた接続導体と、上記配線基板の第二の
面と所定の寸法を持って上記第二の面に対して平面的に
なるように配列された回路基板に対する接続用の高温ハ
ンダからなる金属ボールとを備え、上記ビアホールは上
記配線基板の第一の面に形成した複数の配線電極の各々
に対応するように配列し、上記高温ハンダからなる金属
ボールは上記ビアホールに埋め込んだ接続導体の各々の
直下に配列したことを特徴とする半導体装置であり、半
導体装置としての十分な放熱が図れるという作用を有す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a wiring board having a first surface and a second surface, and the wiring board mounted on the first surface of the wiring board. A semiconductor device electrically connected to the circuit pattern formed on the first surface, a plurality of via holes for electrically connecting the first surface and the second surface of the wiring substrate, and embedded in each of the via holes Ball formed of a connected conductor and a high-temperature solder for connection to a circuit board arranged to be planar with respect to the second surface with the second surface of the wiring substrate having a predetermined dimension. And the via holes are arranged so as to correspond to each of the plurality of wiring electrodes formed on the first surface of the wiring substrate, and the metal ball made of the high-temperature solder is formed of each of the connection conductors embedded in the via holes. Arranged directly below A semiconductor device which is characterized, with the effect that sufficient heat dissipation can be achieved as a semiconductor device.

【0011】請求項2に記載の発明は、接続導体は熱伝
導性のよい材料からなる半導体装置であり、半導体ディ
バイスから発生する熱を速やかに高温ハンダからなる金
属ボールへ伝えるという作用を有する。
According to a second aspect of the present invention, the connection conductor is a semiconductor device made of a material having good thermal conductivity, and has an effect of rapidly transmitting heat generated from a semiconductor device to a metal ball made of high-temperature solder.

【0012】請求項3に記載の発明は、接続導体がハン
ダからなる半導体装置であり、低温プロセスにて容易に
ビアホールを埋め込むことが出来るという作用を有す
る。
According to a third aspect of the present invention, there is provided a semiconductor device in which a connection conductor is formed of solder, and has an effect that a via hole can be easily filled by a low temperature process.

【0013】請求項4に記載の発明は、高温ハンダから
なる金属ボールおよび接続導体が同材料のハンダからな
る半導体装置であり、高温ハンダからなる金属ボールと
接続導体が容易に金属結合することにより接合強度が強
くなるという作用を有する。
According to a fourth aspect of the present invention, there is provided a semiconductor device in which a metal ball made of a high-temperature solder and a connection conductor are made of the same material as the solder, and the metal ball made of the high-temperature solder and the connection conductor are easily metal-bonded. It has the effect of increasing the bonding strength.

【0014】請求項5に記載の発明は、配線基板がセラ
ミックである半導体装置であり、放熱性をより改善する
事が出来るという作用を有する。
According to a fifth aspect of the present invention, there is provided a semiconductor device in which the wiring substrate is made of ceramic, which has an effect that heat dissipation can be further improved.

【0015】請求項6に記載の発明は、高温ハンダから
なる金属ボール及び接続導体が融点温度が異なるハンダ
を用いた半導体装置であり、断線のない半導体装置を実
現するという作用を有する。
According to a sixth aspect of the present invention, there is provided a semiconductor device in which metal balls and connection conductors made of high-temperature solder use solders having different melting points, and have an effect of realizing a semiconductor device without disconnection.

【0016】(実施の形態1)図1は本発明の第1の実
施形態における半導体装置の断面図である。図1におい
て、1は配線基板であり、材質としてはセラミック(ア
ルミナ焼結)等である。2は配線基板1に設けられた貫
通穴であり、図2に示すように、この配線基板1上の半
導体ディバイス(ベアチップ)4がマウントされる面と
この面と対面する高温ハンダからなる金属ボール3が配
列形成される面を電気的に接続するため、穴壁に導電性
材料2aを形成してビアホールを構成している。導電性
材料2aとしてはAg−Pd系ペーストが使用される。
2bは半導体ディバイス4から発生する熱を回路基板
(図示せず)へ速やかに熱伝導させるために前記ビアホ
ール2内に形成された接続導体である。7は半導体ディ
バイス4と配線基板1をワイヤーボンディング装置にて
電気的に結合する金属線である。5は前記配線基板1の
半導体ディバイス4がマウントされる面に形成される高
熱伝導絶縁接着剤である。
(First Embodiment) FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a wiring board, which is made of ceramic (alumina sintered) or the like. Reference numeral 2 denotes a through hole provided in the wiring board 1, and as shown in FIG. 2, a metal ball made of a high-temperature solder facing the surface on which the semiconductor device (bare chip) 4 is mounted on the wiring board 1 In order to electrically connect the surfaces on which the arrays 3 are formed, a conductive material 2a is formed on the hole walls to form via holes. Ag-Pd paste is used as the conductive material 2a.
Reference numeral 2b denotes a connection conductor formed in the via hole 2 to quickly conduct heat generated from the semiconductor device 4 to a circuit board (not shown). Reference numeral 7 denotes a metal wire for electrically connecting the semiconductor device 4 and the wiring board 1 by a wire bonding apparatus. Reference numeral 5 denotes a high heat conductive insulating adhesive formed on the surface of the wiring substrate 1 on which the semiconductor device 4 is mounted.

【0017】6は半導体ディバイス4がマウントされる
面に回路パターンとして形成される配線導体であり、図
3に示すように上記金属線7がボンディングされる配線
電極6aを各ビアホール間に結線する。ここで、上記配
線導体6および配線電極6aとしてはAg−Pd系ペー
ストが使用されている。8は半導体ディバイス4と配線
基板1をワイヤーボンディング装置にて電気的に結合す
る金属線7を保護するための第1の保護樹脂である。9
は、第1の保護樹脂8上に自動表面実装機が使用できる
ように平面化のために形成され、半導体ディバイス4を
さらに保護する第2の保護樹脂である。3は上記ビアホ
ール内に充填した接続導体2bの直下に形成された高温
ハンダからなる金属ボールである。ここで、上記接続導
体2bおよび高温ハンダからなる金属ボール3は各々共
晶ハンダが使用され、接続導体2bとしてのハンダの融
点は高温ハンダからなる金属ボール3としてのハンダの
融点に比べて高く、具体的には接続導体2b用のハンダ
の融点は290度高温ハンダからなる金属ボール3とし
てのハンダの融点は250度のものが使用される。
Reference numeral 6 denotes a wiring conductor formed as a circuit pattern on the surface on which the semiconductor device 4 is mounted. As shown in FIG. 3, a wiring electrode 6a to which the metal wire 7 is bonded is connected between each via hole. Here, an Ag-Pd paste is used as the wiring conductor 6 and the wiring electrode 6a. Reference numeral 8 denotes a first protection resin for protecting the metal wires 7 that electrically connect the semiconductor device 4 and the wiring board 1 with a wire bonding apparatus. 9
Is a second protective resin formed on the first protective resin 8 for planarization so that an automatic surface mounting machine can be used, and further protecting the semiconductor device 4. Reference numeral 3 denotes a metal ball made of a high-temperature solder formed immediately below the connection conductor 2b filled in the via hole. Here, eutectic solder is used for the connection conductor 2b and the metal ball 3 made of high-temperature solder, and the melting point of the solder as the connection conductor 2b is higher than the melting point of the solder as the metal ball 3 made of the high-temperature solder. Specifically, the melting point of the solder for the connection conductor 2b is 250 ° C. The solder as the metal ball 3 made of a high-temperature solder of 290 ° C. is used.

【0018】ところで、ビアホール2用の穴を複数個設
けたセラミック製の配線基板1の片面にAg−Pd系ペ
ーストを用いてビアホール2用の導電性材料2aを印刷
すると共に、配線電極6a及び配線導体6を印刷し、他
方の面からAg−Pd系ペーストを用いてビアホール用
の導電性材料2aを印刷する。その後、850度で焼成
してAg−Pd系ペーストの焼き付けをする。次に、上
記配線基板1のおのおののビアホール2内に共晶ハンダ
を充填して接続導体2bを形成した後、おのおの接続導
体2b直下に共晶ハンダにより高温ハンダからなる金属
ボール3を形成する。このとき、上記複数の高温ハンダ
からなる金属ボール3は配線基板1の面から所定の寸法
をもって平面的に配列される。次に、上記配線基板1上
に半導体ディバイス4が搭載され、ワイヤーボンディン
グ法により金属線7の処理が実行され、第1、第2の保
護樹脂8,9により樹脂封止され、所望の半導体装置と
される。
On the other hand, a conductive material 2a for the via hole 2 is printed on one surface of a ceramic wiring board 1 provided with a plurality of holes for the via hole 2 using an Ag-Pd paste, and the wiring electrode 6a and the wiring The conductor 6 is printed, and the conductive material 2a for via holes is printed from the other surface using an Ag-Pd-based paste. Thereafter, baking is performed at 850 degrees to bake the Ag-Pd based paste. Next, eutectic solder is filled into each via hole 2 of the wiring board 1 to form connection conductors 2b, and metal balls 3 made of high-temperature solder are formed by eutectic solder immediately below each connection conductor 2b. At this time, the metal balls 3 composed of the plurality of high-temperature solders are arranged in a plane from the surface of the wiring board 1 with a predetermined dimension. Next, the semiconductor device 4 is mounted on the wiring board 1, the processing of the metal wires 7 is performed by the wire bonding method, the resin is sealed with the first and second protective resins 8 and 9, and the desired semiconductor device is formed. It is said.

【0019】この半導体装置においては、高温ハンダか
らなる金属ボール3としてのハンダに比べ接続導体2b
としてのハンダの融点が高いので、高温ハンダからなる
金属ボール3の形成時に先に形成した接続導体2bの再
溶融がなく、接続導体2bの断線を防ぐことが出来る。
In this semiconductor device, the connection conductors 2b are compared with solder as metal balls 3 made of high-temperature solder.
Since the melting point of the solder is high, there is no re-melting of the connection conductor 2b previously formed when the metal ball 3 made of high-temperature solder is formed, and the disconnection of the connection conductor 2b can be prevented.

【0020】上記構成の半導体装置は、表面自動実装機
により図示していない回路基板に表面実装され外部電圧
が回路基板の電極パッドから配線基板1の高温ハンダか
らなる金属ボール3を通して接続導体2b、さらに配線
導体6から金属線7を通して半導体ディバイス4へと電
気的に接続され、半導体ディバイス4にて特定の回路処
理を行い前記電気接続経路を通して回路基板へ出力され
る。このとき半導体ディバイス4に発生する熱は、半導
体ディバイス4から高熱伝導絶縁接着剤5を通して配線
基板1上に伝導され、接続導体2bを経由して高温ハン
ダからなる金属ボール3から回路基板へと伝導する。さ
らに配線基板1の表面から空気中へと放出される。
The semiconductor device having the above structure is mounted on a circuit board (not shown) by an automatic surface mounter, and an external voltage is applied from the electrode pads of the circuit board to the connection conductors 2b through metal balls 3 made of high-temperature solder on the wiring board 1. Further, the semiconductor device 4 is electrically connected to the semiconductor device 4 from the wiring conductor 6 through the metal wire 7, and the semiconductor device 4 performs a specific circuit process, and outputs the circuit to the circuit board through the electric connection path. At this time, the heat generated in the semiconductor device 4 is conducted from the semiconductor device 4 to the wiring board 1 through the high heat conductive insulating adhesive 5 and is conducted from the metal ball 3 made of high-temperature solder to the circuit board via the connection conductor 2b. I do. Further, it is released from the surface of the wiring board 1 into the air.

【0021】尚、配線基板の材質としてセラミック基板
による場合を説明したが、セラミック基板以外に樹脂基
板でもよい。この場合も樹脂基板上に半導体ディバイス
がマウントされる面とこの面と対面する高温ハンダから
なる金属ボールが配列形成される面を電気的に接続して
いるビアホールにハンダを埋め込みさらにこのビアホー
ルの直下にハンダボールを形成する構成により、半導体
装置としての十分な放熱が図れると共に、ハンダボール
の接合強度をアップすることができる。
Although the case where the wiring board is made of a ceramic substrate has been described, a resin substrate may be used instead of the ceramic substrate. In this case as well, the solder is buried in a via hole that electrically connects the surface on which the semiconductor device is mounted on the resin substrate and the surface on which the metal balls made of high-temperature solder facing the surface are formed, and directly under the via hole. With the configuration in which the solder balls are formed, sufficient heat radiation as a semiconductor device can be achieved, and the bonding strength of the solder balls can be increased.

【0022】又、ワイヤーボンディング法により半導体
ディバイスを実装したが、他にフリップチップボンディ
ングの手法等により半導体ディバイスを配線基板上に実
装してもよい。
Although the semiconductor device is mounted by the wire bonding method, the semiconductor device may be mounted on the wiring board by a flip chip bonding method or the like.

【0023】[0023]

【発明の効果】以上のように本発明の集積回路装置は、
放熱性の優れた配線基板とこの配線基板上に半導体ディ
バイスがマウントされる面とこの面と対面する高温ハン
ダからなる金属ボールが配列形成される面を電気的に接
続しているビアホールに接続導体を埋め込み、さらにこ
の接続導体直下に高温ハンダからなる金属ボールを形成
することにより、高電力用のベアチップ等の発熱部品に
対して放熱性が優れた半導体装置を提供することが出来
る。
As described above, the integrated circuit device of the present invention
A conductor connected to a via hole that electrically connects the wiring board with excellent heat dissipation and the surface on which the semiconductor device is mounted on this wiring substrate and the surface on which metal balls made of high-temperature solder facing this surface are arranged and formed And a metal ball made of a high-temperature solder is formed immediately below the connection conductor, thereby providing a semiconductor device having excellent heat radiation properties to a heat-generating component such as a high-power bare chip.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態における半導体装置の断面
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】同要部の拡大断面図FIG. 2 is an enlarged cross-sectional view of the main part.

【図3】同製造に使用する配線基板の斜視図FIG. 3 is a perspective view of a wiring board used in the manufacturing.

【符号の説明】[Explanation of symbols]

1 配線基板 2 ビアホール(貫通穴) 2a 導電性材料 2b 接続導体 3 高温ハンダからなる金属ボール 4 半導体ディバイス 5 高熱伝導絶縁接着剤 6 配線導体 7 金属線 8 第1の保護樹脂 9 第2の保護樹脂 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Via hole (through hole) 2a Conductive material 2b Connection conductor 3 Metal ball made of high-temperature solder 4 Semiconductor device 5 High heat conductive insulating adhesive 6 Wiring conductor 7 Metal wire 8 First protective resin 9 Second protective resin

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 第一の面と第二の面とを有する配線基板
と、この配線基板の第一の面に搭載され、上記配線基板
の第一の面に形成した回路パターンに電気的に接続され
た半導体ディバイスと、上記配線基板の第一の面と第二
の面とを導通接続する複数のビアホールと、上記ビアホ
ールのそれぞれに埋め込まれた接続導体と、上記配線基
板の第二の面と所定の寸法を持って上記第二の面に対し
て平面的になるように配列された回路基板に対する接続
用の高温ハンダからなる金属ボールとを備え、上記ビア
ホールは上記配線基板の第一の面に形成した複数の配線
電極の各々に対応するように配列し、上記高温ハンダか
らなる金属ボールは上記ビアホールに埋め込んだ接続導
体の各々の直下に配列したことを特徴とする半導体装
置。
1. A wiring board having a first surface and a second surface, and a circuit pattern mounted on the first surface of the wiring substrate and electrically formed on a circuit pattern formed on the first surface of the wiring substrate. A connected semiconductor device, a plurality of via holes for electrically connecting the first surface and the second surface of the wiring board, connection conductors embedded in each of the via holes, and a second surface of the wiring board And a metal ball made of a high-temperature solder for connection to a circuit board arranged to be planar with respect to the second surface with predetermined dimensions, and the via hole is provided on the first side of the wiring board. A semiconductor device, which is arranged so as to correspond to each of a plurality of wiring electrodes formed on a surface, and wherein the metal balls made of the high-temperature solder are arranged immediately below each of the connection conductors embedded in the via holes.
【請求項2】 接続導体は熱伝導性のよい材料からなる
請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the connection conductor is made of a material having good heat conductivity.
【請求項3】 接続導体がハンダからなる請求項1記載
の半導体装置。
3. The semiconductor device according to claim 1, wherein the connection conductor is made of solder.
【請求項4】 高温ハンダからなる金属ボールおよび接
続導体が同材料のハンダからなる請求項1記載の半導体
装置。
4. The semiconductor device according to claim 1, wherein the metal ball and the connection conductor made of high-temperature solder are made of the same material solder.
【請求項5】 配線基板がセラミックからなる請求項1
記載の半導体装置。
5. The wiring board according to claim 1, wherein the wiring board is made of ceramic.
13. The semiconductor device according to claim 1.
【請求項6】 高温ハンダからなる金属ボールおよび接
続導体が同材料のハンダからなり、各ハンダの融点温度
が異なる請求項1記載の半導体装置。
6. The semiconductor device according to claim 1, wherein the metal ball and the connection conductor made of high-temperature solder are made of the same material, and the melting points of the solders are different.
JP34730096A 1996-12-26 1996-12-26 Semiconductor device Pending JPH10189801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34730096A JPH10189801A (en) 1996-12-26 1996-12-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34730096A JPH10189801A (en) 1996-12-26 1996-12-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10189801A true JPH10189801A (en) 1998-07-21

Family

ID=18389284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34730096A Pending JPH10189801A (en) 1996-12-26 1996-12-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10189801A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205645B2 (en) 2000-02-28 2007-04-17 Hitachi Chemical Co., Ltd. Wiring board, semiconductor device, and method of manufacturing wiring board
WO2019097790A1 (en) * 2017-11-15 2019-05-23 パナソニックIpマネジメント株式会社 Semiconductor module and production method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205645B2 (en) 2000-02-28 2007-04-17 Hitachi Chemical Co., Ltd. Wiring board, semiconductor device, and method of manufacturing wiring board
US7704799B2 (en) 2000-02-28 2010-04-27 Hitachi Chemical Co., Ltd. Method of manufacturing wiring substrate
WO2019097790A1 (en) * 2017-11-15 2019-05-23 パナソニックIpマネジメント株式会社 Semiconductor module and production method therefor
JPWO2019097790A1 (en) * 2017-11-15 2020-10-08 パナソニックセミコンダクターソリューションズ株式会社 Semiconductor module and its manufacturing method
US10847702B2 (en) 2017-11-15 2020-11-24 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor module

Similar Documents

Publication Publication Date Title
KR0141067B1 (en) Electronic package with a thermally conductive support member having a thin circuitized substrate
US5773884A (en) Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
JP3084230B2 (en) Ball grid array package
US5633533A (en) Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
JPH09321073A (en) Package for semiconductor device, and semiconductor device
US6861283B2 (en) Package for integrated circuit with thermal vias and method thereof
JP2004179309A (en) Heat dissipating structure for printed circuit board and method for manufacturing the same
CN211208432U (en) Intelligent power module substrate, intelligent functional module and electronic equipment
JP2004047883A (en) Electric power semiconductor device
JP3603354B2 (en) Hybrid integrated circuit device
EP0817266B1 (en) Mounting structure for an integrated circuit
US7049171B2 (en) Electrical package employing segmented connector and solder joint
US7564128B2 (en) Fully testable surface mount die package configured for two-sided cooling
KR100675030B1 (en) An integrated circuit package
JPH10189801A (en) Semiconductor device
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
JP4934915B2 (en) Semiconductor device
JP3394479B2 (en) Semiconductor device
JPH09191028A (en) Semiconductor device
JPH11220050A (en) Semiconductor package
JP2564645Y2 (en) Hybrid integrated circuit device having heat-generating components
JP2001267460A (en) Semiconductor device
JP2004072003A (en) Multilayer circuit board having metal base, and hybrid integrated circuit using the same
JPH10256414A (en) Semiconductor package
JPS62189798A (en) Composition of hybrid ic