JPH10189707A - Forming method of element isolation region of semiconductor device - Google Patents
Forming method of element isolation region of semiconductor deviceInfo
- Publication number
- JPH10189707A JPH10189707A JP9142576A JP14257697A JPH10189707A JP H10189707 A JPH10189707 A JP H10189707A JP 9142576 A JP9142576 A JP 9142576A JP 14257697 A JP14257697 A JP 14257697A JP H10189707 A JPH10189707 A JP H10189707A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- element isolation
- oxide film
- nitride film
- isolation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の素子分
離領域形成方法に関する。The present invention relates to a method for forming an element isolation region of a semiconductor device.
【０００２】[0002]
【従来の技術】シリコン基板にＦＥＴ、双極性トランジ
スタ、ダイオード、キャパシタ、抵抗等を形成した半導
体装置においては、前記回路素子間を絶縁するための手
段が必要である。この絶縁手段としては、一般的には、
高誘電体物質のシリコン酸化膜による素子分離領域が使
用される。このシリコン酸化膜による素子分離領域は、
良く知られたＬＯＣＯＳ（Local Oxidation of Silico
n）技術で製造される。2. Description of the Related Art In a semiconductor device in which an FET, a bipolar transistor, a diode, a capacitor, a resistor and the like are formed on a silicon substrate, means for insulating the circuit elements is required. In general, the insulation means
An element isolation region using a silicon oxide film of a high dielectric substance is used. The element isolation region by this silicon oxide film
The well-known LOCOS (Local Oxidation of Silico)
n) Manufactured by technology.
【０００３】図３は従来のＬＯＣＯＳ技術で素子分離領
域を製造する方法を示す断面図である。FIG. 3 is a sectional view showing a method for manufacturing an element isolation region by the conventional LOCOS technique.
【０００４】まず図３（ａ）に示すように、熱酸化によ
って厚さ約５００Åの下部シリコン酸化膜１２をシリコ
ン基板１１上に形成する。次に、下部シリコン酸化膜１
２上に厚さが約１０００Åのシリコン窒化膜１３をＣＶ
Ｄ（Chemical Vapor Deposition;化学気相蒸着）法等に
よって形成する。前記下部シリコン酸化膜１２は、この
シリコン窒化膜１３によってシリコン基板１１に印加さ
れる応力（stress）を緩和させるためのものである。First, as shown in FIG. 3A, a lower silicon oxide film 12 having a thickness of about 500 ° is formed on a silicon substrate 11 by thermal oxidation. Next, the lower silicon oxide film 1
A silicon nitride film 13 having a thickness of about 1000
It is formed by a D (Chemical Vapor Deposition) method or the like. The lower silicon oxide film 12 is for reducing stress applied to the silicon substrate 11 by the silicon nitride film 13.
【０００５】次に、図３（ｂ）に示すように、シリコン
窒化膜１３をフォトリソグラフィ技術を使用したエッチ
ングによってパタニングし、回路素子が形成されるシリ
コン基板１１の回路素子領域１９上だけにシリコン窒化
膜パターン１３ａが残るようにする。その結果、素子分
離領域にある下部シリコン酸化膜１２が露出される。[0005] Next, as shown in FIG. 3 (b), the silicon nitride film 13 is patterned by etching using a photolithography technique, and silicon is formed only on the circuit element region 19 of the silicon substrate 11 on which circuit elements are formed. The nitride film pattern 13a is left. As a result, the lower silicon oxide film 12 in the element isolation region is exposed.
【０００６】その後、図３（ｃ）に示すようにシリコン
窒化膜パターン１３ａをマスクとして、素子分離領域の
基板１１表面部を熱酸化し、素子分離領域の基板１１表
面部に約５０００Åの厚さの素子分離酸化膜１４を形成
する。Then, as shown in FIG. 3C, using the silicon nitride film pattern 13a as a mask, the surface of the substrate 11 in the element isolation region is thermally oxidized, so that the surface of the substrate 11 in the element isolation region has a thickness of about 5000 mm. Is formed.
【０００７】その後はシリコン窒化膜パターン１３ａを
除去し、素子分離酸化膜１４によって囲まれている回路
素子領域１９ａに良く知られている方法によって回路素
子を形成する。Thereafter, the silicon nitride film pattern 13a is removed, and a circuit element is formed by a well-known method in the circuit element region 19a surrounded by the element isolation oxide film 14.
【０００８】[0008]
【発明が解決しようとする課題】しかるに、上記のよう
な方法では、シリコン窒化膜パターン１３ａをマスクと
して素子分離領域の基板１１表面部を熱酸化した際、酸
化反応が垂直方向だけでなく、シリコン窒化膜パターン
１３ａの縁の下の領域にも進行するので、素子分離酸化
膜１４にバーズビーク（鳥のくちばし形状）１５が発生
する問題点があった。そして、このバーズビーク１５は
シリコン基板１１上の素子分離領域を拡大させるので、
半導体装置の高集積化を阻害する問題点があった。However, in the above-described method, when the surface of the substrate 11 in the element isolation region is thermally oxidized using the silicon nitride film pattern 13a as a mask, the oxidation reaction occurs not only in the vertical direction but also in the silicon. Since it also proceeds to a region below the edge of the nitride film pattern 13a, there is a problem that a bird's beak (bird's beak) 15 is generated in the element isolation oxide film 14. Since the bird's beak 15 enlarges the element isolation region on the silicon substrate 11,
There is a problem that hinders high integration of semiconductor devices.
【０００９】そこで、バーズビークの成長を抑制しなが
ら素子分離酸化膜を形成する図４に示す従来の他の技術
が提案されている。Therefore, another conventional technique shown in FIG. 4 for forming an element isolation oxide film while suppressing the growth of bird's beak has been proposed.
【００１０】この方法では、図４（ａ）に示すように、
シリコン基板２１上に下部シリコン酸化膜２２を形成し
た後、下部シリコン酸化膜２２上に気相蒸着法によって
ポリシリコン層２６を形成し、さらにこのポリシリコン
層２６上にシリコン窒化膜２３を形成する。In this method, as shown in FIG.
After a lower silicon oxide film 22 is formed on a silicon substrate 21, a polysilicon layer 26 is formed on the lower silicon oxide film 22 by a vapor deposition method, and a silicon nitride film 23 is further formed on the polysilicon layer 26. .
【００１１】次に、図４（ｂ）に示すようにシリコン窒
化膜２３をパターニングして、シリコン窒化膜パターン
２３ａを回路素子領域にだけ残す。その後、シリコン窒
化膜パターン２３ａをマスクとして、ポリシリコン層２
６とシリコン基板２１の表面部を選択的に熱酸化処理す
ることにより素子分離酸化膜２４を形成する。２５は、
この方法による場合のバーズビークを示す。Next, as shown in FIG. 4B, the silicon nitride film 23 is patterned to leave the silicon nitride film pattern 23a only in the circuit element region. Then, using the silicon nitride film pattern 23a as a mask, the polysilicon layer 2
6 and the surface of the silicon substrate 21 are selectively thermally oxidized to form an element isolation oxide film 24. 25 is
A bird's beak according to this method is shown.
【００１２】この方法でもバーズビークが全くなくなる
わけではないが、図３に示す方法に比べてバーズビーク
をはるかに小さくすることができる。ここで、バーズビ
ーク２５の成長を抑制するためにはポリシリコン層２６
を厚く形成することが望ましい。しかるに、ポリシリコ
ン層２６を厚くすると、素子分離酸化膜２４にバーズビ
ーク２５の上で非正常的な突出部２７が成長する問題が
あった。そして、この突出部２７が成長すると、後属工
程で良くない影響、たとえば、後属工程での有害物質が
前記突出部２７とバーズビーク２５間の凹部分に残留す
る問題が生じた。Although this method does not eliminate bird's beak at all, the bird's beak can be made much smaller than the method shown in FIG. Here, in order to suppress the growth of the bird's beak 25, the polysilicon layer 26 is formed.
Is desirably formed thick. However, when the polysilicon layer 26 is thickened, there is a problem that an abnormal projection 27 grows on the bird's beak 25 in the element isolation oxide film 24. When the protruding portion 27 grows, an adverse effect in the subsequent process, for example, a problem that a harmful substance in the subsequent process remains in the concave portion between the protruding portion 27 and the bird's beak 25 occurs.
【００１３】本発明は以上のような従来の問題点を解決
することができる半導体装置の素子分離領域形成方法を
提供することを目的とする。An object of the present invention is to provide a method for forming an element isolation region of a semiconductor device which can solve the above-mentioned conventional problems.
【００１４】[0014]
【課題を解決するための手段】本発明は上述の課題を解
決するために、次のような半導体装置の素子分離領域形
成方法とする。まず、半導体基板上にパッド酸化膜を形
成する。次に、パッド酸化膜上にシリコン窒化膜を形成
する。次に、シリコン窒化膜をパターニングして、前記
半導体基板の回路素子領域上にシリコン窒化膜パターン
を形成するとともに、前記半導体基板の素子分離領域の
前記パッド酸化膜を露出させる。次に、露出した素子分
離領域の前記パッド酸化膜の表面側を除去して、この部
分のパッド酸化膜を他の部分より薄くする。次に、前記
工程により薄くなった部分とその他の厚い部分との境に
生じた前記パッド酸化膜の側壁部および前記シリコン窒
化膜パターンの側壁部にシリコン窒化膜のサイドウォー
ルを形成する。次に、サイドウォールと前記シリコン窒
化膜パターンをマスクとして素子分離領域の前記半導体
基板表面部を熱酸化し、該部分に素子分離酸化膜を形成
する。In order to solve the above-mentioned problems, the present invention provides a method for forming an element isolation region of a semiconductor device as described below. First, a pad oxide film is formed on a semiconductor substrate. Next, a silicon nitride film is formed on the pad oxide film. Next, the silicon nitride film is patterned to form a silicon nitride film pattern on the circuit element region of the semiconductor substrate, and to expose the pad oxide film in the element isolation region of the semiconductor substrate. Next, the exposed surface of the pad oxide film in the element isolation region is removed, and the pad oxide film in this portion is made thinner than the other portions. Next, a side wall of a silicon nitride film is formed on a side wall portion of the pad oxide film and a side wall portion of the silicon nitride film pattern generated at a boundary between the thinned portion and the other thick portions by the above-described process. Next, using the sidewall and the silicon nitride film pattern as a mask, the surface of the semiconductor substrate in the element isolation region is thermally oxidized to form an element isolation oxide film in the portion.
【００１５】[0015]
【発明の実施の形態】次に添付図面を参照して本発明に
よる半導体装置の素子分離領域形成方法の実施の形態を
詳細に説明する。図１および図２は本発明の実施の形態
を工程順に示す断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for forming an element isolation region of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 are sectional views showing an embodiment of the present invention in the order of steps.
【００１６】本発明の実施の形態では、まず図１（ａ）
に示すように、半導体基板としてのシリコン基板３１上
に約７００〜９００Åの厚さを持つパッド酸化膜として
の下部シリコン酸化膜３２を約９５０℃の熱酸化によっ
て形成する。次に、下部シリコン酸化膜３２上に約１３
５０〜１６５０Åの厚さを持つ第１シリコン窒化膜３３
を蒸着法によって蒸着する。このとき、第１シリコン窒
化膜３３を余り厚く形成することは望ましくない。なぜ
ならば、シリコン基板３１内に物理的な応力が生成され
るからである。In the embodiment of the present invention, first, FIG.
As shown in FIG. 5, a lower silicon oxide film 32 as a pad oxide film having a thickness of about 700 to 900.degree. Is formed on a silicon substrate 31 as a semiconductor substrate by thermal oxidation at about 950.degree. Next, on the lower silicon oxide film 32, about 13
First silicon nitride film 33 having a thickness of 50-1650 °
Is deposited by an evaporation method. At this time, it is not desirable to form the first silicon nitride film 33 too thick. This is because physical stress is generated in the silicon substrate 31.
【００１７】次に、図１（ｂ）に示すように、第１シリ
コン窒化膜３３をフォトリソグラフィを利用したエッチ
ングによってパターニングすることにより、基板３１の
回路素子領域３９上に第１シリコン窒化膜パターン３３
ａを形成するとともに、基板３１の素子分離領域上の下
部シリコン酸化膜３２を露出させる。Next, as shown in FIG. 1B, the first silicon nitride film 33 is patterned on the circuit element region 39 of the substrate 31 by patterning by etching using photolithography. 33
While forming a, the lower silicon oxide film 32 on the element isolation region of the substrate 31 is exposed.
【００１８】次に、図２（ａ）に示すように、第１のシ
リコン窒化膜パターン３３ａをマスクとしてウェットエ
ッチングのような等方性エッチングによって、素子分離
領域の露出している下部シリコン酸化膜３２の表面側を
選択的に除去し、この部分の下部シリコン酸化膜３２の
膜厚を他の部分より薄くする。このとき、薄膜部分３２
ａは、他の厚い部分の約３分の１の厚さ、ここでは２２
０〜２８０Åの厚さとされる。また、等方性エッチング
によって下部シリコン酸化膜３２を薄膜化することによ
り、第１シリコン窒化膜パターン３３ａの下にアンダー
カットが形成され、第１シリコン窒化膜パターン３３ａ
の下に延びて薄膜部３２ａが形成される。Next, as shown in FIG. 2A, the first silicon nitride film pattern 33a is used as a mask for isotropic etching such as wet etching to expose the lower silicon oxide film where the element isolation region is exposed. 32 is selectively removed, and the thickness of the lower silicon oxide film 32 in this portion is made thinner than in other portions. At this time, the thin film portion 32
a is about one-third the thickness of the other thick sections, here 22
The thickness is 0 to 280 °. Also, by thinning the lower silicon oxide film 32 by isotropic etching, an undercut is formed under the first silicon nitride film pattern 33a, and the first silicon nitride film pattern 33a is formed.
And a thin film portion 32a is formed.
【００１９】次に、薄膜部３２ａ（薄膜化が終了した素
子分離領域の露出した下部シリコン酸化膜３２）と第１
シリコン窒化膜パターン３３ａの全面に図２（ｂ）に示
すように第２シリコン窒化膜３４を約７８０℃の蒸着法
によって１０００〜１４００Åの厚さに形成する。この
とき、第２シリコン窒化膜３４は、第１シリコン窒化膜
パターン３３ａ下の前記アンダーカット部を埋めて形成
される。その後、第２シリコン窒化膜３４を乾式エッチ
ング法でエッチングすることにより、図２（ｃ）に示す
ように、第１シリコン窒化膜パターン３３ａの側壁部
と、アンダーカット部を埋めて下部シリコン酸化膜３２
の側壁部（薄膜部３２ａを形成することにより生じた側
壁部）を覆って第２シリコン窒化膜のサイドウォール３
４ａを形成する。このとき、下部シリコン酸化膜３２の
薄膜部３２ａはエッチング停止層として機能する。Next, the thin film portion 32a (the lower silicon oxide film 32 where the thinned element isolation region is exposed) and the first
As shown in FIG. 2B, a second silicon nitride film 34 is formed on the entire surface of the silicon nitride film pattern 33a to a thickness of 1000 to 1400 ° by an evaporation method at about 780 ° C. At this time, the second silicon nitride film 34 is formed to fill the undercut portion below the first silicon nitride film pattern 33a. Thereafter, the second silicon nitride film 34 is etched by a dry etching method, as shown in FIG. 2C, to fill the side wall portion and the undercut portion of the first silicon nitride film pattern 33a and form the lower silicon oxide film. 32
Of the second silicon nitride film covering the side wall portion (side wall portion formed by forming the thin film portion 32a).
4a is formed. At this time, the thin film portion 32a of the lower silicon oxide film 32 functions as an etching stop layer.
【００２０】その後、シリコン窒化膜のサイドウォール
３４ａと第１シリコン窒化膜パターン３３ａをマスクと
して使用して、図２（ｄ）に示すように基板３１の素子
分離領域部を約９５０℃で酸化処理することにより、該
部分に約６５００〜７５００Åの素子分離酸化膜３５を
形成する。この熱酸化工程中、下部シリコン酸化膜３２
の側壁部を覆うサイドウォール３４ａによって、酸素が
下部シリコン酸化膜３２に従って回路素子領域３９側に
拡散することが防止される。従って、この方法によれ
ば、素子分離酸化膜３５のバーズビークは非常に小さい
ものとなる。また、図４のポリシリコン層を用いた場合
のようにバーズビークの上に非正常的な突出部が生成さ
れることもない。Then, using the side wall 34a of the silicon nitride film and the first silicon nitride film pattern 33a as a mask, the element isolation region of the substrate 31 is oxidized at about 950 ° C. as shown in FIG. As a result, an element isolation oxide film 35 of about 6500 to 7500 ° is formed in this portion. During this thermal oxidation step, the lower silicon oxide film 32
Oxygen is prevented from diffusing toward the circuit element region 39 according to the lower silicon oxide film 32 by the side wall 34a covering the side wall portion of. Therefore, according to this method, the bird's beak of the element isolation oxide film 35 is very small. Further, unlike the case where the polysilicon layer of FIG. 4 is used, an abnormal projection is not generated on the bird's beak.
【００２１】その後、シリコン窒化膜パターン３３ａと
サイドウォール３４ａを除去した後、基板３１の回路素
子領域３９にＦＥＴトランジスタや双極性トランジス
タ、ダイオード、キャパシタ、あるいは抵抗などの回路
素子を形成する。Thereafter, after removing the silicon nitride film pattern 33a and the sidewalls 34a, circuit elements such as FET transistors, bipolar transistors, diodes, capacitors, and resistors are formed in the circuit element region 39 of the substrate 31.
【００２２】なお、上記のような本発明の方法に類似す
る技術として特開平７−２６３４３２号公報がある。し
かるに、この公報技術では、素子分離領域のパッド酸化
膜をすべて除去したのち、該領域に新たに薄いパッド酸
化膜を形成する方法であるため、工程が面倒になる。こ
れに対して、本発明の方法によれば、素子分離領域の下
部シリコン酸化膜３２の表面側をエッチングして、下部
側は残して薄膜部分３２ａを形成する方法であり、工程
が簡単になる。Japanese Patent Application Laid-Open No. Hei 7-263432 discloses a technique similar to the method of the present invention as described above. However, according to this publication technique, after removing all the pad oxide film in the element isolation region, a new thin pad oxide film is formed in the region, so that the process becomes complicated. On the other hand, according to the method of the present invention, the surface side of the lower silicon oxide film 32 in the element isolation region is etched to form the thin film portion 32a while leaving the lower side, and the process is simplified. .
【００２３】また、他の類似技術として特開平８−８２
４５号公報がある。しかるに、この公報技術では、素子
分離領域の下地酸化膜をすべて除去した状態で窒化膜サ
イドウォールを形成しているので、該サイドウォールが
直接シリコン基板と接するようになり、窒化膜サイドウ
ォールによる応力の問題がある。これに対して、本発明
の方法によれば、下部シリコン酸化膜３２の薄膜部分３
２ａを残すことにより、サイドウォール３４ａ部分も含
めてシリコン窒化膜が直接シリコン基板３１に接するこ
とを防止でき、シリコン窒化膜による応力の問題を防止
できる。Another similar technique is disclosed in Japanese Patent Application Laid-Open No. 8-82.
No. 45 publication. However, according to this technique, the nitride film sidewall is formed in a state where the underlying oxide film in the element isolation region is completely removed, so that the sidewall comes into direct contact with the silicon substrate, and the stress due to the nitride film sidewall is reduced. There is a problem. On the other hand, according to the method of the present invention, the thin film portion 3 of the lower silicon oxide film 32 is formed.
By leaving 2a, it is possible to prevent the silicon nitride film including the side wall 34a from directly contacting the silicon substrate 31, and it is possible to prevent the problem of stress due to the silicon nitride film.
【００２４】[0024]
【発明の効果】以上詳細に説明したように、本発明によ
る半導体装置の素子分離領域形成方法によれば、素子分
離酸化膜のバーズビークを非常に小さくすることができ
るとともに、バーズビークの上に非正常的な突出部が形
成されることを防止できる。また、バーズビークを小さ
くすることができれば、高集積化が可能になるだけでな
く、バーズビーク分だけ素子分離領域を狭めて工程を実
施する必要がなく、適正の大きさの素子分離領域で工程
を進めることができるから、各工程が容易となり、かつ
比較的短い熱酸化時間で素子分離酸化膜を形成できる。
さらに、本発明の方法によれば、類似の公報技術に比較
して工程を簡単にすることができるとともに、シリコン
窒化膜による応力の問題を解決できる。As described above in detail, according to the method for forming an element isolation region of a semiconductor device according to the present invention, a bird's beak of an element isolation oxide film can be made extremely small, and an abnormal state can be formed on the bird's beak. The formation of a temporary protrusion can be prevented. In addition, if the bird's beak can be reduced, not only high integration can be achieved, but also it is not necessary to perform the process by narrowing the element isolation region by the bird's beak, and proceed with the process in an appropriately sized element isolation region. Therefore, each step becomes easy, and an element isolation oxide film can be formed in a relatively short thermal oxidation time.
Further, according to the method of the present invention, the process can be simplified as compared with the similar publication technique, and the problem of the stress caused by the silicon nitride film can be solved.
【図１】本発明による半導体装置の素子分離領域形成方
法の実施の形態を示す断面図。FIG. 1 is a sectional view showing an embodiment of a method for forming an element isolation region of a semiconductor device according to the present invention.
【図２】本発明による半導体装置の素子分離領域形成方
法の実施の形態を示し、図１に続く工程を示す断面図。FIG. 2 is a sectional view showing an embodiment of a method for forming an element isolation region of a semiconductor device according to the present invention, and showing a step following FIG. 1;
【図３】従来の半導体装置の素子分離領域形成方法を示
す断面図。FIG. 3 is a cross-sectional view showing a conventional method for forming an element isolation region of a semiconductor device.
【図４】従来の半導体装置の素子分離領域形成方法の他
の例を示す断面図。FIG. 4 is a sectional view showing another example of a conventional method for forming an element isolation region of a semiconductor device.
３１ シリコン基板 ３２ 下部シリコン酸化膜 ３２ａ 薄膜部分 ３３ 第１シリコン窒化膜 ３３ａ 第１シリコン窒化膜パターン ３４ 第２シリコン窒化膜 ３４ａ サイドウォール ３５ 素子分離酸化膜 Reference Signs List 31 silicon substrate 32 lower silicon oxide film 32a thin film portion 33 first silicon nitride film 33a first silicon nitride film pattern 34 second silicon nitride film 34a sidewall 35 device isolation oxide film
Claims (12)
工程と、 前記パッド酸化膜上にシリコン窒化膜を形成する工程
と、 前記シリコン窒化膜をパターニングして、前記半導体基
板の回路素子領域上にシリコン窒化膜パターンを形成す
るとともに、前記半導体基板の素子分離領域の前記パッ
ド酸化膜を露出させる工程と、 露出した素子分離領域の前記パッド酸化膜の表面側を除
去して、この部分のパッド酸化膜を他の部分より薄くす
る工程と、 前記工程により薄くなった部分とその他の厚い部分との
境に生じた前記パッド酸化膜の側壁部および前記シリコ
ン窒化膜パターンの側壁部にシリコン窒化膜のサイドウ
ォールを形成する工程と、 前記サイドウォールと前記シリコン窒化膜パターンをマ
スクとして素子分離領域の前記半導体基板表面部を熱酸
化し、該部分に素子分離酸化膜を形成する工程とを具備
してなる半導体装置の素子分離領域形成方法。A step of forming a pad oxide film on a semiconductor substrate; a step of forming a silicon nitride film on the pad oxide film; and patterning the silicon nitride film to form a silicon nitride film on a circuit element region of the semiconductor substrate. Forming a silicon nitride film pattern on the semiconductor substrate and exposing the pad oxide film in an element isolation region of the semiconductor substrate; and removing a surface side of the pad oxide film in the exposed element isolation region to form a pad in this portion. A step of making the oxide film thinner than the other portion; and a silicon nitride film on a side wall portion of the pad oxide film and a side wall portion of the silicon nitride film pattern generated at a boundary between the thinned portion and the other thick portion by the step. Forming a sidewall of the semiconductor substrate surface of an element isolation region using the sidewall and the silicon nitride film pattern as a mask The thermally oxidized, the isolation region formation method of a semiconductor device formed by a step of forming a device isolation oxide film is partial.
域形成方法において、半導体基板はシリコン基板である
ことを特徴とする半導体装置の素子分離領域形成方法。2. The method according to claim 1, wherein the semiconductor substrate is a silicon substrate. 2. The method according to claim 1, wherein the semiconductor substrate is a silicon substrate.
域形成方法において、パッド酸化膜は熱酸化によって形
成されることを特徴とする半導体装置の素子分離領域形
成方法。3. The method according to claim 1, wherein the pad oxide film is formed by thermal oxidation.
域形成方法において、パッド酸化膜はシリコン酸化膜で
あることを特徴とする半導体装置の素子分離領域形成方
法。4. The method according to claim 1, wherein the pad oxide film is a silicon oxide film.
域形成方法において、パッド酸化膜上のシリコン窒化膜
は蒸着法で形成されることを特徴とする半導体装置の素
子分離領域形成方法。5. The method according to claim 1, wherein the silicon nitride film on the pad oxide film is formed by an evaporation method.
域形成方法において、シリコン窒化膜パターンはフォト
リソグラフィ技術によって形成されることを特徴とする
半導体装置の素子分離領域形成方法。6. The method according to claim 1, wherein the silicon nitride film pattern is formed by a photolithography technique.
域形成方法において、露出した素子分離領域のパッド酸
化膜は、該パッド酸化膜のその他の部分の約３分の１の
厚さに薄くされることを特徴とする半導体装置の素子分
離領域形成方法。7. The method according to claim 1, wherein a pad oxide film of the exposed element isolation region is thinned to about one third of a thickness of another portion of the pad oxide film. A method for forming an element isolation region of a semiconductor device.
域形成方法において、露出した素子分離領域のパッド酸
化膜の薄膜化は、シリコン窒化膜パターンをマスクにし
て等方性エッチングで行われることを特徴とする半導体
装置の素子分離領域形成方法。8. The method for forming an element isolation region of a semiconductor device according to claim 1, wherein the thinning of the pad oxide film in the exposed element isolation region is performed by isotropic etching using a silicon nitride film pattern as a mask. A method for forming an element isolation region of a semiconductor device.
域形成方法において、露出した素子分離領域のパッド酸
化膜の薄膜化は、シリコン窒化膜パターンをマスクにし
てシリコン窒化膜パターンの下にアンダーカットを有し
て等方性エッチングで行われることを特徴とする半導体
装置の素子分離領域形成方法。9. The method for forming an element isolation region of a semiconductor device according to claim 1, wherein the thickness of the pad oxide film in the exposed element isolation region is reduced under the silicon nitride film pattern using the silicon nitride film pattern as a mask. A method for forming an element isolation region of a semiconductor device, wherein the method is performed by isotropic etching with a cut.
領域形成方法において、サイドウォールは、薄膜化が終
了した素子分離領域の露出したパッド酸化膜とシリコン
窒化膜パターンの全面にシリコン窒化膜を形成したの
ち、該シリコン窒化膜を乾式エッチング法でエッチング
することにより形成されることを特徴とする半導体装置
の素子分離領域形成方法。10. The method for forming an element isolation region of a semiconductor device according to claim 1, wherein the sidewall has a silicon nitride film on the entire surface of the exposed pad oxide film and the silicon nitride film pattern in the element isolation region whose thickness has been reduced. A method for forming an element isolation region of a semiconductor device, comprising: forming a silicon nitride film by a dry etching method after forming the silicon nitride film.
離領域形成方法において、サイドウォール形成用のシリ
コン窒化膜は蒸着法で形成されることを特徴とする半導
体装置の素子分離領域形成方法。11. The method for forming an element isolation region of a semiconductor device according to claim 10, wherein the silicon nitride film for forming the sidewall is formed by an evaporation method.
領域形成方法において、サイドウォールは、アンダーカ
ット部を埋めて形成されることを特徴とする半導体装置
の素子分離領域形成方法。12. The method according to claim 9, wherein the sidewall is formed by filling an undercut portion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1996P-71823 | 1996-12-24 | ||
| KR1019960071823A KR100205612B1 (en) | 1996-12-24 | 1996-12-24 | Method of forming isolation region in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10189707A true JPH10189707A (en) | 1998-07-21 |
| JP3856410B2 JP3856410B2 (en) | 2006-12-13 |
Family
ID=19490837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14257697A Expired - Lifetime JP3856410B2 (en) | 1996-12-24 | 1997-05-30 | Method for forming element isolation region of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3856410B2 (en) |
| KR (1) | KR100205612B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010058339A (en) * | 1999-12-27 | 2001-07-05 | 박종섭 | Method for forming isolation layer of semiconductor device |
-
1996
- 1996-12-24 KR KR1019960071823A patent/KR100205612B1/en not_active IP Right Cessation
-
1997
- 1997-05-30 JP JP14257697A patent/JP3856410B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR100205612B1 (en) | 1999-07-01 |
| JP3856410B2 (en) | 2006-12-13 |
| KR19980052798A (en) | 1998-09-25 |
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