JPH10189589A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH10189589A JPH10189589A JP34069696A JP34069696A JPH10189589A JP H10189589 A JPH10189589 A JP H10189589A JP 34069696 A JP34069696 A JP 34069696A JP 34069696 A JP34069696 A JP 34069696A JP H10189589 A JPH10189589 A JP H10189589A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- metal
- coating film
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体集積回路に関
し、特に多層配線構造の各金属配線層間に塗布焼成形成
された絶縁膜を有する半導体集積回路の金属配線のレイ
アウト構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a layout structure of metal wiring of a semiconductor integrated circuit having an insulating film formed by coating and firing between metal wiring layers of a multilayer wiring structure.
【0002】[0002]
【従来の技術】一般に多層配線構造の半導体集積回路で
は、下層の金属配線と上層の金属配線とを絶縁分離する
ための絶縁膜として、絶縁材を塗布しかつこれを焼成す
る技術が提案されている。この種の技術としては、例え
ば特開平4−10540号公報に示される技術があり、
特に半導体集積回路の高集積化に対処すべく、層間絶縁
膜の平坦性を向上し、上層金属配線の断線や金属配線同
士の短絡を防止している。図8は従来の半導体集積回路
における絶縁膜の形成工程を示す工程フロー断面図であ
る。同図において、先ず(a)のように、半導体基板1
0上に形成した下地絶縁膜11の上に金属配線膜を形成
し、これを選択エッチングして金属配線1,2,3,
4,5をパターニング形成する。その後、(b)のよう
に、全面に第一プラズマ酸化膜12を成長する。さら
に、塗布および焼成により絶縁塗布膜13を形成して、
前記第一プラズマ酸化膜12の表面の段差を緩和する。
次いで、(c)のように、第二プラズマ酸化膜15を成
長し、かつ所要箇所にスルーホールを開口した上で、上
層金属配線16をパターニングする。2. Description of the Related Art In general, in a semiconductor integrated circuit having a multilayer wiring structure, a technique has been proposed in which an insulating material is applied and fired as an insulating film for insulating and separating a lower metal wiring and an upper metal wiring. I have. As this type of technology, for example, there is a technology disclosed in JP-A-4-10540.
In particular, in order to cope with high integration of a semiconductor integrated circuit, the flatness of an interlayer insulating film is improved to prevent disconnection of upper metal wiring and short-circuit between metal wirings. FIG. 8 is a process flow sectional view showing a process of forming an insulating film in a conventional semiconductor integrated circuit. In the figure, first, as shown in FIG.
A metal wiring film is formed on the underlying insulating film 11 formed on the metal wiring 1, and is selectively etched to form the metal wirings 1, 2, 3, and 3.
Patterns 4 and 5 are formed. After that, the first plasma oxide film 12 is grown on the entire surface as shown in FIG. Further, an insulating coating film 13 is formed by coating and baking,
The step on the surface of the first plasma oxide film 12 is reduced.
Next, as shown in (c), after the second plasma oxide film 15 is grown and a through hole is opened at a required position, the upper metal wiring 16 is patterned.
【0003】このような製造工程において、前記した公
報においては、第一プラズマ酸化膜12の膜厚を第二プ
ラズマ酸化膜15よりも厚くすることにより、隣接する
金属配線の間隔寸法を狭くし、塗布焼成により形成され
る絶縁塗布膜13が金属配線間に生じている凹部内に好
適に埋め込むようにすることで、絶縁膜の表面の平坦化
を図っている。In such a manufacturing process, in the above-mentioned publication, the thickness of the first plasma oxide film 12 is made larger than that of the second plasma oxide film 15 so that the distance between adjacent metal wirings is reduced. The surface of the insulating film is flattened by suitably burying the insulating coating film 13 formed by the coating and baking in the recess formed between the metal wirings.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、この公
報に記載の技術では、金属配線間の凹部への絶縁塗布膜
埋め込み性が、局所的に悪化し易い金属配線パターンが
存在するという問題が生じることがある。すなわち、図
8に示した例の場合、金属配線1,2,3,4,5の各
配線幅L1,L2,L3,L4,L5がこの半導体集積
回路の最小金属配線幅に等しく、金属配線1と2の配線
間隔幅S12と金属配線2と3の配線間隔幅S23と金
属配線3と4の配線間隔幅S34と金属配線4と5の配
線間隔幅S45がS12>S23=S34=S45の状
態である場合を示している。この場合、絶縁塗布膜の回
転塗布時に、片隣に広い配線間隔幅S12の領域を有す
る配線間隔幅S23の領域の方が、両隣の配線間隔幅S
23,S45が等しい配線間隔幅S34の領域よりも、
金属配線間の凹部への絶縁塗布膜埋め込み性が悪化し易
くなる。図8の例では、配線間隔幅S23の凹部14へ
の絶縁塗布膜の埋め込み性が悪化する。However, in the technique described in this publication, there is a problem in that there is a metal wiring pattern in which the burying property of the insulating coating film in the recess between the metal wirings tends to be locally deteriorated. There is. That is, in the case of the example shown in FIG. 8, the wiring widths L1, L2, L3, L4, and L5 of the metal wirings 1, 2, 3, 4, and 5 are equal to the minimum metal wiring width of the semiconductor integrated circuit. 1 and 2, the wiring spacing S23 between the metal wirings 2 and 3, the wiring spacing S34 between the metal wirings 3 and 4, and the wiring spacing S45 between the metal wirings 4 and 5 are S12> S23 = S34 = S45. This shows the case where the state is the state. In this case, at the time of spin-coating of the insulating coating film, the area of the wiring interval width S23 having the area of the wide wiring interval width S12 on one side is closer to the wiring interval width S on both sides.
23 and S45 are equal to or larger than the area of the wiring interval width S34.
The embedding property of the insulating coating film in the concave portions between the metal wirings is easily deteriorated. In the example of FIG. 8, the embedding property of the insulating coating film into the recess 14 having the wiring interval width S23 is deteriorated.
【0005】その理由は、図3(a)に示す様に、絶縁
塗布膜の回転塗布中、塗布膜が落ち着くまでは、塗布膜
は配線上部から、低い領域である配線間隔幅S12,S
23の領域に広がろうとする力F1,F4が働き、また
配線上部に塗布膜が留まろうとする力F2,F3も働
く。この場合、狭い配線間隔幅S23の領域よりも広い
配線間隔幅S12の領域の方に塗布膜が広がり易く、塗
布膜が落ち着くまでは力F4よりも力F1の方が強く働
く。この力F1の影響により、力F3が塗布膜を金属配
線2の上部に引っ張る力が強まり、配線間隔幅S23の
領域に埋め込まれようとしている塗布膜の一部が金属配
線2の上部へ引っ張られ、金属配線2を乗り越え、配線
間隔幅S12の領域に広がっていく。この様に、金属配
線2の両側の配線間隔幅S12と配線間隔幅S23がS
12>S23の場合、配線間隔幅S23の領域に埋め込
まれる塗布膜量は、隣により広い配線間隔の領域が無い
配線間隔幅S34の領域よりも、少なくなるからであ
る。The reason for this is that, as shown in FIG. 3A, during the spin-coating of the insulating coating film, until the coating film is settled, the coating film is arranged from the upper portion of the wiring to the lower wiring interval widths S12 and S12.
The forces F1 and F4 that try to spread in the region 23 and the forces F2 and F3 that try to keep the coating film on the wiring also act. In this case, the coating film is more likely to spread in the region with the wider wiring spacing S12 than in the region with the smaller wiring spacing S23, and the force F1 acts stronger than the force F4 until the coating film is settled. Due to the influence of the force F1, the force of the force F3 pulling the coating film to the upper part of the metal wiring 2 is increased, and a part of the coating film to be buried in the area of the wiring interval width S23 is pulled to the upper part of the metal wiring 2. Over the metal wiring 2 and spread to the area of the wiring interval width S12. As described above, the wiring interval width S12 and the wiring interval width S23 on both sides of the metal wiring 2 are S
This is because, in the case of 12> S23, the amount of the coating film buried in the area of the wiring interval width S23 is smaller than that of the area of the wiring interval width S34 in which there is no area with a wider wiring interval next to the area.
【0006】したがって、前記公報に記載の半導体集積
回路では、前記したように第一プラズマ酸化膜12を厚
くすることにより、塗布膜の埋め込み性の向上を図って
いるが、このように第一プラズマ酸化膜12を厚くして
金属配線間の凹部の実効間隔を狭くした場合、金属配線
間の凹部に元々埋め込まれるべき塗布膜量が少なくな
り、配線間隔幅S12の領域への塗布膜流出により配線
間隔幅S23の領域に残る塗布膜の量が減り、第一プラ
ズマ酸化膜12が薄い場合よりも埋め込み性が悪くな
り、前記したような金属配線のパターン部においては逆
に悪化し易くなる。Therefore, in the semiconductor integrated circuit described in the above publication, the embedding property of the coating film is improved by thickening the first plasma oxide film 12 as described above. In the case where the oxide film 12 is thickened to reduce the effective space between the concave portions between the metal wires, the amount of the coating film to be originally buried in the concave portion between the metal wires is reduced, and the wiring film flows out to the region of the wiring space width S12. The amount of the coating film remaining in the region of the interval width S23 is reduced, the embedding property becomes worse as compared with the case where the first plasma oxide film 12 is thin, and the metal wiring pattern portion is liable to be worse on the contrary.
【0007】また、もう他の理由として、第一プラズマ
酸化膜12を厚くすることで、図9(a)に示すよう
に、塗布膜が埋め込まれる凹部のアスペクト比R1(=
凹部実効深さD1÷凹部実効間隔W1)が大きくなり、
絶縁塗布膜の埋め込み性が薄い場合よりも悪くなる場合
があるからである。金属配線間凹部への絶縁塗布膜13
の埋め込み性に影響を与える要因として、塗布膜が埋め
込まれる凹部のアスペクト比R1があり、アスペクト比
R1が大きいほど、絶縁塗布膜13の埋め込み性は悪化
する。また、金属配線間凹部の底部における第−プラズ
マ酸化膜成長膜厚22は、金属配線間隔凹部アスペクト
比R2(=金属配線高さH1÷金属配線間隔W2)に影
響を受け、アスペクト比R2が高いほど、凹部の底部に
おける成長膜厚T1は薄くなる。これにより、第一プラ
ズマ酸化膜12を厚くすることにより、塗布膜が埋め込
まれる凹部アスペクト比R1が大きくなり、絶縁塗布膜
の埋め込み性が悪くなる場合がある。As another reason, by increasing the thickness of the first plasma oxide film 12, as shown in FIG. 9A, the aspect ratio R1 (=
The effective depth D1 of the concave portion / the effective interval W1 of the concave portion is increased,
This is because the embedding property of the insulating coating film may be worse than when the embedding property is thin. Insulating coating film 13 on recess between metal wirings
As a factor that affects the burying property of the insulating film, there is an aspect ratio R1 of the concave portion in which the coating film is buried. As the aspect ratio R1 increases, the burying property of the insulating coating film 13 deteriorates. In addition, the negative-plasma oxide film growth thickness 22 at the bottom of the inter-metal interconnect recess is affected by the inter-metal interconnect recess aspect ratio R2 (= metal interconnect height H1 ÷ metal interconnect interval W2), and the aspect ratio R2 is high. As the thickness increases, the growth thickness T1 at the bottom of the concave portion decreases. As a result, by increasing the thickness of the first plasma oxide film 12, the aspect ratio R1 of the concave portion in which the coating film is buried is increased, and the burying property of the insulating coating film may be deteriorated.
【0008】図9(b)に第一プラズマ酸化膜12の成
長膜厚の違いによる凹部アスペクト比の変化の一例を示
す。金属配線高さH1を8000Å、金属配線間隔W2を15
000Åとし、金属配線間底部の成長膜厚T1が配線上の
成長膜厚T2の80%、金属配線側壁部の成長膜厚T3
が配線上の成長膜厚T2の50%である場合を考える。
第一プラズマ酸化膜12の配線上の成長膜厚T2が6000
Åとすると、配線間底部の成長膜厚T1は4800Åとな
り、凹部アスペクト比R1は(8000Å+6000Å−4800
Å)÷(15000 Å−6000Å×0.50×2)=1.02となる。
また、配線上の成長膜厚T2が8000Åとすると、配線間
底部の成長膜厚T1は6400Åとなり、凹部アスペクト比
R1は(8000Å+8000Å−6400Å)÷(15000 Å−8000
Å×0.50×2)=1.37となる。この様にして、第一プラ
ズマ酸化膜12の膜厚を厚くした場合の方が、塗布膜が
埋め込まれる凹部のアスペクト比R1が大きくなり、絶
縁塗布膜の埋め込み性が悪化し易くなる。絶縁塗布膜埋
め込み性に対しては、第一プラズマ酸化膜12の膜厚と
凹部アスペクト比R1との間にはトレードオフが存在
し、半導体集積回路の集積度が上がってきて、配線幅や
配線間隔が細くなればなるほど、アスペクト比の影響の
方が強くなり、第一プラズマ酸化膜12の厚膜化は埋め
込み性に対して不利になる。FIG. 9B shows an example of a change in the recess aspect ratio due to a difference in the growth film thickness of the first plasma oxide film 12. Metal wiring height H1 is 8000Å, metal wiring interval W2 is 15
000 °, the growth thickness T1 at the bottom between the metal wirings is 80% of the growth thickness T2 on the wirings, and the growth thickness T3 at the side walls of the metal wirings
Is 50% of the growth film thickness T2 on the wiring.
The growth thickness T2 of the first plasma oxide film 12 on the wiring is 6000
Å, the growth film thickness T1 at the bottom between the wirings is 4800Å, and the recess aspect ratio R1 is (8000Å + 6000Å-4800).
Å) ÷ (15000 Å-6000Å × 0.50 × 2) = 1.02.
Further, if the growth thickness T2 on the wiring is 8000 °, the growth thickness T1 at the bottom between the wirings is 6400 °, and the recess aspect ratio R1 is (8000 ° + 8000 ° −6400 °) Å (15000 ° −8000).
Å × 0.50 × 2) = 1.37. As described above, when the thickness of the first plasma oxide film 12 is increased, the aspect ratio R1 of the concave portion in which the coating film is buried is increased, and the burying property of the insulating coating film is easily deteriorated. There is a trade-off between the thickness of the first plasma oxide film 12 and the recess aspect ratio R1 with respect to the embedding property of the insulating coating film. As the spacing becomes smaller, the influence of the aspect ratio becomes stronger, and increasing the thickness of the first plasma oxide film 12 is disadvantageous to the embedding property.
【0009】さらに、前記したように絶縁塗布膜の埋め
込み性が悪化した場合には、その後の工程で別の問題が
発生する。図10はこれを説明するための図であり、ま
ず、同図(a)のように、塗布の埋め込み性が悪化する
と、同図(b)のように第二プラズマ酸化膜15のさら
に上層に形成される上層金属配線16が、同図(c)の
ように、この埋め込み性が悪化した金属配線間の凹部2
1にエッチングされずに残り、歩留まり及び信頼性が悪
化する。これは、上層金属配線16の成膜工程後、上層
金属配線をバターニングする為のフォトレジスト22が
埋め込み性悪化の凹部21に残り易くなり、残った場合
に上層金属配線16をエッチングしきれなくなるためで
ある。また、塗布の埋め込み性が悪化した場合、第二プ
ラズマ酸化膜15のさらに上層に形成される上層金属配
線16が、この埋め込み性が悪化した部分で段切れを起
こし、歩留まり及び信頼性が悪化する。これは、上層の
配線膜成膜工程にて、段差が厳しくなっている部分の側
壁部の上層金属配線16の成膜量が、上部や底部よりも
薄くなるためである。Further, when the burying property of the insulating coating film is deteriorated as described above, another problem occurs in the subsequent steps. FIG. 10 is a diagram for explaining this. First, as shown in FIG. 10A, when the embedding property of the coating is deteriorated, as shown in FIG. As shown in FIG. 3C, the upper metal wiring 16 to be formed has the recesses 2 between the metal wirings whose embedding property has deteriorated.
1 remains without being etched, yield and reliability are degraded. This is because, after the film formation process of the upper metal wiring 16, the photoresist 22 for patterning the upper metal wiring tends to remain in the concave portion 21 having a poor filling property, and if it remains, the upper metal wiring 16 cannot be completely etched. That's why. Further, when the embedding property of the coating is deteriorated, the upper metal wiring 16 formed further above the second plasma oxide film 15 is disconnected at the portion where the embedding property is deteriorated, and the yield and the reliability are deteriorated. . This is because, in the step of forming the upper wiring film, the film thickness of the upper metal wiring 16 on the side wall portion where the step is severe is smaller than that of the upper or bottom portion.
【0010】本発明の目的は、多層配線構造の層間絶縁
塗布膜の配線間埋め込み性を向上し、層間絶縁膜の平坦
性を向上し、半導体集積回路の信頼性及び歩留まりを向
上することにある。An object of the present invention is to improve the inter-wiring embedding property of an interlayer insulating coating film of a multilayer wiring structure, improve the flatness of an interlayer insulating film, and improve the reliability and yield of a semiconductor integrated circuit. .
【0011】[0011]
【課題を解決するための手段】本発明は、同一平面上に
それぞれ所要の間隔で配列された複数の配線と、これら
の配線を覆うように塗布形成される絶縁塗布膜とを備え
る半導体集積回路において、両隣の配線間隔が異なる配
線は、両隣の配線間隔が等しい配線よりもその配線幅を
大きく形成したことを特徴とする。複数の配線は所定の
間隔で配列され、両隣のうちの一方の配線間隔が前記所
定の間隔よりも大きい金属配線は、両隣の配線間隔が前
記所定の間隔の配線よりもその配線幅を大きく形成す
る。また、両隣の配線間隔が等しい配線は、設計上の最
小寸法幅に設定され、両隣の配線間隔が異なる配線は前
記最小寸法幅よりも大きい寸法幅に設定される。According to the present invention, there is provided a semiconductor integrated circuit comprising a plurality of wirings arranged at predetermined intervals on the same plane, and an insulating coating film formed by coating so as to cover these wirings. Is characterized in that a wiring having a different wiring interval on both sides has a larger wiring width than a wiring having an equal wiring distance on both sides. A plurality of wirings are arranged at a predetermined interval, and a metal wiring in which one of the two adjacent wiring intervals is larger than the predetermined interval has a larger wiring width than the wiring with the adjacent wiring intervals of the predetermined interval. I do. In addition, a wiring having the same wiring interval on both sides is set to a minimum dimension width in design, and a wiring having a different wiring interval on both sides is set to a larger dimension width than the minimum dimension width.
【0012】[0012]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図1は、本発明の半導体集積回路の
実施の形態の例を示す平面図とそのAA線に沿う断面図
である。半導体基板10上に下地絶縁膜11が形成さ
れ、この下地絶縁膜11上に複数本の金属配線1,2,
3,4,5が所要の間隔をおいて平行に配列形成されて
いる。ここで、前記配線1〜5の配線幅をそれぞれL
1,L2,L3,L4,L5とし、ここではL2>L1
=L3=L4=L5とする。ただし、前記配線幅L1,
L3,L4,L5はこの同一金属配線層内で最小の金属
配線幅とする。また、金属配線1と2の配線間隔幅S1
2と金属配線2と3の配線間隔幅S23と金属配線3と
4の配線間隔幅S34と金属配線4と5の配線間隔幅S
45がS12>S23=S34=S45の状態である場
合を示している。そして、この実施形態の半導体集積回
路では、両隣の配線間隔幅S12とS23が異なる金属
配線2の配線幅L2が、同一金属配線層内で最小の金属
配線幅L1(L3,L4,L5)よりも太い配線幅を有
する構成とされている。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing an example of an embodiment of a semiconductor integrated circuit according to the present invention, and a cross-sectional view taken along line AA. A base insulating film 11 is formed on a semiconductor substrate 10, and a plurality of metal wirings 1, 2, 2,
3, 4, 5 are arranged in parallel at a required interval. Here, the width of each of the wirings 1 to 5 is L
1, L2, L3, L4, L5, where L2> L1
= L3 = L4 = L5. However, the wiring width L1,
L3, L4, and L5 are the minimum metal wiring widths in the same metal wiring layer. Also, the wiring interval width S1 between the metal wirings 1 and 2
2, the wiring spacing S23 between the metal wirings 2 and 3, the wiring spacing S34 between the metal wirings 3 and 4, and the wiring spacing S between the metal wirings 4 and 5
45 shows a case where S12> S23 = S34 = S45. In the semiconductor integrated circuit of this embodiment, the wiring width L2 of the metal wiring 2 having different wiring spacing widths S12 and S23 on both sides is smaller than the minimum metal wiring width L1 (L3, L4, L5) in the same metal wiring layer. It is configured to have a large wiring width.
【0013】各金属配線1,2,3,4,5は、同種の
膜構造で同時に形成される。金属配線の材料は、アルミ
を主成分とした物質が一般的である。配線幅の違いは、
半導体集積回路のレイアウトデザインする際に、平行に
配置されている隣の金属配線との間隔幅が両隣で異なる
金属配線を、狭い間隔側の隣の金属配線よりも配線幅を
太くデザインすることにより実施する。レイアウトデザ
インする際には、金属配線同士の間隔やスルーホール、
コンタクトホールとの間隔等のデザインルールの制約に
従う範囲内で配線幅を太くデザインする。これにより、
金属配線形成工程に用いるポジ型フォトレジストマスク
作成時に、電子線描画等の方法により、ポジ型フォトレ
ジストマスク上のパターンの配線幅が前記レイアウトデ
ザインに従って形成される。このポジ型フォトレジスト
マスクを用いて金属配線を形成することにより、前記し
た半導体集積回路が形成される。The metal wirings 1, 2, 3, 4, and 5 are formed simultaneously with the same type of film structure. The material of the metal wiring is generally a substance containing aluminum as a main component. The difference in wiring width is
When designing the layout of a semiconductor integrated circuit, by designing a metal wiring with a different spacing width between adjacent metal wirings arranged in parallel on both sides, making the wiring width wider than the adjacent metal wiring on the narrower spacing side carry out. When designing the layout, the distance between metal wirings, through holes,
The wiring width is designed to be as large as possible within the range that complies with the design rules such as the distance from the contact hole. This allows
When forming a positive photoresist mask used in the metal wiring forming step, the wiring width of the pattern on the positive photoresist mask is formed in accordance with the layout design by a method such as electron beam drawing. The above-mentioned semiconductor integrated circuit is formed by forming a metal wiring using this positive photoresist mask.
【0014】図2は、図1に示した金属配線に絶縁膜お
よび上層の金属配線を形成して半導体集積回路を製造す
る際の工程を示す図である。まず、(a)のように、半
導体基板10上に形成した下地絶縁膜11の上に金属膜
を形成し、これを選択エッチングして金属配線1,2,
3,4,5をパターニングし、図1の構造を得る。次い
で、(b)のように、全面に第一プラズマ酸化膜12を
成長する。さらに、(c)のように、絶縁膜を塗布しか
つ焼成して絶縁塗布膜13を形成し、前記第一プラズマ
酸化膜12の表面の段差を緩和する。しかる上で、
(c)のように、全面に第二プラズマ酸化膜15を成長
し、さらに所要箇所にスルーホールを開口した上で上層
金属配線16をパターニングする。FIG. 2 is a view showing a process for manufacturing a semiconductor integrated circuit by forming an insulating film and an upper metal wiring on the metal wiring shown in FIG. First, a metal film is formed on a base insulating film 11 formed on a semiconductor substrate 10 as shown in FIG.
By patterning 3, 4, and 5, the structure of FIG. 1 is obtained. Next, the first plasma oxide film 12 is grown on the entire surface as shown in FIG. Further, as shown in (c), an insulating film is applied and baked to form an insulating coating film 13, and a step on the surface of the first plasma oxide film 12 is reduced. In doing so,
As shown in (c), a second plasma oxide film 15 is grown on the entire surface, and a through hole is opened at a required position, and then the upper metal wiring 16 is patterned.
【0015】この例における特徹は、両隣に平行に配置
されている金属配線1および2との間隔幅である配線間
隔S12とS23が異なる間隔幅(S12>S23)を
有している金属配線2の配線幅L2を、本集積回路の最
小金属配線幅L1(L3,L4,L5)よりも太い配線
幅に形成させることにより、塗布焼成により形成される
絶縁塗布膜13の凹部14への埋め込み性が悪化するこ
とに対する許容マージンを向上し、絶縁層間膜の平坦化
が実現される。The feature of this embodiment is that the metal wirings S12 and S23, which are the widths of the metal wirings 1 and 2 arranged in parallel on both sides, have different widths (S12> S23). 2 is formed to be larger than the minimum metal wiring width L1 (L3, L4, L5) of the present integrated circuit, so that the insulating coating film 13 formed by coating and firing is embedded in the concave portion 14. Thus, the allowable margin for the deterioration of the performance is improved, and the insulating interlayer film is flattened.
【0016】その理由を図3を参照して説明する。同図
(a)のように、絶縁塗布膜の回転塗布中、塗布膜が落
ち着くまでは、塗布膜は配線上部から、低い領域である
配線間隔部6,7に広がろうとする力F1,F4が働
き、また配線上部に塗布膜が留まろうとする力F2,F
3も働く。この場合、狭い配線間隔S12の領域よりも
広い配線間隔S23の領域の方に塗布膜が広がり易く、
塗布膜が落ち着くまでは力F4よりも力F1の方が強く
鋤く。この力F1の影響により、力F3が塗布膜を金属
配線2の上部に引っ張る力が強まり、配線間隔S12の
領域に埋め込まれようとしている塗布膜の一部が金属配
線2の上部へ引っ張られ、金属配線2を乗り越え、配線
間隔S12の領域に広がっていく。この様に、金属配線
2の両側の配線間隔S12と配線間隔S23がS12>
S23の場合、配線間隔S12の領域に埋め込まれる塗
布膜量は、隣により広い配線間隔の領域が無い配線間隔
S23の領域よりも、少なくなり易い。The reason will be described with reference to FIG. As shown in FIG. 3A, during the spin coating of the insulating coating film, the coating film is forced to spread from the upper portion of the wiring to the wiring space portions 6 and 7, which are low regions, until the coating film settles. Works, and the forces F2 and F that the coating film tends to stay on the wiring
3 also works. In this case, the coating film is more likely to spread in the region of the wide wiring interval S23 than in the region of the narrow wiring interval S12,
Until the coating film is settled, the force F1 plows more than the force F4. Due to the influence of the force F1, the force of the force F3 pulling the coating film to the upper part of the metal wiring 2 is increased, and a part of the coating film to be buried in the area of the wiring interval S12 is pulled to the upper part of the metal wiring 2, Over the metal wiring 2, it spreads to the area of the wiring interval S12. As described above, the wiring interval S12 and the wiring interval S23 on both sides of the metal wiring 2 are S12>
In the case of S23, the amount of the coating film buried in the region of the wiring interval S12 tends to be smaller than that of the region of the wiring interval S23 in which there is no region with a wider wiring interval next to the coating film.
【0017】これに対し、同図(b)に示す様に、金属
配線2の配線幅L2を大きくすると、回転塗布時に配線
間隔S12の領域に広がろうとする力F1の影響により
塗布膜を金属配線2の上部に引っ張る力である力F3の
強さが、弱まる効果がある。これは、配線間隔S12と
S23の各領域の距離が広がることにより、力F1の影
響が力F3に伝わり難くなり、また塗布膜が配線間隔S
12の領域から金属配線2を乗り越えていき難くなるた
めである。このため、配線間隔S12の領域の絶縁塗布
膜埋め込み性が悪化することに対する許容マージンが向
上する。On the other hand, as shown in FIG. 1B, when the wiring width L2 of the metal wiring 2 is increased, the coating film is formed by the influence of the force F1 which tends to spread to the area of the wiring interval S12 during spin coating. There is an effect that the strength of the force F3, which is a force pulling the wiring 2 upward, is weakened. This is because the influence of the force F1 is less likely to be transmitted to the force F3 due to the increase in the distance between the wiring intervals S12 and S23, and the coating film becomes
This is because it becomes difficult to get over the metal wiring 2 from the region 12. For this reason, the allowable margin for the deterioration of the filling property of the insulating coating film in the region of the wiring interval S12 is improved.
【0018】因みに、図1の例で、金属配線1,2,
3,4,5の配線幅L1,L2,L3,L4,L5を
1.2μm(この同一金属配線層内で最小の金属配線
幅)とし、金属配線1と2の配線間隔S12と金属配線
2と3の配線間隔S12と金属配線3と4の配線間隔S
34と金属配線4と5の配線間隔S45がS12=1
0.0μm>S23=S34=S45=1.4μmの状
態とし、金属配線は厚さが8000Åのアルミニウムを主成
分とした物質とする。この場合、両隣の配線間隔幅が異
なる金属配線2の配線幅L2を、この同一金属配線層内
で最小の金属配線幅である1.2μm以上となる様にレ
イアウトデザインする。この際には、金属配線同士の間
隔やスルーホール、コンタクトホールとの間隔等のデザ
インルールの制約に従う範囲内で配線幅を大きくする。
これにより、レイアウトデザインされた金属配線幅に従
ったポジ型フォトレジストマスクが、電子線描画等の方
法により作成される。このポジ型フォトレジストマスク
を用いて半導体基板上の金属配線を形成することによ
り、レイアウトデザインされた金属配線幅に従った本発
明の半導体集積回路となる。Incidentally, in the example of FIG.
The wiring widths L1, L2, L3, L4, and L5 of 3, 4, and 5 are set to 1.2 μm (the minimum metal wiring width in the same metal wiring layer), the wiring interval S12 between the metal wirings 1 and 2, and the metal wiring 2 3 between wirings S3 and S3 between metal wirings 3 and 4
34 and the wiring interval S45 between the metal wirings 4 and 5 is S12 = 1.
0.0 μm> S23 = S34 = S45 = 1.4 μm, and the metal wiring is made of a material mainly composed of aluminum having a thickness of 8000 °. In this case, the layout design is performed such that the wiring width L2 of the metal wirings 2 having different wiring spacing widths on both sides is 1.2 μm or more, which is the minimum metal wiring width in the same metal wiring layer. In this case, the wiring width is increased within a range that complies with the constraints of the design rules such as the distance between the metal wirings, the distance between the through-holes, and the contact holes.
Thus, a positive photoresist mask according to the layout-designed metal wiring width is created by a method such as electron beam drawing. By forming the metal wiring on the semiconductor substrate using this positive photoresist mask, the semiconductor integrated circuit of the present invention according to the metal wiring width designed for layout is obtained.
【0019】さらに、種々の金属配線パターンにおけ
る、本発明の他の実施の形態を図4ないし図7に示す。
これらの図は複数本の金属配線におけるLine/Sp
ace(以下、L/Sと略称)がそれぞれ異なる状態を
示す平面図と断面図である。図4の場合は、金属配線1
のみが離れて形成された場合であり、この場合には間隔
S12が大きい領域に隣接されている金属配線2の配線
幅L2を太くする。図5は、金属配線2,3,4が他と
孤立されている場合であり、この場合は間隔S12,S
45に隣接される金属配線2及び金属配線4の配線幅L
2,L4を太く構成する。図6は金属配線2,3が他と
孤立されている場合であり、この場合は間隔S12,S
34に隣接されている金属配線2及び金属配線3の配線
幅L2,L3を太くする。この例は、特に塗布膜の埋め
込み性が厳しいパターンである。図7は配線2と3の端
部が揃っていない状態の場合であり、間隔S12に隣接
される金属配線2の配線幅L2を大きくするとともに、
端部が揃っていないことにより結果として隣接する間隔
S13が大きくされている金属配線3の端部の配線幅L
3′を太くする。FIGS. 4 to 7 show other embodiments of the present invention in various metal wiring patterns.
These figures show Line / Sp in a plurality of metal wirings.
a (hereinafter abbreviated as L / S) are a plan view and a cross-sectional view showing different states. In the case of FIG.
In this case, the wiring width L2 of the metal wiring 2 adjacent to the region where the space S12 is large is increased. FIG. 5 shows a case in which the metal wirings 2, 3, and 4 are isolated from each other.
45, the wiring width L of the metal wiring 2 and the metal wiring 4 adjacent to each other.
2, L4 is made thick. FIG. 6 shows a case where the metal wirings 2 and 3 are isolated from each other.
The wiring widths L2 and L3 of the metal wirings 2 and 3 adjacent to 34 are increased. This example is a pattern in which the embedding property of the coating film is particularly severe. FIG. 7 shows a state in which the ends of the wirings 2 and 3 are not aligned. The wiring width L2 of the metal wiring 2 adjacent to the space S12 is increased, and
The wiring width L at the end of the metal wiring 3 whose adjacent space S13 is increased as a result of the end not being aligned.
Make 3 'thicker.
【0020】前記図4ないし図7のいずれの場合でも、
その金属配線と平行に配置されている隣の金属配線との
間隔幅が、両隣で異なる金属配線に対して、同一金属配
線層内で最小の金属配線幅よりも配線幅が大きく形成さ
れているので、塗布膜が配線間隔から金属配線を乗り越
えて、配線間隔に行き難くなり、塗布焼成により形成さ
れる絶縁塗布膜の凹部への埋め込み性が悪化することに
対する許容マージンが向上し、絶縁層間膜の平坦性が向
上し、半導体集積回路の信頼性及び歩留まりが向上す
る。In any of the cases of FIGS. 4 to 7,
The width of an interval between adjacent metal wirings arranged in parallel with the metal wiring is formed to be larger than the minimum metal wiring width in the same metal wiring layer with respect to different metal wirings on both sides. Therefore, the coating film gets over the metal wiring from the wiring interval, making it difficult to reach the wiring interval, and improving the allowable margin for the deterioration of the embedding property of the insulating coating film formed in the coating by sintering into the concave portion. Is improved, and the reliability and yield of the semiconductor integrated circuit are improved.
【0021】[0021]
【発明の効果】以上説明したように本発明は、両隣の配
線間隔が異なる配線、特に一方の配線間隔が大きい配線
の配線幅を、両隣の配線間隔が等しい配線の配線幅より
も大きく形成することにより、絶縁塗布膜の塗布時に、
絶縁塗布材が配線間隔から配線を乗り越えて、配線間隔
に行き難くなるために、絶縁塗布膜の埋め込み性が厳し
い配線間の凹部への塗布膜埋め込み性が悪化し難くな
る。これにより塗布により形成される絶縁塗布膜の凹部
への埋め込み性が悪化することに対する許容マージンが
向上し、絶縁塗布膜の平坦性を向上し、半導体集積回路
の信頼性及び歩留まりを向上することができる効果があ
る。As described above, according to the present invention, the wiring width of two adjacent wirings having different wiring intervals, in particular, the wiring width of one wiring having a large wiring distance is formed larger than the wiring width of the wiring having the same wiring distance between both adjacent wirings. By doing so, when applying the insulating coating film,
Since the insulating coating material crosses over the wiring from the wiring interval and does not easily go to the wiring interval, the embedding property of the insulating coating film is severe, and the coating film embedding property in the recess between the wirings hardly deteriorates. As a result, it is possible to improve an allowable margin for deterioration of the embedding property of the insulating coating film formed in the concave portion into the concave portion, improve flatness of the insulating coating film, and improve reliability and yield of the semiconductor integrated circuit. There is an effect that can be done.
【図1】本発明の一実施形態における金属配線の平面図
とそのBB線断面図である。FIG. 1 is a plan view of a metal wiring according to an embodiment of the present invention and a cross-sectional view taken along the line BB.
【図2】図1の金属配線に対する本発明の半導体集積回
路の製造工程を示す断面図である。FIG. 2 is a sectional view showing a manufacturing process of the semiconductor integrated circuit of the present invention for the metal wiring of FIG. 1;
【図3】絶縁塗布膜の形成時における、金属配線間の凹
部への塗布膜埋め込み具合を示す断面図とその場合の張
力を説明するための図である。FIGS. 3A and 3B are a cross-sectional view showing how a coating film is embedded in a recess between metal wirings when an insulating coating film is formed, and a diagram for explaining tension in that case.
【図4】本発明の他の第1の実施形態の金属配線の平面
図とその断面図である。FIG. 4 is a plan view and a cross-sectional view of a metal wiring according to another first embodiment of the present invention.
【図5】本発明の他の第2の実施形態の金属配線の平面
図とその断面図である。FIG. 5 is a plan view and a cross-sectional view of a metal wiring according to another second embodiment of the present invention.
【図6】本発明の他の第3の実施形態の金属配線の平面
図とその断面図である。FIG. 6 is a plan view and a sectional view of a metal wiring according to another third embodiment of the present invention.
【図7】本発明の他の第4の実施形態の金属配線の平面
図とその断面図である。FIG. 7 is a plan view and a sectional view of a metal wiring according to another fourth embodiment of the present invention.
【図8】従来の半導体集積回路の製造工程の一例を示す
断面図である。FIG. 8 is a cross-sectional view illustrating an example of a manufacturing process of a conventional semiconductor integrated circuit.
【図9】半導体集積回路における凹部アスペクト比の説
明と、第一プラズマ酸化膜の膜厚の違いによる凹部アス
ペクト比の変化を説明するための断面図である。FIG. 9 is a cross-sectional view for explaining the recess aspect ratio in the semiconductor integrated circuit and explaining the change in the recess aspect ratio due to the difference in the thickness of the first plasma oxide film.
【図10】凹部埋め込み性が悪化した場合の後工程への
影響の例を示す断面図である。FIG. 10 is a cross-sectional view showing an example of an influence on a post-process when the recess filling property is deteriorated.
1〜5 金属配線 10 半導体基板 11 絶縁膜 12 第一プラズマ酸化膜 13 絶縁塗布膜 14 凹部 15 第二プラズマ酸化膜 16 上層金属配線 F1,F4 塗布膜が広がろうとする力 F2,F3 塗布膜が留まろうとする力 1 to 5 metal wiring 10 semiconductor substrate 11 insulating film 12 first plasma oxide film 13 insulating coating film 14 concave portion 15 second plasma oxide film 16 upper metal wiring F1, F4 force to spread coating film F2, F3 coating film The power to stay
Claims (5)
された複数の配線と、これらの配線を覆うように塗布形
成される絶縁塗布膜とを備える半導体集積回路におい
て、両隣の配線間隔が異なる配線は、両隣の配線間隔が
等しい配線よりもその配線幅を大きく形成したことを特
徴とする半導体集積回路。1. A semiconductor integrated circuit comprising a plurality of wirings arranged at required intervals on the same plane and an insulating coating film applied and formed so as to cover these wirings, the wiring intervals on both sides are different. A semiconductor integrated circuit, wherein the wiring is formed to have a larger wiring width than a wiring having an equal distance between both wirings.
隣のうちの一方の配線間隔が前記所定の間隔よりも大き
い金属配線は、両隣の配線間隔が前記所定の間隔の配線
よりもその配線幅を大きく形成してなる請求項1の半導
体集積回路。2. A plurality of wirings are arranged at a predetermined interval, and a metal wiring in which one of the two adjacent wiring intervals is larger than the predetermined interval has a larger wiring interval than the wiring of the two adjacent wirings. 2. The semiconductor integrated circuit according to claim 1, wherein the wiring width is formed large.
の最小寸法幅に設定され、両隣の配線間隔が異なる配線
は前記最小寸法幅よりも大きい寸法幅に設定されてなる
請求項1または2の半導体集積回路。3. A wiring having equal wiring intervals on both sides thereof is set to a design minimum dimension width, and wirings having different wiring intervals on both sides are set to a dimension width larger than the minimum dimension width. 2 semiconductor integrated circuit.
ないし3のいずれかの半導体集積回路。4. The wiring according to claim 1, wherein each wiring is arranged in parallel.
3. The semiconductor integrated circuit according to any one of items 1 to 3.
の下地絶縁膜上に複数本の金属配線が平行に形成され、
これら金属配線に第一の絶縁膜が被着され、この第1の
絶縁膜上に絶縁塗布膜が形成され、さらのその上に第二
の絶縁膜が被着され、前記第二の絶縁膜、第1の絶縁膜
を通してスルーホールが開設されて上層配線が形成され
る多層配線構造を有する半導体集積回路において、前記
金属配線は、両隣のうちの一方の配線間隔が他方よりも
大きい金属配線は、両隣の配線間隔が等しい配線よりも
その配線幅を大きく形成したことを特徴とする半導体集
積回路。5. A base insulating film is formed on a semiconductor substrate, and a plurality of metal wirings are formed in parallel on the base insulating film,
A first insulating film is applied to these metal wirings, an insulating coating film is formed on the first insulating film, and a second insulating film is further applied thereon, and the second insulating film is formed. In a semiconductor integrated circuit having a multilayer wiring structure in which a through-hole is opened through a first insulating film to form an upper wiring, the metal wiring is such that one of two adjacent wirings has a larger wiring spacing than the other. A semiconductor integrated circuit, wherein the wiring width is formed larger than the wiring having the same wiring interval between adjacent wirings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34069696A JP2848367B2 (en) | 1996-12-20 | 1996-12-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34069696A JP2848367B2 (en) | 1996-12-20 | 1996-12-20 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10189589A true JPH10189589A (en) | 1998-07-21 |
JP2848367B2 JP2848367B2 (en) | 1999-01-20 |
Family
ID=18339443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34069696A Expired - Lifetime JP2848367B2 (en) | 1996-12-20 | 1996-12-20 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2848367B2 (en) |
-
1996
- 1996-12-20 JP JP34069696A patent/JP2848367B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2848367B2 (en) | 1999-01-20 |
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