JPH10187087A - Device for generating drive signals of matrix display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a required drive signal easily changeable by combining an input module, which inputs a picture image signal and a synchronizing signal, a picture image signal module, which time-shares picture image signals and a clock module, which generates clock signals and generating various drive signals. SOLUTION: The input module is provided with picture image terminals 31-33, which correspond to three primary colors, a clock input 34, a horizontal synchronization input 35, a vertical synchronization 36, and picture image inputs 37-39 corresponding to three primary colors. The picture image module is provided with a picture image passing output terminal 40, a picture image input terminal 41, a controller I/O terminal 42 and a picture image output terminal 43 which is a multi-pin terminal, from which time-shared picture image signals are outputted. In the picture image module, the number of divided picture image signals is arbitrarily set by changing the setting of a dot sequencer circuit. The clock module is provided with a controller I/O terminal 44 and a clock picture image I/O terminal 45.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure of a device suitable for generating a signal for driving a matrix display device (for example, an active matrix liquid crystal display device) of various types, display capacities, and display methods.

[0002]

2. Description of the Related Art In recent years, various matrix display devices have been known. A well-known liquid crystal display device includes a simple (passive) matrix display device and an active matrix display device. These can be displayed by inputting a video signal and a clock (synchronous) signal from outside. However, there are various signal formats depending on the display device, and it is necessary to process and input a normal video signal accordingly. This is a major difference from a cathode ray tube (CRT) which is a typical display device in the related art.

[0003] For example, an active matrix type display device will be described as an example. FIG. 10 shows an active matrix portion 84 on a substrate 81, a data driver circuit 82,
When these circuits having the scan driver circuit 83 are formed on the same plane on the substrate, it is a monolithic active matrix display device. However, the description of the present invention is the same even if the driver circuit is formed by a semiconductor chip.

The structure shown in FIG. 10A is the simplest monochrome display, and has a synchronization signal input (CLOCK IN) and a video signal input (VIDEO) as input terminals.
IN). It is the same as a normal monochrome CRT. (FIG. 10A) In the case of a color display, as shown in FIG. 10B, a synchronization signal input (CLOCK IN) and video signal inputs (VIDEO INB, G,
R). This is also the same as a normal color CRT. (FIG. 10B)

[0005] However, some matrix display devices have other input terminals and therefore require different drive signals. For example, FIG.
The structure shown in FIG. 1 is for monochrome display, but the synchronization signal input (CLOCK IN) and the first
To fourth video signal input (VIDEO IN 1 to 4)
Having. In a normal CRT, only one video signal is input in the case of monochrome display. However, in a matrix display device, the video signal is divided into a plurality of pieces and input simultaneously at the same time in order to reduce the signal processing speed. May be. (FIG. 11A)

[0006] The structure shown in FIG.
It is also a monochrome display, but the first and second synchronization signal inputs (CLOCK IN 1
And 2) and a video signal input (VIDEO IN). In a normal CRT, only one synchronization signal is input. However, in a matrix display device, in order to reduce the signal processing speed, a plurality of synchronization signals are used with their phases shifted as described above. Circuit (for example,
Shift registers 86 and 87) may be provided. (FIG. 11B)

Similarly, a matrix for color display which has two shift registers and divides a video signal into four parts is composed of first and second synchronization signal inputs (CLOCK IN 1 and CLOCK IN 1) as shown in FIG. 2) and the first to fourth video signal inputs (VIDEO IN) for each of the three primary colors.
R1-4, G1-4, B1-4). (FIG. 11
(C))

For example, there are two shift registers,
The data driver of the matrix display device for displaying by the divided video signals has a structure as shown in FIG. Then, the pulse signals output from the shift registers A1 and B1 (which drive the analog sample and hold), the video signal before division, and the first, fourth, and ninth video signal lines after division Are input as shown in FIG. (FIG. 12, FIG. 1
3)

[0009]

As described above, in the matrix display device, various display methods are required depending on the circuit configuration and the like. Since such various display methods (that is, drive signals) exist, when testing various matrix display devices, it is necessary to recreate a circuit for generating a drive signal for each matrix display device. there were. For example, in a driving signal suitable for the display device illustrated in FIG.
Normal display cannot be performed by driving the display device shown in FIG.

However, making a drive circuit for each matrix display device is time-consuming and expensive, and hinders efficient work. The present invention has been made in view of the above points, and an object of the present invention is to provide a matrix display device capable of easily changing a required drive signal.

[0011]

The invention disclosed in this specification is characterized in that a signal for driving a matrix display device is generated using at least the following three modules. That is, a first module (input module) for inputting a video signal and a synchronization signal, a second module (video signal module) for time-dividing the video signal, and a third module (clock module) for generating a clock signal.

Each of these modules is independent. Further, the second module is characterized in that the number of divisions of the video signal can be set arbitrarily. For this purpose, a chip (sequencer chip) that controls this setting is replaced, or an EPROM, an EEPROM,
A programmable chip using a rewritable semiconductor element such as a ROM may be used. Further, both the clock signal and the output phase of the third module may be changeable.

Various drive signals can be generated by combining the above modules. Further, a module having another function may be added. For example, a module (correction module, for example, a γ correction module) that corrects an image signal according to an initially set upward direction, a module that functions as an interface (interface module) for connection to a computer, A module for inputting / outputting a control signal (control module), a module for connecting to an inspection circuit such as an oscilloscope (trigger module), and the like.

If these modules are used by inserting them into the main frame 1 as shown in FIG. 2, wiring is easy. FIG. 1 shows a state where various modules are inserted into the main frame 1. That is, from the left, the controller module 2, the interface module 3, the gamma correction modules 4 to 6, the input module 7, the video module 8, the clock module 9, the video module 10, the clock module 11, and the video module 1.
2, clock module 13, trigger module 14
It is. (FIGS. 1 and 2)

The main frame has a back portion of each module and connection pins, and is provided with, for example, a common power supply and a common bus line (particularly, clock distribution and timing synchronization signals) for each module. Of course, in use,
The mainframe does not need to be always filled with modules. For example, as shown in FIG. 3, from the left, the input module 22, the video modules 23 and 24, the clock module 25, the video modules 26 and 27, the clock module 28, and the video module 29 and 30 are mainframe 2
1 and nothing may be inserted on the left side of the input module. (FIG. 3) Hereinafter, the present invention will be described in more detail with reference to Examples.

[0016]

【Example】

Embodiment 1 In the present invention, a module is used according to a drive signal to be generated. FIG. 4 shows an example of the front of an input module, a video module, and a clock module, which are typical modules of the present invention.
Other formats may be used.

As shown in FIG. 4A, the input module includes video output terminals 31 to 33 corresponding to the three primary colors, a clock input 34, a horizontal synchronization input 35, a vertical synchronization input 36, and video inputs 37 to 37 corresponding to the three primary colors. 39. In the case of a monochrome signal, a video signal may be input to one of the video inputs 37 to 39 and output from the corresponding video outputs 31 to 33. (FIG. 4 (A))

The video module has a video passing output terminal 40, a video input terminal 41, a controller input / output terminal 42, and a video output terminal 43, as shown in FIG. The video passage output terminal is a terminal for outputting a signal input to a module as it is and connecting it to another module. The controller input / output terminal is a terminal for connecting to the controller module. Further, a time-divided video signal is output from the video output terminal. This terminal is a multi-pin terminal. (FIG. 4 (B))

The clock module has a controller input / output terminal 44 and a clock video output terminal 45, as shown in FIG. From the clock output terminal, clock signals having different phases are output. Therefore, this terminal is a multi-pin terminal. For example, a basic clock is shifted from the first wire, a clock shifted by a half cycle from the second wire, a clock shifted by a quarter cycle from the third wire, and a clock shifted from the fourth wire by the fourth wire. Clocks shifted by 3/4 period in phase are output. (FIG. 4 (C))

FIG. 7 shows a circuit block of the video module. Among them, ESIMI-017 and ESIMI-01
The circuit configuration of the 8-QVSH is shown in FIGS. 8 and 9, respectively. In a video module, one module divides a video signal into a maximum of eight. Dot sequencer circuit (Dot
By changing the setting of (Sequence), the number of divisions can be changed from 1 to 8, and it is also possible to connect video modules in two stages and divide up to 16 stages. It is also possible to perform more divisions. (FIGS. 7 to 9)

FIG. 5 shows one connection example of the module of the present invention in the main frame 51. In this example, one input module 52 and one clock module are used, and three video modules (53 to 55) corresponding to the three primary colors are used. Then, the three primary color terminals of the input module are connected to the respective video modules. As a result, there are a total of four output wirings, namely, video output wirings 56, 58, 59 of three primary colors and a clock output wiring 57.

The drive signal processed by the above configuration can drive the color display device shown in FIGS. 10B and 11C. At this time, in order to drive the display device in FIG. 10B, the image is not divided, and in order to drive the display device in FIG. 11C, the image is divided into four. Change the dot sequencer circuit settings of the module. (Fig. 5)

Embodiment 2 FIG. 6 shows an example of connection of a module of the present invention to a main frame 61. In this example, the input module 62 and the clock module 6
3 and one video module in total (64 to 69). The three primary color terminals of the input module are connected to 64, 66, and 68 among the video modules. Further, video output terminals of these video modules 64, 66, 68 are connected to other video modules 65, 67, 69. This is to divide the video signal into 16, and for that purpose, the setting of the dot sequencer circuit of each video module is changed. The output wiring is a three primary color video output wiring 71
To 73 and the clock output wiring 70 in total. (FIG. 6)

[0024]

According to the present invention, signals for driving various types of matrix display devices can be easily obtained with minimal changes. As described above, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 shows an example of a mainframe and a module of the present invention.

FIG. 2 shows the mounting of a main frame and a module according to the present invention.

FIG. 3 shows an example of a mainframe and a module of the present invention.

FIG. 4 illustrates a front view of an input module, a video module, and a clock module according to the first embodiment.

FIG. 5 illustrates a connection example of each module according to the first embodiment.

FIG. 6 illustrates a connection example of each module according to the second embodiment.

FIG. 7 is a circuit block diagram of a video module according to the first embodiment.

FIG. 8 shows an example of a circuit used in the video module of the first embodiment.

FIG. 9 shows an example of a circuit used in the video module of the first embodiment.

FIG. 10 illustrates an arrangement of input terminals, drivers, and the like of the matrix display device.

FIG. 11 illustrates an arrangement of input terminals, drivers, and the like of the matrix display device.

FIG. 12 shows an outline of a data driver circuit of a matrix display device.

FIG. 13 illustrates an example of a signal used for a data driver circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main frame 2 Controller module 3 Interface module 4-6 γ correction module 7 Input module 8, 10, 12 Video module 9, 11, 13 Clock module 14 Trigger module 21 Main frame 22 Input module 23, 24, 26 Video module 27, 29, 30 Video module 25, 28 Clock module 51 Main frame 52 Input module 53, 54, 55 Video module 56, 58, 59 Video output wiring 57 Clock output wiring 61 Main frame 62 Input module 64 to 69 Video module 63 Clock module 71 To 73 Video output wiring 70 Clock output wiring 81 Substrate 82 Data driver circuit 83 Scan driver circuit 84 Matrix circuit 86, 8 7 Shift register

Claims (1)

[Claims] A first module for inputting a video signal and a synchronization signal; a second module for time-dividing the video signal; and a third module for generating a clock signal. An apparatus for generating a drive signal for a matrix display device, wherein each of the third to third modules is independent, and the second module can arbitrarily set the number of divisions of a video signal.