JPH0532757B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an X-Y dot matrix display device, and more particularly to a multi-divided parallel drive type X-Y dot matrix display device with a large display screen.

BACKGROUND OF THE INVENTION There is a line-sequential scanning method using dynamic X-Y matrix drive. This is X in Figure 1.
- At the Y electrode (X-Y matrix screen) 1,
The X electrodes are automatically scanned in order from the top, that is, from X ₁ to X _N , in a time-sharing manner, and when each X electrode is selected, the Y electrode on the This method forms a screen by adding data, ie, ON or OFF data, to the Y electrodes _Y1 to _YM all at once to perform display line by line.

FIG. 2 is a timing diagram of signals applied to the X and Y electrodes of FIG. 1. The operation shown in FIG. 1 will be briefly described with reference to FIGS. 1 and 2.

The scanning signal of the X electrode is obtained by inputting a pulse S of 1/N duty into the shift register 2,
Obtained by shifting with CP1. Then, the latch circuit 3 reads out the contents of the shift register 2 little by little at the timing of the clock pulse CP2, and
Give it to the electrode.

The display data on each line of the X electrodes, that is, the data on the Y electrodes, is obtained by shifting the serial input data DI input into the shift register 4 using the clock pulse CP2, and then using the clock pulse CP2 in the latch circuit 5.
By latching at 1, it can be added to Y electrodes Y ₁ to Y _M at once.

By the way, the frequencies f _CP1 , f _CP2 , f _S of each of these signals
The relationship between f FLM and the repetition frequency f _FLM for scanning the X electrode is as follows: f _FLM = f _S = f _CP1 /N (N: number of X electrodes) = f _CP2 /M・N (M: number of Y electrodes) It's working. Here, the repetition frequency
f _FLM is a level that does not cause flickering to the human eye.
35Hz or higher is required. Assuming that the display screen size is a large one with N=64 and M=480, in order to make f _FLM ≧35, f _CP2 ≧1.07 MHz from equation (1). However, when the frequency exceeds 1MHz,
Generally, XY matrix driver LSI (for example,
For LCD dot matrix drivers,
LH5006, HD44100, etc.) specifications are exceeded.

Therefore, in the case of such a large screen, it is well known that the frequency can be lowered by dividing the display screen, for example, driving two screens in parallel.

Figure 3 shows how the display screen is divided as described above.
X-Y when driving as two screen parallel display
FIG. 2 is a block diagram showing the flow of signals applied to the matrix screen 1'. 4 is a timing diagram of the signals in the block diagram of FIG. 3. In FIG. 3, as in FIG. 1 described above, the scanning signal of the X electrode of the X-Y matrix screen 1' is obtained by inputting a pulse S of 1/N duty into the shift register 2.
Obtained by shifting with clock pulse CP1. On the other hand, the display data on each line of the X electrode, that is, the Y electrode data, is divided into serial input data DI1 that displays the upper half of the screen and serial input data DI2 that displays the lower half of the screen. DI2 is
They are transferred in shift registers 6 and 8 with clock pulse CP2, and latched in latch circuits 7 and 9 with clock pulse CP1. Then, each is applied to the Y electrode at once.

Therefore, if the screen is split into two, for example, the serial input data will be split between DI1 and DI2.
One is required. In other words, the input data
The external circuit for supplying DI1 and DI2 is
This means that they are required separately. In other words, as shown in Figure 5, the disadvantage is that, for example, 8-bit data from the memory corresponding to each of the upper and lower half-screens must be converted from parallel to serial via the respective data buses. It is.

OBJECTS OF THE INVENTION Therefore, it is an object of the present invention to provide a multi-divided parallel drive type X-Y dot matrix display device with a large display screen, which allows the circuit to be simplified and miniaturized.

SUMMARY OF THE INVENTION To put it simply, the present invention is a dot matrix display device that drives an XY electrode matrix line-sequentially, and which divides a display screen into multiple screens for display. This XY dot matrix display device makes it possible to simplify the circuit by using a common data bus and parallel/serial converter by placing data signals on a common data bus instead of separate data buses.

The above objects and features of the present invention will become clearer from the description of one embodiment with reference to the following drawings.

DESCRIPTION OF THE EMBODIMENTS FIG. 6 is a block diagram of an embodiment of the present invention, clearly showing the features of this embodiment. That is, a screen data memory storing screen data to be displayed and a parallel/serial converter 18 are connected by a common data bus 17. The data in the screen data memory 16 is multiplexed onto the data bus 17, subjected to parallel/serial conversion by a parallel/serial converter 18, and then sent to a demultiplexer 19. The demultiplexer 19 separates the serial conversion data into data DI1 for the upper half screen and data DI2 for the lower screen.

Each of the separated data DI1 and DI2 is
As shown in FIG.
and is sent to shift register 9. The subsequent operations are performed in the same manner as described in FIG.

As in this embodiment, by first extracting data from the screen data memory 16 via the common data bus 17 and converting it from parallel to serial using the parallel/serial converter 18, for example, an 8-bit data bus and a parallel/serial converter can be used in common. The circuit can be simplified.

Next, FIG. 7 shows a more specific circuit of the conventional device, and FIG. 8 shows a specific circuit of an embodiment of the present invention, which corresponds to FIG.
Further, FIG. 9 shows a signal timing diagram of the conventional device shown in FIG. 7, and FIG. 10 shows a signal timing chart of the device of the embodiment of the present invention shown in FIG.

The operation of the apparatus of this embodiment will be explained in more detail with reference to FIGS. 8 and 10. Data DB 0 to 7 multiplexed from the screen data memory 16 (FIG. 6) onto the common data bus ₁₇ (FIG. 6) are converted into serial data by a parallel/serial converter 18. That is, the multiplexed 8-bit signals DB _{0 to 7} are converted by the parallel/serial converter 18 into control signals a _{0 to 2} sent from the controller, for example, one of the control signals (000), as shown in FIG. DB ₀ of 8-bit signals DB _{0 to 7} is selected, then 8-bit signal DB ₁ is selected for one of the control signals (001), and then 8-bit signal DB 1 is selected for one of the control signals (010). In contrast, the 8-bit signal _DB2 is selected. In this way, the 8-bit signals DB _0-7 are sequentially selected by one of the control signals a _0-2 , so the 8-bit signals DB _0-7 output during the period t1 are controlled. signal
A parallel signal can be converted into a serial signal by sequentially extracting one of a _{0 to 2} for a time shorter than time t1 and arranging them sequentially in time. Furthermore, the same operation is repeated at the next time _t2 . This signal converted to serial data is Z
It is. The converted signal Z is applied to the D terminals of D flip-flop 22 and D flip-flop 23, respectively. The other input terminals of these D flip-flops 22 and 23 are supplied with a clock pulse CP2 having the same cycle as the switching of the serial conversion data. That is, the clock pulse CP2 is applied to the other input terminal of the D flip-flop 22 via the inverter 25,
Clock pulse CP2 is directly connected to flip-flop 2
3 is applied to the other input terminal. therefore,
At the falling and rising edges of clock pulse CP2,
When signal Z is latched by D flip-flops 22 and 23, signals DI1' and DI2 are obtained, respectively. Furthermore, this signal DI1' is applied to the D terminal of the D flip-flop 24, and the clock pulse CP
If it is latched at the falling edge of 2, the signal DI1 will be obtained. Therefore, the data output from the screen data memory (FIG. 6) can be separated into serial data to be applied to the Y electrodes of the upper half screen and the lower half screen, respectively.

In the description of each of the above embodiments, the screen is divided into upper and lower halves, but the screen is not limited to this, and may be divided into three, four, or more for parallel driving. This invention can also be applied to That is, even in the case of multi-division parallel driving, it is possible to share the data bus and the parallel/serial converter.

Effects of the Invention As described above, according to the present invention, in a multi-divided parallel drive type Since signal conversion is performed using a parallel/serial converter, data buses and parallel/serial converters are used to convert signals.
The serial converter can be shared, and the circuit can be simplified and simplified. Furthermore, when this circuit is integrated and housed on one chip, it has the effect that the number of terminals on the chip package can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display section of an X-Y dot matrix display device which is the background of the present invention. FIG. 2 is a timing diagram of the signals in the block diagram shown in FIG. Figure 3 shows the X-
FIG. 2 is a block diagram of a display section of a Y dot matrix display device. FIG. 4 is a timing diagram of the signals in the block diagram shown in FIG. FIG. 5 is a block diagram of a conventional device, and is a circuit block diagram for providing signals for the display section shown in FIG. FIG. 6 is a block diagram of a signal conversion circuit according to an embodiment of the present invention. 7th
This figure is a concrete circuit block diagram of the block diagram shown in FIG. 5. FIG. 8 is a more specific circuit block diagram of one embodiment of the present invention shown in FIG. FIG. 9 is a timing diagram of signals in the circuit shown in FIG. 7. FIG. 10 is a timing diagram of signals in the circuit block diagram shown in FIG. 8. 1st
FIG. 1 is an explanatory diagram of the operation of the serial/parallel converter 18. In the figure, 1 is an X-Y matrix screen, 2,
4 is a shift register, 3 and 5 are latch circuits, 16
17 is a screen data memory, 17 is a data bus, 18 is a parallel/serial converter, 19 is a demultiplexer, and 22, 23, and 24 are D flip-flops.

Claims (1)

[Scope of Claims] 1. A matrix type display device that displays a matrix type display divided into two display areas by selectively feeding signals to strip electrodes arranged in mutually orthogonal directions, comprising: In order to drive the two regions individually, two drive systems are connected to the strip electrodes, an image data memory that stores screen data to be displayed in units of one screen, and parallel output signals from the screen data memory. a parallel/serial converter circuit that receives the data via a single bus line and converts it into a serial signal, and a serial output signal of the parallel/serial converter circuit that is sequentially converted to
a demultiplexer consisting of two flip-flops and an inverter, and a flip-flop that adjusts the timing according to the two display areas, and a demultiplexer that divides the two signals divided by the demultiplexer into 1. A matrix display device comprising circuits that respectively supply two drive systems.