JPH10178109A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, in which the number of manufacturing process is reduced and a capacitor of high reliability is provided, and a manufacturing method thereof. SOLUTION: A silicon nitride film 10, which is formed in the same manufacturing process as a silicon nitride film acting as such a dielectric substance of a capacitor as a component of a STC(stacked capacitor) type memory cell of a SRAM(static random access memory), is placed under a silicon-oxide- contained insulating film 13 on the side surface of connection holes 15 and 16 provided on a semiconductor region 7, acting as a source and a drain of a MOSFET (metal oxide semiconductor field effect transistor). The silicon nitride film 10 is used as an etching stopper film at formation of the connection holes 15 and 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multilayer wiring structure having a capacitor and an active element such as a MOSFET (metal).
The present invention relates to a semiconductor integrated circuit device that is effective when applied to a semiconductor integrated circuit device having an Oxide Semiconductor Field Effect Transistor) and a method of manufacturing the same.

[0002]

2. Description of the Related Art The present inventors have studied a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a method of manufacturing a semiconductor integrated circuit device having a MOSFET, a MOSF
After the ET is formed, a silicon oxide film is formed thereon, and the silicon oxide film is formed on the silicon oxide film by using a photolithography technique and a selective etching technique. A contact hole is formed for a semiconductor region disposed between a field silicon oxide film having a LOCOS (Local Oxidation of Silicon) structure and a side wall silicon oxide film on a side wall of a gate electrode.

However, in the above-described manufacturing method, since the silicon oxide film for forming the contact hole, the field silicon oxide film, and the side wall silicon oxide film are made of the same material, the photolithography technique and the selective etching technique are used. When forming a contact hole by using the contact hole, a region where the contact hole is formed is set to be wide in consideration of misalignment between the field silicon oxide film and the side wall silicon oxide film so that they are not etched. Needed.

Therefore, even if misalignment between the field silicon oxide film and the side wall silicon oxide film and the contact hole occurs, the field silicon oxide film and the side wall silicon oxide film are not damaged by etching when forming the contact hole. There is a manufacturing method which adopts a mode of forming a silicon nitride film as an etching stopper film below a silicon oxide film formed on a semiconductor substrate.

Further, a stacked capacitor (stacked capacitor)
capacitor (STC) type memory cell with SRA
In a method of manufacturing a semiconductor integrated circuit device having M (Static Random Access Memory), after forming a lower electrode of a capacitor which is a capacitive element, forming an insulating film as a dielectric on the lower electrode, The upper electrode. In this case, the lower electrode and the upper electrode of the capacitor use, for example, a titanium nitride (TiN) film, and the insulating film as a dielectric uses, for example, a silicon nitride film.

[0007] Documents relating to the manufacturing process of a semiconductor integrated circuit device provided with a MOSFET include, for example, 1
On December 15, 990, Keigaku Shuppan Co., Ltd., published by Keigaku Shuppan Co., Ltd., is described in "Illustrated Super LSI Engineering", pp. 117-135.

[0008]

However, the aforementioned M
In a method of manufacturing a semiconductor integrated circuit device having an OSFET, if a silicon nitride film is formed as an etching stopper film below a silicon oxide film when a contact hole is formed in the silicon oxide film, the number of manufacturing steps increases. A problem has occurred.

In the above-described method of manufacturing a semiconductor integrated circuit device having an SRAM having an STC type memory cell, a silicon nitride film as a dielectric in a capacitor as a capacitor is formed by plasma CVD (Chemical Vapor Deposition).
or the deposition method, the adhesion between the titanium nitride film as the lower electrode of the capacitor and the silicon nitride film thereon is weakened by heat treatment applied after the formation of the capacitor, and the nitrided film as the lower electrode is formed. There is a problem that the silicon nitride film is peeled off from the titanium film.

An object of the present invention is to reduce the number of manufacturing steps,
In addition, it is an object of the present invention to provide a semiconductor integrated circuit device that can include a highly reliable capacitor and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, a silicon nitride film formed by the same manufacturing process as a silicon nitride film as a dielectric of a capacitor such as a component of an STC type memory cell of an SRAM has an M thickness.
It is arranged below the insulating film on the side surface of the connection hole provided on the source and the drain of the OSFET, and the silicon nitride film is used as an etching stopper film when forming the connection hole. Things.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a field insulating film made of a silicon oxide film having a LOCOS structure is formed by thermally oxidizing a selective region on a surface of a substrate such as a semiconductor substrate. Thereafter, a plurality of MOSFETs are formed in the element formation region of the substrate, and at least one or more MOSFETs are formed on the field insulating film.
A step of forming two rows of wiring layers connected to the gate electrode in the SFET by the same manufacturing process as that of the gate electrode; and forming a lower electrode of the capacitor on one field of the two wiring layers on the field insulating film. Forming a silicon nitride film as a dielectric of the capacitor on the entire surface of the substrate after being formed in a state of being connected to the surface, and then forming an upper electrode of the capacitor on the field insulating film in two rows of wiring layers; Forming a state in which it is connected to the surface of the other wiring layer;
After forming an insulating film containing silicon oxide on a substrate, a connection hole is formed in the insulating film containing silicon oxide on a semiconductor region as a source and a drain of a MOSFET by using a photolithography technique and a selective etching technique. Then, a step of forming the silicon nitride film as an etching stopper film, and thereafter, a step of removing the silicon nitride film below the connection hole by etching.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) In this embodiment, an SRA
The present invention relates to a semiconductor integrated circuit device having an M and a method of manufacturing the same, particularly, a capacitor and a CMOSFET (Complementary Metal Oxide) as components of an STC memory cell.
A semiconductor integrated circuit device having an SRAM provided with a semiconductor field effect transistor) and a method of manufacturing the same.

FIG. 1 is a circuit diagram showing an STC type memory cell of an SRAM in a semiconductor integrated circuit device having an SRAM according to the present embodiment. As shown in the figure, the STC type memory cell of the SRAM of the present embodiment is arranged at the intersection of a pair of complementary data lines (data line DL, data line / (bar) DL) and word line WL. And a pair of driving MOSFETs Q ₂ and Q ₄ and a pair of load MOSFETs Q 2
Is composed of _1, Q ₃ and a pair of transfer MOSFETQ _5, Q _6. Among these MOSFETs, drive MOSFETs Q ₂ and Q ₄ and transfer MOSFETs
Q ₅ and Q ₆ are constituted by N-channel MOSFETs, and the load MOSFETs Q ₁ and Q ₃ are constituted by P-channel MOSFETs. And four N-channel MOSFETs
T and the two P-channel MOSFETs are of a CMOS type.

Six MOSFs constituting the memory cell
In the ET, a pair of drive MOSFETs Q ₂ and Q ₄ and a pair of load MOSFETs Q ₁ and Q ₃ constitute a flip-flop circuit as an information storage unit that stores 1-bit information. The one of the input and output terminals of the flip-flop circuit (accumulation nodes) source of the transfer MOSFET Q _5, is electrically connected to one of the drain region, the other of the input and output terminals (storage node) is the source of the transfer MOSFET Q _6, It is electrically connected to one of the drain regions.

[0019] The source of the transfer MOSFET Q _5, the other drain region is the data line DL is electrically connected, the source of the transfer MOSFET Q _6, the other drain region data line / DL is electrically connected I have. Further, one end of the flip-flop circuit (load MOSFETs Q ₁ ,
The source regions of the Q ₃₎ is connected to the power supply voltage (Vcc),
Multi-end (source regions of drive MOSFETs Q ₂ and Q ₄ )
Are connected to a reference voltage (Vss). Power supply voltage (Vc
c) is, for example, 3V, and the reference voltage (Vss) is, for example, 0V.
V (GND).

The input / output terminals of the flip-flop circuit are cross-coupled via a pair of local lines L ₁ and L ₂ . The pair of local wirings L ₁ and L ₂ in the present embodiment are formed using different wiring layers. The capacitor in the thin insulating film interposed between them and the upper local wiring L ₂ and the lower local wiring L ₁ (capacitor element)
C. That is, the upper local wiring L ₂ forms one electrode of the capacitor C, and the lower local wiring L ₁
Constitutes the other electrode, and the insulating film constitutes a dielectric film. Therefore, a capacitor with an insulating film disposed so as to overlap the upper layer of the local wiring L ₂ lower and the local wiring L ₁ vertically, interposed between them and the upper local wiring L ₂ and the lower local wiring L ₁ By configuring C, the storage node capacity of the memory cell can be increased.
It is possible to prevent a decrease in α-ray soft error resistance due to a reduction in memory cell size and a decrease in operating power supply voltage.

FIG. 2 is a plan view schematically showing an STC type memory cell of the above-described SRAM for describing a semiconductor integrated circuit device having the SRAM of the present embodiment and a method of manufacturing the same. Note that, in FIG.
Each MOSFET in the C-type memory cell and its source /
4 schematically shows the arrangement of drain and gate electrodes, capacitors, and their connection holes.

In FIG. 2, G ₁ is a gate electrode of MOSFET Q ₁ and MOSFET Q ₂ and a conductive layer connecting them, and G ₂ is a MOSFET Q ₃ and MOSFET Q ₃
A conductive layer connecting the gate electrode and those with FETs Q _4, G ₃ is MOSFET Q ₅ and MOSFET
The gate electrode and a conductive layer connecting them with Q ₆ is (word line WL). Also, H _1a to H _6a Each MOS
A connecting hole corresponding to each source of Q ₁ to Q ₆ is a FET, H _1b ~H _5b is a connecting hole corresponding to the drain of Q ₁ to Q ₅ are each MOSFET. H _G1 is a connection hole connected to G ₁ and one electrode of the capacitor C, and H _G2 is a connection hole connected to G ₂ and the other electrode of the capacitor C. Further, in the same figure, a region indicated by a two-dot chain line is a region where the capacitor C is arranged. The area shown by the dotted line is the area where the source and drain of each MOSFET are arranged.

Next, a semiconductor integrated circuit device having an SRAM according to the present embodiment and a method of manufacturing the same will be described with reference to FIGS. FIG. 3 to FIG.
FIG. 4 is a cross-sectional view illustrating the method of manufacturing the semiconductor integrated circuit device having the RAM. 3 to 10, the left-side view is a cross-sectional view along the line AA ′ in FIG.
FIG. 5 is a cross-sectional view of a region where a capacitor of M STC type memory cells is arranged. The diagram on the right is BB 'in FIG.
Is a cross-sectional view along the line, is a cross-sectional view of the area for arranging the MOSFET Q ₂ of the STC memory cell of SRAM.

First, as shown in FIG. 3, an n-type well 2 and a p-type well 3 are formed on a p-type semiconductor substrate 1 made of, for example, single crystal silicon. The region is thermally oxidized to form a field insulating film 4 made of a silicon oxide film having a LOCOS structure. Note that n
The step of forming the p-type well 2 and the p-type well 3 may be performed after the field insulating film 4 is formed.

Next, as shown in FIG.
After a gate insulating film 5 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 1 on which the p-type well 3 is formed, the surface of the gate insulating film 5 is made of a conductive polycrystalline silicon film or the like. The gate electrode 6 is formed. The gate electrode 6 formed on the field insulating film 4 in the figure on the left is a conductive layer connected to a lower electrode of a capacitor and a conductive layer connected to an upper electrode, which will be described later.

Thereafter, an n-type impurity is ion-implanted into a selective region on the surface of the p-type wafer 3 and diffused to form an n-type semiconductor region 7 serving as a source and a drain of the N-channel MOSFET. Thereafter, although not shown, p-type impurities are ion-implanted into a selective region on the surface of the n-type wafer 2 and diffused to form a p-type semiconductor region serving as a source and a drain of the P-channel MOSFET. Form. Next, a sidewall insulating film (sidewall spacer) 8 made of, for example, a silicon oxide film or the like is formed on the side surface of the gate electrode 6.
To form

Next, as shown in FIG. 5, the lower electrode 9 of the capacitor connected to the gate electrode 6 in the region where the capacitor is to be formed (the leftmost gate electrode 6 in FIG. 5) is formed.

That is, a titanium nitride (TiN) film serving as the lower electrode 9 of the capacitor is formed on the semiconductor substrate 1 to have a thickness of about several hundred angstroms by using the sputtering method or the CVD method. After that, the surface of the titanium nitride film is exposed to an atmosphere gas containing nitrogen such as plasma ammonia (NH ₃ ) or plasma nitrogen (N ₂ ), so that the surface of the titanium nitride film has a molecular weight excess nitrogen. , A titanium nitride film having a stable surface state can be obtained. Next, using a photolithography technique and a selective etching technique, an unnecessary region of the titanium nitride film is removed to form a pattern as a lower electrode 9 of the capacitor.

Thereafter, as shown in FIG.
Silicon nitride (Si), which is a capacitor dielectric,
_The 3N ₄ ) film 10 is formed with a thickness of about several hundred angstroms using a high temperature heating type thermal CVD apparatus.
In this case, the high temperature heating type thermal CVD apparatus is, for example, 80
By a high-temperature heating method of about 0 to 900 ° C,
Unnecessary substances such as moisture can be eliminated from the formed silicon nitride film 10, and the silicon nitride film 10 can have high heat resistance, high reliability, and high performance. Further, since a chemical reaction with the titanium nitride film as the lower electrode 9 under the silicon nitride film 10 can be prevented, the silicon nitride film 10 can have high reliability and high performance.

Next, as shown in FIG. 7, the silicon nitride film 10 on the gate electrode 6 (the second gate electrode 6 from the left end in FIG. 7) in the region for forming the capacitor is formed by photolithography and selective etching. And the connection hole 11 is formed in that area.

Thereafter, an upper electrode 12 of the capacitor connected to the gate electrode 6 (the second gate electrode 6 from the left end in FIG. 7) in which the connection hole 11 is formed in a region where the capacitor is formed is formed. That is, a titanium nitride film to be the upper electrode 12 of the capacitor is formed on the semiconductor substrate 1 to a thickness of about several hundred angstroms by using a sputtering method or a CVD method. Then, using a photolithography technique and a selective etching technique, an unnecessary region of the titanium nitride film is removed to form a pattern as the upper electrode 12 of the capacitor. Note that the upper electrode 12 of the capacitor can be in the form of a conductive film made of various materials such as a conductive polycrystalline silicon film or a laminated film of a titanium nitride film and a conductive polycrystalline silicon film.

Next, as shown in FIG. 8, an insulating film 13 containing silicon oxide is formed on the semiconductor substrate 1. In this case, the insulating film 13 containing silicon oxide is formed, for example, by forming a silicon oxide film using a CVD method, a plasma CVD method, a spin coating method, or the like, and then, if necessary, using a CM.
P (Chemical Mechanical Polishing)
By flattening the surface using the method,
The insulating film 13 is flattened. In another embodiment, a PSG (Phospho Silicate Glass) film can be formed by using a plasma CVD method or the like. Also,
When the insulating film 13 containing silicon oxide is formed, the region of the capacitor may be exposed to a high temperature of 700 ° C. to 900 ° C. In some cases, the titanium nitride film (the lower electrode 9 of the capacitor) is exposed to the above-described nitrogen-containing atmosphere gas. Since the surface is exposed, the titanium nitride film as the lower electrode 9 of the capacitor and the silicon nitride film 10 thereon have a non-reactive effect, and their adhesion is high. There is no reduction.

Thereafter, the insulating film 1 containing silicon oxide
After a resist film 14 is formed on the contact hole 3, the contact hole 1 is formed using a photolithography technique and a selective etching technique.
5 and connection holes 16 are formed. That is, the resist film 1 patterned using the photolithography technique
4 is used as an etching mask, and the insulating film 13 is connected to the connection holes 15 and 1 by dry etching.
6 is formed. In this case, the insulating film 13 containing silicon oxide is dry-etched, and the underlying silicon nitride film 10 becomes an etching stopper film for dry etching (the silicon oxide as a part of the insulating film 13 is etched, As in the case where the silicon nitride film 10 is not etched), carbon monoxide (CO) gas and hydrogen (H)
Is used as an etching gas, or a mixed gas with a carbon fluoride (C _x F _y ) gas containing Al or a mixed gas obtained by adding an argon (Ar) gas to the mixed gas. Further, as the carbon fluoride (C _x F _y ) gas,
C ₄ F ₈ gas or CF ₄ gas is used.

Therefore, when forming the connection holes 15 and 16 in the insulating film 13 containing silicon oxide,
Silicon nitride film 1 functioning as an etching stopper film
0 is disposed under the insulating film 13 so that the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film under the silicon nitride film 10 In addition, it is possible to prevent etching when forming the connection hole 16.

Thereafter, the insulating film 1 containing silicon oxide
3 as an etching mask, the insulating film 1
An operation of removing the silicon nitride film 10 below the connection holes 15 and the connection holes 16 formed by using dry etching using another etching gas is performed. In this case, the silicon nitride film 10 is dry-etched, and the insulating film 13 containing silicon oxide (side surfaces of the connection holes 15 and the connection holes 16) becomes an etching stopper film for the dry etching (the silicon nitride film 10 is etched). Then, the carbon fluoride gas is used as an etching gas so that the silicon oxide that is a part of the insulating film 13 is not etched). C ₄ F ₈ gas or the like is used as the carbon fluoride gas.

Therefore, only the silicon nitride film 10 in the connection holes 15 and 16 is etched and removed by the dry etching, and the silicon oxide on the side walls of the connection holes 15 and the connection holes 16 is contained by the dry etching. The insulating film 13, the field insulating film 4 made of a silicon oxide film under the silicon nitride film 10, and the sidewall insulating film 8 made of the silicon oxide film can be prevented from being etched when the silicon nitride film 10 is removed. .

Next, as shown in FIG. 9, after the unnecessary resist film 14 is removed, tungsten (W) is buried in the connection holes 15 and 16 by using, for example, a selective CVD method to form connection holes. A plug 17 is formed in the connection hole 16 and a plug 18 is formed in the connection hole 16. In this case, connection hole 1
Plugs 17 and 18 embedded in the layers 5 and 16 are made of a high-melting point metal such as titanium (Ti) or molybdenum (Mo) other than tungsten, a high-melting point metal compound such as TiN or TiW, or a conductive material such as aluminum or conductive polycrystalline silicon. After the conductors are buried in the connection holes 15 and 16 by using a selective CVD method, a CVD method, or a sputtering method, unnecessary conductors on the insulating film 13 are selectively etched or subjected to CMP. The plugs 17 and 18 can be formed by removing them by a method or the like.

Thereafter, as shown in FIG.
After a conductor such as aluminum is deposited on the insulating film 13 including the layers 7 and 18 by using a sputtering method or the like, a wiring layer pattern is formed by using a photolithography technique and a selective etching technique. 17 and a wiring layer 2 on the plug 18.
0 are simultaneously formed. Next, after a multilayer wiring layer is formed on the semiconductor substrate 1 as necessary, a passivation film (not shown) is formed thereon, thereby completing the semiconductor integrated circuit device manufacturing process.

In FIG. 10, the drawing on the left is a cross-sectional view along the line AA 'in FIG. 2, and is a cross-sectional view of a region where the capacitors of the STC type memory cell of the SRAM are arranged. 2 is a cross-sectional view taken along the line BB 'in FIG. 2, and shows the MO of the STC type memory cell of the SRAM.
Is a cross-sectional view of the area are arranged SFETQ _2.

In FIG. 10, the leftmost gate electrode 6 is
Corresponds to G ₁ in FIG. 2, MOSFET Q ₁ and MOS
A conductive layer connecting the gate electrode 6 and those with FETs Q _2. The capacitor C on the surface of the gate electrode 6 of the left through the connecting hole corresponding to the connection hole H _G1
Are connected to each other.

The second gate electrode 6 from the left end is
Corresponds to G ₂ in FIG. 2, MOSFET Q ₃ and MOS
FETQ is a conductive layer which connects the gate electrode 6, and their _four. The upper electrode 12 of the capacitor C through the connection hole 11 corresponding to the connecting holes H _G2 is coupled to the second surface of the gate electrode 6 from the left end.

In FIG. 10, the MOSFET shown on the right is
Is the MOSFET Q ₂ of the SRAM STC type memory cell.
And the semiconductor region 7 on the left side thereof corresponds to the source,
The right semiconductor region 7 corresponds to the drain.

The connection hole 15 on the left semiconductor region 7 corresponding to the source of the MOSFET Q ₂ corresponds to the connection hole H _2a in FIG. 2 and the connection hole 15 on the right semiconductor region 7 corresponding to the drain of the MOSFET Q ₂ . The connection hole 16 corresponds to the connection hole _H2b in FIG.

Therefore, each MOSFET in FIG.
Connecting holes H _1a to H _6a and the connecting hole H _1b to H _5b corresponding to the drains of the MOSFET Q ₁ to Q ₅ corresponding to each source of Q ₁ to Q ₆ is connected in the connection hole 15 (FIG. 2 described above It can be formed using the same manufacturing process as that for forming the hole H _2a ) and the connection hole 16 (corresponding to the connection hole H _2b in FIG. 2).

[0045] The wiring layer 19 on the plug 17 embedded in the contact hole 15 on the left side of the semiconductor region 7 corresponding to the source of MOSFET Q _2, one end of the flip-flop circuit in FIG. 1 (driving MOSFET Q ₂ , Q ₄
Are connected to the ground (GND) wiring layer that supplies a reference voltage (Vss) of 0 V, for example.

[0046] The wiring layer 20 on the plug 18 embedded in the connection hole 16 on the right side of the semiconductor region 7 corresponds to the drain of MOSFET Q ₂ has a drain region and a local interconnection of the load MOSFET Q ₃ in FIG. 1 L ₁ is a wiring layer connected to the.

According to the above-described semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, silicon nitride film 10 serving as a capacitor dielectric is formed on the entire surface of semiconductor substrate 1. A photolithography technique using the silicon nitride film 10 as an etching stopper film when forming the connection holes 15 and 16 in the insulating film 13 containing silicon oxide after forming the insulating film 13 containing silicon oxide thereon. After the insulating film 13 containing silicon oxide is etched by the selective etching technique, the silicon nitride film 10 below the connection holes 15 and 16 is etched only by the silicon nitride film 10 to form the connection hole 1.
Insulating film 13 containing silicon oxide film on side surfaces of 5, 16
The field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film under the silicon nitride film 10 are etched by using an etching method.
The connection holes 15 and 16 are formed by removing the silicon nitride film 10 by etching.

Therefore, when the connection holes 15 and 16 are formed in the insulating film 13 containing silicon oxide, the silicon nitride film 10 functioning as an etching stopper film is disposed under the insulating film 13 so that The field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film under the silicon nitride film 10 can be prevented from being etched. Further, only the silicon nitride film 10 in the connection holes 15 and 16 is removed by etching, and the insulating film 1 containing silicon oxide on the side walls of the connection holes 15 and 16 is removed by the etching.
3. The field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film under the silicon nitride film 10 can be prevented from being etched when the silicon nitride film 10 is removed.

As a result, when the connection holes 15 and 16 are formed in the insulating film 13 containing silicon oxide by using the photolithography technique and the selective etching technique, the region where the connection holes 15 and 16 are formed is formed. By disposing the silicon nitride film 10 serving as a dielectric of the capacitor,
Even if the alignment accuracy between the photolithography technique and the selective etching technique is increased, the connection holes 15 and 16 overlap with the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film. Since the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film can be prevented from being damaged by etching when the connection holes 15 and 16 are formed, misalignment thereof can be prevented. Even if there is, the connection holes 15 and 16 can be formed by fine processing without considering the misalignment.

Further, since the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film can be prevented from being broken by etching when forming the connection holes 15 and 16, A semiconductor integrated circuit device having connection holes 15 and 16 with high reliability can be manufactured with a high manufacturing yield. Also,
The contact hole 1 is formed on the insulating film 13 containing silicon oxide by using photolithography technology and selective etching technology.
When forming the connection holes 15 and 16, the silicon nitride film 1 serving as a dielectric of the capacitor is formed when the connection holes 15 and 16 are formed.
The silicon nitride film 10 as an etching stopper film is formed by arranging the silicon nitride film 10 as an etching stopper film
Is used as the manufacturing process for forming the silicon nitride film 10 serving as the dielectric of the capacitor, so that the silicon nitride film 10 as the etching stopper film can be formed without increasing the number of manufacturing processes. Can be easily formed.

According to the semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, the lower electrode of the capacitor connected to the gate electrode 6 (the leftmost gate electrode 6 in FIG. 5) in the region where the capacitor is formed 9 is made of a titanium nitride (TiN) film, and the surface of the titanium nitride film is exposed to an atmosphere gas containing nitrogen such as plasma ammonia or plasma nitrogen. Since a reaction between excessive titanium and nitrogen can be performed, a titanium nitride film having a stable surface state can be obtained. Thereafter, a silicon nitride film 10 serving as a dielectric of the capacitor is formed on the entire surface of the semiconductor substrate 1 by using a high-temperature heating type thermal CVD apparatus.

Therefore, unnecessary substances such as moisture in the silicon nitride film 10 can be eliminated, and the silicon nitride film 10 having high heat resistance, high reliability and high performance can be obtained.
Further, since a chemical reaction with the titanium nitride film as the lower electrode 9 under the silicon nitride film 10 can be prevented, the silicon nitride film 10 can have high reliability and high performance. Further, in the manufacturing process after the formation of the capacitor, for example, when the insulating film 13 containing silicon oxide is formed, the region of the capacitor may be exposed to a high temperature of 700 ° C. to 900 ° C. Since the surface of the titanium nitride film (the lower electrode 9 of the capacitor) is exposed to the gas, the titanium nitride film as the lower electrode 9 of the capacitor and the silicon nitride film 1 thereon are formed.
0 has a non-reactive effect, their adhesion is high,
They do not reduce their adhesion. As a result, it is possible to prevent a change and failure of the capacitance of the capacitor.
A semiconductor integrated circuit device having a highly reliable and high performance capacitor can be manufactured.

According to the above-described semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, the region where the capacitor is formed is disposed on field insulating film 4 between the regions where MOSFETs are formed. Since a wide range of capacitors can be formed on the field insulating film 4 according to the design specifications without being affected by the MOSFET, a large-capacity capacitor can be arranged according to the design specifications.
As a result, the STC type memory cell of the SRAM in the semiconductor integrated circuit device having the SRAM according to the present embodiment can increase the storage node capacity of the memory cell.
It is possible to prevent a decrease in α-ray soft error resistance due to a reduction in memory cell size and a decrease in operating power supply voltage.

(Embodiment 2) FIGS. 11 to 18 are cross-sectional views showing manufacturing steps of a semiconductor integrated circuit device according to another embodiment of the present invention. The semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same are a semiconductor integrated circuit device having an SRAM and a method of manufacturing the same as in the above-described first embodiment. SR with capacitor and CMOSFET
A semiconductor integrated circuit device having an AM and a method of manufacturing the same. Therefore, the circuit diagram showing the STC type memory cell of the SRAM in the semiconductor integrated circuit device having the SRAM of the present embodiment is the same as that of FIG. 1, and the semiconductor integrated circuit device having the SRAM of the present embodiment and a method of manufacturing the same. 2 is a plan view schematically showing an STC type memory cell of the SRAM described above.

Next, a semiconductor integrated circuit device having an SRAM according to the present embodiment and a method for manufacturing the same will be described with reference to FIGS. In addition, in FIGS.
The drawing on the left is a cross-sectional view taken along the line AA 'in FIG. 2, and is a cross-sectional view of a region where a capacitor of the STC type memory cell of the SRAM is arranged. 2 is a cross-sectional view taken along the line BB 'in FIG.
It is a cross-sectional view of the area for arranging the MOSFET Q ₂ type memory cell.

First, as shown in FIG. 11, an n-type well 2 is formed on a p-type semiconductor substrate 1 made of, for example, single crystal silicon.
And a p-type well 3 are formed, a groove 25 is formed in a selective region on the surface of the semiconductor substrate 1, a silicon oxide film is buried in the groove 25, and the surface of the semiconductor substrate 1 is formed by a CMP method. To form a field insulating film 4 made of a silicon oxide film having a trench isolation structure. The step of forming the n-type well 2 and the p-type well 3 can be performed after the field insulating film 4 is formed.

The manufacturing process for forming the field insulating film 4 made of a silicon oxide film having a trench isolation structure is as follows. That is, after a silicon oxide film and a silicon nitride film are formed on the surface of the semiconductor substrate 1, a trench 2 is formed around the element active region (element isolation region) using photolithography and selective etching.
5 is formed. Next, a silicon oxide film is deposited on the semiconductor substrate 1 by using the CVD method, and the silicon oxide film is buried in the trench 25. Then, unnecessary oxidation on the semiconductor substrate 1 is performed by using the CMP method. The silicon film is removed and the surfaces of the silicon oxide film buried in the semiconductor substrate 1 and the trench 25 are planarized to form a field insulating film 4 made of a silicon oxide film having a trench isolation structure.

In this case, the surface of semiconductor substrate 1 having field insulating film 4 made of a silicon oxide film having a trench isolation structure is flattened. That is, the surface of the field insulating film 4 and the surface of the semiconductor substrate 1 having the p-type well 3 as the element active region are in the same plane state, and they are planarized using the CMP method. ing.

Thereafter, as shown in FIG. 12, a gate insulating film 5 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 1 on which the n-type well 2 and the p-type well 3 are formed. After a gate electrode 6 made of a conductive polycrystalline silicon film or the like on the surface of the gate insulating film 5 and a silicon nitride film 21 formed on the gate electrode 6, the gate is formed using photolithography technology and selective etching technology. The silicon nitride film 21, the gate electrode 6, and the gate insulating film 5 serving as regions are patterned, for example, 1000 to 4.
A gate region having a height of about 000 angstroms is formed.

The gate electrode 6 formed on the field insulating film 4 in the figure on the left is a conductive layer connected to a lower electrode and a conductive layer connected to an upper electrode of a capacitor described later. In addition to the conductive polycrystalline silicon film, the gate electrode 6 may be a laminated film of a conductive polycrystalline silicon film and a metal film such as a high melting point metal or a conductive polycrystalline silicon film on the conductive polycrystalline silicon film. And a multilayer wiring structure such as a laminated film with a silicide film such as a titanium silicide film or a tungsten silicide film.

Thereafter, an n-type impurity is ion-implanted into a selective region on the surface of the p-type wafer 3 and diffused to form an n-type semiconductor region 7 serving as a source and a drain of the N-channel MOSFET. Thereafter, although not shown, p-type impurities are ion-implanted into a selective region on the surface of the n-type wafer 2 and diffused to form a p-type semiconductor region serving as a source and a drain of the P-channel MOSFET. Form. Next, a sidewall insulating film (sidewall spacer) 8 made of, for example, a silicon oxide film or the like is formed on the side surface of the gate electrode 6.
To form

Next, as shown in FIG.
After the silicon oxide film 22 is deposited on the silicon nitride film 21 by using the CVD method, the unnecessary silicon oxide film 22 up to the surface of the silicon nitride film 21 is removed by using the CMP method, and the silicon oxide film 22 is planarized. Do. In this case, the silicon nitride film 21 on the gate electrode 6 is used as an etching stopper film.

Thereafter, as shown in FIG. 14, the silicon nitride film on the gate electrode 6 (the left end and the second gate electrode 6 from the left end in FIG. 14) in the region for forming the capacitor is formed by photolithography and selective etching. And removing the remaining area in a state where the area is covered with a resist film as an etching mask, and forming the gate electrode 6 in the area where the capacitor is to be formed (the left end and the second gate electrode 6 from the left end in FIG. 14). The connection holes 23 and 24 are formed on the substrate.

Next, as shown in FIG. 15, a capacitor is formed on the field insulating film 4 in the region where the capacitor is to be formed by using the same manufacturing process as in the first embodiment. That is, after the lower electrode 9 of the capacitor connected to the gate electrode 6 (the leftmost gate electrode 6 in FIG. 15) is formed using a titanium nitride film, the semiconductor substrate 1
Silicon nitride film 10 serving as a capacitor dielectric
Is formed with a film thickness of about several hundred angstroms using a high-temperature heating type thermal CVD apparatus. Thereafter, the gate electrode 6 in which the connection hole 24 is formed in the region where the capacitor is formed (the second gate electrode 6 from the left end in FIG. 15)
Is formed on the upper electrode 12 of the capacitor connected to.
In this case, since the capacitor of the present embodiment is formed on the flattened field insulating film 4 and the flattened silicon oxide film 22, the capacitor is flatter than the capacitor of the first embodiment. The structure of the capacitor can be obtained.

Next, as shown in FIG. 16, an insulating film 13 containing silicon oxide is formed on the semiconductor substrate 1 by using the same manufacturing process as in the first embodiment, and thereafter, After a resist film 14 is formed on the insulating film 13 containing silicon, the connection holes 15 and the connection holes 1 are formed by using a photolithography technique and a selective etching technique.
6 is formed. When forming the connection holes 15 and the connection holes 16, the silicon nitride film 10 functioning as an etching stopper film is formed under the insulating film 13 by using the same manufacturing process as in the first embodiment. The arrangement prevents the silicon oxide film 22 under the silicon nitride film 10, the field insulating film 4 made of the silicon oxide film, and the sidewall insulating film 8 made of the silicon oxide film from being etched by the insulating film 13. can do.

Next, as shown in FIG. 17, using the same manufacturing process as in the first embodiment, the insulating film 13 containing silicon oxide is used as an etching mask to form the insulating film 13. An operation of removing the silicon nitride film 10 under the connection holes 15 and 16 formed in the step (a). Therefore, by this dry etching,
Silicon nitride film 1 in connection hole 15 and connection hole 16
0 is removed by etching, and the insulating film 13 containing silicon oxide and the silicon nitride film 1 on the side walls of the connection holes 15 and 16 are dry-etched.
The silicon oxide film 22 below 0, the field insulating film 4 made of a silicon oxide film, and the sidewall insulating film 8 made of a silicon oxide film can be prevented from being etched when the silicon nitride film 10 is removed.

After that, the silicon oxide film 22 below the connection holes 15 and 16 is made to have the same height as the height of the gate region.
An operation of etching away by about 000 to 4000 angstroms is performed. In this case, over-etching is performed to form a field insulating film 4 made of a silicon oxide film.
Even if the sidewall insulating film 8 made of a silicon oxide film is etched, since the etching is performed after the upper insulating film 13 containing silicon oxide (for example, several hundred angstroms) is etched, the etching amount is increased. Insulating film 13 containing silicon oxide
(For example, several hundred angstroms), and over-etching can be reduced, so that the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film can be prevented from being extremely etched.

As a result, when the connection holes 15 and 16 are formed, it is possible to prevent a destruction phenomenon in which a leak current is generated in the semiconductor region 7 and the gate electrode 6 thereunder, thereby providing high reliability. The connection holes 15 and 16 can be formed with a high production yield.

Next, as shown in FIG. 18, after removing the unnecessary resist film 14 using the same manufacturing process as that of the first embodiment, the connection hole 15
The plug 17 is formed in the connection hole 16 and the plug 18 is formed in the connection hole 16.
To form Thereafter, a wiring layer 19 is formed on the plug 17 and a wiring layer 20 is formed on the plug 18 at the same time. Next, after a multilayer wiring layer is formed on the semiconductor substrate 1 as necessary, a passivation film (not shown) is formed thereon, thereby completing the semiconductor integrated circuit device manufacturing process.

In FIG. 18, the drawing on the left is a cross-sectional view taken along the line AA 'in FIG. 2, and is a cross-sectional view of a region where the capacitors of the STC type memory cell of the SRAM are arranged. 2 is a cross-sectional view taken along the line BB 'in FIG. 2, and shows the MO of the STC type memory cell of the SRAM.
Is a cross-sectional view of the area are arranged SFETQ _2.

In FIG. 18, the leftmost gate electrode 6 is
Corresponds to G ₁ in FIG. 2, MOSFET Q ₁ and MOS
A conductive layer connecting the gate electrode 6 and those with FETs Q _2. The lower electrode 9 of the capacitor C on the surface of the gate electrode 6 of the left through the connecting hole 23 corresponding to the connecting holes H _G1 is connected.

The second gate electrode 6 from the left end is
Corresponds to G ₂ in FIG. 2, MOSFET Q ₃ and MOS
FETQ is a conductive layer which connects the gate electrode 6, and their _four. The upper electrode 12 of the capacitor C through the connection hole 24 corresponding to the connecting holes H _G2 is coupled to the second surface of the gate electrode 6 from the left end.

In FIG. 18, the MOSFET shown on the right side of FIG.
Is the MOSFET Q ₂ of the SRAM STC type memory cell.
And the semiconductor region 7 on the left side thereof corresponds to the source,
The right semiconductor region 7 corresponds to the drain.

The connection hole 15 on the left semiconductor region 7 corresponding to the source of the MOSFET Q ₂ corresponds to the connection hole H _2a in FIG. 2 and the connection hole 15 above the right semiconductor region 7 corresponding to the drain of the MOSFET Q ₂ . The connection hole 16 corresponds to the connection hole _H2b in FIG.

Therefore, each MOSFET in FIG.
Connecting holes H _1a to H _6a and the connecting hole H _1b to H _5b corresponding to the drains of the MOSFET Q ₁ to Q ₅ corresponding to each source of Q ₁ to Q ₆ is connected in the connection hole 15 (FIG. 2 described above It can be formed using the same manufacturing process as that for forming the hole H _2a ) and the connection hole 16 (corresponding to the connection hole H _2b in FIG. 2).

[0076] The wiring layer 19 on the plug 17 embedded in the contact hole 15 on the left side of the semiconductor region 7 corresponding to the source of MOSFET Q _2, one end of the flip-flop circuit in FIG. 1 (driving MOSFET Q ₂ , Q ₄
Are connected to the ground (GND) wiring layer that supplies a reference voltage (Vss) of 0 V, for example.

[0077] The wiring layer 20 on the plug 18 embedded in the connection hole 16 on the right side of the semiconductor region 7 corresponds to the drain of MOSFET Q ₂ has a drain region and a local interconnection of the load MOSFET Q ₃ in FIG. 1 L ₁ is a wiring layer connected to the.

According to the semiconductor integrated circuit device and the method of manufacturing the same according to the first embodiment, the first embodiment is used.
Similarly to the above, a silicon nitride film 10 serving as a dielectric of a capacitor is formed on the entire surface of the semiconductor substrate 1, and an insulating film 13 containing silicon oxide is formed on the silicon nitride film 10. When forming the connection holes 15 and 16 in the insulating film 13 to be contained, the silicon nitride film 10 is used as an etching stopper film. Therefore,
According to the semiconductor integrated circuit device and the method of manufacturing the same of the present embodiment, the same effects as those of the first embodiment can be obtained.

This embodiment has a manufacturing process different from that of the above-described first embodiment, and the silicon oxide film 22 below the connection holes 15 and 16 is formed to have a height of 1000 to 4000 which is the same as the height of the gate region. We are doing the work of etching away about Angstrom. In this case, even if over-etching is performed to etch the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film, the insulating film 13 containing the upper silicon oxide (for example, several hundreds) Angstrom)
Is performed after another etching step, the amount of etching is smaller than that of the insulating film 13 containing silicon oxide as an upper layer (for example, several hundred angstroms), and over-etching can be reduced. In addition, the field insulating film 4 made of a silicon oxide film and the sidewall insulating film 8 made of a silicon oxide film can be prevented from being extremely etched.

As a result, when the connection holes 15 and 16 are formed, it is possible to prevent a destruction phenomenon in which a leak current is generated in the semiconductor region 7 and the gate electrode 6 thereunder, thereby achieving high reliability. The connection holes 15 and 16 can be formed with a high production yield.

According to the above-described semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, field insulating film 4 made of a silicon oxide film having a trench isolation structure.
Semiconductor substrate 1 having field insulating film 4
Is flattened. That is, the surface of the field insulating film 4 and the surface of the semiconductor substrate 1 having the p-type well 3 as the element active region are in the same plane state, and they are planarized using the CMP method. ing.
After the silicon oxide film 22 is deposited on the semiconductor substrate 1 by using the CVD method, the unnecessary silicon oxide film 22 up to the surface of the silicon nitride film 21 is removed by using the CMP method, and the silicon oxide film is removed. 22 is flattened.

Therefore, the capacitor of the present embodiment is formed on flattened field insulating film 4 and flattened silicon oxide film 22,
A structure of the capacitor which is flatter than the capacitor of the first embodiment can be obtained.

As a result, according to the semiconductor integrated circuit device and the method of manufacturing the same of the present embodiment, a flattened capacitor can be formed. Can be placed in a range. As a result, the SRAM of the present embodiment
STC of SRAM in semiconductor integrated circuit device having semiconductor
Since the type memory cell can increase the storage node capacity of the memory cell, it is possible to prevent a decrease in α-ray soft error resistance due to a reduction in memory cell size and a decrease in operating power supply voltage.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, the present invention provides, in addition to an embodiment in which a CMOSFET is formed as a semiconductor element on a semiconductor substrate,
An embodiment in which various semiconductor elements such as a MOSFET and a bipolar transistor are formed on a semiconductor substrate can be adopted. As a substrate on which a semiconductor element is formed, an SOI (Silicon on Insul) which is a substrate different from the semiconductor substrate is used.
ator) An SOI substrate in which a silicon single crystal thin film is formed over an insulating region having a structure can be used.

The present invention also relates to the first and second embodiments described above.
In addition to the embodiment in which a capacitor is formed as a constituent element of the STC memory cell of the SRAM 2 in various embodiments,
M STC memory cells or DRAM (Dynamic Rand)
The present invention can be applied to a semiconductor integrated circuit device having various capacitors such as a memory in which a capacitor is formed as a component of an STC memory cell of an om Access Memory or a device having a memory and a logic.

[0087]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, when forming a connection hole in an insulating film containing silicon oxide, a silicon nitride film functioning as an etching stopper film is disposed below the insulating film. As a result, the alignment accuracy between the photolithography technology and the selective etching technology is increased, and even if the connection hole overlaps with the field insulating film made of the silicon oxide film and the sidewall insulating film made of the silicon oxide film, the connection is made. Since the field insulating film made of a silicon oxide film and the sidewall insulating film made of a silicon oxide film can be prevented from being etched and destroyed by the etching at the time of forming the holes, any misalignment between them can be prevented. The connection hole can be formed by fine processing without taking into account the above.

In addition, since the field insulating film made of a silicon oxide film and the side wall insulating film made of a silicon oxide film can be prevented from being broken by the etching at the time of forming the connection hole, a highly reliable connection can be achieved. A semiconductor integrated circuit device having holes can be manufactured with a high manufacturing yield.

When a connection hole is formed by using photolithography technology and selective etching technology on an insulating film containing silicon oxide, a silicon nitride serving as a dielectric of a capacitor is formed in a region where the connection hole is formed. By arranging the silicon nitride film as an etching stopper film using the manufacturing process of forming a film, a silicon nitride film serving as a dielectric of a capacitor is formed as a manufacturing process of forming the silicon nitride film as an etching stopper film. Since the same process as that for forming the silicon nitride film is used, a silicon nitride film as an etching stopper film can be easily formed without increasing the number of manufacturing processes.

(2). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, the lower electrode of the capacitor connected to the gate electrode in the region where the capacitor is formed is formed of a titanium nitride film, and furthermore, for example, plasma ammonia or plasma nitrogen is used. By performing the treatment of exposing the surface of the titanium nitride film to an atmosphere gas containing nitrogen, the surface of the titanium nitride film can react with nitrogen having an excessive molecular weight and nitrogen. can do. Thereafter, a silicon nitride film serving as a dielectric of the capacitor is formed on the entire surface of the semiconductor substrate by using a high-temperature heating type thermal CVD apparatus.

Therefore, unnecessary substances such as moisture can be eliminated from the silicon nitride film, and a highly reliable and high-performance silicon nitride film having good heat resistance can be obtained. Further, since a chemical reaction with a titanium nitride film as a lower electrode below the silicon nitride film can be prevented, a highly reliable and high-performance silicon nitride film can be obtained.

Further, in the manufacturing process after the formation of the capacitor, the region of the capacitor may be exposed to a high temperature of 700 ° C. to 900 ° C., for example, when an insulating film containing silicon oxide is formed. Since the process of exposing the surface of the titanium nitride film (the lower electrode of the capacitor) to an atmosphere gas containing the titanium nitride film as the lower electrode of the capacitor and the silicon nitride film thereon have a non-reactive effect, The degree of their adhesion is high, and their adhesion is not reduced. As a result, a change in capacitance of the capacitor, a defect, and the like can be prevented, so that a semiconductor integrated circuit device having a highly reliable and high performance capacitor can be manufactured.

(3). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, the region where the capacitor is formed is disposed on the field insulating film between the region where the MOSFET is formed, and is not affected by the MOSFET. Since a wide range of capacitors can be formed on the field insulating film according to the design specifications, large-capacity capacitors can be arranged according to the design specifications. As a result, the STC type memory cell of the SRAM in the semiconductor integrated circuit device having the SRAM according to the present invention can increase the storage node capacity of the memory cell. A decrease in line soft error resistance can be prevented.

(4). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, the semiconductor integrated circuit device has a field insulating film made of a silicon oxide film having a trench isolation structure,
The surface of the semiconductor substrate having the field insulating film is flattened. That is, the surface of the field insulating film and the surface of the semiconductor substrate which is an element active region are in the same plane state, and they are flattened by using the CMP method. After a silicon oxide film is deposited on a semiconductor substrate, an unnecessary silicon oxide film up to the surface of the silicon nitride film in the gate region is removed by using a CMP method, and the silicon oxide film is planarized.

Therefore, since the capacitor of the present invention is formed on the flattened field insulating film and the flattened silicon oxide film, the capacitor of the present invention is smaller than the capacitor formed on the LOCOS structure field insulating film. Can also be a planarized capacitor structure.

As a result, according to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, since a flattened capacitor can be formed, the size of the capacitor is larger than that of the capacitor formed on the field insulating film having the LOCOS structure. Capacitors of capacitance can be arranged in a narrow range.
As a result, the STC type memory cell of the SRAM in the semiconductor integrated circuit device having the SRAM according to the present invention can increase the storage node capacity of the memory cell. A decrease in line soft error resistance can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an STC type memory cell of an SRAM in a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention;

2 is a plan view schematically showing an STC type memory cell of the SRAM shown in FIG. 1 for describing a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention and a method of manufacturing the same.

FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention;

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device having the SRAM according to the embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention.

FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to an embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device having the SRAM according to the embodiment of the present invention;

FIG. 10 is a sectional view illustrating the method of manufacturing the semiconductor integrated circuit device having the SRAM according to one embodiment of the present invention;

FIG. 11 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 12 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 13 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 17 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

FIG. 18 is a sectional view illustrating a method of manufacturing a semiconductor integrated circuit device having an SRAM according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 well 3 well 4 field insulating film 5 gate insulating film 6 gate electrode 7 semiconductor region 8 sidewall insulating film (sidewall spacer) 9 lower electrode of capacitor 10 silicon nitride film 11 connection hole 12 upper electrode of capacitor 13 silicon oxide Insulating film containing 14 resist film 15 connection hole 16 connection hole 17 plug 18 plug 19 wiring layer 20 wiring layer 21 silicon nitride film 22 silicon oxide film 23 connection hole 24 connection hole 25 groove C capacitor DL, / DL data line G ₁ The gate electrode G ₂ gate electrode G ₃ gate electrode H _1a to H _6a connecting holes H _1b to H _5b connection hole L _1, L ₂ local interconnection Q _1, Q ₃ load MOSFET (P-channel MOSFE
T) MOSFET for driving Q ₂ and Q ₄ (N-channel MOSFET
T) Q ₅ , Q ₆ transfer MOSFET (N-channel MOSFET
T) Vcc power supply voltage Vss Reference voltage WL Word line

Claims (9)

[Claims] A silicon nitride film formed by the same manufacturing process as a silicon nitride film as a dielectric of a capacitor is formed under the insulating film on the side surface of a connection hole provided on a source and a drain of a MOSFET. A semiconductor integrated circuit device which is arranged. 2. The semiconductor integrated circuit device according to claim 1, wherein said capacitor is disposed on a field insulating film separating a plurality of MOSFETs. 3. The semiconductor integrated circuit device according to claim 1, wherein the lower electrode and / or the upper electrode of the capacitor is formed using a titanium nitride film. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the field insulating film below a region where the capacitor is formed has a LOCOS structure or a trench isolation structure. A semiconductor integrated circuit device comprising a field insulating film. 5. The semiconductor integrated circuit device according to claim 1, wherein said capacitor is an SRA.
A semiconductor integrated circuit device, which is a constituent element of an M or DRAM STC type memory cell. 6. A step of thermally oxidizing a selective region on the surface of the substrate to form a field insulating film made of a silicon oxide film having a LOCOS structure, and thereafter, forming a plurality of MOSFETs in an element forming region of the substrate. And forming two rows of wiring layers connected to the gate electrodes of at least one of the MOSFETs on the field insulating film by the same manufacturing process as the gate electrodes. Forming a lower electrode of the capacitor in a state of being connected to the surface of one of the wiring layers of the two rows, and thereafter forming a silicon nitride film as a dielectric of the capacitor on the entire surface of the substrate And thereafter, connecting the upper electrode of the capacitor to the surface of the other wiring layer of the two rows of wiring layers on the field insulating film. Forming an insulating film containing silicon oxide on the substrate; forming a connection hole in the insulating film on a semiconductor region as a source and a drain of the MOSFET by photolithography. Forming the silicon nitride film as an etching stopper film using and selective etching technology;
Removing the silicon nitride film below the connection hole by etching. 7. A step of forming a groove in a selective region on a surface of a substrate, forming a field insulating film made of a silicon oxide film having a trench isolation structure in the groove, and thereafter, forming a field insulating film in an element forming region of the substrate. Forming a plurality of MOSFETs each having a silicon nitride film on the surface of the gate electrode, and forming a wiring layer connected to a gate electrode of at least one of the MOSFETs on the field insulating film on the field insulating film; Forming two rows by the same manufacturing process as the silicon nitride film formed on the surface; and forming an insulating film containing a silicon oxide film on the substrate, and then forming the silicon nitride film on the surface of the gate electrode. Is used as an etching stopper film, and the surface of the insulating film containing silicon oxide is After the step of planarizing and removing the silicon nitride film on the surface of the two rows of wiring layers on the field insulating film, a lower electrode of a capacitor is formed on the two rows of wiring layers on the field insulating film. Forming a silicon nitride film as a dielectric of a capacitor on the entire surface of the substrate; and forming a capacitor on the field insulating film over the entire surface of the substrate. Forming an upper electrode in a state of being connected to the surface of the other wiring layer of the two rows of wiring layers; forming an insulating film containing silicon oxide on the substrate; Using a photolithography technique and a selective etching technique to form a connection hole in the insulating film above the semiconductor region as a drain and the silicon nitride film as an etching stopper film Forming, and then, removing the silicon nitride film under the connection hole by etching. Thereafter, etching the insulating film containing silicon oxide that was under the silicon nitride film in the connection hole. A method of manufacturing a semiconductor integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the lower electrode of the capacitor is formed using a titanium nitride film, and then the lower electrode is formed in an atmosphere gas containing nitrogen. A method of manufacturing a semiconductor integrated circuit device, comprising: performing a process of exposing a surface; and thereafter, forming silicon nitride serving as a dielectric of a capacitor on the entire surface of the substrate by using a high-temperature heating type thermal CVD apparatus. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein said plurality of MOSFETs formed on said substrate include a plurality of MOSFETs.
SFET is included, and it is ST of SRAM
A method for manufacturing a semiconductor integrated circuit device, which is a component of a C-type memory cell.