JPH10173199A - Thin film transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of processes at the time of manufacturing a thin film transistor having no alignment area in its channel width. SOLUTION: Before a metallic film 27 used for forming a silicide layer 28 is formed, ions are implanted into a thin semiconductor film 25 by using a mask of photoresist pattern 26 formed by performing rear surface exposure by using a gate electrode 22 as a mask. When the metallic film 27 is formed thereafter, the silicide layer 28 is formed between the metallic film 27 and the ion-implanted area 25a of the thin semiconductor film 25. After the silicide layer 28 is formed, the metallic film 27 and the photoresist pattern 26 are removed. The photoresist pattern 26 also has the function of a channel protective film and no problem is raised even when the metallic film 27 and pattern 26 are removed after the silicide layer 28 is formed. Therefore, the number of processes for manufacturing a thin film transistor can be reduced, because the formation of the conventional channel protective film composed of silicon nitride is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, a conventional thin film transistor used as a switching element of an active matrix type liquid crystal display device does not have an alignment region in a channel width (for example, Japanese Patent Laid-Open No. 7-3029).
No. 10). Next, an example of manufacturing such a conventional thin film transistor will be described with reference to FIGS.
Will be described in order.

First, as shown in FIGS. 10A and 10B, a gate electrode 2 and a gate line 3 are formed at predetermined locations on an upper surface of a transparent substrate 1 made of glass or the like, and a gate insulating film is formed on the upper surface. 4, a semiconductor thin film 5 is formed on the upper surface, a channel protective film 6 made of silicon nitride is formed on the upper surface, and a photoresist pattern 7 is formed at a predetermined position on the upper surface. In this case, the photoresist pattern 7 is formed by back surface exposure (exposure from the lower surface side of the transparent substrate 1) using the gate electrode 2 and the gate line 3 as a mask, so that the gate electrode 2 and the gate line 3 are formed.
And is formed only on the gate electrode 2 and the gate line 3. Therefore, the length L of the photoresist pattern 7 on the gate electrode 2 in the channel length direction is equal to the width of the gate electrode 2.

Next, when the channel protective film 6 is etched using the photoresist pattern 7 as a mask, FIG.
(A) and (B) are obtained. That is, the channel protective film 6 remains only under the photoresist pattern 7. In this state, the channel protective film 6 is formed only on the gate electrode 2 and the gate line 3. Therefore, the length L of the channel protection film 6 on the gate electrode 2 in the channel length direction is the same as the width of the gate electrode 2. Next, the photoresist pattern 7 is removed. Next, when ions (impurities) such as phosphorus and boron are implanted using the channel protective film 6 as a mask, an ion implanted region 5a is formed in the semiconductor thin film 5 in a region other than under the channel protective film 6.

Next, as shown in FIGS. 12A and 12B, a conductive film 8 for forming an element region made of a metal material such as chromium, which can be silicided, is formed on the upper surface. A photoresist pattern 9 is formed at the position of. In this case, the photoresist pattern 9 is formed so as to form a substantially cross shape with the channel protective film 6 on the gate electrode 2 by crotting the channel protective film 6, and the width D is the same as the intended channel width. It has become. Further, a silicide layer 10 is formed between the conductive film 8 and the semiconductor thin film 5. Next, when the conductive film 8, the silicide layer 10, the channel protective film 6, and the semiconductor thin film 5 are etched using the photoresist pattern 9 as a mask, the result is as shown in FIGS. 13A and 13B.

That is, the conductive film 8 remains only under the photoresist pattern 9, and the silicide layer 2 only under the conductive pattern 8.
The channel protective film 6 remains, and the semiconductor thin film 2 remains only therebelow. In this state, the conductive film 8 is formed so as to cross the gate electrode 2 and form a substantially cross shape with the gate electrode 2, but the channel protective film 6 is formed only above the gate electrode 2 and below the conductive film 8. Have been. Therefore, the semiconductor thin film 5 is formed only under the conductive film 8 including the channel protection film 6. The portion of the semiconductor thin film 5 below the channel protective film 6 is a channel region 5b composed of an intrinsic region, and both sides thereof are a source region 5c and a drain region 5d composed of an ion implanted region 5a. As a result, the semiconductor thin film 5 has a channel region 5b whose channel length is self-aligned with the width L of the gate electrode 2 and is formed to have the same length L as the width of the gate electrode 2. Channel regions 5 on both sides of the
The structure has the source region 5c and the drain region 5d formed to have the same width as the width D of b, and the effective channel width becomes the desired channel width.

[0007]

The reason why the channel protective film 6 is provided in such a conventional thin film transistor is that, when the conductive film 8 is formed in the manufacturing process shown in FIG. Channel region 5b shown
This is to prevent a silicide layer from being formed on the upper surface of the substrate. For this reason, in the manufacturing process shown in FIG. 10, a photoresist pattern 7 is formed on the formed channel protection film 6, and the channel protection film 6 is etched using the photoresist pattern 7 as a mask. In many cases, there was a problem that productivity was low. An object of the present invention is to reduce the number of manufacturing steps.

[0008]

According to a first aspect of the present invention, there is provided a thin film transistor having a gate electrode, a gate insulating film, and a channel region having a length that is self-aligned with the gate electrode. A semiconductor thin film having a source region and a drain region formed with the same width as the width of the channel region, a source electrode connected to the source region, and a drain electrode connected to the drain region. A channel protective film is not provided on the channel region. 6. A method of manufacturing a thin film transistor according to claim 5, wherein a gate electrode is formed on a substrate, a gate insulating film and a semiconductor thin film are formed on an upper surface thereof, and a resist pattern self-aligned with the gate electrode is exposed on the upper surface by back exposure. And a metal film capable of being silicided is formed on the upper surface thereof, and a silicide layer is formed between the metal film and the semiconductor thin film except under the resist pattern.

According to a fifth aspect of the present invention, a resist pattern is formed on an upper surface of a semiconductor thin film, and when a metal film capable of being silicided is formed on the upper surface, a resist pattern is formed on the upper surface of the semiconductor thin film below the resist pattern. The silicide layer can be prevented from being formed. Therefore, the resist pattern can have a function as a channel protective film, and there is no problem even if the metal film and the resist pattern are removed after the silicide layer is formed. As a result, a thin film transistor in which the channel protective film is not provided on the channel region as in the first aspect can be obtained. In addition, the number of manufacturing steps can be reduced because the channel protection film does not need to be formed unlike the related art.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 6 show respective manufacturing steps of a thin film transistor according to an embodiment of the present invention. Therefore, referring to these figures in order,
The structure of the thin film transistor of this embodiment will be described together with its manufacturing method.

First, as shown in FIGS. 1A and 1B,
A gate electrode 22 and a gate line 23 made of chromium or the like are formed at predetermined positions on the upper surface of a transparent substrate 21 made of glass or the like to a thickness of about 1000 °, and a gate insulating film 24 made of silicon nitride is formed on the upper surface to a thickness of about 3000 °. And a semiconductor thin film 25 made of single crystal silicon, amorphous silicon, polysilicon or the like having a film thickness of 50
A film is formed to a thickness of about 0 °, and a photoresist pattern 26 is formed at a predetermined location on the upper surface. In this case, the photoresist pattern 26 includes the gate electrode 22 and the gate line 2.
3 is formed by back exposure (exposure from the lower surface side of the transparent substrate 21) using the mask 3 as a mask.
And only on the gate line 23. Therefore, the photoresist pattern 26 on the gate electrode 22
Is the same as the width of the gate electrode 22 in the channel length direction. Next, when ions (impurities) such as phosphorus and boron are implanted using the photoresist pattern 26 as a mask, an ion implanted region 25a is formed in the semiconductor thin film 25 in a region other than under the photoresist pattern 26.

Next, as shown in FIGS. 2A and 2B,
A metal film 27 made of a silicidable metal material such as chromium, molybdenum, titanium, and tungsten is formed on the upper surface to a thickness of about 200 ° by plasma CVD. Then, the ion implantation region 25 of the metal film 27 and the semiconductor thin film 25 is formed.
A silicide layer 28 having a thickness of about several tens of millimeters is formed between the silicide layer 28 and a. That is, no silicide layer is formed on the upper surface of the semiconductor thin film 25 in a region (channel region to be described later) 25b of the semiconductor thin film 25 below the photoresist pattern 26. Next, when the metal film 27 and the photoresist pattern 26 are removed, as shown in FIGS.
A portion of the silicide layer 28 and the semiconductor thin film 25 other than the ion implantation region 25a is exposed.

Next, as shown in FIGS. 4A and 4B,
A photoresist pattern 29 for forming an element region is formed at a predetermined location on the upper surface. In this case, the photoresist pattern 29 is formed so that the exposed portion of the semiconductor thin film 25 on the gate electrode 22 is crotched to form a substantially cross shape with the exposed portion, and the width D is the same as the intended channel width. It has become. Next, when the silicide layer 28 and the semiconductor thin film 25 are etched using the photoresist pattern 29 as a mask, the result is as shown in FIGS. 5A and 5B.

That is, the silicide layer 28 and the semiconductor thin film 25 remain only under the photoresist pattern 29. In this state, a portion of the semiconductor thin film 25 on the gate electrode 22 is a channel region 25b composed of an intrinsic region,
Both sides are a source region 25c and a drain region 25d, each of which is formed by an ion implantation region 25a. As a result, the semiconductor thin film 25 has a channel length of the gate electrode 2.
2 having a length L which is self-aligned with the width L of the gate electrode 22 and has the same length L as the width of the gate electrode 22. Each of the two sides of the channel region 25b has the same width D as the width D of the channel region 25b. Source region 25c formed in width
And a drain region 25d, and the effective channel width is the desired channel width. Thereafter, the photoresist pattern 29 is removed.

Next, as shown in FIGS. 6A and 6B,
A pixel electrode 30 made of ITO is formed at a predetermined position on the upper surface to a thickness of about 500 °. Next, a source electrode 31, a drain electrode 32, and a drain line 33 made of an aluminum-titanium alloy are formed at predetermined locations on the upper surface with a thickness of 3000.
Formed to the extent. In this state, the pixel electrode 30 is connected to the source region 25c of the semiconductor thin film 25 via the silicide layer 28 and the source electrode 31, and the drain electrode 32 is connected to the drain region 25d via the silicide layer 28. In this case, the source electrode 31 and the drain electrode 32 are in direct contact with the silicide layer 28. Thus, the thin film transistor of this embodiment is manufactured. In the state shown in FIG. 6, the channel region 25b and a part of the silicide layer 28 are exposed, but are directly covered by a passivation film or the like formed on the entire upper surface in a later step.

As described above, in the method of manufacturing a thin film transistor of this embodiment, as shown in FIG. 2, a photoresist pattern 26 is formed on the upper surface of a semiconductor thin film 25, and a metal film 27 which can be silicided is formed on the upper surface. When the film is formed, a silicide layer can be prevented from being formed on the upper surface of the semiconductor thin film 25 under the photoresist pattern 26. Therefore, the photoresist pattern 26
Can have a function as a channel protective film,
Moreover, there is no problem even if the metal film 27 and the photoresist pattern 26 are removed after the silicide layer 28 is formed. As a result, as shown in FIG.
A thin film transistor over which a channel protective film is not provided can be obtained. In addition, the number of manufacturing steps can be reduced because the channel protection film does not need to be formed unlike the related art.

In the above embodiment, as shown in FIG. 1, after ion implantation, a metal film 27 is formed to form a silicide layer 28 as shown in FIG. The steps may be reversed. That is, first, FIG.
As shown in (A) and (B), a photoresist pattern 26 is formed at a predetermined location on the upper surface of the semiconductor thin film 25.
Next, as shown in FIGS. 8A and 8B, a metal film 27 is formed on the upper surface to a thickness of about 50 to 200 °. Then, a silicide layer 28 is formed between the metal film 27 and the semiconductor thin film 25 except under the photoresist pattern 26. Next, as shown in FIGS. 9A and 9B, when ions are implanted using the photoresist pattern 26 as a mask, an ion implanted region 25a is formed in the semiconductor thin film 25 in a region other than under the photoresist pattern 26. . In this case, due to the ion implantation energy at this time, a metal such as chromium is injected from the metal film 27 in a region other than under the photoresist pattern 26 into the semiconductor thin film 25 through the silicide layer 28. For this reason, silicidation is promoted, and the thickness of the silicide layer 28 can be further increased.

[0018]

As described above, according to the present invention, it is not necessary to form a channel protective film as in the prior art, so that the number of manufacturing steps can be reduced accordingly.
As a result, productivity can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B show an initial step in manufacturing a thin film transistor according to an embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line BB.

2 (A) is a plan view, and FIG. 2 (B) is a cross-sectional view taken along the line BB of FIG.

3 (A) is a plan view, and FIG. 3 (B) is a cross-sectional view taken along the line BB of FIG.

4 (A) is a plan view, and FIG. 4 (B) is a cross-sectional view along the line BB, showing a step following FIG. 3;

5 (A) is a plan view, and FIG. 5 (B) is a sectional view taken along the line BB, showing a step following FIG.

6 (A) is a plan view, and FIG. 6 (B) is a sectional view taken along the line BB, showing a step following FIG. 5;

7A and 7B show an initial step in manufacturing a thin film transistor according to another embodiment of the present invention, wherein FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along the line BB.

8 (A) is a plan view, and FIG. 8 (B) is a sectional view taken along the line BB, showing a step following FIG. 7;

FIG. 9 shows a step following FIG. 8, in which (A) is a plan view and (B) is a cross-sectional view along the line BB.

10A and 10B show an initial step in manufacturing a conventional thin film transistor. FIG. 10A is a plan view, and FIG.
Sectional drawing which follows the -B line.

11A and 11B show a step following the step shown in FIG. 10, wherein FIG. 11A is a plan view and FIG. 11B is a cross-sectional view along the line BB.

FIG. 12 shows a step following FIG. 11, in which (A) is a plan view and (B) is a cross-sectional view along the line BB.

13 (A) is a plan view, and FIG. 13 (B) is a sectional view taken along the line BB of the step following FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Transparent substrate 22 Gate electrode 24 Gate insulating film 25 Semiconductor thin film 26 Photoresist pattern 27 Metal film 28 Silicide layer 29 Photoresist pattern 31 Source electrode 32 Drain electrode

Claims (8)

[Claims] A source having a gate electrode, a gate insulating film, and a channel region having a length self-aligned with the gate electrode, and having a width equal to the width of the channel region on both sides of the channel region. A semiconductor thin film having a region and a drain region, a source electrode connected to the source region, and a drain electrode connected to the drain region, wherein a channel protective film is not provided over the channel region. Characteristic thin film transistor. 2. The thin film transistor according to claim 1, wherein an impurity is implanted into the source region and the drain region. 3. The method according to claim 1, wherein
A thin film transistor, wherein a silicide layer is interposed between the semiconductor thin film and the source electrode and the drain electrode. 4. The thin film transistor according to claim 3, wherein the silicide layer is in direct contact with the source electrode and the drain electrode. 5. A gate electrode is formed on a substrate, a gate insulating film and a semiconductor thin film are formed on an upper surface thereof, and a resist pattern self-aligned with the gate electrode is formed on an upper surface thereof by backside exposure. Forming a silicide-forming metal film on the substrate, and forming a silicide layer between the metal film and the semiconductor thin film except under the resist pattern. 6. The method according to claim 5, wherein an impurity is implanted into the semiconductor thin film using the resist pattern as a mask before forming the metal film. 7. The method according to claim 5, wherein an impurity is implanted into the semiconductor thin film using the resist pattern as a mask after forming the metal film. 8. The semiconductor device according to claim 5, wherein after removing the metal film and the resist pattern, a predetermined position between the gate electrode and the upper surface of the semiconductor thin film is provided. A method of manufacturing a thin film transistor, comprising: forming a resist pattern for forming an element region having the same width as a channel width; and etching the silicide layer and the semiconductor thin film using the resist pattern as a mask.