JPH10173127A - Manufacturing method of resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable forming of a diffused region and a small-resistance region having equal areas and accurately form a resistor having specified resistance; a large-resistance part to be a resistance body composed of low-concn. impurity regions covered with a mask pattern is sandwiched between the diffused region and the small-resistance region. SOLUTION: On a base 10 a resistance film 15 is formed and patterned to form a resistance pattern 21 having specified width and length, and contact patterns 22 widen than the pattern 21 connecting to both ends of the pattern 21 are formed. A mask pattern 31 having a shorter length than the spacing between the contact patterns 22 and wider width than that of the resistance pattern 21 covers the resistance pattern 21 with a larger spacing between the mask pattern 31 and each contact pattern 22 than the mask alignment deviation caused at forming of the mask pattern 21. Using the mask pattern 31 as a mask an impurity is doped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a resistor, and more particularly, to a method for manufacturing a resistor mounted on a semiconductor device.

[0002]

2. Description of the Related Art With the recent increase in precision of characteristics required for semiconductor integrated circuits, attention has been paid to techniques for improving the precision of active elements such as resistors as well as passive elements of transistors. As resistors used in semiconductor integrated circuits, there are a polycrystalline silicon resistor using a polycrystalline silicon film formed on an insulating film, and a diffusion resistor using a diffusion layer formed by an impurity introduced into a silicon substrate. The polycrystalline silicon resistor is often used in a process using polycrystalline silicon because it has a small parasitic capacitance, does not have the effect of a field-effect transistor, and has no bias limitation.

As shown in FIG. 9, a general polycrystalline silicon resistor is formed on a silicon oxide film 112 and is formed by a polycrystalline silicon film pattern doped with a predetermined impurity. Electrodes 113 and 114 are connected to the upper portions on both ends of the pattern. In such a polycrystalline silicon resistor 111, a plurality of polycrystalline silicon resistors having different sheet resistances in the same polycrystalline silicon film are formed by appropriately setting the impurity concentration in the polycrystalline silicon of the resistor main body 115. It becomes possible to do.

A so-called dog-bone type polycrystalline silicon resistor 120 as shown in FIG. 10 has also been proposed as a resistor capable of obtaining a high resistance in a small area. The polycrystalline silicon resistor 120 includes a resistor pattern 121 serving as a resistor main body, and a contact pattern 122 formed continuously on both ends thereof and serving as a contact portion. The width wc ′ of the contact pattern 122 is wider than the width wr ′ of the resistance pattern 121. In such a configuration, generally, each contact pattern 122 to which a wiring (not shown) is connected is formed with low resistance, and the resistance pattern 121 is formed with high resistance. Therefore, a contact portion 141 is formed on each contact pattern 122.

The dog-bone type polycrystalline silicon resistor 120 is manufactured as follows. The manufacturing method will be described with reference to the manufacturing process diagram of FIG. As shown in FIG. 11A, after a polycrystalline silicon film is formed on an insulating film (not shown), the polycrystalline silicon film is patterned by lithography and etching to obtain a predetermined width wr ′. Resistance pattern 121 having length lr '
And a contact pattern 122 (122A, 122B) continuous with both ends of the resistance pattern 121 and having a width wc 'wider than the width wr' of the resistance pattern 121.
And are formed. Thereafter, a resist film pattern 131 covering the resistance pattern 121 is formed by lithography. That is, the resist film pattern 131 is formed to have a length equal to the length lr 'of the resistance pattern 121, and has a width wider than the width wr' of the resistance pattern 121. Then, the contact pattern 122 is doped with impurities by performing ion implantation using the resist film pattern 131 as a mask.

Thereafter, the resist film pattern 131 is removed. Subsequently, heat treatment is performed. As a result, as shown in FIG. 11B, the impurities in the resistance pattern 121 are activated. At that time, the contact pattern 122
The impurities therein are diffused to the resistance pattern 121 side, and a diffusion region 125 is formed. As described above, if no misalignment of the photomask occurs when the resist film pattern 131 is formed, the polycrystalline silicon resistor 120 can be formed without the problem that the resistance value is deviated from the design value.
Is formed.

[0007]

However, in the above-described method of manufacturing a polycrystalline silicon resistor, the resist film pattern is usually misaligned with the resist pattern, as shown in FIG. 131 is formed over a part of one contact pattern 122 (for example, contact pattern 122B). In this state, ion implantation is performed, and after removing the resist film pattern 131, heat treatment is performed. As a result, as shown in (2) of FIG. 12, due to the difference in impurity concentration between the resistance pattern 121 and the contact pattern 122, the impurity in the high concentration contact pattern 122 is diffused toward the low concentration resistance pattern 121, A diffusion region 125 is formed.

In this case, the one diffusion region 125A is not formed in the one contact pattern 122A, but has a width smaller than that of the contact pattern 122.
And the other diffusion region 125B is formed in the contact pattern 122B, so that the impurity concentration distribution in the resistance region near both contact patterns 122 becomes asymmetric. In addition, since the high-resistance region 123 is formed up to the contact pattern 122B, the area of the high-resistance region 123 for determining the resistance value is larger than an assumed value. That is, since the resistance value becomes smaller than the assumed value, the aim of the resistance value deviates from the assumed value. This is extremely disadvantageous for improving the characteristics required of recent semiconductor integrated circuits, for example, for improving the timing characteristics.

[0009]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a resistor which has been made to solve the above problems. That is, in the first manufacturing method, a resistive film formed on a base is patterned to form a resistive pattern having a predetermined width and length, and a resistive pattern that is continuous at both ends of the resistive pattern and is smaller than the width of the resistive pattern. A contact pattern having a wide width is formed. Next, after masking the resistor pattern with a mask pattern, impurity doping is performed using the mask pattern as a mask. At this time, a mask pattern having a length shorter than the interval between the contact patterns and having a width wider than the width of the resistance pattern is used. Further, an interval is provided between the mask pattern and each contact pattern that is larger than the mask misalignment generated when the mask pattern is formed. In the impurity doping, the dose is set so that the contact pattern has a higher concentration than the resistance pattern.

In the first manufacturing method, the mask pattern has a length shorter than the interval between the contact patterns formed wider than the resistance pattern and has a width wider than the width of the resistance pattern. From using
An interval is provided between the mask pattern and the contact pattern. Therefore, in the impurity doping using this mask pattern as a mask, both ends of the contact pattern and the resistor pattern connected to the contact pattern are heavily doped with impurities. Therefore, when the impurity is diffused from the high-concentration impurity region to the low-concentration impurity region, the impurity is not diffused into the contact pattern, but is diffused into the resistance pattern patterned to a constant width. Is formed. for that reason,
The high resistance portion is formed in a resistance pattern having a constant width. In addition, by providing the gap between the mask pattern and the contact pattern larger than the mask misalignment generated when forming the mask pattern, even if the mask misalignment occurs when forming the mask pattern, the mask The pattern is not formed so as to cover the contact pattern. Therefore, if the mask pattern is always formed to a fixed length, the length of the high resistance portion is formed to be the length obtained by subtracting the diffusion region from the length of the mask pattern. The resistance value of the high resistance portion becomes constant.

In a second manufacturing method, after a resistive film is formed on a substrate, a mask pattern is formed so as to cover a portion of the resistive film where a resistive pattern is to be formed, and then the mask pattern is used as a mask. To dope the resistive film with impurities. After removing the mask pattern, a resist pattern having a predetermined width and length is formed by using the resist film portion covered by the mask pattern, and the resist pattern is formed by using the resist film in an impurity-doped region. A contact pattern which is continuous with both ends of the pattern and is wider than the resistance pattern is formed. At this time, the mask pattern is formed to have a length shorter than the interval between the contact patterns formed wider than the resistance pattern and to have a width wider than the width of the resistance pattern. In addition, a gap is provided between the mask pattern and the wide portion of each contact pattern, which is larger than the mask misalignment generated when the mask pattern is formed. In the impurity doping, the dose is set so that the contact pattern has a higher concentration than the resistance pattern.

In the second manufacturing method, since the mask pattern is formed to have a length shorter than the interval between the contact patterns formed wider than the resistance pattern, the mask pattern and the contact pattern are to be formed. An interval is provided between the region and the region. Therefore, in the impurity doping using this mask pattern as a mask, impurities are doped at a high concentration on both ends of a region where a contact pattern is to be formed and a region where a resistor pattern is to be connected between the region where the contact pattern is to be formed. Therefore, when the impurity diffuses from the high-concentration impurity region to the low-concentration impurity region,
The impurity is not diffused into the contact pattern, but is diffused into the resistance pattern patterned to a constant width to form a diffusion region. Therefore, the high resistance portion is formed in a resistance pattern having a constant width. Moreover,
The distance between the mask pattern and the contact pattern is
By providing a larger mask misalignment amount generated when forming a mask pattern, even if a mask misalignment occurs when forming the mask pattern, the mask pattern is not formed to cover the contact pattern. Therefore, if the mask pattern is always formed to a fixed length, the length of the high resistance portion is formed to be the length obtained by subtracting the diffusion region from the length of the mask pattern. , The resistance value of the high resistance portion becomes constant.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One example of an embodiment according to the first invention will be described with reference to FIGS.

As shown in the sectional view of FIG. 1A, a local oxidation method [for example, LOC
OS (Local Oxidation of Silicon) method], the element isolation film 12 is formed of a silicon oxide film. After that, chemical vapor deposition (hereinafter referred to as CVD)
Our silicon substrate 1 is obtained by our Deposition method.
1 and the device isolation film 12 (in the drawing, the device isolation film 12
(Shown only above), a first insulating film 1 made of silicon oxide
3 is formed to form a substrate 10. Further, a polycrystalline silicon film 14 is formed by a CVD method. Then, boron difluoride (BF ₂ ) is introduced as a P-type impurity into the polycrystalline silicon film 14 by ion implantation to form a resistance film 15 made of the polycrystalline silicon film 14. The ion implantation conditions include, for example, a dose amount of 2 × 10
Set to about ¹⁴ / cm ² .

Next, as shown in the sectional view along the line AA in FIG. 1 (2) and the layout diagram in FIG. 3 (3), an etching mask is formed on the resistive film 15 in a region where a resistor is to be formed by resist coating and lithography. Is formed. Thereafter, etching using the resist pattern 16 as a mask [for example, reactive ion etching (hereinafter referred to as RIE)
on Etching)], the resistive film 15 is patterned. Then, a resistance pattern 21 having a predetermined width wr and a length l, and a width wc which is continuous to both end sides of the resistance pattern 21 and is wider than the width wr of the resistance pattern 21
And a contact pattern 22 (22A, 22B) having the following. Therefore, the resistance pattern 21 and the contact patterns 22 (22A, 22B) are so-called dogbone patterns.

Thereafter, the resist pattern 16 is removed by, for example, ashing. Next, as shown in the layout diagram of FIG. 1 (4), a mask pattern 31 made of resist is formed in a state of covering the resistance pattern 21 by resist coating and lithography techniques. The mask pattern 31 has a length lm shorter than the interval lc (= 1) between the wide portions of the contact patterns 22 (22A, 22B) and a width larger than the width wr of the resistance pattern 21. wm. Then, the resistance pattern 2 on the contact patterns 22A and 22B side
The length ls for exposing 1 is set to be larger than the maximum value b of the mask misalignment generated in the exposure step when forming the mask pattern 31. A portion indicated by a two-dot chain line in the drawing indicates the formation position of the mask pattern 31 when the amount of misalignment of the mask in the longitudinal direction of the resistance pattern 21 is maximized in the exposure step when the mask pattern 31 is formed. For example, if the maximum value of the mask misalignment is 0.
If the thickness is 3 μm, the mask pattern 3 is formed using a photomask in which the mask pattern 31 is patterned so that the portion of the resistance pattern 21 on the side of the contact patterns 22A and 22B is exposed at least larger than 0.3 μm.
Exposure for forming 1 is performed. Here, for example, the contact pattern 22A, 22B is set to be about 0.6 μm from the edge on the resistance pattern 21 side.
A mask pattern 31 was formed so as to expose the resistance pattern 21 on the sides A and 22B, thereby covering a portion of the resistance pattern 21 to be a high resistance region.

Thereafter, impurity doping is performed using the mask pattern 31 as a mask. In this impurity doping, the region to be doped with impurities is a mask pattern 31.
The dose is set so that the concentration becomes higher than that of the portion of the resistance pattern 21 covered by the above. For example, if boron difluoride is added to the resistance film 15 (see FIG.
Ions are implanted at a dose of about × 10 ¹⁵ / cm ² .
As a result, the portion 21A of the resistance pattern 21 covered by the mask pattern 31 becomes the high resistance region 23,
The other portions 21 </ b> B of the resistance pattern 21 and the contact patterns 22 become low resistance regions 24.

Thereafter, the mask pattern 31 is removed by, for example, ashing. Next, as shown in the cross-sectional view of FIG. 2A, a second insulating film 17 covering the resistance pattern 21 and the contact pattern 22 is formed on the first insulating film 13 using, for example, silicon oxide. Subsequently, heat treatment for activating impurities implanted in the resistance pattern 21 and the contact pattern 22 is performed by, for example, high-temperature annealing at 800 ° C. to 1000 ° C.

As a result, as shown in the layout diagram of FIG. 2B, the impurities are activated and diffused from the low-resistance region 24 to the high-resistance region 23 to form a resistance pattern. Diffusion region 25 with length ld to 21
(25A, 25B) are formed. Thus, the resistor 26 including the resistor pattern 21 and the contact pattern 22 is formed. The length l of the resistance pattern 21
Is the length lr of the high resistance region 23 and the resistance pattern 2
It is designed in consideration of the length ls × 2 of the portion exposing 1 and the length ld × 2 of the diffusion region 25. In FIG. 2B, illustration of the second insulating film 17 is omitted.

Next, as shown in FIG. 2C, after forming a resist film 32 on the second insulating film 17 by applying a resist, the resist 26 is formed by lithography.
A window 33 is opened in the resist film 32 located on the region where the extraction electrode is to be formed, that is, above the contact patterns 22. Thereafter, the contact holes 18 (18) reaching the respective contact patterns 22 from the bottoms of the respective windows 33 by RIE using the resist film 32 as a mask.
A, 18B) are formed on the second insulating film 17.

Thereafter, the resist film 32 is removed by, for example, ashing. Subsequently, as shown in FIG. 2D, the contact hole 1 is formed by sputtering.
The wiring forming film 34 is formed of, for example, an aluminum (Al) -based metal inside the inside 8 and on the second insulating film 17. afterwards,
Normal resist coating, lithography technology and RIE
As a result, the portion indicated by the two-dot chain line of the wiring forming film 34 is removed to form the extraction electrode 35 (35A) connected to the contact pattern 22A, and the extraction electrode 35 (3) connected to the contact pattern 22B.
5B) is formed.

When the resistor 26 formed by the above manufacturing method is viewed in a plan view, as shown in the layout diagram of FIG.
It comprises a resistance pattern 21 and contact patterns 22 formed continuously on both sides thereof. And the resistance pattern 21
Is formed at the center by a high resistance region 23 made of a polycrystalline silicon film into which a low concentration of boron difluoride is ion-implanted. On the other hand, the resistance pattern 21
In both sides of the high resistance region 23 in FIG.
A, 25B are formed, and a low-resistance region 2 is formed by ion-implanting high-concentration boron difluoride into a polycrystalline silicon film.
4, the respective contact patterns 22A and 22B are formed.

As described above, since the high-resistance region 23 serving as the resistance main body portion is formed by transferring the mask pattern 31 (portion indicated by a two-dot chain line) only to the resistance pattern 21 having no change in the width wr, The resistance value is determined by the length lm of the mask pattern 31. Therefore, it is possible to set the resistance value with high accuracy. Further, since the contact patterns 22A and 22B are formed in the low resistance region 24, the contact resistance in the contact patterns 22A and 22B is reduced.

Next, the case where the resist 26 is formed by the above-described manufacturing method and the case where no misalignment of the photomask occurs when the mask pattern 31 is formed will be described with reference to FIG. The case where the misalignment of the photomask occurs will be described with reference to FIG. 4 and 5, the mask pattern 31 is longer than the maximum value b of the mask misalignment generated in the exposure step when forming the mask pattern 31 to expose the resistance pattern 21 on each contact pattern 22 side. Ls
Is formed to be large.

First, the case where no misalignment of the photomask has occurred will be described below. As shown in FIG. 4A, there is no misalignment of the photomask when the mask pattern 31 is formed, and as shown in FIG. Area 23
The impurity in the low resistance region 24 (24A, 24B) diffuses (diffuses in the direction of the arrow) to the side, and the length l
A diffusion region 25 (25A, 25B) of d is formed.
In this case, the resistance value r ₁ of the resistor 26 is

[0026]

(Equation 1)

## EQU1 ## However, usually, as shown in FIG. 5A, misalignment of the photomask occurs. The maximum value of this misalignment is defined as b. Therefore,
In the illustrated case, the distance between the contact pattern 22A and the mask pattern 31 is ls + b, and the distance between the contact pattern 22B and the mask pattern 31 is ls-b. In this case, as shown in FIG. 5B, a subsequent heat treatment causes the high resistance region 23 to move from the low resistance region 24 side.
The impurity in the low resistance region 24 (24A, 24B) diffuses to the side, and the diffusion region 25 having the length ld is formed in the resistance pattern 21.
(25A, 25B) are formed. As a result, the resistance 26
The resistance value r ₂ of

[0028]

(Equation 2)

## EQU1 ## From the above equations (1) and (2), if the heat treatment is performed under the same conditions, r _1ML ,
The four resistance values of r _1MR , r _2ML and r _2MR are equal,
Also, the resistance values of r _1H and r _2H become equal. Further r _2LL
Is increased by the amount of misalignment b, and r _1LR
Becomes smaller by the amount of misalignment b,

[0030]

(Equation 3)

The following relational expression is obtained. Therefore, as a result, the whole resistance values r ₁ and r ₂ become equal. This relationship is maintained as long as the length ls of the pattern exposed portion is set to be larger than the misalignment amount b. Therefore, variation in resistance due to misalignment of the photomask at the time of patterning of the mask pattern 31 can be suppressed, so that a resistor can be formed with high precision, and characteristics required for recent semiconductor integrated circuits can be improved with high precision. Realization can be achieved.

The step of implanting ions into the contact pattern 22 for reducing the contact resistance is not used because the step is also used as the ion implantation for forming a low-resistance region having a low sheet resistance. In addition, since the resistance wr is narrowed and the width wr is reduced without forming it, a high resistance is obtained, so that the resistance 26 can be miniaturized. As a result, the area of the resistance 26 can be reduced.

Next, an example of the embodiment of the second invention will be described with reference to FIG.
This will be described with reference to FIGS. FIGS. 6 to 8
Here, the same components as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals.

As shown in the cross-sectional view of FIG. 6A, an element isolation film 12 is formed of a silicon oxide film on a P-type silicon substrate 11 serving as a base by a local oxidation method (for example, a LOCOS method). . Thereafter, the first insulating film 1 made of silicon oxide is formed on the silicon substrate 11 by CVD.
3 is formed to form the base 10. Further, a polycrystalline silicon film 14 is formed by a CVD method. Then, boron difluoride is introduced as a P-type impurity into the polycrystalline silicon film 14 by ion implantation to form a resistance film 15 made of the polycrystalline silicon film 14. The ion implantation conditions include, for example, a dose amount of 2 × 10 ¹⁴ / cm
Set to about ² .

Next, as shown in the layout diagram of FIG. 6B, a resist pattern and a lithography technique are used to form a resistance pattern forming region 41 (a portion indicated by a two-dot chain line) on the resistance film 15 in the width direction. The mask pattern 31 to be covered is formed to have a width lm shorter than the interval L between the regions 42 (42A, 42B) where the respective contact patterns are to be formed (portions indicated by two-dot chain lines).

That is, when the mask pattern 31 is formed, the length ls at which the contact pattern forming area 42 is exposed in the resistance pattern forming area 41 is assumed when the mask pattern 31 is formed. The value on the mask is set to a value larger than the sum b of the maximum value of the amount of misalignment and the maximum value of the amount of misalignment assumed for a resist mask (not shown) formed when patterning the resistive film 15 later. Is set by For example, if the maximum value of the misalignment that can occur between the time of forming the mask pattern 31 and the time of forming the resist mask (not shown) is 0.3 μm, it is larger than at least 0.3 μm and the contact pattern forming region 42 side Is set on the mask such that the region 41 where the resistance pattern is to be formed is exposed. As a result, variation in the resistance value due to misalignment of the mask can be suppressed. Here, for example, ls = from the portion of the contact pattern formation region 42 formed wider than the width wr of the resistance pattern formation region 41.
The resist pattern was formed so as to expose the region 41 where the resistance pattern was to be formed, about 0.6 μm.

Subsequently, as shown in the cross-sectional view of FIG. 6C, using the mask pattern 31 as a mask, a dose amount such that the concentration becomes higher than that of the resistive film 15 covered with the mask pattern 31 is obtained. Then, ion implantation is performed on the resistance film 15. For example, 2 × 10 ¹⁵ boron difluoride / cm
Ion implantation is performed at a dose of about ² . As a result, the resistive film 15 under the mask pattern 31 is
And the other part of the resistance film 15 becomes the low resistance region 24.

Thereafter, the mask pattern 31 is removed by, for example, ashing. Next, as shown in the layout diagram of FIG. 6D, a resist film is formed on the resistance film 15 by applying a resist. Then, a resist pattern 51 serving as a mask used for patterning the resistor is formed by lithography technology. The resist pattern 51 is on the region 41 where the resistance pattern is to be formed set in the high resistance region 23 and is a region that is continuous with the region 41 where the contact pattern is to be formed 42 (42A, 42A, 42B).

At this time, a distance ds (= d) between the region 42 where the contact pattern is to be formed and the high resistance region 23 is formed.
The length ls) of the area where the resistance pattern formation area 41 on the contact pattern formation area 42 side is exposed is determined by the maximum value of the mask misalignment generated when the mask pattern 31 is formed and the resist pattern 51. The value is set to be larger than a value b obtained by adding the maximum value of the mask misalignment generated at the time of formation. Therefore, the portions 51A and 51B serving as masks for forming the contact patterns of the resist pattern 51 do not cover the high-resistance region 23, and the portions 51R serving as masks for forming the resistive body portions of the resist pattern 51 are not formed. Are formed so as to cross over the high resistance region 23.

Thereafter, as shown in the cross-sectional view of FIG. 7A, RIE is performed using the resist mask 51 as a mask, and the portion of the resistive film 15 indicated by a two-dot chain line is removed.
The resistive film pattern 52 is formed by the remaining resistive film 15.

As a result, as shown in FIG. 7B, the resistance film pattern 52 is mainly formed of the high resistance region 23 having a low impurity concentration, and has a predetermined width wr and a predetermined length l. It comprises a pattern 21 and a contact pattern 22 formed of a low resistance region 24 having a high impurity concentration and having a width wider than the width of the resistance pattern 21 and continuously formed on both ends of the resistance pattern 21. , So-called dog bone type. In this drawing, illustration of the resist mask 51 is omitted.

Thereafter, the resist mask 51 is removed by, for example, ashing. Next, as shown in the cross-sectional view of FIG. 7C, a second insulating film 17 covering the resistive film pattern 52 is formed on the first insulating film 13 using, for example, silicon oxide. Subsequently, a heat treatment for activating the impurities implanted in the resistive film pattern 52 is performed.
For example, annealing is performed at a high temperature of 800 ° C. to 1000 ° C.

As a result, as shown in the layout diagram of FIG. 7D, the impurities in the resistive film pattern 52 are activated and the high-resistance region 2 is moved from the low-resistance region 24 side.
The impurity diffuses to the third side, and the length l
A diffusion region 25 (25A, 25B) of d is formed.
In this manner, a so-called dogbone type resistor 2 composed of each contact pattern 22 and the resistor pattern 21 is provided.
6 are formed. Note that the length l (=
The distance L between the contact patterns 22 is determined by the length lr of the high-resistance region 23 serving as the resistor main body, the region 42 (the portion indicated by the two-dot chain line) where each contact pattern is to be formed, and the mask pattern 31 (two points). This is designed in consideration of the distance ls × 2 from the area indicated by the chain line) and the diffusion length ld × 2. Therefore, the length lm of the mask pattern 31
Is designed in consideration of the length lr and the diffusion length ld × 2 of the high resistance region 23 serving as the resistance main body. In FIG. 7D, the illustration of the second insulating film 17 is omitted.

Thereafter, the same steps as those described with reference to FIGS. 2 (3) and (4) are performed, and as shown in FIG. 8, the contact holes 1 reaching the respective contact patterns 22 are formed.
8 (18A, 18B) is formed on the second insulating film 17. Further, after forming a wiring forming film inside the contact hole 18 and on the second insulating film 17, the wiring forming film is patterned and the lead electrodes 35A, 35B connected to the contact patterns 22A, 22B are formed into the contact holes 18A, 18B. Formed.

The resistor 26 formed by the manufacturing method according to the second aspect of the present invention has a width wr by transferring the mask pattern 31 so that the high-resistance region 23 serving as the resistor main body does not overlap the region 42 where the mask pattern is to be formed. Is formed in the region 41 where the resistance pattern is to be formed, where the resistance does not change, the resistance value is determined by the length lm of the mask pattern 31. Therefore, it is possible to set the resistance value with high accuracy. Further, the contact pattern 22 is
Therefore, the contact resistance of the contact pattern 22 is reduced.

Also, in the case where the resistor is formed by the manufacturing method of the second invention, similarly to the manufacturing method of the first invention, when the mask pattern 31 is formed, the resistance pattern forming region 41 is formed. As long as the length ls where the contact pattern forming area 42 is exposed is set to be larger than the misalignment amount b, the mask pattern 3
Variations in resistance due to misalignment of the photomask during patterning 1 can be suppressed. As a result, a resistor can be formed with high accuracy in a state having a desired resistance value,
For example, it is possible to realize, for example, high precision timing characteristics required for recent semiconductor integrated circuits.

The step of implanting ions into the contact pattern 22 for reducing the contact resistance is not used because the step is also used as the ion implantation for forming a low-resistance region having a low sheet resistance. Further, since a high resistance can be obtained by narrowing the width without increasing the length of the resistor, the resistance element can be miniaturized, and as a result, the area of the resistance element can be reduced.

Further, in the resistor 26 formed by each of the above-described manufacturing methods, the contact pattern 22 serving as a contact portion with the extraction electrodes 35A and 35B is formed with low resistance, so that the contact resistance with the extraction electrodes 35A and 35B is reduced. Variation is reduced. Also, resistance pattern 2
Since the width of the contact pattern 22 is formed wider than the width of 1, the connection between the extraction electrodes 35A and 35B and the contact pattern 22 is facilitated. Therefore, a margin for mask alignment of the lithography technique at the time of electrode formation is secured. Further, since the sheet resistance is increased by lowering the impurity concentration in the resistance film 15 forming the resistance pattern 21, a high resistance value can be obtained.
Therefore, there is no need to increase the length of the high-resistance region 24 serving as the resistance main body to obtain a high resistance, so that the area of the resistance element does not increase in order to form the high resistance.
Therefore, the resistance element in the semiconductor integrated circuit can be miniaturized.

[0049]

As described above, according to the first aspect of the present invention, since the mask pattern covering the resistor pattern is formed shorter than the length of the resistor pattern, it is necessary to provide an interval between the mask pattern and the contact pattern. it can. Since impurity doping is performed using such a mask pattern as a mask, high-concentration impurity regions can be formed on both sides of the resistance pattern. After that, the diffusion region formed when the impurity is diffused from the high-concentration impurity region to the low-concentration impurity region covered by the mask pattern is formed only in the resistance pattern having a certain width, and is wider than the resistance pattern. No contact pattern is formed. Therefore, as long as the distance between the mask pattern and the contact pattern is set to be larger than the mask misalignment,
No diffusion region is formed in the contact pattern without being affected by mask misalignment.

According to the second aspect of the present invention, the impurity doping is performed using the mask pattern having a length shorter than the interval between the regions where the contact patterns are to be formed, which are wider than the resistance pattern, so that the resistance pattern is formed. High-concentration impurity regions can be formed at both ends of the planned region. After patterning the resistive film, the diffusion region formed when the impurity diffuses from the high-concentration impurity region to the low-concentration impurity region covered with the mask pattern is limited to a resistance pattern having a certain width. It is formed and is not formed in the contact pattern wider than the resistance pattern. Therefore, as long as the gap between the mask pattern and the region where the contact pattern is to be formed is provided to be larger than the mask misalignment, the mask misalignment is not affected and no diffusion region is formed in the contact pattern.

Therefore, in each invention, the area of the diffusion region and the area of the low resistance region are formed to be equal to each other with the high resistance portion serving as the resistance main body formed by the low concentration impurity region covered by the mask pattern interposed therebetween. As a result, a resistor having a predetermined resistance value can be formed with high accuracy. Also,
Since a high resistance is obtained by narrowing the width without increasing the resistance pattern, miniaturization of the element of the semiconductor integrated circuit and reduction of the element area can be realized.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram (part 1) of an embodiment according to the first invention.

FIG. 2 is a manufacturing process diagram (part 2) of the embodiment according to the first invention;

FIG. 3 is a layout diagram of resistors formed by the manufacturing method of the first invention.

FIG. 4 is an explanatory diagram of a resistor when no misalignment occurs in the manufacturing method of the first invention.

FIG. 5 is an explanatory diagram of a resistor when misalignment occurs in the manufacturing method of the first invention.

FIG. 6 is a manufacturing process diagram (part 1) of the embodiment according to the second invention;

FIG. 7 is a manufacturing process diagram (part 2) of the embodiment according to the second invention.

FIG. 8 is a manufacturing step diagram (part 3) of the embodiment according to the second invention;

FIG. 9 is an explanatory diagram of a normal polycrystalline silicon resistor according to the related art.

FIG. 10 is an explanatory diagram of a conventional dog-bone type polycrystalline silicon resistor.

FIG. 11 is a manufacturing process diagram of a conventional dog-bone type polycrystalline silicon resistor.

FIG. 12 is an explanatory diagram of a problem related to the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Base 15 Resistance film 21 Resistance pattern 22 Contact pattern 26 Resistance 31 Mask pattern

Claims (8)

[Claims] A resistive film formed on a substrate is patterned to form a resistive pattern having a predetermined width and length, and a resistive pattern that is continuous with both ends of the resistive pattern and is wider than the resistive pattern. Forming a contact pattern having a contact pattern, and covering the resistor pattern with a mask pattern, and then performing an impurity doping using the mask pattern as a mask. A method of manufacturing a resistor, wherein the resistor has a length shorter than an interval between patterns and a width wider than a width of the resistor pattern. 2. The method of manufacturing a resistor according to claim 1, wherein a distance between the mask pattern and each of the contact patterns is greater than a mask misalignment amount generated when the mask pattern is formed. A method for manufacturing a resistor. 3. The method of manufacturing a resistor according to claim 1, wherein the impurity doping is set to a dose such that the contact pattern has a higher concentration than the resistance pattern. . 4. The method of manufacturing a resistor according to claim 2, wherein the impurity doping is set to a dose such that the contact pattern has a higher concentration than the resistance pattern. . 5. After forming a resistive film on a substrate, a mask pattern is formed so as to cover a portion of the resistive film where a resistive pattern is to be formed, and the resistive film is formed using the mask pattern as a mask. Doping an impurity into the resist pattern, removing the mask pattern, forming a resistor pattern having a predetermined width and length using a resistive film in a region where the resistive pattern is to be formed, and forming a region doped with the impurity. Forming a contact pattern having a portion that is continuous to both ends of the resistance pattern and has a width greater than the width of the resistance pattern using the resistance film. The pattern has a length shorter than the interval between the contact patterns formed wider than the resistance pattern, and A method of manufacturing a resistance characterized by having a width greater than the width of the over down. 6. The method of manufacturing a resistor according to claim 5, wherein a difference between the mask pattern and the wide portion of each of the contact patterns is determined by a mask misalignment amount generated when the mask pattern is formed. A method for manufacturing a resistor, wherein a large interval is provided. 7. The method of manufacturing a resistor according to claim 5, wherein in the impurity doping, a dose is set so that the contact pattern has a higher concentration than the resistance pattern. . 8. The method of manufacturing a resistor according to claim 6, wherein the impurity doping is set to a dose such that the contact pattern has a higher concentration than the resistance pattern. .