JPH10171549A - Pll clock driver device and lsi device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily perform highly accurate clock skewness adjustment by making a skewness adjustment circuit compare the phases of clock signals outputted from a clock driver with the clock signals for skewness adjustment inputted from the outside and set a required value to a control register. SOLUTION: When the clock signals outputted from the clock driver 9 and the clock signals 103 for the skewness adjustment from the outside are inputted, the skewness adjustment circuit 8 compares the phases of the inputted clock signals from the clock driver 9 and the clock signals 103 for the skewness adjustment from the outside and sets the required value to the control register 6. Then, based on the set required value, a PLL circuit 7 adjusts the phase of the clock signals 100 inputted from the outside and outputs the clock signals. Thus, at the time of a system operation, the clock phase is automatically adjusted and the highly accurate clock skewness adjustment is easily performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL clock driver device and an LSI device, and more particularly, to a PLL clock driver device and an L device in a computer system.
A PLL clock driver device which can be applied to a system for adjusting the clock skew of an SI device, and in particular, which can automatically adjust a clock phase during system operation and easily perform high-accuracy clock skew adjustment; It relates to an LSI device.

[0002]

2. Description of the Related Art In a computer system, when a plurality of LSI devices are used in clock synchronization, if the clock phases of the LSI devices do not match, data cannot be exchanged between the LSI devices stably. Therefore, in a conventional computer system, when a plurality of LSI devices are used in clock synchronization, the clock skew is adjusted by adjusting the length of signal lines at the stage of designing a board in order to match the phases of the clocks of the LSI devices. Is going. Hereinafter, a specific description will be given with reference to the drawings.

FIG. 15 is a block diagram showing a board image using a conventional PLL clock driver and LSI device. Each of the PLL clock drivers 80 to 82 includes a plurality of clock outputs and one feedback clock input. In order to match the phases of the clock inputs of the LSI device 83 and the LSI device 84, the delay times of the clock signal 182, the clock signal 183, and the feedback clock signal 186 are made equal on the board.

In FIG. 15, the clock signal 180 and the clock signal 181 have the same delay time, the clock signal 182 and the clock signal 183 have the same delay time as the feedback clock signal 186, and the clock signal 184 and the clock signal 185 have the same delay time. And the delay time of the feedback clock signal 187.
Thereby, the phases of the clock inputs in the LSI devices 83 to 86 can be matched, so that the clock skew can be reduced.

[0005]

In a conventional PLL clock driver device and LSI device having the above-described configuration,
The adjustment of the clock skew is not taken into consideration during the operation of the system, and the adjustment of the clock phase is performed based on the length of the signal line and the like at the stage of board design. For this reason, since the clock driver itself does not have a function of adjusting the clock phase, the clock phase cannot be adjusted during the operation of the system, and there has been a problem that it is difficult to perform highly accurate clock skew adjustment. In particular, when a clock signal line drawn from a clock driver straddles between layers of a board or is connected via a connector, the impedance differs depending on the material, and the impedance must be accurately obtained for each different material. It is troublesome to accurately determine the delay time of the clock signal.

Further, conventionally, there has been a problem that it is not easy to forcibly change the phase of a clock to operate the system in order to evaluate an operation margin as a necessary system.

Accordingly, the present invention provides a PLL that can easily adjust clock skew with high accuracy by adjusting the clock phase during system operation, and can easily change the phase of the clock easily. It is an object to obtain a clock driver device and an LSI device.

[0008]

According to the first aspect of the present invention,
In a PLL clock driver device having a plurality of clock control blocks that generate a clock based on a clock signal input from the outside, the clock control block includes a control register and an external input based on a value set in the control register. A PLL circuit that adjusts the phase of a clock signal to be output and outputs a clock signal, and a clock that inputs a clock signal output from the PLL circuit, outputs two clock signals to the outside, and outputs a clock signal to the inside A driver and a skew adjustment circuit for comparing the phases of a clock signal output from a clock driver and a skew adjustment clock signal input from the outside and setting the skew adjustment circuit in a control register.

According to a second aspect of the present invention, there is provided a clock signal for connecting one of two clock signals output from the clock driver and inputting one of the first clock signals to another circuit device. Line, connected to the clock driver and skew adjustment circuit,
Of the two clock signals output in parallel with the clock signal line on the board and output from the clock driver,
A skew adjustment clock signal line for inputting the other second clock signal to the skew adjustment circuit as a skew adjustment clock signal.

According to a third aspect of the present invention, the control register comprises:
A value required for adjusting the phase of the clock signal input to the PLL circuit is set from an external circuit.

According to a fourth aspect of the present invention, the control register comprises:
It is characterized by comprising a non-volatile memory.

According to a fifth aspect of the present invention, there is provided a feedback circuit for outputting a skew adjustment signal input from the outside to the outside.

According to a sixth aspect of the present invention, a selector for selecting whether to output the clock signal output from the clock driver to the skew adjustment circuit or to use the ground output as the skew adjustment clock signal is provided. It is assumed that.

According to a seventh aspect of the present invention, a control register includes:
A PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in the control register and outputs the clock signal, and a clock that outputs the clock signal input from the outside as a skew adjustment clock signal An output circuit; and a skew adjustment circuit that compares a phase of a clock signal output from the PLL circuit with a phase of a skew adjustment clock signal output from the clock output circuit and sets the phase in a control register. .

According to an eighth aspect of the present invention, a clock signal line is connected to the PLL circuit for inputting an external clock signal to the PLL circuit and the clock output circuit, and is connected to the clock output circuit and the skew adjustment circuit. And a skew adjustment clock signal line wired in parallel with the clock signal line on the substrate and for inputting a skew adjustment clock signal output from the clock output circuit to the skew adjustment circuit. Things.

According to a ninth aspect of the present invention, the control register comprises:
A value required for adjusting the phase of the clock signal input to the PLL circuit is set from an external circuit.

According to a tenth aspect of the present invention, the control register comprises a nonvolatile memory.

An invention according to claim 11 is a PLL control register, and a PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in the PLL control register and outputs a clock signal; A parameter setting register in which parameters for skew adjustment are set;
An automatic swing circuit for automatically changing the skew based on the set skew adjustment parameters and setting the skew in the PLL control register.

According to a twelfth aspect of the present invention, there is provided a PLL control register, a PLL circuit for adjusting a phase of a clock signal input from the outside based on a value set in the PLL control register and outputting a clock signal, A parameter setting register in which parameters for skew adjustment are set;
An automatic swing circuit for automatically changing the skew based on the set skew adjustment parameters and setting the skew in the PLL control register.

According to a thirteenth aspect of the present invention, there is provided a control register for forcibly changing a phase of a clock to set a value for safely operating within a range in which the system operates normally, and a control register for setting a value set in the control register. And a PLL circuit that adjusts the phase of the clock signal input from the outside based on the output and outputs the clock signal.

According to a fourteenth aspect of the present invention, a control register for forcibly changing a phase of a clock to set a value that safely operates within a range in which the system normally operates, and a value set in the control register. And a PLL circuit that adjusts the phase of the clock signal input from the outside based on the output and outputs the clock signal.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. FIG. 1 shows a PL according to the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an L clock driver device. In FIG. 1, reference numeral 1 denotes a PLL clock driver. The PLL clock driver 1 includes a plurality of clock control blocks 2 to 4 that generate a clock based on a clock signal input from the outside.

FIG. 2 is a block diagram showing the configuration of the clock control block shown in FIG. 2, a clock control block 2-4 includes a control register 6 and a PLL circuit 7 which adjusts the phase of a clock signal 100 input from the outside based on a value set in the control register 6 and outputs a clock signal. And a clock signal output from the PLL circuit 7 and input the two clock signals 101 and 1 to the outside.
02 and outputs the clock signal to the inside, and compares the phase of the clock signal output from the clock driver 9 with the phase of the skew adjustment signal 103 input from the outside, and sets it in the control register 6. And a skew adjustment circuit 8.

First, the PLL circuit 7 adjusts the phase of the clock signal 100 input from the outside based on the value set in the control register 6 and outputs the clock signal. The clock driver 9 receives a clock signal output from the PLL circuit 7 and outputs two clock signals 101,
102 and a clock signal to the skew adjustment circuit 8.

When the clock signal output from the clock driver 9 and the external skew adjustment clock signal 103 are input, the skew adjustment circuit 8 inputs the clock signal from the clock driver 9 and the external skew. The phase of the adjustment clock signal 103 is compared and set in the control register 6. Thereby, the PLL circuit 7
Adjusts the phase of the clock signal 100 input from the outside based on the value set in the control register 6 and outputs the clock signal.

FIG. 3 is a diagram showing a board image using the PLL clock driver device and the LSI device shown in FIGS. In FIG. 3, 10 to 12 indicate P shown in FIGS.
PLL clock driver devices 13 and 14 have the same configuration as the LL clock driver device 1. LSI devices 13 and 14 are connected to the PLL clock driver device 11.
LSI devices 5 and 16 are connected to the PLL clock driver device 12.

PLL clock driver devices 10 to 12
Are hierarchically connected to each other and use an LSI using a clock generated by the PLL clock driver devices 10 to 12
Devices 13 to 16 are connected. From the PLL clock driver device 10 to the PLL clock driver devices 11, 1
2 are connected by one clock signal line 105, 106, and from the PLL clock driver device 11 to the LSI devices 13, 14, one clock signal line 107,
108, the PLL clock driver device 12 to the LSI devices 15 and 16 are connected by one clock signal line 109 and 110, respectively.

The clock signal lines 105 to 110 are connected to the clock drivers 9 constituting the clock driver devices 10 to 12, and one of the two clock signals 101 and 102 output from the clock driver 9 Is a clock signal line for inputting to the other circuit device.

Separately, the skew adjustment clock signal lines 111 to 116 are connected as shown in FIGS.
The skew adjusting clock signal lines 111 to 116 are wired in parallel with the respective clock signal lines 105 to 110 on the substrate and are connected in a feedback manner. The skew adjustment clock signal lines 111 to 116 are connected to the clock driver 9 and the skew adjustment circuit 8, are connected in parallel with the clock signal lines 105 to 110 on the board, and are two output from the clock driver 9. Clock signals 101, 10
2 is a skew adjustment clock signal line for inputting the other clock signal 101 to the skew adjustment circuit 8 as the skew adjustment clock signal 103.

Skew adjusting clock signal lines 111 to 1
Numeral 16 is wired in parallel with each of the clock signal lines 105 to 110 on the substrate and connected in a feedback manner. Therefore, the skew adjustment clock signal lines 111 to 116 are twice as long as the clock signal lines 105 to 110, and the delay time is twice as long as the clock signal lines 105 to 110. The skew adjustment clock signal lines 111 to 116 and the clock signal lines 105 to 110 may extend between layers of the substrate,
The effect of passing through a connector or the like is the same as described above.

Each of the PLL clock driver devices 10 to 12
In the skew adjustment circuit 8, the delay time of the skew adjustment clock signal lines 111 to 116 can be determined from the phase difference between the skew adjustment clock signals 111 to 116, and the skew adjustment clock signal lines 111 to 11
The half of the delay time of the clock signal line 105
The delay time is about 110. The control register 6 sets the PLL circuit 6 so as to output the phase earlier by the delay time of the clock signal lines 105 to 110. As a result, the phases at the clock input pins of the LSI devices 13 to 16 become the same, and hierarchical connection of clocks becomes possible.

As described above, in the present embodiment, the PLL clock driver devices 10 to 12 having the plurality of clock control blocks 2 to 4 for generating the clock signals 101 and 102 based on the clock signal 100 input from the outside.
And a PLL circuit 7 that adjusts the phase of the clock signal 100 input from the outside based on the value set in the control register 6 and outputs the clock signal, A clock driver 9 that receives a clock signal output from the PLL circuit 7, outputs two clock signals 101 and 102 to the outside, and outputs a clock signal to the skew adjustment circuit 8, and a clock output from the clock driver 9. Signal and skew adjustment clock signal 10 input from outside
The skew adjustment circuit 8 compares the three phases and sets the skew in the control register 6. Therefore, the PLL clock driver devices 10 to 12 themselves can have a function of adjusting the clock phase. Therefore, the clock phase can be automatically adjusted during the operation of the system, so that highly accurate clock skew adjustment can be easily performed. In addition, even when the PLL clock driver devices 10 to 12 are used hierarchically, the clock phase can be automatically adjusted during system operation.

In the present embodiment, one of the two clock signals 101 and 102 output from the clock driver 9 is connected to the clock driver 9 and one of the two clock signals 102 is input to another circuit device. Clock signal lines 105 to 110, and two clock signals which are connected to the clock driver 9 and the skew adjustment circuit 8, are wired on the substrate in parallel with the clock signal lines 105 to 110, and are output from the clock driver 9. 10
The skew adjustment clock signal lines 111 to 116 for inputting the other clock signal to the skew adjustment circuit 8 as the skew adjustment clock signal among the skew adjustment clock signals 111 to 116 are provided. The delay time of the skew adjustment clock signal lines 111 to 116 can be obtained from the phase difference of 116, and the delay time of the clock signal lines 105 to 110 can be easily obtained from the obtained delay time. Therefore, by setting the PLL circuit 6 by the control register 6 so as to output the phase faster by the delay time of the clock signal lines 105 to 110, the phases at the clock inputs of the LSI devices 13 to 16 are made the same. be able to.

In this embodiment, the control register 6
Has been described from the inside by the skew adjustment circuit 8, but the present invention is not limited to this, and as shown in FIG.
The value required to adjust the phase of the clock signal input to the PLL circuit 7 may be set from an external circuit 118 such as a JTAG circuit. In this case, since the control register 6 can be externally controlled, the phase of the PLL circuit 7 can be forcibly adjusted regardless of the output of the skew adjustment circuit 8. Therefore, an operation margin as a necessary system can be easily evaluated.
Further, it is preferable that the control register 6 is configured using a nonvolatile memory. In this case, it is not necessary to adjust the phase of the PLL circuit 7 each time the power is turned on.

Embodiment 2 This embodiment relates to claim 5
Only the features according to the described invention will be described. In the present embodiment, in the PLL clock driver device according to the first embodiment shown in FIGS. 1 and 2, a feedback circuit that outputs a skew adjustment signal input from the outside to the outside is added to the PLL clock driver device. Make up. Hereinafter, a specific description will be given with reference to the drawings.

FIG. 5 shows a PLL according to a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a clock driver device.
In FIG. 5, the same reference numerals as those in FIGS. 1 and 2 denote the same or corresponding parts. is there. The influence of the delay of the package of the PLL clock driver device 17 and the input driver is adjusted in advance in the feedback circuit 19. By arranging the feedback circuit 19, two skew adjustment pins are added to the input pin side of the PLL clock driver device 17. Note that the feedback circuit 19 is a PLL clock driver 1 outside the clock control blocks 2 to 4.
7, but may be arranged in the clock control blocks 2 to 4.

FIG. 6 is a diagram showing a board image using the PLL clock driver device and the LSI device shown in FIG. In FIG. 6, reference numerals 20 to 22 denote PLL clock driver devices, and PLL clock driver devices 20 to 22.
Of the PLL clock driver devices 21 and 22,
Like the PLL clock driver device 17 shown in FIG. 5, a feedback circuit 19 is provided. 23 and 24 are LSI devices connected to the PLL clock driver device 21, and 25 and 26 are PLL clock driver devices 2
2 is an LSI device connected thereto.

PLL clock driver devices 20 to 22
Are hierarchically connected to each other and use LSIs that use clocks generated by PLL clock driver devices 20 to 22
Devices 23 to 26 are connected. From the PLL clock driver device 20 to the PLL clock driver devices 21 and
2 are connected by one clock signal line 121, 122, and from the PLL clock driver device 21 to the LSI devices 23, 24, one clock signal line 123,
The clock signal lines 125 and 126 connect the PLL clock driver device 22 to the LSI devices 25 and 26, respectively.

Two skew adjustment clock signal lines 12
1 and 128 correspond to the PLL clock driver device 20 and the PL
The L clock driver device 21 is connected and wired in parallel with the clock signal line 121 on the board. The two skew adjustment clock signal lines 129 and 130 connect the PLL clock driver device 20 and the PLL clock driver device 22, and are wired in parallel with the clock signal line 122 on the board.

The clock signal line 123 of the PLL clock driver device 21 is connected to the LSI device 23,
The skew adjustment clock signal line 131 of the clock driver device 21 is wired in parallel with the clock signal line 123 on the substrate and is connected in a feedback manner. The clock signal line 124 of the PLL clock driver device 21 is connected to the LSI device 24, and the skew adjustment clock signal line 132 of the PLL clock driver device 21 is wired in parallel with the clock signal line 124 on the board and connected in a feedback manner. .

The clock signal line 125 of the PLL clock driver device 22 is connected to the LSI device 25,
The skew adjustment clock signal line 133 of the clock driver device 22 is wired in parallel with the clock signal line 125 on the substrate and is connected in a feedback manner. The clock signal line 126 of the PLL clock driver device 22 is connected to the LSI device 26, and the skew adjustment clock signal line 134 of the PLL clock driver device 22 is wired in parallel with the clock signal line 126 on the substrate and is connected in a feedback manner. .

The feedback circuit 19 of the PLL clock driver 21 is connected to the skew adjustment clock signal line 1.
The skew adjustment clock signal 119 input from the outside via the skew adjustment clock signal line 128
Output to the outside through As a result, the skew adjustment clock signal 119 output from the PLL clock driver device 20 is once transmitted to the PLL clock driver device 21.
, And is fed back to the PLL clock driver device 20.

The feedback circuit 19 of the PLL clock driver device 22 is connected to the skew adjustment clock signal line 1.
The skew adjustment clock signal 119 input from the outside via the skew adjustment clock signal line 130
Output to the outside through As a result, the skew adjustment clock signal 119 output from the PLL clock driver device 20 is once transmitted to the PLL clock driver device 22.
, And is fed back to the PLL clock driver device 20.

As described above, in the present embodiment, the skew adjustment signal 1 input from the external PLL clock driver device 20 is supplied to the PLL clock driver devices 21 and 22.
9 is provided by providing a feedback circuit 19 for outputting the clock signal 9 to an external PLL clock driver device 20.
The skew adjustment signal 19 output from the L clock driver device 20 is directly converted into a skew adjustment signal P
Instead of feeding back to the LL clock driver devices, the PLL clock driver devices 21 and
2 can be fed back to the PLL clock driver device 20 after passing through the feedback circuit 19. Therefore, the PLL clock driver devices 21 and 22
By adjusting the effects of the delay of the package and the input driver in the feedback circuit 19 in advance, it is possible to perform more accurate skew adjustment than in the case where the feedback circuit 19 of the first embodiment is not arranged. .

Embodiment 3 This embodiment relates to claim 6
Only the features according to the described invention will be described. In the present embodiment, in the PLL clock driver device of the first embodiment shown in FIGS. 1 and 2, the clock signal output from the clock driver in the PLL clock driver device is output to the skew adjustment circuit as a skew adjustment clock signal. Or a selector for selecting whether to output to ground (GND). Hereinafter, a specific description will be given with reference to the drawings.

FIG. 7 shows a PLL according to a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a clock control block in the clock driver device. In FIG. 7, the same reference numerals as those in FIG. 2 denote the same or corresponding parts, and 29 denotes a clock signal 101 output from the clock driver 9 output to the skew adjustment circuit 8 as a skew adjustment clock signal 103 or output to GND. This is a selector for selecting whether or not to perform.

In the PLL clock driver device of the present embodiment, the selector 29 outputs the clock signal 101 output from the clock driver 9 to the skew adjustment circuit 8 as a skew adjustment clock signal 103 or to GND. Or choose. This selector 2
The selection of the output 9 is configured so that it can be accessed from the internal control register 6 or from outside (not shown).

With this configuration, when a substrate similar to that of FIG. 3 of the first embodiment is configured, the selector 29 converts the clock signal 101 input from the clock driver 9 into a skew adjustment signal during skew adjustment. The skew adjustment signal is output to the skew adjustment circuit 8 as a signal 103, and the selector 29 outputs the skew adjustment signal 103 to the GND output when the skew adjustment is completed.

The skew adjustment clock signal line for sending the skew adjustment clock signal 103 output from the selector 29 to the skew adjustment circuit 8 is connected to the clock signal 1 output from the clock driver 9 as in FIG. 3 of the first embodiment.
02 is fed back and connected in parallel on the board and a clock signal line for sending the signal 02 to an external circuit.

As described above, in the present embodiment, after the skew adjustment is completed and the skew adjustment clock signal line is wired in parallel with the clock signal line on the substrate, the skew adjustment clock signal line is set to the GND output. With such a configuration, the influence of clock noise can be reduced.

Embodiment 4 FIG. FIG. 8 is a block diagram showing a configuration of a circuit block in an LSI device according to a fourth embodiment of the present invention. In FIG. 8, reference numeral 30 denotes a circuit block.
And adjusting the phase of the clock signal 138 input from the outside based on the value set in the control register 31 to 2
PLL circuit 32 that outputs two clock signals 141 and 150, a clock output circuit 33 that outputs a clock signal 138 input from the outside as a skew adjustment clock signal 139, and a clock signal 141 output from the PLL circuit 32 and a clock. A skew adjustment circuit 34 for comparing the phase of the skew adjustment clock signal 139 output from the output circuit 33 and setting the same in the control register 31.

The PLL circuit 32 adjusts the phase of the clock signal 138 input from the outside based on the value set in the control register 31, outputs the clock signal 141 to the skew adjustment circuit 34, and As the clock signal 150. At the same time, the clock output circuit 33 outputs the clock signal 138 input from the outside to the skew adjustment circuit 34 as the skew adjustment clock signal 139.

The skew adjusting circuit 34 is a PLL circuit 32
Clock signal 141 output from the clock output circuit 33 and the skew adjustment clock signal 139 output from the clock output circuit 33
Are compared and set in the control register 31. Thus, the PLL circuit 32 outputs the clock signal 13 input from the outside based on the value set in the control register 31.
8 is adjusted to output clock signals 141 and 150.

FIG. 9 shows an L having the circuit block shown in FIG.
FIG. 3 is a block diagram showing a board image using an SI device and a clock driver. In FIG. 9, reference numeral 35 denotes a clock driver having no skew adjustment function.
Reference numeral 8 denotes an LSI device having the circuit block 30 shown in FIG. The clock signal 138 shown in FIG. 8 is output from the clock driver 35 and input to the LSI devices 36 to 38, respectively.

The LSI devices 36 to 38 receive the clock signal 1
38 is connected to a clock driver 35 that outputs the clock signal 38. The clock driver 35 and the LSI devices 36 to 38 are connected by one clock signal line 142 to 144, respectively. The clock signal lines 142 to 144 are connected to the LSI device 3
PLL circuit 32 of circuit block 30 constituting 6 to 38
And a signal line connected to the clock output circuit 33 and the clock driver 35 for inputting the clock signal 138 output from the clock driver 35 to the clock output circuit 33 and the PLL circuit 32 of the LSI devices 36 to 38.

Separately, the skew adjustment clock signal lines 145 to 147 are connected as shown in FIGS.
The skew adjustment clock signal lines 145 to 147 are wired in parallel with the respective clock signal lines 142 to 144 on the substrate and are connected in a feedback manner. The skew adjustment clock signal lines 145 to 147 are connected to the clock output circuit 33 and the skew adjustment circuit 34, are connected in parallel with the clock signal lines 142 to 144 on the board, and are output from the clock output circuit 33. This is a signal line for inputting the skew adjustment clock signal 139 to the skew adjustment circuit 34.

Skew adjustment clock signal lines 145-1
47 is connected in parallel to each of the clock signal lines 142 to 144 on the substrate and connected in a feedback manner. Therefore, the skew adjustment clock signal lines 145 to 147 are twice as long as the clock signal lines 142 to 144, and the delay time is twice as long as the clock signal lines 142 to 144. It should be noted that the skew adjustment clock signal lines 145 to 147 and the clock signal lines 142 to 144 may extend between layers of the substrate,
The effect of passing through a connector or the like is the same as described above.

In the skew adjustment circuit 34 in each of the LSI devices 36 to 38, the skew adjustment clock signal 13
9, the skew adjustment clock signal line 1
The delay time of the clock signal lines 142 to 144 is half the delay time of the skew adjustment clock signal lines 145 to 147. The control register 31 includes clock signal lines 142 to
P so that the phase is output earlier by the delay time of 144
The LL circuit 32 is set. Thereby, each LSI device 3
The phases of the clocks inside 6 to 38 are the same.

As described above, in this embodiment, the circuit blocks 30 of the LSI devices 36 to 38 are
And a clock signal 13 input from an external clock driver 35 based on a value set in the control register 31.
And a clock output circuit that outputs a clock signal 141 and a clock signal 138 input from an external clock driver 35 to the skew adjustment circuit 34 as a skew adjustment clock signal 139. 33 and a skew adjustment circuit 34 that compares the phase of the clock signal 141 output from the PLL circuit 32 with the phase of the skew adjustment clock signal output from the clock output circuit 33 and sets the phase in the control register 31. , The LSI devices 36 to 38 themselves can have a function of adjusting the clock phase. Therefore, the clock phase can be automatically adjusted during the operation of the system, so that highly accurate clock skew adjustment can be easily performed.

In this embodiment, the PLL circuit 32
The clock signal 138 from the external clock driver 35 is connected to the PLL circuit 32 and the clock output circuit 33.
Clock signal lines 142 to 144 for input to the clock output circuit 33 and the skew adjustment circuit 34, and are wired on the board in parallel with the clock signal lines 142 to 144, and output from the clock output circuit 33. And the skew adjustment clock signal line 139 for inputting the skew adjustment clock signal 139 to the skew adjustment circuit 34. To 147 are obtained, and the clock signal lines 142 to 144 are calculated from the obtained delay times.
Can be easily obtained. Therefore, the clock phases inside the LSI devices 36 to 38 can be made the same.

In this embodiment, the control register 3
1 has been described from the inside by the skew adjustment circuit 34, but the present invention is not limited to this, and the control register 31 is input to the PLL circuit 32 as shown in FIG. The value required to adjust the phase of the clock signal to be applied may be set from an external circuit 120 such as a JTAG circuit. in this case,
Since the control register 31 can be controlled from the outside, regardless of the output of the skew adjustment circuit 34, P
The phase of the LL circuit 32 can be adjusted. Therefore, an operation margin as a necessary system can be easily evaluated. Further, it is preferable that the control register 31 is configured using a nonvolatile memory. In this case, it is not necessary to adjust the phase of the PLL circuit 32 each time the power is turned on.

Embodiment 5 FIG. 11 is a block diagram showing a configuration of a circuit block in an LSI device according to a fifth embodiment of the present invention. In FIG. 11, reference numeral 39 denotes a circuit block. The circuit block 39 adjusts the phase of a clock signal 149 input from the outside based on a PLL control register 41 and a value set in the PLL control register 41. PLL circuit 40 for outputting clock signal
And a parameter setting register 43 in which parameters for skew adjustment are set; and an automatic swing for automatically changing the skew based on the skew adjustment parameters set in the parameter setting register 43 and setting the skew in the PLL control register 41. And a circuit 42.

First, in the parameter setting register 43,
Skew adjustment parameters such as the phase and time range to be changed are set by a JTAG circuit or the like. The auto-swing circuit 42 automatically changes the skew in accordance with the parameter set in the parameter setting
Set in the L control register 41. The PLL circuit 40
In accordance with the value set in the LL control register 41, the phase of the clock signal 149 input from the outside is changed and output.

FIG. 12 is a block diagram showing a board image using the LSI device and the clock driver shown in FIG. In FIG. 12, reference numeral 45 denotes a clock driver having no skew adjustment function, and reference numerals 46 and 47 denote LSI devices connected to the clock driver 45 via clock signal lines 151 and 152. The circuit block 39 is provided in the LSI device 46 and is not provided in the LSI device 47.

For example, the phase of the clock in the LSI device 46 is changed by the automatic swing circuit 42 so that the clock phase is forcibly shifted from the LSI device 47. The operating margin of the system is evaluated by changing the parameters and confirming how much the system operates normally.

As described above, in the present embodiment, the LSI device 46 is controlled by the PLL control register 41 and the clock signal 149 input from the external clock driver 45 based on the value set in the PLL control register 41. A PLL circuit 40 that adjusts the phase and outputs a clock signal, a parameter setting register 43 in which parameters for skew adjustment are set, and a skew is automatically set based on the skew adjustment parameters set in the parameter setting register 43. And an auto-swing circuit 42 that sets the PLL control register 41 by changing
The SI device 46 itself can have a function of adjusting the clock phase. Therefore, the clock phase can be automatically adjusted during the operation of the system, so that highly accurate clock skew adjustment can be easily performed.

In the above embodiment, the LSI device 4
6, a PLL control register 41,
A PLL circuit 40 that adjusts the phase of a clock signal 149 input from the outside and outputs a clock signal based on a value set in the PLL control register 41, and a parameter setting register 43 in which parameters for skew adjustment are set. A description has been given of a case in which the skew is automatically changed based on the skew adjustment parameter set in the parameter setting register 43 and the auto-swing circuit 42 is set in the PLL control register 41. May be provided with a circuit block 39 similar to that of the fifth embodiment in the PLL clock driver device. That is, a circuit block of the PLL clock driver device includes a PLL control register, a PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in the PLL control register, and outputs a clock signal, It is composed of a parameter setting register in which skew adjustment parameters are set, and an auto-swing circuit that automatically changes the skew based on the skew adjustment parameters set in the parameter setting register and sets the skew in the PLL control register. . In this case, since the PLL clock driver device itself can be provided with a function of adjusting the clock phase, the clock phase can be automatically adjusted during the system operation, and the highly accurate clock skew adjustment can be easily performed. be able to.

Embodiment 6 FIG. FIG. 13 is a diagram showing a configuration of a circuit block in an LSI device according to a sixth embodiment of the present invention. In FIG. 13, reference numeral 48 denotes a circuit block. This circuit block 48 is a control register for forcibly changing the phase of a clock signal and setting a value that operates most safely within a range in which the system normally operates. 4
9 and a PLL circuit 50 that adjusts the phase of the clock signal 161 input from the outside and outputs the clock signal.

FIG. 14 is a block diagram showing a configuration of a system using the LSI device and the clock driver shown in FIG. In FIG. 14, reference numerals 58 to 60 denote separated substrates. A clock driver 61 is disposed on the substrate 58, an LSI device 62 is disposed on the substrate 59, and an LSI device 63 is disposed on the substrate 60. Is done. The clock driver 58 and the LSI device 62 connect the clock signal line 163
, And the clock driver 58 and the LSI device 63 are connected via a clock signal line 164. L
The SI devices 62 and 63 include the circuit block 4 shown in FIG.
8 is built-in.

The clock driver 58 and each LSI device 6
2 and 63 are connected by clock signal lines 163 and 164, respectively. However, in this example, since there is no connection of the skew adjustment clock signal line, the skew cannot be adjusted by the method described in the fourth embodiment. Therefore, when setting up the system for the first time, a skew is externally measured using a measuring instrument such as an oscilloscope and set in an internal register. Usually, it operates as it is.

Next, for example, when the substrate 60 is replaced with another one for the convenience of the system, the skew is shifted, so it is necessary to readjust the skew again. In the present embodiment, the skew is not adjusted externally, but the substrate 60 is adjusted.
In the LSI device 63 to be replaced, the range in which the system operates normally is obtained by forcibly changing the phase of the clock signal using S / W or the like, and the safest operation is performed within the normal operating range. The value is set in the control register 49 in the LSI device 63. The PLL circuit 50 adjusts the phase of the clock signal 161 input from the clock driver 58 through the clock signal line 164 based on the value set in the control register 49, and outputs a clock signal.

As described above, in the present embodiment, the value that safely operates the circuit block 48 of the LSI device 63 within the range in which the phase of the clock signal is forcibly changed and the system normally operates is set. A control register 49 and a PLL circuit 50 that adjusts the phase of a clock signal 161 input from an external clock driver 61 and outputs a clock signal based on a value set in the control register 49.
Even if the skew of the LSI device 63 is shifted by replacing the substrate 60 with another one, the skew of the LSI device 63 is measured by an external oscilloscope or the like without adjusting the skew in the control register. Since the skew of the device 63 can be adjusted, a stable system operation can be realized.

In the above embodiment, the LSI device 6
3 is changed to a control register 49 in which a value that safely operates within a range in which the system operates normally by forcibly changing the phase of the clock signal, and a value set in the control register 49. A case has been described in which the PLL circuit 50 adjusts the phase of the clock signal 161 input from the external clock driver 61 and outputs the clock signal based on the clock signal 161. However, the present invention is applied to a PLL clock driver device. A circuit block 48 similar to that of the sixth embodiment may be provided. That is, the circuit block of the PLL clock driver device is set in the control register in which a value that safely operates within a range in which the system operates normally by forcibly changing the phase of the clock signal is set in the control register. And a PLL circuit that adjusts the phase of the clock signal input from the outside based on the value and outputs the clock signal. In this case, even if the skew of the PLL clock driver device is deviated by replacing the board with another one, the skew of the deviated PLL clock driver device is measured without performing skew adjustment by a control register by measuring each externally with an oscilloscope or the like. Can be adjusted, so that a stable system operation can be realized.

[0074]

According to the first aspect of the present invention, in a PLL clock driver device having a plurality of clock control blocks for generating a clock based on a clock signal input from the outside, the clock control block includes a control register and a control register. A PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in a register and outputs a clock signal, and a clock signal output from the PLL circuit and inputs two clock signals to the outside. A clock driver that outputs a clock signal to a skew adjustment circuit, and a skew adjustment circuit that compares a phase of a clock signal output from the clock driver with a phase of a skew adjustment clock signal input from the outside and sets the phase in a control register And the PLL
The clock driver device itself can have a function of adjusting the clock phase. Therefore, the clock phase can be automatically adjusted during the operation of the system, so that highly accurate clock skew adjustment can be easily performed.

According to the second aspect of the present invention, the second circuit connected to the clock driver and output from the clock driver is used.
A clock signal line for inputting one of the clock signals to another circuit device, a clock driver and a skew adjustment circuit, and wired on the board in parallel with the clock signal line; and A skew adjustment clock signal line for inputting the other clock signal of the two clock signals output from the clock driver to the skew adjustment circuit as a skew adjustment clock signal; The delay time of the skew adjustment clock signal line can be obtained from the signal phase difference, and the delay time of the clock signal line can be easily obtained from the obtained delay time.

According to the third aspect of the present invention, the control register is configured such that a value necessary for adjusting the phase of the clock signal input to the PLL circuit is set from an external circuit, so that the control register is externally provided. , The phase of the PLL circuit can be forcibly adjusted regardless of the output of the skew adjustment circuit.

According to the fourth aspect of the present invention, since the control register is constituted by a nonvolatile memory, it is not necessary to adjust the phase of the PLL circuit every time the power is turned on.

According to the fifth aspect of the present invention, a feedback circuit for outputting a skew adjustment signal input from an external PLL clock driver device to the external PLL clock driver device is arranged in the PLL clock driver device. The skew adjustment signal output from the PLL clock driver device is not fed back to the PLL clock driver device that directly outputs the skew adjustment signal, but is passed through the feedback circuit of the lower PLL clock driver device and then skew adjustment is performed. This signal can be fed back to the PLL clock driver device that outputs the application signal. For this reason, by adjusting the influence of the delay of the package and the input driver of the PLL clock driver device in which the feedback circuit is arranged in advance in the feedback circuit, skew adjustment with higher accuracy than in the case where the feedback circuit is not arranged. It can be performed.

According to a sixth aspect of the present invention, the skew adjustment clock signal line is grounded while the skew adjustment clock signal line is wired in parallel with the clock signal line on the substrate. The effect of clock noise can be reduced.

According to a seventh aspect of the present invention, the LSI device comprises:
A control register, a PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in the control register and outputs the clock signal, and a clock signal for adjusting the skew input from the outside And a skew adjustment circuit that compares the phase of the clock signal output from the PLL circuit with the phase of the skew adjustment clock signal output from the clock output circuit and sets the phase in the control register. Since the function of adjusting the clock phase can be provided in the LSI device itself, the clock phase can be automatically adjusted during the operation of the system, and the clock skew adjustment with high accuracy can be easily performed.

The invention according to claim 8 is connected to a PLL circuit, and is connected to a clock signal line for inputting an external clock signal to the PLL circuit and the clock output circuit, and to the clock output circuit and the skew adjustment circuit. And a skew adjustment clock signal line for wiring the skew adjustment clock signal output from the clock output circuit to the skew adjustment circuit, which is wired in parallel with the clock signal line on the substrate. Accordingly, the delay time of the skew adjustment clock signal line can be obtained from the phase difference of the skew adjustment clock signal, and the delay time of the clock signal line can be easily obtained from the obtained delay time. Therefore, the clock phase inside each LSI device can be made the same.

According to the ninth aspect of the present invention, the control register is configured so that a value necessary for adjusting the phase of the clock signal input to the PLL circuit is set from an external circuit. , The phase of the PLL circuit can be forcibly adjusted regardless of the output of the skew adjustment circuit.

According to the tenth aspect of the present invention, since the control register is constituted by a nonvolatile memory, it is not necessary to adjust the phase of the PLL circuit each time the power is turned on.

According to an eleventh aspect of the present invention, a PLL clock driver device adjusts a phase of a clock signal input from the outside based on a PLL control register and a value set in the PLL control register to convert the clock signal. A PLL circuit to be output, a parameter setting register in which a skew adjustment parameter is set, and an automatic skew that is automatically changed and set in a PLL control register based on the skew adjustment parameter set in the parameter setting register. With the swing circuit, L
Since the SI device itself can be provided with the function of adjusting the clock phase, the clock phase can be automatically adjusted during the operation of the system, and the highly accurate clock skew adjustment can be easily performed.

According to a twelfth aspect of the present invention, an LSI device
A PLL control register, a PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in the PLL control register, and outputs a clock signal, and parameter setting in which parameters for skew adjustment are set The clock phase can be adjusted in the LSI device itself by comprising a register and an auto-swing circuit that automatically changes the skew based on the skew adjustment parameter set in the parameter setting register and sets the skew in the PLL control register. Therefore, the clock phase can be automatically adjusted during system operation, and highly accurate clock skew adjustment can be easily performed.

According to the thirteenth aspect of the present invention, the PLL clock driver device is provided with a control register for forcibly changing a phase of a clock and setting a value for safely operating within a range in which the system operates normally. And a PLL circuit that adjusts the phase of a clock signal input from the outside based on the value set in the clock signal and outputs the clock signal, thereby replacing the board with another PLL clock. Even if the skew of the driver device is shifted, it is possible to adjust the skew of the shifted PLL clock driver device without externally measuring the skew with an oscilloscope or the like and adjusting the skew with the control register.
A stable system operation can be realized.

According to the fourteenth aspect of the present invention, the LSI device is set in the control register for forcibly changing the clock phase and setting a value that safely operates within a range in which the system operates normally. And a PLL circuit that adjusts the phase of a clock signal input from the outside based on the set value and outputs the clock signal, thereby replacing the board with another one and changing the skew of the LSI device. Even if it deviates, without skew adjustment in the control register by measuring each externally with an oscilloscope etc.,
Since the skew of the shifted LSI device can be adjusted, a stable system operation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PLL clock driver device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock control block shown in FIG.

FIG. 3 is a diagram showing a board image using the PLL clock driver device and the LSI device shown in FIGS.

FIG. 4 is a block diagram showing a configuration in which a control register in the control block shown in FIG. 2 is set from an external circuit.

FIG. 5 is a block diagram showing a configuration of a PLL clock driver device according to a second embodiment of the present invention.

FIG. 6 shows the PLL clock driver device shown in FIG.
It is a figure showing the substrate image using the SI device.

FIG. 7 is a block diagram illustrating a configuration of a clock control block in a PLL clock driver device according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a circuit block in an LSI device according to a fourth embodiment of the present invention.

9 is a diagram showing a board image using an LSI device having the circuit block shown in FIG. 8 and a clock driver.

10 is a block diagram showing a configuration in which a control register in the circuit block shown in FIG. 8 is set from an external circuit.

FIG. 11 is a block diagram showing a configuration of a circuit block in an LSI device according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a board image using the LSI device and the clock driver shown in FIG. 11;

FIG. 13 is a block diagram showing a configuration of a circuit block in an LSI device according to a sixth embodiment of the present invention.

14 is a block diagram showing a configuration of a system using the LSI device and the clock driver shown in FIG.

FIG. 15 shows a conventional PLL clock driver device and LS.
It is a block diagram which shows the board | substrate image using I apparatus.

[Explanation of symbols]

1, 10 to 12, 17, 20 to 22 PLL clock driver device, 2 to 4 clock control blocks, 6, 31,
49 control register, 7, 32, 40, 50 PLL circuit, 8, 34 skew adjustment circuit, 9, 35, 45 clock driver, 13-16, 23-26, 36-3
8, 46, 47 LSI device, 19 feedback circuit, 29 selector, 30, 39, 48 circuit block, 33 clock output circuit, 41 PLL control register, 42 auto swing circuit, 43 parameter setting register, 58-60 board, 100- 102,13
8, 141, 148, 149, 150, 161 clock signal, 103, 119, 139 Skew adjustment clock signal, 105-110, 121-126, 142-
144, 151, 152, 163, 164 clock signal lines, 111 to 116, 127 to 134, 145 to 14
7 Clock signal line for skew adjustment, 118, 120
External circuit.

Claims (14)

[Claims] 1. A PLL clock driver device having a plurality of clock control blocks for generating a clock based on a clock signal input from the outside, wherein the clock control block is based on a control register and a value set in the control register. PL that adjusts the phase of the clock signal input from the outside and outputs the clock signal
A clock signal output from the L circuit and the PLL circuit is input, and two clock signals are output to the outside,
A clock driver that outputs a clock signal to the inside; and a skew adjustment circuit that compares a phase of the clock signal output from the clock driver with a phase of a skew adjustment clock signal input from the outside and sets the phase in a control register. PLL clock driver device. A clock signal line connected to the clock driver for inputting one of the first clock signals of the two clock signals output from the clock driver to another circuit device; The other of the two clock signals, which is connected to the skew adjustment circuit, is wired in parallel with the clock signal line on the substrate, and is output from the clock driver, and uses the other second clock signal as a skew adjustment clock signal 2. The PLL clock driver device according to claim 1, further comprising a skew adjustment clock signal line for inputting to the adjustment circuit. 3. The control register according to claim 1, wherein a value necessary for adjusting a phase of a clock signal input to the PLL circuit is set from an external circuit. PLL clock driver device. 4. The PL according to claim 1, wherein the control register comprises a nonvolatile memory.
L clock driver device. 5. The PLL clock driver device according to claim 1, further comprising a feedback circuit that outputs a skew adjustment signal input from the outside to the outside. 6. A skew adjustment clock signal comprising a selector for selecting whether to output a clock signal output from a clock driver to a skew adjustment circuit or to output the clock signal to a ground output.
6. The PLL clock driver device according to any one of claims 1 to 5. 7. A control register, and a PLL circuit for adjusting a phase of a clock signal input from the outside based on a value set in the control register and outputting a clock signal,
A clock output circuit that outputs a clock signal input from the outside as a skew adjustment clock signal, and a control register that compares the phases of the clock signal output from the PLL circuit and the skew adjustment clock signal output from the clock output circuit. And a skew adjustment circuit for setting the skew. 8. A clock signal line connected to the PLL circuit for inputting a clock signal from the outside to the PLL circuit and the clock output circuit, and connected to the clock output circuit and the skew adjustment circuit, and a clock signal on the substrate. 8. A skew adjustment clock signal line which is wired in parallel with the signal line and which inputs a skew adjustment clock signal output from the clock output circuit to the skew adjustment circuit. LSI device. 9. The control register according to claim 7, wherein a value necessary for adjusting the phase of the clock signal input to the PLL circuit is set from an external circuit. LSI device. 10. The control register according to claim 7, wherein the control register comprises a nonvolatile memory.
LL clock driver device. 11. A PLL control register, a PLL circuit for adjusting a phase of a clock signal input from the outside based on a value set in the PLL control register and outputting a clock signal, and a skew adjustment parameter. A PLL clock driver device comprising: a parameter setting register to be set; and an auto-swing circuit for automatically changing a skew based on a set skew adjustment parameter and setting the skew in a PLL control register. 12. A PLL control register, a PLL circuit that adjusts the phase of a clock signal input from the outside based on a value set in the PLL control register and outputs a clock signal, and a parameter for skew adjustment. An LSI device comprising: a parameter setting register to be set; and an auto-swing circuit that automatically changes a skew based on a set skew adjustment parameter and sets the skew in a PLL control register. 13. A control register for forcibly changing a phase of a clock and setting a value for safely operating within a range in which the system operates normally, and an external input based on a value set in the control register. And a PLL circuit that adjusts the phase of the clock signal and outputs the clock signal. 14. A control register for forcibly changing a phase of a clock to set a value for safely operating within a range in which the system operates normally, and an external input based on a value set in the control register. And a PLL circuit that adjusts the phase of the clock signal and outputs the clock signal.