JPH10163499A - Manufacture of thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form the LDD(light doped drain) region of a thin film transistor with good controllability without increasing the manufacture process, connecting the manufacture of the thin film transistor. SOLUTION: A gate insulating film 4 is formed on the crystallized silicon film 3 formed in a given position on an insulating substrate 1, and then a gate electrode 5 of a predetermined pattern is made on the gate insulating film 4. Next, a first film 7 is made all over after formation of a self oxide film 6 on the surface of the gate electrode 5, and then, the first film is patterned to provide openings 8, 10, and 12 at least in the region where the formation of a heavily doped source-drain region is planned, and the separation places of the gate electrodes 5 in circuit constitution. With the patterned first film as a mask, the gate insulating film 4, the self oxide film 6, and the gate electrodes 5 exposed in the openings 10 and 12 are removed by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly to an LDD (Lig) of a crystallized silicon thin film transistor (TFT) used as a data driver and a gate driver of a liquid crystal display device.
The present invention relates to a method for manufacturing a thin film transistor having a feature in a step of forming an htly doped drain region.

[0002]

2. Description of the Related Art Conventionally, liquid crystal display devices have been used for OA terminals, projectors, etc. because of their small size, light weight, and low power consumption. In particular, for a high quality liquid crystal display device, an active matrix type liquid crystal display device provided with a switching TFT for each pixel is used.

In such an active matrix type liquid crystal display device, a TFT for an address and a TFT for a driver in a peripheral portion of a pixel for controlling a voltage applied to a gate line or a data line of each pixel TFT are used in recent liquid crystal display devices. High-mobility devices are required in accordance with high definition and high quality devices. To meet such demands, polycrystalline silicon TFTs using a polycrystalline silicon film as a semiconductor layer constituting the TFT have been developed. It is starting to be adopted.

A polycrystalline silicon film used in such a TFT is obtained by annealing an amorphous silicon film formed by a P-CVD method (plasma chemical vapor deposition) at a high temperature of about 600 ° C. to form a polycrystalline silicon film. A polycrystalline silicon film directly formed by LP-CVD (low pressure chemical vapor deposition) or an amorphous silicon film instantaneously melt-crystallized by irradiation with an energy beam such as a laser or a flash lamp. Used.

[0005] However, since such a polycrystalline silicon film uses an inexpensive glass substrate, heat treatment at a higher temperature cannot be performed, and the off-state current is higher than that of a single-crystal silicon TFT. There is a problem.

In order to solve such a problem of off-current, adoption of an LDD structure is being studied. An LDD region having a low impurity concentration is provided between a source / drain region having a high impurity concentration and a channel region. Thereby, the electric field between the channel and the drain region (source region) when the TFT is in the off state is relaxed to reduce the leak current.

Here, the conventional process of forming the LDD region is as follows.
9 and 10, FIG. 9 shows a method used for a semiconductor memory or the like using a polycrystalline silicon film for a gate electrode, and FIG. 10 shows a method using an Al film for a gate electrode. This method is used for a liquid crystal display panel or the like that performs a large screen display.

Referring to FIG. 9A, first, a polycrystalline silicon film 53 is deposited on a glass substrate 51 via a base oxide film 52, patterned into a predetermined shape, and then a gate oxide film 54 and a polycrystalline silicon film are deposited. Then, the polycrystalline silicon film is patterned to form a polycrystalline silicon gate electrode 55, and then a low dose P ion 56 is ion-implanted to form an n ⁻ type region 57.

Next, in order to form a sidewall serving as a mask when forming a high impurity concentration source / drain region, see FIG.
An oxide film 58 is deposited on the entire surface.

Next, as shown in FIG. 9C, the oxide film 58 is anisotropically etched using reactive ion etching to form a sidewall 59 on the side wall of the polycrystalline silicon gate electrode 55.

Next, as shown in FIG. 9D, P + ions 60 are again implanted at a high dose to form n ⁺ -type source / drain regions 61, whereby the n ⁻ -type regions where P ions 60 have not been implanted are formed. 57
Becomes the n ⁻ -type LDD region 62.

In this case, the n ⁻ -type LDD region 62 is self-aligned with the polysilicon gate electrode 55 and the sidewall 59 by using the polysilicon gate electrode 55 and the sidewall 59 as an ion implantation mask. Can be formed.

Referring to FIG. 10A, a method of forming another LDD region will now be described.
After a polycrystalline silicon film 53 is deposited on a glass substrate 51 via a base oxide film 52 and patterned into a predetermined shape, a gate oxide film 54 and an Al film are deposited,
After the Al film is patterned using the photoresist pattern 64 to form the Al gate electrode 63, the porous anodic oxide film 65 is formed by performing anodic oxidation in an oxalic acid aqueous solution.

Referring to FIG. 10B, after the photoresist pattern 64 is removed,
By performing anodic oxidation in a tartaric acid aqueous solution, a strong and dense anodic oxide film 66 is formed on the surface of the Al gate electrode 63. Note that this dense anodic oxide film 66 has a temperature of 300 ° C.
Hillock (hilloc) generated even at a low temperature heat treatment
Due to the effect of reducing k), it is becoming a standard process in recent liquid crystal display panel.

Next, as shown in FIG. 10C, an Al gate electrode 63 and a porous anodic oxide film 65 are formed.
Is used as a mask to pattern the gate oxide film 54 by dry etching to expose the source / drain formation regions of the polycrystalline silicon film 53.

Next, after the porous anodic oxide film 65 is removed, 10 k
High dose P ions with low acceleration energy of about eV 6
7 are ion-implanted to form n ⁺ -type source / drain regions 61 which are self-aligned with the gate oxide film 54, and
0 keV high acceleration energy and low dose P ions 6
7 is transmitted through the gate oxide film 54 and ion-implanted so that the n ⁻ -type L is self-aligned with the dense anodic oxide film 66.
A DD region 62 is formed.

Also in this case, by using the dense anodic oxide film 66 and the gate oxide film 54 as an ion implantation mask, the n ⁻ -type LDD region 62 is formed with respect to the dense anodic oxide film 66 and the gate oxide film 54. It can be formed in a self-aligned manner.

[0018]

However, the method of forming the LDD region shown in FIG.
When a large liquid crystal substrate of m is applied, there is a problem in that the in-plane uniformity of the anisotropic etching is problematic, and the size of the LDD region varies.

The size of the LDD region of the TFT used in the peripheral circuit of the active matrix type liquid crystal display device is preferably 2 μm or more from the viewpoint of reducing the leakage current.
Although a length is required, the width of the sidewall depends on the height of the gate electrode and the like, and it is difficult to form an LDD region having a length of 2 μm or more with good controllability.

In the case where a liquid crystal display panel for displaying a large screen is formed by using polycrystalline silicon having a higher resistance than Al as the gate electrode, a problem of signal delay due to the high resistance of the polycrystalline silicon is caused. Occurs.

On the other hand, in the case of the method for forming the LDD region shown in FIG. 10, a problem arises in the uniformity of anodic oxidation.
In particular, it is very difficult to form an anodic oxide film of 2 μm or more with good controllability.

When the anodic oxidation method is used, it is necessary to connect all the gate electrodes in the first patterning step in order to apply a positive voltage to all the gate electrodes. In order to form a peripheral circuit, a separate resist process for separating the gate electrode is required.

Therefore, an object of the present invention is to form an LDD region of a TFT with good controllability without increasing the number of manufacturing steps.

[0024]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. FIG.
FIG. 2A is a sectional view of a main part taken along a dashed line in a plan view of the main part shown in FIG. 1 (a) and 1 (b) (1) In the method of manufacturing a thin film transistor according to the present invention, a crystallized silicon film 3 is formed at a predetermined position on an insulating substrate 1.
Forming a gate insulating film 4 on the crystallized silicon film 3, forming a gate electrode 5 having a predetermined pattern on the gate insulating film 4, contacting the gate electrode 5 with the gate insulating film 4. Forming a self-oxidized film 6 formed by oxidizing the gate electrode 5 on a non-existing surface, forming a first film 7 on the entire surface, at least a region where a high impurity concentration source / drain region is to be formed and a gate electrode 5, a step of patterning the first film 7 so as to provide the openings 8, 10, and 12 at the separation locations, and etching and removing the gate insulating film 4 and the self-oxidizing film 6 using the patterned first film 7 as a mask. And a step of etching and removing the gate electrode 5 exposed in the openings 10 and 12.

As described above, since the LDD region of the TFT formed in the polycrystalline silicon film 3 is formed by using the resist process, even in the case of a liquid crystal display panel having a large screen display, the LDD region having a large size is used. For example, an LDD region having a width of 2 μm or more can be formed with good controllability.

Further, by utilizing a process for patterning the gate insulating film 4 for forming the LDD region, a separation point of the gate electrode 5 in the circuit structure, that is, a formation portion of the gate connection wiring layer 9 and a gate electrode Opening 1 also in connection part 11
Since the first film 7 is patterned so as to provide 0 and 12, a separate resist process is not required for the step of dividing the gate electrode 5, and the throughput is improved.

(2) The present invention is characterized in that, in the above (1), the gate electrode 5 is formed of a metal containing aluminum as a main component.

As described above, the gate electrode 5 is made of a metal mainly composed of aluminum, for example, Al or Al—Sc.
Is used, the signal delay can be reduced, and a highly dense self-oxide film 6 serving as a mask in the step of etching the gate electrode 5 can be formed. Can be suppressed.

(3) The present invention is characterized in that in the above (1) or (2), the self-oxidizing film 6 is an anodic oxide film.

As described above, by using anodic oxidation, particularly anodic oxidation in a tartaric acid aqueous solution, a highly dense self-oxide film 6 can be formed, and generation of hillocks in a subsequent heat treatment step can be prevented. Can be suppressed.

(4) The present invention is characterized in that, in the above (1) or (2), the self-oxidized film 6 is a thermal oxide film heat-treated in an oxidizing atmosphere.

As described above, by performing heat treatment in an oxidizing atmosphere, particularly in a steam atmosphere, a highly dense self-oxidized film 6 can be formed. The effect of reducing defect levels, improving the interface characteristics between the crystallized silicon film 3 and the gate insulating film 4, and densifying the gate insulating film 4 can be obtained.

(5) Further, according to the present invention, in any one of the above (1) to (4), the gate electrode 5 exposed in the openings 10 and 12 is removed by etching using the first film 7 as a mask. It is characterized by.

As the first film 7, a film having a selective etching property with respect to the gate electrode 5, for example, a resist film or a metal film such as Cr may be used. However, when the Cr film is used, the etching controllability is improved, but a step of etching the Cr film is required.

(6) Further, according to the present invention, in any one of the above (1) to (4), the first film 7 can etch the gate electrode 5, The first film 7 and the gate electrode 5 exposed in the openings 10 and 12 are simultaneously removed by etching.

As described above, the gate electrode 5 is used as the first film 7.
By using a film that can be etched in the etching step, the first film 7 can be removed at the same time in the etching step of the gate electrode 5, and the step is simplified.

(7) The present invention is characterized in that, in the above (6), the first film 7 is formed of a metal containing aluminum as a main component.

As described above, by using a metal mainly composed of aluminum, for example, Al or Al—Sc as the first film 7, the first film 7 can be controlled at substantially the same etching rate as the gate electrode 5. Etching can be performed well, and no excessive or insufficient etching occurs.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a manufacturing process of a first embodiment of the present invention relating to a method of manufacturing a thin film transistor used for a peripheral circuit of an active matrix type liquid crystal display device will be described with reference to FIGS. I do. Note that FIG.
6A to 6I show main part cross-sectional views along the dashed line in the main part plan view on the right side.

Referring to FIG. 2A, first, L is placed on a transparent glass substrate 21 serving as a TFT substrate.
After using a P-CVD method, a SiO ₂ film serving as a base oxide film 22 having a thickness of 10 to 500 nm, for example, 200 nm, and a polycrystalline silicon film 23 having a thickness of 10 to 200 nm, for example, 50 nm are deposited. By patterning, an island-shaped region made of the polycrystalline silicon film 23 is formed at a predetermined position in the peripheral drive circuit portion and the pixel portion.

Next, referring to FIG. 2B, the surface of the polycrystalline silicon film 23 is lightly hydrofluoric acid-treated to remove contaminants, and then LP-CVD is used to form a film having a thickness of 50 to 200 nm, for example, 100 nm. After depositing an SiO ₂ film to be the gate oxide film 24, and then depositing an Al film having a thickness of 100 to 500 nm, for example, 200 nm using a sputtering method, the gate electrode 25 and the gate electrode 25 are formed by patterning the Al film. A gate connection wiring layer 26 integrally connected to each gate electrode 25 is formed.

Next, as shown in FIG. 3C, the whole is immersed in a tartaric acid aqueous solution, and anodic oxidation is performed by applying a positive voltage to the gate connection wiring layer 26 from an external power supply 28 to thereby form the gate electrode 25 and the gate connection wiring. An anodic oxide film 27 having a thickness of 50 to 200 nm, for example, 100 nm is formed on the surface of the layer 26.

Next, as shown in FIG. 3D, a photoresist 29 is applied to the entire surface, and is patterned by a usual photolithography process.
An opening 30 for forming ⁺ -type and p ⁺ -type source / drain regions is provided, and openings 31 and 32 are also formed at locations where the Al film needs to be cut due to the circuit configuration.

In this case, the thickness of the photoresist 29 on the side wall of the gate electrode 25, that is, the LDD length is set to 0.5 to 0.5 in consideration of the required length of the LDD region.
It is set to be 5.0 μm, for example, 2.0 μm.

Next, as shown in FIG. 4E, CHF _{3 is}
Opening 3 by dry etching using
After removing the gate oxide film 24 and the anodic oxide film 27 exposed at 0, 31, and 32, the gate electrode 25 exposed at the opening 32 by wet etching using phosphoric acid and the gate electrode 25 exposed at the opening 31 are formed. Gate connection wiring layer 2
6 is removed by etching.

Referring to FIG. 4F, after removing the photoresist 29, a new photoresist is applied and patterned to form a photoresist 33 so as to cover a region where a p-channel TFT is to be formed. , Acceleration energy 5-30
At keV, for example, 10 keV, 5.0 × 10 ¹⁴ -1.
P ions 34 are ion-implanted at a dose of 0 × 10 ¹⁶ cm ⁻² , for example, 2.0 × 10 ¹⁵ cm ⁻² to form the gate oxide film 2.
In addition to forming the n ⁺ -type source / drain region 35 which is self-aligned with No. 4, at an acceleration energy of 30 to 100 keV, for example, 70 keV, 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵
cm ⁻² , for example, at a dose of 1.0 × 10 ¹⁴ cm ^−2.
Ions 34 are implanted to form an n ⁻ -type LDD region 36 that is self-aligned with the anodic oxide film 27.

Next, after the photoresist 33 is removed, a new photoresist is applied and patterned to form a photoresist 37 so as to cover the n-channel type TFT formation region, Acceleration energy 5-30ke
V, for example, at 10 keV, 5.0 × 10 ^{14 to} 1.0 ×
B ions 38 are implanted at a dose of 10 ¹⁶ cm ^-2 , for example, 2.0 × 10 ¹⁵ cm ^-2 to form p ⁺ -type source / drain regions 39 which are self-aligned with the gate oxide film 24. At an acceleration energy of 30 to 100 keV, for example, 50 keV, 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ c
B ions 38 are implanted at a dose of m ⁻² , for example, 1.0 × 10 ¹⁴ cm ⁻² to form a p ⁻ type LDD region 40 that is self-aligned with the anodic oxide film 27.

Referring to FIG. 5H, after removing the photoresist 37, the P-CV
Using Method D, a thickness of 10 to 100 nm, for example, 50 n
An SiO ₂ film 41 serving as an etching stopper of m and a SiN film 42 serving as a first interlayer insulating film having a thickness of 200 to 500 nm, for example, 350 nm are deposited.
By patterning, n ⁺ -type source / drain regions 35, p ⁺ -type source / drain regions 39, and contact holes 43 and 44 for the gate electrode 25 are formed.

Next, in order to form a drive circuit and a data bus line, a thickness of 20 to 200 n is formed by using a sputtering method.
m, for example, a Ti film 45 of 100 nm and a thickness of 10
0 to 500 nm, for example, 300 nm Al wiring layer 46
Is deposited and then patterned to form a wiring layer having a predetermined pattern for forming a drive circuit and a data bus line.

As described above, in the first embodiment of the present invention, since the openings 30 for forming the LDD regions are formed by the photolithography process, it is necessary to perform the mask alignment with high accuracy. By L
The length of the DD area can be set with good controllability.

In addition, since the openings 31 and 32 are formed at the locations where the Al film is divided from the viewpoint of the circuit configuration by using the step of forming the openings 30 for forming the LDD regions, they are not necessary after anodic oxidation. The connection portion of the gate electrode 25 and the gate connection wiring layer 26 can be removed without increasing the number of photolithography steps, and the throughput is improved.

In the first embodiment,
Although the photoresist 29 is used to form the openings 30, 31, and 32, the photoresist containing carbon causes deposits to be formed in the dry etching process and causes poor etching controllability. May be used, but in this case, another etching step is required to etch the metal film such as Cr.

The gate electrode 2 exposed at the opening 32
5 and etching of the gate connection wiring layer 26 exposed in the opening 31 may be performed after ion implantation.
In this case, it is possible to prevent charge accumulation, that is, device destruction due to charge-up during ion implantation or photoresist stripping.

Next, a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. This second embodiment uses an Al film instead of the photoresist 29. ,
Since the other steps are substantially the same except for the etching step involved, only the main parts of the manufacturing steps are shown. 7 (a) to 8 (d) are cross-sectional views of a main part taken along a dashed line in a plan view of a main part on the right side.

Referring to FIG. 7 (a), first, a transparent glass substrate 21 serving as a TFT substrate is
Using a CVD method, a thickness of 10 to 500 nm, for example,
An SiO ₂ film to be a 200 nm base oxide film 22, and
After depositing an amorphous silicon film having a thickness of 10 to 200 nm, for example, 50 nm, the entire surface is subjected to laser annealing, the amorphous silicon film is polycrystallized, and then patterned to form predetermined portions of the peripheral drive circuit portion and the pixel portion. An island region made of the polycrystalline silicon film 23 is formed at a location.

Next, after the surface of the polycrystalline silicon film 23 is lightly treated with hydrofluoric acid to remove contaminants, ECR-C
A VD method (Electron Cyclotron Resonance-CVD method) is used to deposit a 50-200 nm-thick, for example, 100-nm-thick, SiO ₂ film serving as the gate oxide film 24, and then a 100-500 nm-thickness using a sputtering method For example, after depositing a 200 nm Al film, the Al film is patterned to form a gate electrode 25 and a gate connection wiring layer 26 integrally connected to each gate electrode 25.

Next, the whole is immersed in a tartaric acid aqueous solution, and anodic oxidation is performed by applying a positive voltage from an external power supply to the gate connection wiring layer 26 to thereby form the gate electrode 25.
And a thickness of 50 to 200 n on the surface of the gate connection wiring layer 26.
m, for example, after forming an anodic oxide film 27 having a thickness of 100 nm, the thickness is 50 to 20
An Al film 47 having a thickness of 0 nm, for example, 100 nm is deposited.

Next, a photoresist 48 is applied to the entire surface and patterned by a normal photolithography process to obtain n
⁺ -Type and p ⁺ -type together with the source and drain regions provide an opening 30 for forming a, the circuit configuration, after forming an opening 31 and 32 at a position off of the Al film is required, the photo Using the resist 48 as a mask, the exposed portion of the Al film 47 is etched away by wet etching using phosphoric acid.

In this case, the length of the LDD on the side wall of the gate electrode 25 of the Al film 47 is also the required LDD length.
In consideration of the length of the region, 0.5 to 5.0 μm, for example,
The photoresist 48 is patterned so as to have a thickness of 2.0 μm.

Next, after the photoresist 48 is removed, the Al film 4 is removed.
7 as a mask and dry gas using CHF ₃ as a source gas.
The gate oxide film 24 and the anodic oxide film 27 exposed in the openings 30, 31, and 32 are removed by etching.

Next, as shown in FIG. 8D, the entire surface is etched by wet etching using phosphoric acid, so that the gate electrode 25 exposed in the opening 32 and the gate connection wiring layer 26 exposed in the opening 31 are etched. At the same time as the removal, the Al film 4
7 is also etched away at the same time.

Next, the following description is based on the first embodiment.
Similarly, apply photoresist and pattern
This covers the region where the p-channel TFT will be formed.
A photoresist is formed as shown in FIG.
× 30 keV, for example, 5.0 × 10 at 10 keV¹⁴
~ 1.0 × 10¹⁶cm^-2For example, 2.0 × 10^Fifteencm
^-2Ion implantation of P ions at a dose of
N self-aligned to 24 ⁺Form source / drain regions
And acceleration energy of 30-100 keV, for example
For example, at 70 keV, 1.0 × 10¹³~ 1.0 × 10^Fifteenc
m^-2For example, 1.0 × 10¹⁴cm^-2At the dose of
N is ion-implanted to self-align with the anodic oxide film 27
^-A type LDD region is formed.

Next, after removing the photoresist,
A new photoresist is applied and patterned to form a photoresist so as to cover the n-channel TFT formation region.
At keV, for example, 10 keV, 5.0 × 10 ¹⁴ -1.
B ions are implanted at a dose of 0 × 10 ¹⁶ cm ⁻² , for example, 2.0 × 10 ¹⁵ cm ⁻² to form p ⁺ -type source / drain regions that are self-aligned with the gate oxide film 24. Acceleration energy 30-100 keV, for example, 5
At 0 keV, 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ cm ⁻² ,
For example, p ^- type L self-aligned with the anodic oxide film 27 by ion implantation of B ions at a dose of 1.0 × 10 ¹⁴ cm ^−2.
A DD region is formed.

Next, after removing the photoresist,
Using a P-CVD method, a SiO film serving as an etching stopper having a thickness of 10 to 100 nm, for example, 50 nm
₂ film and a thickness of 200 to 500 nm, for example, 350
A SiN film serving as a first interlayer insulating film having a thickness of nm is deposited and then patterned to form an n ⁺ -type source / drain region, a p ⁺ -type source / drain region, and a contact hole for a gate electrode.

Next, in order to form a drive circuit and a data bus line, a thickness of 20
A 200 nm, for example, 100 nm, Ti film and a 100 to 500 nm, for example, 300 nm, Al wiring layer are deposited and then patterned to form a driving circuit and a data bus line by patterning. Form a layer.

As described above, in the second embodiment of the present invention, as in the first embodiment, the LD
Since the opening 30 for forming the D region is formed by a photolithography process, the length of the LDD region can be set with good controllability by performing mask alignment with high accuracy.

In addition, since the openings 31 and 32 are formed at the locations where the Al film is divided in the circuit configuration by using the step of forming the openings 30 for forming the LDD regions, unnecessary portions are formed after anodic oxidation. The connection portion of the gate electrode 25 and the gate connection wiring layer 26 can be removed without increasing the number of photolithography steps, and the throughput is improved.

In the second embodiment,
Since the same Al film 47 as the gate electrode is used as a mask in the patterning process of the gate oxide film 24 and the anodic oxide film 27, the Al film 47 can be removed simultaneously with the connection portion of the gate electrode 25 and the gate connection wiring layer 26. And the process is simplified.

Further, in the second embodiment, the polycrystalline silicon film is formed by laser annealing. However, similarly to the first embodiment, the polycrystalline silicon film is directly formed by the LP-CVD method. A crystalline silicon film may be formed, and conversely, also in the first embodiment,
A polycrystalline amorphous silicon film formed by a P-CVD method by laser annealing may be used.

Further, in each of the above embodiments, Al is used as the gate electrode material. However, the present invention is not limited to Al, and any metal having Al as its main component, such as Al—Sc, may be used. The use of such a metal reduces the wiring resistance and simplifies the patterning process. In particular, when Al-Sc containing Sc is used, generation of hillocks can be suppressed.

Further, in addition to such a metal containing Al as a main component, a metal such as Ta, Ti, or Cr may be used. In any case, in the case of the second embodiment, In this case, the Al film used as a mask in the patterning step for forming the LDD structure may be made of a material having substantially the same etching rate as the gate electrode, usually the same material.

In each of the above embodiments, the gate electrode is oxidized by anodic oxidation. However, the gate electrode may be formed by thermal oxidation in an oxygen atmosphere, in particular, by thermal oxidation in a steam atmosphere. For example, in a water vapor atmosphere of 20 Torr at a substrate temperature of 450 ° C.,
By performing the time oxidation treatment, a dense self-oxidized film can be formed, the defect level in the polycrystalline silicon film can be reduced, the interface characteristics of the polycrystalline silicon film / gate oxide film can be improved, and the gate oxidation can be performed. The effect of densification of the film is also obtained.

Further, in the above embodiment, after forming the source / drain regions with a high impurity concentration,
Although the D region is formed, this order may be reversed.

In each of the above embodiments, a method of manufacturing a complementary TFT for a drive driver used in an active matrix type liquid crystal display device is described. However, the present invention is not limited to the complementary type. Is SOI
An ordinary semiconductor integrated circuit device may be configured using a TFT having a (Silicon on Insulator) structure or a SOS (Silicon on Sapphire) structure.

In each of the above embodiments, the TFT is formed using a polycrystalline silicon film. However, the crystallized silicon film of the present invention is not limited to a normal polycrystalline silicon film. It includes a giant polycrystal or single crystal silicon film.

As the insulating substrate, in addition to an inexpensive glass substrate, a Pyrex substrate, a quartz glass substrate, a substrate provided with an insulating film on a single crystal silicon substrate, or a Sa substrate.
A single crystal insulator substrate such as pphire may be used.

[0077]

According to the present invention, since the process for forming the LDD region is performed by the resist process, even if a large area substrate is used, the L of any length can be controlled with good control.
Since the DD region can be formed, and the step of dividing the gate electrode and the connection wiring layer is performed by using the resist process for forming the LDD region, the yield and reliability can be improved without increasing the number of manufacturing steps. Thus, an active matrix type liquid crystal display device with high definition and high quality can be realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG.

FIG. 5 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG. 4;

FIG. 6 is an explanatory view of the manufacturing process of the first embodiment of the present invention after FIG. 5;

FIG. 7 is an explanatory diagram of a manufacturing process of a main part of a second embodiment of the present invention.

FIG. 8 is an explanatory diagram of a main part manufacturing process of the second embodiment of the present invention after FIG. 7;

FIG. 9 is an explanatory diagram of a conventional method of forming an LDD region.

FIG. 10 is an explanatory diagram of another conventional method for forming an LDD region.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Insulating substrate 2 Base insulating layer 3 Crystallized silicon film 4 Gate insulating film 5 Gate electrode 6 Self-oxidizing film 7 First film 8 Opening 9 Gate connection wiring layer 10 Opening 11 Gate electrode connecting part 12 Opening 21 Glass Substrate 22 Base oxide film 23 Polycrystalline silicon film 24 Gate oxide film 25 Gate electrode 26 Gate connection wiring layer 27 Anodized film 28 External power supply 29 Photoresist 30 Opening 31 Opening 32 Opening 33 Photoresist 34 P ion 35 n ⁺ Type source / drain region 36 n ^- type LDD region 37 photoresist 38 B ion 39 p ⁺ type source / drain region 40 p ^- type LDD region 41 SiO ₂ film 42 SiN film 43 contact hole 44 contact hole 45 Ti film 46 Al wiring Layer 47 Al film 48 photoresist 51 glass Substrate 52 Base oxide film 53 Polycrystalline silicon film 54 Gate oxide film 55 Polycrystalline silicon gate electrode 56 P ion 57 n ⁻ type region 58 Oxide film 59 Side wall 60 P ion 61 n ⁺ source / drain region 62 n ⁻ LDD Region 63 Al gate electrode 64 photoresist pattern 65 porous anodic oxide film 66 dense anodic oxide film 67 P ion

Claims (7)

[Claims] A step of forming a crystallized silicon film at a predetermined position on an insulating substrate, a step of forming a gate insulating film on the crystallized silicon film, and forming a gate electrode of a predetermined pattern on the gate insulating film. Forming a self-oxidized film formed by oxidizing the gate electrode on a surface of the gate electrode that is not in contact with the gate insulating film; forming a first film over the entire surface; Patterning the first film so as to provide an opening in a region where a source / drain region is to be formed and in a circuit configuration where the gate electrode is separated;
A step of etching and removing the gate insulating film and the self-oxidized film by using the film as a mask, and a step of etching and removing the gate electrode exposed in the opening. 2. The method according to claim 1, wherein the gate electrode is formed of a metal containing aluminum as a main component. 3. The method according to claim 1, wherein the self-oxidizing film is an anodic oxide film. 4. The method according to claim 1, wherein the self-oxidized film is a thermally oxidized film thermally oxidized in an oxidizing atmosphere. 5. The method according to claim 1, wherein the gate electrode exposed in the opening is removed by etching using the first film as a mask. 6. The first film, wherein the first film is capable of etching the gate electrode and is etched by an etching means having selectivity with respect to the self-oxidizing film. 5. The method according to claim 1, wherein the gate electrode and the gate electrode exposed in the opening are removed by etching at the same time. 6. 7. The method according to claim 6, wherein the first film is formed of a metal containing aluminum as a main component.
A method for manufacturing the thin film transistor according to the above.