JPH10163474A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can get high breakdown strength stably and its manufacture. SOLUTION: An n<+> -type drain region 5 is made at roughly center of a device formation area 4, and a p<+> -type body 6 and a p-type channel region 7 are so made as to surround the n<+> -type drain region 5. Then, an n<+> -type source region 8 is made such that it is involved in the p<+> -type body 6 and the p-type channel region 7, and a p<-> -type impurity region 9 is made in the device formation region 4 between the p-type channel region 7 and the n<+> -type drain region 5, and a p<++> -type impurity region 10 is made such that it is involved in the p<-> -type impurity region 9. Then, a field plate 15 is made so that it may be electrically connected with the p<++> -type impurity region 10 and that it may be extended in the direction of the n<+> -type drain region 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an LDMOSFE.
T and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional LDMOSFET.
FIG. Conventional lateral double diffusion MOS field effect transistor (LDMOSFET: Lateral Doubl)
e Diffused MOSFET) has a p-type semiconductor substrate 1 and an n-type epitaxial layer 2 formed on the p-type semiconductor substrate 1. P ++ reaching the semiconductor substrate 1
An element isolation region 3 is formed, and an n-type epitaxial layer 2 is formed.
Are formed with a plurality of p ++ type element isolation regions 3 and a plurality of element formation regions 4 which are insulated from adjacent element formation regions 4 by the p type semiconductor substrate 1.

In addition, a high-concentration n + type drain region 5 is formed at a substantially central portion in the element formation region 4 so as to be exposed on the surface of the element formation region 4, and is electrically connected to the n + type drain region 5. A drain electrode 13 made of aluminum or the like is formed up to the adjacent element formation region 4 straddling the p ++ type element isolation region 3. And surrounds the n + type drain region 5 while being in contact with the p ++ type element isolation region 3;
The element formation region 4 is exposed on the surface of the element formation region 4.
A p ++ type body 6 having a lower concentration than the p ++ type element isolation region 3 is formed therein, surrounds the n + type drain region 5 while being in contact with the p ++ type body 6, and is exposed to the surface of the element formation region 4. A p-type channel region 7 having a lower concentration than the p + -type body 6 is formed in the formation region 4. Except for the lower part of the drain electrode 13 and its vicinity, p
++-type element isolation region 3, p + -type body 6, and p-type channel region 7; and high concentration n + -type source region 8 is formed in element formation region 4 so as to be exposed on the surface of element formation region 4. Have been.

In addition, the n + type drain region 5 and the p-type drain region 5 are exposed in the drift region exposed between the n + type drain region 5 and the p-type channel region 7 in the surface of the element forming region 4. A p-type impurity region 9 having a lower concentration than the p-type channel region 7 is formed apart from the channel region 7. Then, a high-concentration p ++-type impurity region 10 is formed in the element formation region 4 so as to be included in the p − -type impurity region 9 and exposed on the surface of the element formation region 4.

An oxide film 11 as an insulating film is formed on n-type epitaxial layer 2 and is interposed between n + -type drain region 5 and n + -type source region 8 exposed on the surface of element formation region 4. An insulated gate 12 made of polysilicon or the like is formed at a portion of the p-type channel region 7 exposed on the surface of the element formation region 4 via an oxide film 11 so as to be electrically connected to the insulated gate 12. A gate electrode (not shown) made of aluminum or the like.
Then, the p ++ type element isolation region 3 and the n ++ type source region 8
And source electrode 14 made of aluminum or the like is formed so as to be electrically connected to p ++ type impurity region 10.
It constitutes an LDMOSFET.

Hereinafter, a method of manufacturing a conventional LDMOSFET will be described. FIG. 6 shows a conventional LDM.
FIG. 4 is a schematic cross-sectional view showing a manufacturing process of an OSFET. First, p
N type epitaxial layer 2 on one main surface of type semiconductor substrate 1
Is formed, and an oxide film 11 is formed on the n-type epitaxial layer 2 by performing thermal oxidation. Then, a photoresist (not shown) is applied on the oxide film 11, patterned into a predetermined shape by a photolithography technique, and the oxide film 11 is selectively etched using the patterned photoresist as a mask to form an opening ( (Not shown)
Is formed, and the photoresist is removed by plasma ashing or the like.

Subsequently, using the oxide film 11 in which the opening is formed as a mask, a p-type impurity such as boron (B) is deposited,
A p ++ type element isolation region 3 is formed by an oxidation and drive process, and an element formation region 4 composed of an n type epitaxial layer 2 insulated and separated by the p type semiconductor substrate 1 and the p ++ type element isolation region 3 is formed (FIG. 6 ( a)).

Next, a photoresist (not shown) is applied on the oxide film 11, patterned into a predetermined shape by photolithography, and the oxide film 11 is selectively etched using the patterned photoresist as a mask. (Not shown), and the photoresist is removed by plasma ashing or the like. And
Using the oxide film 11 in which the opening is formed as a mask, a p-type impurity such as boron (B) is ion-implanted, and the p-type impurity region 9 is formed by an oxidation and drive process.
(B)).

Next, a photoresist (not shown) is applied on the oxide film 11 and patterned into a predetermined shape by photolithography, and the oxide film 11 is selectively etched using the patterned photoresist as a mask. (Not shown), and the photoresist is removed by plasma ashing or the like. And
Using the oxide film 11 with the opening formed as a mask, a p-type impurity such as boron (B) is ion-implanted, and a p + type body 6 is formed by an oxidation and drive process (FIG. 6C).

Next, the oxide film 11 on the portion where the p-type channel region 7 is formed is removed by etching, and thermal oxidation is performed. Then, polysilicon is formed on the oxide film 11 by a low-pressure CVD method or the like, and is patterned into a predetermined shape by etching. An insulating gate 12 made of polysilicon is formed on the portion where the p-type channel region 7 is formed via the oxide film 11. It is formed (FIG. 6D).

Next, a photoresist (not shown) is applied on the oxide film 11 and the insulating gate 12, patterned into a predetermined shape by a photolithography technique, and the photoresist patterned into the predetermined shape is used as a mask. A p-type impurity such as boron (B) is ion-implanted using the insulating gate 12 as one end of the mask, and the photoresist is removed.
Is formed (FIG. 6E).

Next, using a photoresist patterned into a predetermined shape as a mask, a p-type impurity such as boron (B) is ion-implanted, and the photoresist is removed. Area 9
A p ++ type impurity region 10 is formed therein (FIG. 6).
(F)).

Next, an n-type impurity such as phosphorus (P) is ion-implanted using a photoresist patterned in a predetermined shape as a mask, and the photoresist is removed. Forming a p-type drain region 5 and p ++ type element isolation regions 3 and p
An n + type source region 8 is formed so as to be included in the + type body 6 and the p type channel region 7 (FIG. 6G).

Next, an oxide film 11 is formed on the oxide film 11 and the insulating gate 12 by a normal pressure CVD method or the like using silane (SiH ₄ ) as a source gas.
Oxide film 11 on n + type source region 8 and insulating gate 12
Is removed by etching, and n + type drain regions 5 and n
A drain electrode 13, a source electrode 14, and a gate electrode (not shown) are formed so as to be electrically connected to the + source region 8 and the insulating gate 12 (FIG. 6 (h)).

In a conventional LDMOSFET, when a voltage equal to or higher than a threshold is applied to the gate electrode, p
A channel is formed in the n-type channel region 7, and a current flows between the n + type drain region 5 and the n + type source region 8,
When the gate potential is equal to the source potential, no current flows between the n + -type drain region 5 and the n + -type source region 8, so that the n + -type drain region 5 and the n + -type source region 8
And a voltage is applied between them.

In such an LDMOSFET, a high potential is applied to the drain electrode 13 and a low potential is applied to the source electrode 14 to deplete the entire device forming region 4 and to form the device forming region 4.
The electric field strength on the surface of the substrate is alleviated to maintain the breakdown voltage between the drain and the source at a high voltage. This is the so-called RESUR
F (Reduced SURface Field) principle is used and "I
nternational Electoronic Device Meeting Techni
cal Digest ", Dec., pp. 238-240 (1979).

Here, when the impurity concentration of the element forming region 4 is high, the element forming region 4 between the p-type channel region 7 and the n + -type drain region 5 must have A p-type impurity region 9 is formed.

FIG. 7 shows the p-
4 is a graph showing a relationship between an impurity concentration of a type impurity region 9 and a breakdown voltage between a drain and a source. According to FIG.
The breakdown voltage between the sources has an optimum value in a limited narrow concentration range of the impurity concentration of the p − -type impurity region 9 on the surface of the element formation region 4.

When the impurity concentration of the p− type impurity region 9 on the surface of the element forming region 4 is low, the withstand voltage between the drain and the source is reduced because the depletion layer in the p− type impurity region 9 has an n + type source. It is easy to extend in the direction of the area 8,
p ++ formed in p− type impurity region 9 for electrically connecting n + type source region 8 and p− type impurity region 9
This is because the electric field concentrates near the type impurity region 10.

[0020]

The L having the above-described configuration
In the DMOSFET, there is a problem that it is difficult to control the impurity concentration of the p-type impurity region 9 on the surface of the element formation region 4 so as to be within a narrow concentration range having an optimum value with respect to the withstand voltage between the drain and the source. Was.

Further, there is a problem that the withstand voltage between the drain and the source varies due to the variation in the impurity concentration of the p-type impurity region 9 on the surface of the element forming region 4, and it is difficult to stably obtain a high withstand voltage.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of stably obtaining a high breakdown voltage and a method of manufacturing the same.

[0023]

According to the first aspect of the present invention,
A first conductivity type semiconductor substrate, formed on one main surface of the first conductivity type semiconductor substrate, a first conductivity type element isolation region formed so as to reach the first conductivity type semiconductor substrate from the surface, and An element formation region comprising a second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate; and a high-concentration first layer formed substantially at the center of the element formation region so as to be exposed on the surface of the element formation region. A two-conductivity-type drain region, a drain electrode electrically connected to the high-concentration second-conductivity-type drain region, and drawn out to another element formation region across the element isolation region; A high-concentration first-conductivity-type body formed in the element formation region so as to surround the conductivity-type drain region and to be exposed on a surface of the element formation region; the high-concentration second conductivity-type drain region; Guidance The high-concentration first conductivity type body formed at a location adjacent to the high-concentration first conductivity type body in the element formation region so as to be exposed on the surface of the element formation region between the high-concentration first conductivity type body and the mold body. Except for the low-concentration first conductivity type channel region and the high-concentration first conductivity type body and the first conductivity type channel region except for the lower part and the vicinity of the drain electrode, the channel region is exposed to the surface of the element formation region. A high-concentration second-conductivity-type source region formed in the element formation region, and the first conductive layer interposed between the high-concentration second-conductivity-type source region and the high-concentration second-conductivity-type drain region. An insulating gate formed on the mold channel region via an insulating film, a gate electrode formed so as to be electrically connected to the insulating gate, and the first electrode exposed on the surface of the element forming region. Conductive type A low-concentration first-conductivity-type impurity region having a lower concentration than the first-conductivity-type channel region formed in the element formation region between the channel region and the high-concentration second-conductivity-type drain region; A high-concentration first-conductivity-type impurity that is included in the first-conductivity-type impurity region and has a higher concentration than the high-concentration first-conductivity-type body formed in the element formation region so as to be exposed on the surface of the element formation region. A semiconductor device comprising: a high-concentration first conductivity type source region and a high-concentration first conductivity type impurity region; and a source electrode formed to be electrically connected to the high-concentration first conductivity type impurity region. A field plate electrically connected to the conductivity type impurity region and extending toward the high-concentration second conductivity type drain region is formed.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the field plate is formed in a step shape so as to be away from the low concentration first conductivity type impurity region. is there.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the high concentration first conductivity type impurity region is reduced in a direction of the high concentration second conductivity type drain region. It is characterized by having a concentration gradient so as to obtain a concentration.

According to a fourth aspect of the present invention, a second conductivity type epitaxial layer is formed on one main surface of the first conductivity type semiconductor substrate, and the first conductivity type semiconductor substrate is formed from the surface of the second conductivity type epitaxial layer. Forming a first conductivity type device isolation region so as to reach the first conductivity type device isolation region and the second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate. To form
Forming a high-concentration second-conductivity-type drain region substantially at the center of the device-forming region so as to be exposed on the surface of the device-forming region; electrically connecting to the high-concentration second-conductivity-type drain region; Forming a drain electrode extending to another element formation region across the isolation region; surrounding the high-concentration second conductivity type drain region; and forming a drain electrode in the element formation region so as to be exposed on the surface of the element formation region. Forming a high-concentration first-conductivity-type body, and exposing the element-forming region to the surface of the element-forming region between the high-concentration second-conductivity-type drain region and the high-concentration first-conductivity-type body. A first conductivity type channel region having a lower concentration than the high concentration first conductivity type body is formed at a location adjacent to the high concentration first conductivity type body in the inside, and except for the lower portion of the drain electrode and its vicinity, High concentration A high-concentration second-conductivity-type source region is formed in the element formation region so as to be included in the one-conductivity-type body and the first-conductivity-type channel region and exposed on the surface of the element formation region; Forming an insulating gate on the first conductivity type channel region interposed between the mold source region and the high-concentration second conductivity type drain region via an insulating film, and electrically connecting to the insulating gate. Forming a gate electrode on the first conductive type in the element forming region between the first conductive type channel region and the high-concentration second conductive type drain region so as to be exposed on the surface of the element forming region. Forming a low-concentration first-conductivity-type impurity region having a concentration lower than that of the channel region; being included in the low-concentration first-conductivity-type impurity region; and being formed in the element formation region so as to be exposed on the surface of the element formation region. High concentration first conductivity Forming a high-concentration first-conductivity-type impurity region having a higher concentration than the body, and forming a source electrode so as to be electrically connected to the high-concentration second-conductivity-type source region and the high-concentration first-conductivity-type impurity region; Forming a field plate so as to be electrically connected to the high-concentration first-conductivity-type impurity region and to extend in the direction of the high-concentration second-conductivity-type drain region. It is characterized by having done.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the insulating film below the field plate is formed of a plurality of types of insulating films having different etching rates. A step portion is formed in the insulating film by utilizing the difference in the etching rate, and the field plate is formed stepwise by forming the field plate on the step portion.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth or fifth aspect, the field plate is formed simultaneously with the formation of the insulating gate. Is what you do.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the fourth to sixth aspects, the low concentration first conductivity type impurity region is adjacent to the high concentration first conductivity type impurity region. By using the field plate as a mask, ion implantation is performed to penetrate the mask, thereby lowering the low-concentration first conductivity type impurity region toward the high-concentration second conductivity type drain region. It is characterized by having a concentration gradient such that

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, the ion implantation is performed when forming the high concentration first conductivity type body or the first conductivity type channel region. It is characterized in that it is performed simultaneously.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the first conductivity type is p-type and the second conductivity type is n for convenience of explanation.
Although described as a type, the present invention is also applied to a case where p-type and n-type are reversed.

FIG. 1 shows an LDM according to an embodiment of the present invention.
FIG. 2 is a schematic sectional view showing an OSFET. L according to the present embodiment
The DMOSFET is an LDMOS shown in FIG.
In the FET, n is electrically connected to the source electrode 14 and n
The field plate 15 is formed so as to extend in the direction of the + type drain region 5. here,
Field plate 15 is formed stepwise in a direction away from p − -type impurity region 9.

The impurity concentration and the thickness of the n-type epitaxial layer 2 are optimally set according to a desired breakdown voltage. In general, the product of the impurity concentration and the thickness of the n-type epitaxial layer 2 is about 1 × 10 ¹² / It is desirable to set to cm ² .

Hereinafter, the LDMOSFET according to the present embodiment will be described.
Will be described with reference to the drawings. FIG. 2 is a schematic cross-sectional view illustrating a manufacturing process of the LDMOSFET according to the present embodiment. In the manufacturing process of the LDMOSFET according to the present embodiment, in the manufacturing process of the LDMOSFET shown in FIG. 6 as a conventional example, the processes up to FIG. 6C are the same as the processes up to FIG. 2C according to the present embodiment. Therefore, the description is omitted here, and the description will be started from the step of FIG. The oxide film 11 on the location where the p-type channel region 7 is formed is removed by etching, and thermal oxidation is performed. Then, the reduced pressure C is formed on the oxide film 11.
Polysilicon is formed by a VD method or the like, and is patterned into a predetermined shape by etching, so that an insulating gate 12 made of polysilicon is formed on the portion where the p-type channel region 7 is formed via an oxide film 11. When the insulating gate 12 is formed, the field plate 1 made of polysilicon is simultaneously formed.
5 is formed (FIG. 2D).

Next, a photoresist (not shown) is formed on the oxide film 11, the insulating gate 12, and the field plate 15.
Is applied and patterned into a predetermined shape by a photolithography technique. A photoresist patterned into the predetermined shape is used as a mask, and a p-type impurity such as boron (B) is ion-implanted using the insulating gate 12 as one end of the mask. After removing the photoresist, a p-type channel region 7 is formed by a drive process (FIG. 2E).

Next, using a photoresist patterned in a predetermined shape as a mask, a p-type impurity such as boron (B) is ion-implanted, and the photoresist is removed. Area 9
A p ++ type impurity region 10 is formed therein (FIG. 2)
(F)).

Next, an n-type impurity such as phosphorus (P) is ion-implanted using the photoresist patterned in a predetermined shape as a mask, and the photoresist is removed. Forming a p-type drain region 5 and p ++ type element isolation regions 3 and p
An n + type source region 8 is formed so as to be included in the + type body 6 and the p type channel region 7 (FIG. 2G).

Next, the oxide film 11 is formed on the oxide film 11, the insulating gate 12, and the field plate 15 by a normal pressure CVD method using silane (SiH ₄ ) as a source gas.
The oxide film 11 on the n + type drain region 5, the n + type source region 8 and the insulating gate 12 is removed by etching, and
A drain electrode 13 and a gate electrode (not shown) made of aluminum (Al) or the like are formed so as to be electrically connected to the + type drain region 5 and the insulated gate 12, and p +
A source electrode made of aluminum (Al) or the like is formed so as to be electrically connected to + element isolation region 3, n + source region 8, p ++ impurity region 10, and field plate 15 (FIG. 2 (h)). .

In this embodiment, since the field plate 15 is provided so as to be electrically connected to the source electrode 14 and to extend in the direction of the n + -type drain region 5, the p + -type impurity region 10 is thereby formed. It is possible to reduce the electric field concentration at the place where the impurity concentration is reduced, and to widen the impurity concentration range on the surface of the element forming region 4 of the p − -type impurity region 9 for obtaining the optimum value of the drain-source breakdown voltage. FIG. 3 is a graph showing the relationship between the impurity concentration of the p − -type impurity region 9 on the surface of the element forming region 4 and the withstand voltage between the drain and the source according to the present embodiment.

In this embodiment, the field plate 15 is formed at the same time when the insulating gate 12 is formed. However, the present invention is not limited to this.
Independently of the insulated gate 12, the field plate 15
May be formed.

In this embodiment, the field plate 15 is formed with one step. However, the present invention is not limited to this. For example, a plate-shaped plate or a plate having two or more steps can be used. May be formed, and by forming one having two or more steps, the electric field concentration can be further reduced. Here, as an example of a method of forming the stepped field plate 15,
An oxide film having a different etching rate, for example, an oxide film formed by thermal oxidation and an oxide film formed by a normal pressure CVD method are formed on the oxide film 11 below the field plate 15, and the etching rates of the two oxide films are reduced. The step portion is formed using the difference, and the field plate 15 is formed on the step portion, whereby the step-shaped field plate 15 can be formed.

Further, in this embodiment, the p ++ type impurity region 10 is formed to have a constant impurity concentration, but is not limited to this.
The impurity concentration of the p ++-type impurity region 10 may have a concentration gradient toward the n + -type drain region 5, so that a higher breakdown voltage can be obtained.
Here, as an example of a manufacturing process for giving a concentration gradient to the impurity concentration of the p ++ type impurity region 10, when forming the p ++ type impurity region 10, ion implantation is performed using the field plate 15 as a part of a mask. Can be formed by penetrating the field plate 15 and shallowly implanting ions into the p − -type impurity region 9 (FIG. 4F). That is, by implanting ions into a part of the field plate 15, an impurity region having a lower impurity concentration than the p ++ type impurity region 10 is formed at a position adjacent to the p ++ type impurity region 10.

[0043]

According to the first aspect of the present invention, the first conductive type semiconductor substrate is formed on one main surface of the first conductive type semiconductor substrate and formed so as to reach the first conductive type semiconductor substrate from the surface. An element formation region comprising a first conductivity type element isolation region and a second conductivity type epitaxial layer which is insulated and separated by the first conductivity type semiconductor substrate; and an element formation region substantially exposed in a surface of the element formation region. A high-concentration second-conductivity-type drain region formed at the center, and a drain electrode electrically connected to the high-concentration second-conductivity-type drain region and extending to another element formation region across an element isolation region; A high-concentration first-conductivity-type body, a high-concentration second-conductivity-type drain region, and a high-concentration second-conductivity-type drain region formed in the element formation region so as to surround the high-concentration second conductivity-type drain region and to be exposed on the surface of the element formation region; First conductivity type The first conductive type body having a lower concentration than the high-concentration first conductive type body formed at a location adjacent to the high-concentration first conductive type body in the element forming region so as to be exposed on the surface of the element forming region between the first conductive type body and the first conductive type body. Except for the conductive type channel region and the lower part of the drain electrode and its vicinity, the high-concentration first conductive type body and the first conductive type channel region are included in the element formation region so as to be exposed on the surface of the element formation region. High-concentration second-conductivity-type source region, and a first-conductivity-type channel region interposed between the high-concentration second-conductivity-type source region and the high-concentration second-conductivity-type drain region. Insulated gate, a gate electrode formed so as to be electrically connected to the insulated gate, and a first conductivity type channel region and a high concentration second conductivity type drain region so as to be exposed on the surface of the element formation region. Element formation between Forming a low-concentration first-conductivity-type impurity region having a lower concentration than the first-conductivity-type channel region formed in the region; and forming the element so as to be included in the low-concentration first-conductivity-type impurity region and exposed on the surface of the element formation region. Electrically connected to the high-concentration first-conductivity-type impurity region having a higher concentration than the high-concentration first-conductivity-type body formed in the region, and to the high-concentration second-conductivity-type source region and the high-concentration first-conductivity-type impurity region And a source electrode formed so as to be electrically connected to the high-concentration first-conductivity-type impurity region and extending toward the high-concentration second-conductivity-type drain region. Since the formed field plate is formed, the electric field concentration can be reduced by the field plate, and the element formation region table of the low-concentration first conductivity type impurity region for obtaining the optimum value of the drain-source withstand voltage. The range of impurity concentration on the surface can be expanded,
A semiconductor device capable of stably obtaining a high breakdown voltage can be provided.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the field plate is formed stepwise so as to be away from the low-concentration first conductivity type impurity region. And a high withstand voltage can be stably obtained.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the high-concentration first-conductivity-type impurity region is reduced in concentration toward the high-concentration second-conductivity-type drain region. Since the concentration gradient is provided, electric field concentration can be further reduced, and a high breakdown voltage can be obtained stably.

According to a fourth aspect of the present invention, a second conductivity type epitaxial layer is formed on one main surface of the first conductivity type semiconductor substrate, and reaches the first conductivity type semiconductor substrate from the surface of the second conductivity type epitaxial layer. Forming a first conductivity type device isolation region so as to form a device formation region comprising a first conductivity type device isolation region and a second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate; A high concentration second conductivity type drain region is formed substantially at the center of the element formation region so as to be exposed on the surface of the formation region, electrically connected to the high concentration second conductivity type drain region, and straddling the element isolation region. Forming a drain electrode extending to another element forming region, surrounding the high-concentration second-conductivity-type drain region, and forming a high-concentration first-conductivity-type body in the element forming region so as to be exposed on the surface of the element forming region; The shape Then, at a location adjacent to the high-concentration first conductivity type body in the element formation region so as to be exposed on the surface of the element formation region between the high-concentration second conductivity type drain region and the high-concentration first conductivity type body. Forming a first conductivity type channel region having a lower concentration than the high concentration first conductivity type body, and being included in the high concentration first conductivity type body and the first conductivity type channel region except for the lower part of the rain electrode and its vicinity, A high concentration second conductivity type source region is formed in the element formation region so as to be exposed on the surface of the element formation region, and is interposed between the high concentration second conductivity type source region and the high concentration second conductivity type drain region. An insulating gate is formed on the first conductive type channel region via an insulating film, a gate electrode is formed so as to be electrically connected to the insulating gate, and the first conductive type is formed so as to be exposed on the surface of the element formation region. Channel region and high concentration Than the first conductivity type channel region in the element forming region between the conductivity type drain region to form a low concentration first conductivity type impurity regions of low concentration,
Forming a high-concentration first-conductivity-type impurity region higher in concentration than the high-concentration first-conductivity-type body in the element-forming region so as to be included in the low-concentration first-conductivity-type impurity region and exposed on the surface of the element-forming region; Forming a source electrode so as to be electrically connected to the high-concentration second-conductivity-type source region and the high-concentration first-conductivity-type impurity region. Since the field plate is formed so as to be electrically connected and to extend in the direction of the high-concentration second conductivity type drain region, electric field concentration can be reduced by the field plate, and between the drain and the source. A semiconductor that can obtain a stable high withstand voltage by expanding the concentration range of the impurity concentration on the element forming region surface of the low-concentration first conductivity type impurity region for obtaining the optimum value of the withstand voltage. It is possible to provide a manufacturing method of the device.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the insulating film under the field plate is formed of a plurality of types of insulating films having different etching rates, and the etching rate of the insulating film is reduced. The step portion is formed in the insulating film by utilizing the difference between them, and the field plate is formed stepwise by forming the field plate on the step portion, so that the field plate can be easily formed stepwise. Thus, a high breakdown voltage can be stably obtained.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth or fifth aspect, a field plate is formed at the same time when an insulating gate is formed, so that the number of steps is increased. Electric field concentration can be alleviated without causing a high withstand voltage stably.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the fourth to sixth aspects, a portion adjacent to the high concentration first conductivity type impurity region in the low concentration first conductivity type impurity region is provided. By using the field plate as a mask and performing ion implantation so as to penetrate the mask, the low-concentration first-conductivity-type impurity region becomes a low-concentration gradient toward the high-concentration second-conductivity-type drain region. , The concentration of the electric field can be further reduced, and a high breakdown voltage can be obtained stably.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, the ion implantation is performed simultaneously with the formation of the high-concentration first conductivity type body or the first conductivity type channel region. Therefore, the concentration of the electric field can be reduced without increasing the number of steps, and a high withstand voltage can be stably obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an LDMOSFET according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the LDMOSFET according to the embodiment.

FIG. 3 is a graph showing p on the surface of an element formation region according to the embodiment.
9 is a graph showing the relationship between the impurity concentration of a negative impurity region and the withstand voltage between the drain and the source.

FIG. 4 is an LDMOSFET according to another embodiment of the present invention.
It is a schematic sectional drawing which shows the manufacturing process of.

FIG. 5 is a schematic sectional view showing an LDMOSFET according to a conventional example.

FIG. 6 is a schematic sectional view showing a manufacturing process of an LDMOSFET according to a conventional example.

FIG. 7 is a graph showing a relationship between an impurity concentration of a p-type impurity region on a surface of an element forming region and a withstand voltage between a drain and a source according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 p-type semiconductor substrate 2 n-type epitaxial layer 3 p ++-type element isolation region 4 element formation region 5 n + -type drain region 6 p + -type body 7 p-type channel region 8 n + -type source region 9 p--type impurity region 10 p ++-type impurity region DESCRIPTION OF SYMBOLS 11 Oxide film 12 Insulated gate 13 Drain electrode 14 Source electrode 15 Field plate

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Nagahama 1048 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Works, Ltd.

Claims (8)

[Claims] 1. A first conductivity type semiconductor substrate, and a first conductivity type formed on one main surface of the first conductivity type semiconductor substrate and formed to reach the first conductivity type semiconductor substrate from a surface. An element formation region including an element isolation region and a second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate, and formed substantially at the center of the element formation region so as to be exposed on the surface of the element formation region. A high-concentration second-conductivity-type drain region, and a drain electrode electrically connected to the high-concentration second-conductivity-type drain region and extending to another element formation region across the element isolation region; A high-concentration first-conductivity-type body formed in the element formation region so as to surround the high-concentration second-conductivity-type drain region and to be exposed on the surface of the element-formation region; And said The high-concentration first formed at a location adjacent to the high-concentration first conductivity-type body in the element formation region so as to be exposed on the surface of the element formation region between the high-concentration first conductivity type body and the high-concentration first conductivity type body. A first conductive type channel region having a lower concentration than the conductive type body, and the high concentration first conductive type body and the first conductive type channel region except for a portion below and near the drain electrode; A high-concentration second-conductivity-type source region formed in the element formation region so as to be exposed on the surface of the element, and interposed between the high-concentration second-conductivity-type source region and the high-concentration second-conductivity-type drain region An insulating gate formed on the first conductivity type channel region via an insulating film, a gate electrode formed to be electrically connected to the insulating gate, and exposed on a surface of the element forming region. So before A low-concentration first-conductivity-type impurity region having a lower concentration than the first-conductivity-type channel region formed in the element formation region between the first-conductivity-type channel region and the high-concentration second-conductivity-type drain region; ,
The high-concentration first conductivity type body, which is included in the low-concentration first conductivity type impurity region and has a higher concentration than the high-concentration first conductivity type body formed in the element formation region so as to be exposed on the surface of the element formation region. A semiconductor device comprising: a conductive impurity region; and a source electrode formed so as to be electrically connected to the high-concentration second conductivity-type source region and the high-concentration first conductivity-type impurity region. A semiconductor device comprising a field plate electrically connected to a first-concentration first-conductivity-type impurity region and extending toward the high-concentration second-conductivity-type drain region. 2. The semiconductor device according to claim 1, wherein said field plate is formed stepwise so as to be away from said low-concentration first conductivity type impurity region. 3. The high-concentration first-conductivity-type impurity region has a concentration gradient so as to have a low concentration toward the high-concentration second-conductivity-type drain region. Alternatively, the semiconductor device according to claim 2. 4. A second conductivity type epitaxial layer is formed on one main surface of the first conductivity type semiconductor substrate, and a second conductivity type epitaxial layer is formed so as to reach the first conductivity type semiconductor substrate from the surface of the second conductivity type epitaxial layer. Forming a first conductivity type element isolation region, and forming an element formation region comprising the first conductivity type element isolation region and the second conductivity type epitaxial layer insulated and separated by the first conductivity type semiconductor substrate; Forming a high-concentration second conductivity type drain region substantially at the center of the element formation region so as to be exposed on the surface of the formation region; electrically connecting to the high concentration second conductivity type drain region; Forming a drain electrode extending to another element formation region across the element formation region, surrounding the high-concentration second-conductivity-type drain region, and forming a drain electrode in the element formation region so as to be exposed on the surface of the element formation region. Dark A first conductivity type body is formed, and is exposed in a surface of the element formation region between the high concentration second conductivity type drain region and the high concentration first conductivity type body. Forming a first conductivity type channel region having a lower concentration than the high concentration first conductivity type body at a location adjacent to the high concentration first conductivity type body, and excluding the lower portion of the drain electrode and the vicinity thereof, Contained in the first conductivity type body and the first conductivity type channel region,
Forming a high-concentration second-conductivity-type source region in the element-forming region so as to be exposed on the surface of the element-forming region; and forming the high-concentration second-conduction-type source region and the high-concentration second-conduction-type drain region. Forming an insulating gate on the first conductivity type channel region interposed therebetween with an insulating film interposed therebetween, forming a gate electrode so as to be electrically connected to the insulating gate, and exposing the gate electrode to a surface of the element forming region. A low-concentration first-conductivity-type impurity region having a lower concentration than the first-conductivity-type channel region in the element formation region between the first-conductivity-type channel region and the high-concentration second-conductivity-type drain region. Formed in the low-concentration first conductivity type impurity region and in the element formation region so as to be exposed on the surface of the device formation region, the high-concentration first conductivity type body having a higher concentration than the high-concentration first conductivity type body. Form one conductivity type impurity region A method of manufacturing a semiconductor device, comprising: forming a source electrode so as to be electrically connected to the high-concentration second conductivity type source region and the high-concentration first conductivity type impurity region; A method of manufacturing a semiconductor device, wherein a field plate is formed so as to be electrically connected to a region and to extend in a direction of the high-concentration second conductivity type drain region. 5. The insulating film below the field plate is composed of a plurality of types of insulating films having different etching rates, and a step portion is formed in the insulating film by utilizing a difference between the etching rates of the insulating films. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said field plate is formed in a step shape by forming said field plate on said stepped portion. 6. The method of manufacturing a semiconductor device according to claim 4, wherein said field plate is formed simultaneously when said insulating gate is formed. 7. The method according to claim 7, wherein the field plate is used as a mask to perform ion implantation at a position adjacent to the high concentration first conductivity type impurity region in the low concentration first conductivity type impurity region so as to penetrate the mask. 7. The low-concentration first-conductivity-type impurity region is provided with a concentration gradient so as to have a low concentration toward the high-concentration second-conductivity-type drain region.
The manufacturing method of the semiconductor device described in the above. 8. The method according to claim 7, wherein the ion implantation is performed simultaneously with the formation of the high-concentration first conductivity type body or the first conductivity type channel region.
The manufacturing method of the semiconductor device described in the above.