JPH10163209A - Semiconductor device and reflection type liquid crystal driving semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the quantity of light entering a device from a via hole part of a highest layer metal by forming at least the upper face of the highest layer writing using a metal where a metal filling the highest via hole can be deposited, and filling the highest via hole with the metal. SOLUTION: In a ship, the third layer metal wiring 40 of the highest layer is formed by TiN/Ti where tungsten W with which the via hole 30 is filled can be deposited. The via hole 30 is filled with W being a filling metal 42. The surface of the second metal wiring 44 lower than the third layer metal wiring 40 being the highest layer by one is coated by a low reflection film 46 constituted of a substance TiN with a low reflection rate. One layer film of Ti, TiN or TiW or the two layer film of Ti and TiN or TiW formed on it can be used for the third layer metal wiring 40. Then, the metal of Mo, Al, Cu and the like can be used for the filling metal 42. Thus, transmission light can be set to almost 0%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having at least two layers of metal and a reflection-type liquid crystal driving semiconductor device in which metal is also spread over regions other than wirings, and more particularly to, for example, a silicon (Si) chip. Irradiated light suitable for use in a semiconductor chip whose surface is irradiated with light, such as a reflective liquid crystal driving element for base liquid crystal,
1. Field of the Invention The present invention relates to a semiconductor device that does not reach a base transistor portion inside the device and cause a malfunction, and a reflective liquid crystal driving semiconductor device using the semiconductor device.

[0002]

2. Description of the Related Art When a transistor is irradiated with light, a current flows due to, for example, recombination. Such a current is unexpected and causes a malfunction of the semiconductor device. In ordinary semiconductor devices, this problem is solved by incorporating the package into a light-impermeable package. However, there is a semiconductor device whose surface is irradiated with light, such as a reflective liquid crystal driving semiconductor device.

In such a semiconductor chip, conventionally, as shown in FIG. 17, a method of shielding light by laying a metal in a region other than the wiring has been devised. In the figure, 10 is a semiconductor substrate made of, for example, silicon Si, 12 is a diffusion layer region serving as a source or a drain formed in a well in the semiconductor substrate 10, and 14 is for electrically isolating elements. LOCOS (Local Oxi
dation of Silicon), 16 is a first interlayer insulating film formed on the semiconductor substrate 10 including the diffusion layer region 12 and LOCOS 14, 18 is the first interlayer insulating film 16
Polysilicon (p-Si) which is a conductor formed therein
The gate 20 is a first-layer metal wiring, which is made to be electrically connected to the diffusion layer region 12 or the polysilicon gate 18 by a contact hole 17 at a necessary position. A first wiring 22 is formed on the first-layer metal wiring 20. The second interlayer insulating film, 24
Is a second layer metal wiring formed on the second interlayer insulating film 22; 26 is a third interlayer insulating film formed on the second layer metal wiring 24; A third-layer metal wiring 32 formed on the insulating film 26 and electrically connected to the second-layer metal wiring 24 via the via hole 30 is a space between the third-layer metal wirings 28.

In this semiconductor chip, in order to prevent the transmission of incident light, metal (usually aluminum-silicon alloy Al-Si) is used in the second layer metal wiring 24 and the third layer metal wiring 28 in regions other than the wiring. To form a dummy wiring and a light shielding band.

However, even in such a semiconductor chip, as the amount of irradiated light increases,
The following problems arise.

That is, when the semiconductor chip is irradiated with light, the irradiated light may reach the diffusion layer region 12 of the underlying transistor through two paths I1 and I2 shown in FIG.

I1. The portion of the via hole 30 of the uppermost layer (third layer) metal wiring 28 has a smaller metal film thickness than the flat portion due to the metal coverage. The light passes through the via hole 30 portion of the upper metal wiring 28 and repeatedly reflects irregularly on the metal surface to reach the underlying transistor.

I2. The irradiated light passes through the space 32 between the uppermost metal wirings 28 where no metal is present,
Again, irregular reflection is repeated on the metal surface to reach the underlying transistor.

The light transmitted through the uppermost metal wiring 28 from the via hole 30 and the space 32 cannot reach the underlying transistor directly because of the light-shielding band. The reflection may be repeated to reach the underlying transistor indirectly.

Conventionally, as a wiring connecting each element of a semiconductor device, a plurality of diffusion layer regions 12 serving as a source and a drain are provided on a semiconductor substrate 10 as shown in an example of a MOS transistor in FIG. This is performed by using a first-layer metal wiring 20 such as aluminum between the diffusion layer regions 12 through the contact holes 17. Each wiring layer varies depending on the arrangement of each element. In FIG. 18, a lower wiring layer formed by the polysilicon gate 18 is also provided.

In this case, as is well known, the flatness of the wiring interlayer film with respect to the lower wiring layer depends on the wiring width and the wiring interval of the polysilicon wiring 18 and the like which are the lower wirings. Dependent. Therefore, assuming that various wiring intervals occur inside the semiconductor device,
There is a problem that the conditions and method for forming the interlayer film become complicated.

To solve such a problem, FIG.
As shown in FIG. 1, electrically independent dummy wirings 21 are provided at wide wiring intervals. By forming such a dummy wiring 21, the wiring interval can be reduced, and the conditions and method for forming an interlayer film can be simplified as compared with the case where there is no dummy wiring.

However, in the conventional method of providing the dummy wiring 21 independent of the normal wiring 20, if the interval between the normal wirings 20 is not wider than the interval at which the dummy wiring having the minimum wiring width allowed in the process can be arranged, the dummy wiring 21 is not provided. There was a problem that wiring could not be inserted.

That is, as shown in FIG. 20, if the distance between the regular wirings 20 is greater than or equal to 2S + L (where S is the minimum wiring distance allowed by the wiring rule, and L is also the minimum wiring width), the width is L. The above-described L + α dummy wiring 21 can be inserted. However, as shown in FIG. 21, if the interval between the regular wirings 20 is less than 2S + L,
Is less than the minimum wiring width L, which violates the design rule, so that the dummy wiring 21 is finally erased and the dummy wiring 21 cannot be left.

As described above, the flattening of the wiring interlayer film depends on the wiring interval. For example, as shown in FIG. 22, as shown in FIG. , General SOG (Spin On Glass)
In the case where the coating film 34 is sandwiched between the CVD oxide films 36 by s), there is an optimum wiring interval for flattening the interlayer film by filling the concave portion with the coating film 34. However, if there is a wiring interval in which a hole cannot be inserted, the interlayer film cannot be sufficiently flattened.

Also, an LSI (Large Scale Integrated) is used.
With the higher integration of d circuit), finer wiring and multilayer wiring have been developed. In order to realize wiring miniaturization and multilayering, it is necessary to secure a depth of focus when exposing a resist pattern in a wiring patterning process, and therefore, planarization in each layer is becoming important. .

One of the methods for flattening each layer is to form a so-called CMP (Chemical Mechanic) by forming an oxide film on the formed wiring and then polishing and flattening a step portion.
calPolishing) method, which is widely used.

The CMP method will be described with reference to FIGS. An interlayer insulating film 16 and a metal wiring 2 formed thereon are previously formed on a semiconductor substrate 10 such as a silicon substrate.
0 is formed by an ordinary method. From this state, first, as shown in FIG. 23, in order to insulate between the metal wirings 20 and between upper wirings (not shown) formed on the metal wirings 20 in a process after the metal wiring 20. An insulating film 22 is formed. Next, the surface of the insulating film 22 is chemically and mechanically polished by a CMP method.
A flat interlayer film as shown in FIG.

When the insulating film 22 is formed in the course of the CMP method, a portion 2 of the insulating film 22 having the lowest surface level is used.
2l needs to be relatively higher than the surface position 20u of the metal wiring 20 by an insulating film thickness required between the wiring and the upper wiring (not shown). There are the following three methods for this.

A. High-density plasma CVD (Chemical Vapor D)
The film is formed using the eposition method.

B. For example, the space between the wirings is buried with SOG (Spin On Glass) or the like.

C. A thick film is formed by a normal CVD method until the wiring is embedded.

However, the high-density plasma CVD method used in the method A is the latest technology at present and requires the introduction of a new apparatus. Further, in the method B, since the film quality of the filling material used in the SOG is poor and the insulating property is low, it is necessary to form a sandwich structure in which the filling material is sandwiched above and below by a material having good insulating properties. Would. Therefore, the C method is often selected. However, even in the C method, in a film formation method with poor coverage that does not reflect the step of the base,
As shown in FIG. 25, an overhang is formed in the upper portion between the wirings, and a void 38 is generated below the overhang. Therefore, when polishing is performed to the level of the broken line A by the CMP method, a recess 22r is formed on the flat surface.

In order to prevent this, for example, TEOS
It is necessary to use a film formation method with good coverage such as a base P-CVD method. However, the wiring spacing
When there is a wide portion of about 5 μm, as shown in FIG.
Since the ratio (film formation ratio) of the thickness B of the insulating film 22 deposited on the wiring 20 to the thickness C of the insulating film 22 deposited between the wirings is about 5 to 3, for example, a step (wiring In the case where the thickness of the wiring is 5000 ° and the insulating film thickness of 5000 ° is to be left on the wiring after the CMP process, the insulating film on the wiring is formed to be considerably thick as about 17000Å = (5000Å + 5000Å) × 5 ÷ 3, After that, it is necessary to polish about 12000Å = 17000Å-5000Å by the CMP method, which causes a large loss in the throughput of the apparatus and the manufacturing cost.

In order to prevent this, a dummy pattern is arranged between the metal wirings 20 to reduce the distance between the wirings, the space between the wirings is filled by film growth from the wiring side wall 20s, and the insulating film thickness required before the CMP is reduced. It is devised to do so. However, even in this method, as shown in FIG. 26, the film formation ratio on the wiring side wall 20s is considerably low, for example, B: D = 5: 2, so that the wirings arranged in parallel as shown in FIG. There is a problem that a slight increase in the wiring interval, which occurs when the substrate 20 is bent, leads to an increase in the thickness of the insulating film before the CMP, which lowers the throughput and increases the manufacturing cost. Was. In the example shown in FIG. 27, the wiring interval between the wiring straight portions is 1.2 μm, but the wiring bent portion has 1.2. √ Spread to 2 μm.

In the wiring pattern of FIG. 27, the minimum insulating film thickness between the wiring pattern and the upper wiring is
Consider the case of forming a flat insulating film as Å. On a silicon substrate (not shown), an interlayer insulating film 16 and a metal wiring 20 having a thickness of 6000.degree.
It is assumed that it is formed by an ordinary method using the pattern No. 7. At this time, a cross-sectional view along the line EE in FIG. 27, which is the widest wiring interval in the pattern, is as shown in FIG. From this state, using a P-TEOS CVD apparatus which is an insulating film forming apparatus having good coverage, an insulating film 22 for insulating the upper wiring is formed. P-TE
In the OS CVD apparatus, the film formation ratio between the upper part of the wiring and the side wall is 5
Since there are two pairs, the wiring interval shown in FIG.
In order to embed m, as shown in FIG.
A film thickness of Å is required. Since the maximum thickness at which a stable film can be formed at one time by the P-TEOS CVD apparatus is 9000 °, the film is formed by dividing 7000 ° into three times. The shape after film formation is as shown in FIG. From this state, CM
Polishing 14000 ° with P provides a desired flat insulating film shape as shown in FIG.

As described above, in the wiring pattern of FIG.
After the insulating film 16 is formed at 21000 ° or more in three times, if it is not polished by CMP at 14000 °, the structure shown in FIG.
Such a flat insulating film cannot be formed.

[0028]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to reduce the amount of light entering the device from a via hole portion of the uppermost metal. Make it an issue.

Another object of the present invention is to prevent light entering the device from reaching the underlying transistor due to multiple reflection.

According to the present invention, the wiring interval between S and L + 2S, which does not allow the insertion of dummy wiring in the conventional method, is reduced to facilitate the flattening of the interlayer film and the area of the light-shielding band. And reducing the amount of light entering the lower layer is a third problem.

A fourth object of the present invention is to make it possible to form an insulating film, which needs to be planarized in a later step, with a minimum necessary thickness.

A fifth object of the present invention is to provide a reflective liquid crystal driving semiconductor device formed integrally with a chip.

[0033]

According to a first aspect of the present invention, there is provided a semiconductor device having a multi-layered wiring, wherein at least one layer of the multi-layered wiring has a space between wirings where a dummy wiring is allowed to be inserted into a region other than the wiring. Is provided with a dummy wiring, at least the lower surface of the uppermost layer wiring is formed of a metal that can be deposited in the uppermost via hole connecting the uppermost layer wiring and the wiring under the uppermost layer, and at least the upper surface of the uppermost layer wiring, The metal that fills the top via hole is made of metal that can be deposited,
The first problem is solved by filling the uppermost via hole with metal.

Here, the uppermost layer wiring is made of titanium Ti,
It can be formed of a single layer film of titanium nitride TiN or titanium tungsten alloy TiW, or a two-layer film of Ti and TiN or TiW deposited thereon.

The uppermost layer wiring may further include another metal such as an aluminum-based alloy deposited thereon.

Further, the uppermost via hole can be filled with tungsten W, molybdenum Mo, aluminum Al or copper Cu.

As described above, by filling the uppermost via hole with a metal such as W, the effective film thickness of the metal in the via hole portion is increased, so that light can be prevented from entering from the uppermost via hole.

According to a first aspect of the present invention, there is provided a semiconductor device having at least two layers of wirings in which a metal is also spread in a region other than the wirings. The second problem has been solved by forming the material with a low material.

Here, the surface of the wiring one layer below the uppermost wiring can be formed of TiN.

As described above, at least the surface of the wiring one layer below the uppermost wiring is formed of a material having a low reflectivity particularly in the visible light region, such as TiN, so that light is reflected by the underlying transistor by multiple reflection. Is prevented from reaching.

According to a first aspect of the present invention, at least the lower surface of the uppermost wiring is formed of a material on which a metal filling the via hole can be deposited, and the via hole is filled with the metal and one layer of the uppermost wiring is formed. Both the first and second problems are solved by forming at least the surface of the lower wiring with a material having a low reflectance particularly in the visible light region.

According to a second aspect of the present invention, in a semiconductor device in which multilayer wiring is performed, a dummy wiring is provided in a space between at least one layer of the multilayer wiring where the dummy wiring can be inserted, and the dummy wiring is provided. The space between wirings where insertion is not allowed is reduced from the space between normal wirings, thereby solving the third problem.

Further, the plurality of wiring patterns facing the inter-wiring space are made to be substantially equally thick.

According to a third aspect of the present invention, in the semiconductor device having the multilayer wiring, the wiring interval of the wiring bent portion of at least one wiring pattern is made narrower than that in the case of the simple bent pattern, whereby the fourth object is achieved. Is solved.

Further, the wiring interval of the wiring bent portion is set as follows.
It is narrowed by making corners on the outer wiring corners.

Further, the inside wiring corners are cut off so that the wiring intervals at the bent portions are not too narrow.

Further, the wiring interval of the wiring bent portion is set as follows.
The distance is set to be equal to or less than the wiring interval of the wiring straight portion.

According to a fourth aspect of the present invention, there is provided a reflection type liquid crystal driving semiconductor device having at least two layers of wiring in which a metal is spread also in a region other than the wiring, and at least the lower surface of the uppermost wiring is the uppermost layer. The uppermost via hole is formed of a metal capable of depositing a metal filling the uppermost via hole, and the uppermost via hole is formed of a metal capable of depositing a metal filling the uppermost via hole. The via hole is filled with metal, and at least the surface of the wiring one layer below the uppermost wiring is formed of a material having low reflectivity, and a space between wirings where insertion of a dummy wiring is not allowed is formed in the wiring space. A semiconductor chip that is reduced by thickening a wiring pattern facing the semiconductor chip, and a reflective liquid that is disposed on the semiconductor chip and that is driven by the semiconductor chip. By providing a part it is obtained by solving the fifth problem of.

[0049]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In the first embodiment according to the first invention, as shown in FIG. 1, a semiconductor substrate 10 made of Si, a diffusion layer region 12, a LOCOS 14, a first interlayer insulating film 16
, Contact hole 17 and polysilicon gate 18
A first layer metal wiring 20 made of, for example, Al-Si;
In a semiconductor chip having an interlayer insulating film 22 and a third interlayer insulating film 26 and having a metal spread over a region other than the wiring, the third-layer metal wiring 40 of the uppermost layer is formed by tungsten filling the via hole 30. TiN / T on which W can be deposited
i, the via hole 30 is filled with W, which is a filling metal 42, and the third-layer metal wiring 40 of the uppermost layer is formed.
The surface of the second-layer metal wiring 44 one layer below is covered with a low-reflection film 46 made of a material having low reflectance (TiN in the embodiment).

This semiconductor chip can be manufactured by the following procedure.

That is, first, as shown in FIG.
0, a well is formed, element isolation is performed by LOCOS 14, a gate oxide film is formed by oxidation, polysilicon is deposited thereon, and a gate 18 is patterned.
The diffusion layer region 12 is formed, and the first interlayer insulating film 16 is formed of, for example, NSG (Non-doped Silicon Glass) and BPS.
A two-layer structure of G (Boron-Phosphorous Silicon Glass), a contact hole 17 is opened, and a first-layer metal wiring 20 is formed of Al-Si (S
i 1%) is deposited at about 3000 to 8000 °, and metal patterning is performed.

Next, as shown in FIG. 3, the second interlayer insulating film 22 is formed by plasma CVD (Chemical Vapor Depos) using TEOS (Si (OC ₂ H ₅ ) ₄ ) as a raw material, for example.
oxide film (referred to as p-TEOS), organic SOG (Spin on Glass), and again p-TEO
The first via hole 23 is formed as a three-layer structure of S.

Next, as shown in FIG. 4, Al-Si is deposited as the second-layer metal wiring 44 by, for example, about 3000-8000 ° by sputtering, and then TiN forming the low-reflection film 46 is deposited for 200-200 nm. The second-layer metal wiring 44 is patterned by depositing about 1000 °. This second-layer metal wiring 44 also serves as a light-shielding band.

Next, as shown in FIG. 5, as the third interlayer insulating film 26, for example, p-TEOS is 1.0 to 2.0 μm
Deposition to the extent of CMP (Chemical Mechanical Polish)
ng), about 0.5 to 1.0 μm is polished, and p-TEOS or plasma silicon nitride p is further polished.
Deposit about 0.2 to 0.5 μm of SiN; And
The second via hole 30 is opened.

Next, as shown in FIG. 6, the second interlayer insulating film 2 is formed.
Ti that is easy to adhere to 6 and has good familiarity
Deposited to a certain degree, and having sufficient conductivity and corrosion resistance.
iN is deposited in a thickness of about 1000 to 3000 ° by a sputtering method.

Further, as shown in FIG. 7, tungsten W is deposited by the CVD method at a temperature of about 5000 to 15000.degree., And the deposited film is etched back by the thickness of the deposited metal to fill only the inside of the second via hole 30 with the filling metal. Some W
Remain, and W in the other portion is completely removed.
Here, TiN / Ti is deposited before CVD of W because W is deposited only on a metal portion.

Further, by patterning TiN / Ti, a semiconductor device according to the first invention as shown in FIG. 1 is obtained.

In this embodiment, the uppermost third-layer metal wiring 40 is formed of TiN / Ti.
A single-layer film of N or TiW or a two-layer film of Ti and TiN or TiW formed thereon can be used. Note that the configuration and material of the uppermost layer wiring are not limited to those described above.
On N / Ti, for example, Al, Al-Si, Al-Cu
It is also possible to deposit a metal having higher conductivity, such as an Al-based alloy, and pattern it to form the uppermost layer wiring. In this case, the conductivity of the uppermost wiring can be further increased.

In this embodiment, since the via holes are filled with W, subsequent etch-back is easy, and only the via holes can be filled with metal. The filling metal is not limited to this, but Mo,
Metals such as Al and Cu can be used.

In a conventional semiconductor device having a multi-layered wiring, a via hole is filled with metal and an interlayer insulating film formed thereon is planarized in order to make a smooth connection between wiring layers. For the upper layer wiring, there is no need to further form wiring on it, so it is not necessary to bury metal in the uppermost via hole, which increases the cost, so metal is buried in the uppermost via hole. Had not been. According to the first aspect of the invention, in order to prevent light from entering the inside of the semiconductor, the via hole of the uppermost layer wiring having the highest effect is filled with metal.

In this embodiment, since the surface of the second-layer wiring one layer below the uppermost-layer wiring is covered with TiN, the reflection of the surface can be achieved without lowering the conductivity of the second-layer wiring. Rate can be reduced. Note that the configuration and material of the second-layer wiring are not limited to those described above.
Instead of -Si or TiN, other materials may be used, or the entire second layer wiring may be formed of a material having a low reflectance.

Next, the second invention will be described as a specific example with reference to the second embodiment.

In this embodiment, the minimum wiring width L is 1.4 μm, and the minimum wiring interval S is 1.0 μm.
Further, in order to perform patterning, it is necessary to use a reticle, but in order to form a reticle, there is a minimum spot size G for that purpose. Here, this is 0.1 μm.

FIG. 8 shows a state in which the normal wiring 20 between the diffusion layer regions is formed by the conventional technique.

FIG. 9 shows a state where a dummy wiring 23 is added to the normal wiring 20 shown in FIG. 8 by a conventional method. When arranging the dummy wiring, for example, an inverted pattern (pattern of a non-wiring portion) of the regular wiring 20 shown in FIG. 8 is formed, and this inverted pattern is formed by, for example, S + (L / 2) = 1.0 + (1). ./4/2)=1.7 μm undersize, and then L / 2 = 1.4 / 2 = 0.7 μm oversize, so that the dummy wiring whose spacing from the regular wiring 20 is the minimum wiring spacing S is obtained. 21 can be generated.

Here, instead of simply undersizing the inverted pattern of the wiring area by S, it is necessary to oversize by L / 2 and then oversize by L / 2 to restore the original pattern. If the size is simply undersized by S, a portion violating the rule of the minimum wiring width L occurs, and this is to prevent this. For example, if the wiring interval is 3.0 μm, the undersized S of the inverted pattern has a width of 3.0− (2 × 1.0) = 1.0 μm due to the undersize of the inverted pattern having a width of 3 μm. This violates the wiring width of 1.4 μm. On the other hand, if the size is S + (L / 2), the pattern becomes 3.0− (2 × 1.7) = − 0.4 μm. No violations occur.

By generating the dummy wiring 21 by such an operation and combining it with the regular wiring 20, a wiring pattern after the dummy wiring is inserted can be obtained. FIG.
This state is shown. The wiring interval M after the dummy wiring is inserted is 2 × {S + (L / 2)} = 2 × {1.0+ (1.4 / 1.4
2)｝ = less than 3.4 μm.

The pattern as shown in FIG. 9 is obtained by the conventional technique, and the method of inserting the dummy wiring is not limited to the method described above.

FIG. 10 shows a specific example in which the inter-wiring interval of the pattern in which the dummy wiring shown in FIG. 9 is inserted is reduced to the minimum inter-wiring interval according to the second invention.

In the present embodiment, in the above specific example, the space between the wirings where the insertion of the dummy wiring is not allowed and the minimum spacing S is equal to or more than 1.0 μm and 2S + L = 3.4 μm is set to the wiring facing the space between the wirings. It is characterized in that it is reduced by thickening the pattern. Thereby, the planarization of the subsequently formed interlayer insulating film and the area of the light-shielding band are increased,
The amount of light entering the lower layer can be reduced.

Further, the wiring pattern facing the space between the wirings is substantially uniformly thickened.

Further, it is desirable that the inter-wiring space is reduced to a minimum wiring interval. The specific realization method is not particularly limited, and can be realized by CAD.

Next, a third embodiment according to the third invention will be described in detail.

In this embodiment, as shown in FIG. 11, 45 ° corners are formed at the outer wiring corners in the wiring bent portion as shown in FIG. 27, so that the wiring interval of the wiring bent portion is reduced. This is set to be equal to or less than the wiring interval of the straight traveling portion.

The film forming process of this embodiment is compared with FIGS. 28, 29 and 30 of the conventional example, and FIGS.
As shown in FIG. In the case of the wiring pattern of FIG. 11, a case will be described in which a flat insulating film having a wiring step of 6000 ° and a minimum insulating film thickness between the upper layer wiring and 7000 ° is formed as in the conventional example.

An interlayer insulating film 16 and a metal wiring 20 having a thickness of 6000.degree. Formed on the interlayer insulating film 16 on a silicon substrate (not shown) in advance by a normal method using the pattern shown in FIG. And At this time, a cross-sectional view along the line FF in FIG. 11, which is the widest wiring interval in the pattern, is as shown in FIG. From this state, PT
An insulating film 22 that insulates the upper wiring is formed by using EOS CVD. In P-TEOS CVD equipment,
Since the film formation ratio between the upper part of the wiring and the side wall is 5: 2, FIG.
In order to embed 1.2 μm between the wirings shown in FIG.
As shown in the figure, a film thickness of about 14000 ° is required. P-
Since the maximum thickness at which a stable film can be formed at one time by the TEOS CVD apparatus is 9000 °, the film is formed by dividing 7000 ° into two times. The shape after film formation is as shown in FIG. From this state, 7000mm polishing by CMP,
A desired flat insulating film shape as shown in FIG. 14 is obtained.

As described above, when the wiring pattern shown in FIG. 11 is used, the insulating film is divided into two times, and the film is formed at 14000.degree. And polished by CMP at 7000.degree. To form the flat insulating film 22 shown in FIG. it can.

It is empirically known that, when the polishing is performed by the CMP method, if the shaving amount is large, the in-plane uniformity of the polished surface is reduced. However, according to the present embodiment, the polishing by the CMP method is performed. Since the amount can be reduced from 14000 ° to 7000 °, not only the throughput is improved, but also the in-plane uniformity is improved. Note that the polishing method is not limited to the CMP method.

In this embodiment, since only corners are formed on the outer wiring pattern, the wiring interval of the bent portion is 1 / √2 of the wiring interval of the straight portion, but the design of the wiring pattern is difficult. Easy.

The method of narrowing the wiring interval between the wiring bent portions as compared with the case of a simple bent pattern as shown in FIG. 27 is not limited to this, and is different from that of the fourth embodiment shown in FIG. It is also possible to make corners at the outer wiring corners and cut corners at the inner wiring corners. In this case, the wiring interval of the bent part is
The interval can be set to be close to the interval of the wiring of the straight section.

Next, a fifth embodiment according to the fourth invention will be described in detail.

FIG. 16 is a sectional view showing the structure of a reflective liquid crystal driving semiconductor device according to the sixth embodiment.

In this embodiment, a P + buried region 112 and an N + buried region 114 are formed on a semiconductor substrate 10 made of, for example, P-type silicon by, for example, buried epitaxial, and a P well 116 and an N well are respectively formed thereon. 11
8 are formed. The P well 116 and the N well 11
8 are separated by, for example, a LOCOS 14. The source region 12 is formed on each of the wells 116 and 118, respectively.
2. By forming the drain region 124 and the gate 18, high-breakdown-voltage transistors are formed in a matrix.

On the first interlayer insulating film 16 covering the transistor portion, for example, a first aluminum (Al) -based material
The layer metal wiring 20 is formed. The bent portion of the first-layer metal wiring 20 may or may not be cornered according to the third invention.

On the second interlayer insulating film 22 covering the first-layer metal wiring 20, a second-layer metal wiring
4 are formed. A third covering the second-layer metal wiring 24;
On the interlayer insulating film 26, a third-layer metal wiring 140 made of, for example, an Al-based material is formed. This third layer metal wiring 14
The surface of 0 is laminated with TiN and has low reflection according to the first invention.

The surface of the fourth interlayer insulating film (uppermost interlayer insulating film) 142 covering the third-layer metal wiring 140 is polished and flattened by a CMP method, and a P-SiN layer 144 is formed as an upper layer. According to the first invention, for example, TiN / T
A fourth layer metal wiring (uppermost layer wiring) 146 of i material is formed. According to the first invention, W is filled as the filling metal 42 in the via hole 30 that connects the fourth-layer metal wiring 146 and the third-layer metal wiring 140.

All or some of the metal wirings in each layer are provided with dummy wirings as required, and the space between the wirings is reduced by the second invention.

The fourth-layer metal wiring 146 serves as a liquid crystal pixel electrode layer disposed on a chip.

A liquid crystal driving chip 148 is formed from the semiconductor substrate 10 to the fourth layer metal wiring 146, and a liquid crystal unit 150 is disposed on the chip 148.

The liquid crystal part 150 has a dielectric reflection film 152 whose reflection surface is flattened into a mirror surface for reflecting the incoming light.
And a transparent electrode 154 disposed thereon with a space therebetween.
And a liquid crystal 156 sealed between the dielectric reflection film 152 and the transparent electrode 154, and a glass 158 for protecting the liquid crystal disposed on the transparent electrode 154.

In this liquid crystal driving semiconductor device, the S-polarized light incident from the glass surface in the direction of arrow G is converted into S + P-polarized light again in the surface direction by the mirror-flattened dielectric reflection film 152. At the time of reflection, the intensity of the reflected light is changed by changing the driving state of transistors formed in a matrix for each pixel on the chip 148, thereby changing the arrangement state of the liquid crystal, thereby forming an image. ing.

Chip 14 adopting first to third inventions
Since the configuration and operation other than 8 are the same as those of the known Si chip-based liquid crystal, detailed description is omitted.

In this embodiment, the first to third inventions are applied to the reflection type liquid crystal driving semiconductor device, but the application of the first to third inventions is not limited to this.

[0095]

According to the first aspect of the present invention, when W is not buried in the via hole 30 and the thickness of TiN / Ti is 1500 ° / 300 °, the thickness of the via hole 30 is 1000 ° / By embedding W in the via hole 30, the transmitted light could be reduced to almost 0%.

On the other hand, considering the case where the light transmitted through the space 32 of the third-layer metal wiring is multiply reflected between the second-layer metal wiring and the third-layer metal wiring, the reflectance of Al-Si is set to 0.1.
90, the reflectance of Ti under the third-layer metal wiring 40 is 0.9
0, the reflectance of TiN on the surface of the second-layer metal wiring 44 is 0.1
If TiN is not used on the surface of the second-layer metal wiring 44, the light intensity after six reflections is 0.90, that is, 0.6.
The power is about 53%. On the other hand, according to the first invention,
When the surface of the second-layer metal wiring 44 is made of TiN, 0.1.
The product of the cube of 9 and the cube of 0.1 is 0.07%, which has the effect of almost completely blocking the multiple reflected light.

As an additional effect, when any insulating film is deposited on the third-layer metal wiring 40 by, for example, a method such as evaporation, the via hole 30 is buried according to the first invention. As a result, the insulating film in the via hole portion is properly deposited, and the insulating film is hardly peeled off, and the reliability is also improved.

Further, according to the second aspect of the present invention, it is possible to increase the width of the wiring layer on both sides and reduce the wiring interval even if the wiring interval is such that a dummy wiring cannot be inserted. Therefore, the coverage of the upper layer wiring can be further improved, wiring defects can be eliminated, and a wiring with higher reliability can be formed by simplifying the manufacturing method. Further, the effect of blocking light can be increased.

Further, even when the coupling capacitance of the wiring is a problem, optimization can be achieved by appropriately selecting the final maximum wiring interval value F.

According to the third aspect of the present invention, the thickness of the insulating film before polishing for obtaining a desired flat insulating film can be reduced to the minimum necessary, thereby improving the throughput of the film forming apparatus and the polishing apparatus. And the manufacturing cost can be reduced. In the case of flattening by the CMP method, the polishing amount can be reduced, and the flatness is improved.

Further, according to the fourth invention, it is possible to provide a reflection type liquid crystal driving semiconductor device formed integrally with a chip.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor chip of a first embodiment according to a first invention;

FIG. 2 is a cross-sectional view showing a state in which a first-layer metal wiring is patterned, for explaining a manufacturing process of the first embodiment;

FIG. 3 is a sectional view showing a state in which a first via hole is opened in a second interlayer insulating film in a manufacturing process of the first embodiment.

FIG. 4 is a sectional view showing a state where a second-layer metal wiring is patterned in a manufacturing process of the first embodiment;

FIG. 5 is a sectional view showing a state in which a second via hole is opened in a third interlayer insulating film in a manufacturing process of the first embodiment.

FIG. 6 is a sectional view showing a state where a third-layer metal wiring is deposited in the manufacturing process of the first embodiment;

FIG. 7 is a sectional view showing a state in which metal is filled in a second via hole in a manufacturing process of the first embodiment.

FIG. 8 is a top view showing a normal circuit pattern before dummy wiring is inserted, for explaining a second embodiment according to the second invention;

9 is a top view showing a state where a dummy wiring is inserted into the circuit pattern of FIG. 8;

10 is a top view of an example in which a wiring pattern facing an inter-wiring space where insertion of a dummy wiring of the circuit pattern of FIG. 9 is not allowed is thickened;

FIG. 11 is a plan view showing an example of a wiring pattern according to a third embodiment according to the third invention;

FIG. 12 is a sectional view taken along the line FF of FIG. 11;

FIG. 13 is a sectional view showing a state immediately after an insulating film is formed on the metal wiring of FIG. 12;

14 is a cross-sectional view showing a state after the insulating film of FIG. 13 has been polished to a predetermined thickness.

FIG. 15 is a plan view showing an example of a wiring pattern according to a fourth embodiment according to the third invention;

FIG. 16 is a partial cross-sectional view showing a main part of a reflective liquid crystal driving semiconductor device according to a fifth embodiment of the fourth invention;

FIG. 17 is a cross-sectional view showing a configuration of a semiconductor chip in which a metal is spread over a region other than the conventional wiring.

FIG. 18 is a top view showing an example of a multilayer wiring in a conventional MOS transistor.

FIG. 19 is a top view showing a state where dummy wiring is added to the wiring pattern of FIG. 18;

FIG. 20 is a top view showing a conventional state where a dummy wiring is inserted in a place where there is a sufficient wiring interval;

FIG. 21 is a top view showing a conventional state in which a dummy wiring is to be arranged in a place where a wiring interval is insufficient.

FIG. 22 is a cross-sectional view of a semiconductor chip for describing a problem of the related art.

FIG. 23 is a sectional view showing a conventional state immediately after an insulating film is formed on a metal wiring;

24 is a cross-sectional view showing a state after polishing the insulating film of FIG. 23;

FIG. 25 is a cross-sectional view showing a conventional state in which an insulating film is formed on a wiring by a film forming method with poor coverage.

FIG. 26 is a diagram for explaining a conventional film forming ratio.

FIG. 27 is a plan view showing an example of a conventional simple bent pattern.

FIG. 28 is a sectional view taken along the line EE in FIG. 27;

FIG. 29 is a sectional view showing a state immediately after an insulating film is formed on the metal wiring of FIG. 28;

FIG. 30 is a sectional view showing a state after the insulating film of FIG. 29 has been polished to a predetermined thickness;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... Diffusion layer area 14 ... LOCOS 16 ... 1st interlayer insulation film 18 ... Polysilicon 20, 20R, 20L ... 1st layer metal wiring 21 ... Dummy wiring 22 ... 2nd interlayer insulation film 24, 44 ... Two-layer metal wiring 26 ... Third interlayer insulating film 28, 40 ... Third-layer metal wiring 23, 30 ... Via hole 42 ... Filling metal 46 ... Low reflection film 50, 52, 54, 56 ... Virtual wiring pattern 50N, 52N .. 56N notch 148 semiconductor chip 150 liquid crystal unit 154 liquid crystal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Mizuno 2-3-2 Uchisaiwaicho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation Tokyo Main Office (72) Inventor Masanori Iwahashi 2-3-2 Uchisaiwaicho, Chiyoda-ku, Tokyo No. Kawasaki Steel Corporation Tokyo Head Office (72) Inventor Toshihiro Shimizu 2-3-2 Uchisaiwaicho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation Tokyo Headquarters (72) Inventor Masaaki Fujishima 2-chome Uchisaiwaicho, Chiyoda-ku, Tokyo No. 3 Kawasaki Steel Corporation Tokyo Head Office (72) Inventor Koji Hanihara 465 Osatocho, Kofu City, Yamanashi Prefecture Inside (72) Inventor Itaru Tsuchiya 465 Osatocho, Kofu City, Yamanashi Prefecture Pioneer Video Stock Inside the company (72) Inventor Yasuo Yagi 2680 Nishihanawa, Tatomi-cho, Nakakoma-gun, Yamanashi Prefecture Pioneer Corporation

Claims (5)

[Claims] In a semiconductor device in which multilayer wiring is performed, at least one layer of the multilayer wiring is provided with a dummy wiring in a space between wirings where insertion of a dummy wiring is allowed in a region other than the wiring. At least the lower surface of the wiring is the uppermost wiring and the first wiring.
It is formed of a metal that can be deposited in the uppermost via hole connecting the wiring under the layer, and at least the upper surface of the uppermost wiring is
A semiconductor device, wherein a metal filling a top via hole is formed of a depositable metal, and the top via hole is filled with a metal. 2. A semiconductor device having at least two layers of wiring, in which metal is also spread in a region other than the wiring, wherein at least the surface of the wiring one layer below the uppermost wiring is formed of a material having a low reflectance. A semiconductor device characterized by the above-mentioned. 3. A semiconductor device in which multilayer wiring is performed, wherein a dummy wiring is provided in a space between wirings where insertion of dummy wiring is allowed in at least one layer of the multilayer wiring, and between wirings where insertion of dummy wiring is not allowed. A semiconductor device, wherein a space is reduced from a space between normal wirings. 4. A semiconductor device having a multi-layer wiring, wherein a wiring interval of a wiring bent portion of at least one wiring pattern is narrower than a case of a simple bent pattern. 5. A semiconductor device comprising at least two layers of wiring in which metal is also spread in a region other than the wiring, wherein at least the lower surface of the uppermost wiring is formed by the uppermost wiring and the first wiring.
It is formed of a metal that can be deposited in the uppermost via hole connecting the wiring under the layer, and at least the upper surface of the uppermost wiring is
A metal filling the uppermost via hole is formed of a metal that can be deposited, the via hole is filled with the metal, and at least a surface of the wiring one layer below the uppermost wiring is formed of a material having a low reflectance. The space between the wirings where the insertion of the dummy wiring is not allowed is reduced by enlarging the wiring pattern facing the space between the wirings, and the semiconductor chip disposed on the semiconductor chip is driven by the semiconductor chip. And a reflection type liquid crystal unit.