JP2000058649A - Manufacture of semiconductor device comprising multilayer interconnection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce capacitance between adjoining wirings, corresponding to a minute multilayer interconnection, and to connect with sure an interlayer connection metal to the wiring of upper and lower layers for preventing short failures. SOLUTION: After an insulating film 202, a first metal layer 203, and a first interlayer insulating film 204 are sequentially formed on a semiconductor substrate 201, an opening part is formed at the first interlayer insulating film 204, while an interlayer connection metal 208 is formed at the opening part. After a first wiring is formed by selectively removing a part of the first interlayer insulating film 204, the first metal layer 203, and the insulating film 202 by photolithography and dry- etching, a second interlayer insulating film 212 is formed using a plasma CVD apparatus. After the second interlayer insulating film 212 is flattened, its surface is partially etched. After that, a third interlayer insulating film 214 is deposited. The third interlayer insulating film 214 is so flattened by a CMP method that the surface of the third interlayer insulating film 214 is in the same plane of the upper surface of the interlayer connection metal 208 and the surface of the first interlayer insulating film 204. A second wiring 216 is so formed as to connect to the interlayer connection metal 208.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art A remarkable progress in semiconductor processing technology in recent years has made it possible to make wirings and devices ultra-fine and highly integrated, so that the performance of ULSI has been improved. However, with the integration of wiring, the delay of a signal in the wiring determines the speed of the device. Therefore, in the ULSI of the so-called 0.25 μm generation or later, as the material of the interlayer insulating film, a material having a low relative dielectric constant, for example, a material having a low relative dielectric constant instead of the conventional SiO ₂ (relative dielectric constant ε = 4.3) is used. SiOF doped with fluorine (ε =
3.5) and SiO: C (ε = 2.8 to 3.2) containing organic substances are being used. However, these materials have problems in terms of hygroscopicity and heat resistance, so that it is difficult to construct a process using the materials.

Further, in order to reduce a delay between wirings, which is a particularly large delay, a hole formed by air (ε = 1.0) is intentionally provided in an insulating material between wirings. A technique for lowering the relative dielectric constant between wirings has been proposed (Japanese Patent Application Laid-Open No. 62-5643). Hereinafter, this technique will be described with reference to FIG. FIG. 20 is a cross-sectional view showing the structure of a conventional semiconductor device.
In FIG. 20, a hole 6 is provided between the wirings 3 and 4 and a hole 7 is provided between the wirings 4 and 5 in the insulating substance 2 provided on the semiconductor substrate 1 of the semiconductor device. As a material of the insulating substance 2, SiO ₂ is used. The capacitance between the wiring 3 and the wiring 4 is equal to the capacitance between the wiring 3 and the hole 6, the capacitance of the hole 6 itself, and the capacitance between the hole 6 and the wiring 4 connected in series. Can be considered. Material of insulating substance 2 which is a portion other than the holes SiO
Compared to the relative dielectric constant of _2, the relative dielectric constant of the void formed by air is about 1/4. Therefore, by providing the holes, the capacitance between adjacent wirings can be reduced. As a result, a signal delay between adjacent wirings can be suppressed, so that a semiconductor device having a wide operation margin and hardly malfunctioning can be realized, and a low-cost process can be achieved because there is no need to use a new material.

[0004]

However, according to the above conventional structure, the wiring and the interlayer connection hole are designed so as to be borderless, that is, designed so that the wiring width and the diameter of the interlayer connection hole have the same dimensions, and When the misalignment occurs in the photolithography process, the following problem occurs. First, since the interlayer connection hole and the hole are integrated when the interlayer connection hole is opened, a short circuit failure of the wiring occurs due to the metal for interlayer connection entering the integrated region. Second, the connection area between the metal for interlayer connection in the interlayer connection hole and the wiring is small, so that a connection failure occurs.

[0005] These defects will be described with reference to FIGS. 21 and 22. 21 (a), 21 (b) and 22
(A) to (c) are process flow diagrams showing a conventional method for manufacturing a multilayer wiring included in a semiconductor device. First, as shown in FIG. 21A, an insulating film 12, a first wiring 13, and an interlayer insulating film 14 are sequentially formed on a semiconductor substrate 11. Since SiO ₂ deposited by the plasma CVD method is used as the interlayer insulating film 14, the step coverage is poor. That is, the ratio of the deposited film thickness in the wiring gap 15 which is a region between the first wirings 13 to the deposited film thickness in the flat portion is low. As a result, the wiring gap 1
5, holes 16 are formed in the interlayer insulating film 14. However, since the step coverage does not become 0%, not all of the wiring gaps 15 become voids, and the interlayer insulating film 14 exists between the wirings. Therefore, for the purpose of reducing the relative dielectric constant between the wirings, a method of further lowering the deposition rate of the interlayer insulating film 14 in the wiring gap 15 to lower the relative dielectric constant can be considered. In this case,
The holes 16 occupy a larger area. Next, FIG.
As shown in (b), the interlayer insulating film 14 is planarized by removing a part of the interlayer insulating film 14 by using a resist etch back method, a chemical mechanical polishing (CMP) method, or the like.

Next, as shown in FIG. 22A, an interlayer connection hole 17 is formed by using photolithography and dry etching. Here, the wiring width of the first wiring 18
And the diameter 19 of the interlayer connection hole are the same size, and
Consider a case where an alignment shift of only the shift size 20 occurs in photolithography. In this case,
The interlayer connection hole 17 at a position shifted from the upper surface of the first wiring 13 due to the alignment shift is formed deeper than the position of the upper surface. Therefore, the interlayer connection hole 17 is
Integrate with Next, as shown in FIG. 22B, an interlayer connection metal 21 made of tungsten is formed in the interlayer connection hole 17 by using a CVD method. Since the tungsten 21 formed by the CVD method has good step coverage, it fills not only the interlayer connection holes 17 in FIG. As a result, via the interlayer connection metal 21 formed in the portion that was the hole 16,
Short-circuit failure in which adjacent first wirings 13 are connected to each other occurs. If an attempt is made to lower the relative dielectric constant in the wiring gap 15, the holes 16 occupy a larger area, so that short-circuit defects are more likely to occur. On the other hand, FIG.
If the deviation dimension 20 in (a) is further increased, the connection area between the first wiring 13 and the metal 21 for interlayer connection buried in the interlayer connection hole 17 becomes smaller. A connection failure with the metal for interlayer connection 21 occurs. In particular, when an organic material is used as the material of the interlayer insulating film 14, the connection failure easily occurs. When the etching is performed deeper in the interlayer connection hole 17, the first metal 21 for interlayer connection is formed.
Short-circuit failure in which the wiring 13 and the semiconductor substrate 11 are connected to each other occurs. Next, as shown in FIG. 22C, a second wiring 22 to be connected to the first wiring 13 via the metal 21 for interlayer connection is formed by the metal 21 for interlayer connection and the interlayer insulating film 14. Formed on

The present invention has been made in view of the above-mentioned conventional problems, and provides a semiconductor device and a method of manufacturing the same, which minimizes inter-wiring capacitance and hardly causes short-circuit failure or connection failure even when an alignment shift occurs. The purpose is to:

[0008]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, comprising the steps of: covering a surface of a substrate with an insulating film; Depositing, forming a first interlayer insulating film on the conductive film, forming an interlayer connection hole reaching the conductive film in the first interlayer insulating film, Embedding a metal for interlayer connection into the first wiring layer; and forming a masking layer defining a first wiring layer pattern on the first interlayer insulating film so as to cover at least a part of the metal for interlayer connection. The first interlayer insulating film is etched using the masking layer as a mask, and the conductive film is etched using the masking layer and the interlayer connection metal as a mask.
Forming a wiring layer, removing the masking layer, and depositing a second interlayer insulating film on the substrate to cover the interlayer connection metal and a first wiring layer;
Exposing at least a portion of the metal for interlayer connection by flattening the second interlayer insulating film; and forming a second wiring layer electrically connected to an upper portion of the metal for interlayer connection. Forming.

According to another method of manufacturing a semiconductor device of the present invention, a step of covering the surface of a substrate with an insulating film, a step of depositing a conductive film on the insulating film, and a step of forming a first interlayer insulating film on the conductive film Forming an interlayer connection hole reaching the conductive film in the first interlayer insulating film; embedding a metal for interlayer connection in the interlayer connection hole; Partially etching the upper surface of the metal for interlayer connection from the first interlayer insulating film, and forming a masking layer for defining a first wiring layer pattern with the metal for interlayer connection. Forming on the first interlayer insulating film so as to cover at least a part of the first interlayer insulating film; and etching the first interlayer insulating film using the masking layer as a mask to remove the masking layer and the interlayer connecting metal. Make a mask Etching the conductive film, thereby forming a first wiring layer from the conductive film, removing the masking layer, and forming a second interlayer so as to cover the interlayer connection metal and the first wiring layer. Depositing an insulating film on the substrate, flattening the second interlayer insulating film to expose at least a part of the metal for interlayer connection, and an upper portion of the metal for interlayer connection. Forming a second wiring layer electrically connected to the second wiring layer.

It is preferable that the etching of the conductive film is performed so that the interlayer connection metal is not substantially etched.

The step of forming the second interlayer insulating film includes:
It is preferable that voids formed of a closed region where the second interlayer insulating film does not exist are also formed in the wiring gap between the first wirings.

In the step of flattening the second interlayer insulating film, it is preferable that the holes are not exposed.

It is preferable that the dielectric constant of the material used for the second interlayer insulating film is smaller than the dielectric constant of the material used for the first interlayer insulating film.

The step of forming the second interlayer insulating film includes:
Forming a first interlayer insulating layer forming a part of the second interlayer insulating film, and forming a second interlayer insulating layer forming another part of the second interlayer insulating film into the first interlayer insulating film; Forming the first interlayer insulating layer, wherein in the step of forming the first interlayer insulating layer, voids are formed in a gap of 0.5 μm or less among gaps formed by the first wiring layer. In the step of substantially covering the gap of 0.5 μm or less with the first interlayer insulating layer and forming the second interlayer insulating layer, the step of forming the second interlayer insulating layer may include: A part of the second interlayer insulating layer may enter a gap that is not substantially covered by the first interlayer insulating layer.

As the first interlayer insulating layer, silane / N ₂
First plasma CV formed using O-based gas plasma
D membranes can be used.

As the second interlayer insulating layer, a second plasma CVD film formed by using high-density plasma to which a substrate bias voltage is applied can be used.

In the step of forming the first wiring layer, the first interlayer insulating film and the conductive film are etched using the masking layer as a mask, and then a part of a base insulating film of the conductive film is etched. And forming a groove on the surface of the insulating film.

In the step of forming the second wiring layer, a groove is formed on the surface of the first interlayer insulating film by etching at least the first interlayer insulating film using the groove forming pattern as a mask. Forming a second metal layer on the metal for interlayer connection, the first interlayer insulating film, and the second interlayer insulating film; and forming a second metal layer inside the trench in the second metal layer. Forming a second wiring by removing a portion other than the above.

According to still another method of manufacturing a semiconductor device of the present invention, there is provided a lower wiring layer including a plurality of wirings formed on the same insulating film, wherein the plurality of wirings include a first wiring,
A lower wiring layer including a second wiring adjacent to the first wiring at a first gap and a third wiring adjacent to the first wiring at a second gap wider than the first gap; Forming a structure having a first interlayer insulating film formed on the first wiring, the second wiring, and the third wiring; and substantially blocking the space above the first gap. , The first
Depositing a first interlayer insulating layer forming a lower portion of the second interlayer insulating film so as to form a hole in the gap between the first interlayer insulating film, and forming an upper portion of the second interlayer insulating film. Depositing a second interlayer insulating layer having better coverage than the interlayer insulating layer to fill the second gap and completely cover the holes.

Preferably, the method further includes a step of flattening the second interlayer insulating film so as not to expose the holes.

It is preferable that the second interlayer insulating layer is formed of an organic film having a lower dielectric constant than the first interlayer insulating layer.

The semiconductor device according to the present invention is a lower wiring layer comprising a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are a first wiring and a first wiring from the first wiring. A lower wiring layer including a second wiring adjacent with a gap therebetween, and a third wiring adjacent with a second gap from the first wiring, the first wiring, the second wiring, and the third wiring A first interlayer insulating film formed on the first wiring, a connection metal formed in the first interlayer insulating film and in contact with an upper surface of the first wiring, the first gap and the second gap. A second interlayer insulating film formed above the gap and forming a hole in each of the first gap and the second gap;
And an upper wiring layer electrically connected to the metal for interlayer connection.

The upper wiring layer may be a wiring having a buried structure, and the upper wiring layer may be formed in the second interlayer insulating film.

The lower insulating film of the lower wiring layer has a groove formed below the first gap and the second gap, and a groove is formed in the groove from an upper surface of the lower insulating film. And a part of the second interlayer insulating film having a height that does not protrude upward.

The upper end portion of the metal for interlayer connection is the first
It is preferable to project above the upper surface of the interlayer insulating film.

The first wiring has a side surface portion locally protruding toward the second wiring and / or the third wiring, and the upper surface of the side surface portion is covered with the metal for interlayer connection. It may be. Further, it is preferable that the side surface portion of the first wiring is formed in a self-aligned manner with respect to the metal for interlayer connection.

A semiconductor device according to the present invention is a lower wiring layer composed of a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are a first wiring and a first wiring from the first wiring. A lower wiring layer including a second wiring adjacent with a gap therebetween, and a third wiring adjacent with a second gap from the first wiring, the first wiring, the second wiring, and the third wiring A first interlayer insulating film formed thereon and a second interlayer insulating film covering the lower wiring layer and having an upper surface planarized, wherein the second gap is larger than the first gap. Broadly, the second interlayer insulating film includes a first interlayer insulating layer and a second interlayer insulating layer formed on the first interlayer insulating layer.
The first interlayer insulating layer and the second interlayer insulating layer block the upper part of the first gap, and a hole is formed in the first gap, The second gap is filled with the first interlayer insulating layer and the second interlayer insulating layer.

It is preferable that the second interlayer insulating layer has better coverage than the first interlayer insulating layer.

The first interlayer insulating layer is formed from a silicon oxide film, and the second interlayer insulating layer is formed from an organic coating film having a dielectric constant lower than that of the first interlayer insulating layer. Is preferred.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, comprising: forming a first interlayer insulating film on a first wiring layer; Forming an interlayer connection hole in the interlayer insulating film, embedding an interlayer connection metal in the opened interlayer connection hole, and using the first wiring pattern as a mask to form the first interlayer insulating film and the first interlayer insulating film. By sequentially etching the wiring layer, the first
Forming the first wiring, and forming the first interlayer insulating film and the first
Forming a second interlayer insulating film on the semiconductor substrate on which the wiring is formed, and removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed. Flattening the surfaces of the second interlayer insulating film, the first interlayer insulating film, and the metal for interlayer connection so as to be on the same plane, and forming a second metal layer on the same plane Forming a second wiring by etching the second metal layer using the second wiring pattern as a mask.

Another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring,
A first interlayer insulating film is formed on the first wiring layer, an interlayer connection hole is opened in the formed first interlayer insulating film, and an interlayer connection metal is buried in the opened interlayer connection hole. Forming a first wiring by sequentially etching the first interlayer insulating film and the first wiring layer using the first wiring pattern as a mask; and forming the first interlayer insulating film. Forming a second interlayer insulating film on the semiconductor substrate on which the film and the first wiring are formed; and removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed Thereby, a step of flattening the surfaces of the second interlayer insulating film, the first interlayer insulating film, and the metal for interlayer connection so as to be flush with each other, and at least using the groove forming pattern as a mask The first interlayer insulating film is etched to form the first interlayer insulating film. Forming a groove having a predetermined depth from the surface of the interlayer insulating film; and forming a second metal layer on the metal for interlayer connection, the first interlayer insulating film, and the second interlayer insulating film. Forming a second wiring by removing a portion of the second metal layer other than inside the trench.

Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, wherein a first interlayer insulating film is formed on a first wiring layer formed on an insulating film. Forming a film, forming an interlayer connection hole in the formed first interlayer insulating film, embedding a metal for interlayer connection in the opened interlayer connection hole, and masking the first wiring resist pattern. Forming a first wiring by sequentially etching the first interlayer insulating film, the first wiring layer, and at least a part of the insulating film using the first interlayer insulating film;
Forming a second interlayer insulating film on the semiconductor substrate on which the first wiring is formed, and removing the second interlayer insulating film until the surface of the metal for interlayer connection is exposed; Flattening the surfaces of the two interlayer insulating films and the metal for interlayer connection so as to be on the same plane, forming a second metal layer on the same plane, and forming a second wiring resist pattern. Forming a second wiring by etching the second metal layer using masking for masking.

Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, wherein a first interlayer insulating film is formed on a first wiring layer formed on an insulating film. Forming a film, opening an interlayer connection hole in the formed first interlayer insulating film, and embedding a metal for interlayer connection in the opened interlayer connection hole; and forming a film from the surface of the first interlayer insulating film. Forming a first wiring by etching a part of the first interlayer insulating film and the first wiring layer sequentially using a first wiring resist pattern for masking; Forming a second interlayer insulating film on the semiconductor substrate on which the first wiring has been formed; and forming the second interlayer insulating film on the semiconductor substrate until the surface of the metal for interlayer connection is exposed.
Removing the interlayer insulating film to planarize the surfaces of the second interlayer insulating film and the metal for interlayer connection so as to be flush with each other;
Forming a second wiring by etching the second metal layer using the second wiring resist pattern for masking.

Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, wherein a first interlayer insulating film is formed on a first wiring layer formed on an insulating film. Forming a film, forming an interlayer connection hole in the formed first interlayer insulating film, embedding a metal for interlayer connection in the opened interlayer connection hole, and masking the first wiring resist pattern. Forming a first wiring by sequentially etching the first interlayer insulating film, the first wiring layer, and the insulating film using the first wiring, and forming the first wiring on the semiconductor substrate on which the first wiring is formed. Forming the second interlayer insulating film and removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed, thereby forming the second interlayer insulating film and the first interlayer insulating film. So that the surfaces of the interlayer insulating film and the surface of each have the same plane Carrying out the step of supporting, selectively etching the surface of the second interlayer insulating film, and then depositing a third interlayer insulating film; and forming the third interlayer insulating film until the surface of the first interlayer insulating film is exposed. Removing the third interlayer insulating film to flatten the surfaces of the third interlayer insulating film, the first interlayer insulating film, and the interlayer connection metal so as to be flush with each other. Forming a second metal layer on the flat surface and forming the second wiring by etching the second metal layer using the second wiring resist pattern for masking. .

It is preferable that the semiconductor device further includes a void formed of a closed region where the second interlayer insulating film does not exist in the wiring gap between the first wirings.

It is preferable that the dielectric constant of the second interlayer insulating film is smaller than the dielectric constant of the first interlayer insulating film.

[0037] Before the step of forming the first wiring, the method may further include a step of partially etching the surface of the first interlayer insulating film.

As a method of forming the second interlayer insulating film, high-density plasma CVD may be used.

As a method of forming the second interlayer insulating film, a high-density plasma CV with a bias voltage applied to a substrate is used.
D may be used.

It is preferable that the dielectric constant of the material used for the second interlayer insulating film is smaller than the dielectric constant of the material used for the first interlayer insulating film.

In the step of flattening the second interlayer insulating film, it is preferable to use chemical mechanical polishing.

The step of forming the second interlayer insulating film includes:
Forming a first interlayer insulating layer forming a part of the second interlayer insulating film, and forming a second interlayer insulating layer forming another part of the second interlayer insulating film into the first interlayer insulating film; A step of forming on a layer may be included.

In the step of forming the first interlayer insulating layer, an interval of the gap formed by the first wiring layer is set to 0.
In the step of forming the second interlayer insulating layer, the first interlayer insulating layer substantially covers the gap of 0.5 μm or less by the first interlayer insulating layer so as to form a hole in the gap of 5 μm or less. In the gap formed by the first wiring layer, a part of the second interlayer insulating layer may enter a gap that is not substantially covered by the first interlayer insulating layer.

As the first interlayer insulating layer, silane / N ₂
First plasma CV formed using O-based gas plasma
A D film may be used.

As the second interlayer insulating layer, a second plasma CVD film formed using high-density plasma to which a substrate bias voltage is applied may be used.

In the step of flattening the second interlayer insulating film, the second interlayer insulating layer may be removed without removing the first interlayer insulating layer.

The step of forming the second interlayer insulating film includes:
It is preferable that the height of the upper end of the hole measured from the upper surface of the first wiring be 500 nm or less.

The step of forming the second interlayer insulating film includes:
The gap formed by the first wiring layer is 0.8 μm.
It is preferable to form holes in gaps of m or less.

The step of forming the second interlayer insulating film includes:
The gap formed by the first wiring layer is 0.5 μm.
It is preferable to form pores having a porosity of 0.5 or more in gaps of m or less.

In the step of flattening the second interlayer insulating film, the second interlayer insulating layer may be removed without removing the first interlayer insulating layer.

A semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, which is used for connecting a first wiring formed on a semiconductor substrate to the first wiring and a wiring of another layer. A metal for interlayer connection formed on the first wiring, and the first metal other than the portion where the metal for interlayer connection is present;
A first interlayer insulating film formed in all regions of the wiring, and a second interlayer insulating film formed in all regions other than the first wiring when the semiconductor substrate is viewed in a plan view; A second wiring formed at least on the metal for interlayer connection and connected to the first wiring via the metal for interlayer connection.

Another semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, and comprises a plurality of first wiring layers arranged on an insulating film, and a plurality of first wiring layers on each of the plurality of first wiring layers. A first interlayer insulating film formed in the first interlayer insulating film, an interlayer connecting hole opened in the first interlayer insulating film and located on the plurality of first wiring layers, and embedded in the interlayer connecting hole; A metal for interlayer connection in contact with a first wiring layer, a second interlayer insulating film formed so as to cover the plurality of first wiring layers, and the plurality of first wiring layers; A concave portion formed on the surface of the insulating film.

Still another semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, and comprises a plurality of first wiring layers arranged on an insulating film, and each of the plurality of first wiring layers. A first interlayer insulating film formed thereon, an interlayer connection hole opened in the first interlayer insulating film, located on the plurality of first wiring layers, and buried in the interlayer connection hole; A metal for interlayer connection in contact with the first wiring layer;
And a second interlayer insulating film provided on a region where the wiring layer is not formed, wherein the upper surface of the metal for interlayer connection protrudes above the upper surface of the first interlayer insulating film. The second interlayer insulating film includes: the plurality of first wiring layers; a first interlayer insulating layer forming a part of the second interlayer insulating film;
A second interlayer insulating layer forming another part of the second interlayer insulating film, wherein the first interlayer insulating layer has a gap of 0.5 μm or less in a gap formed by the first wiring layer. The gap substantially covers the gap of 0.5 μm or less so as to form a hole in the gap, and a part of the second interlayer insulating layer is formed of the gap formed by the first wiring layer. It is preferable that the semiconductor device enters the gap substantially not covered by the first interlayer insulating layer.

It is preferable that the height of the upper end of the hole measured from the upper surface of the first wiring is 500 nm or less.

It is preferable that voids are formed in gaps formed by the first wiring layer with a gap of 0.8 μm or less.

It is preferable that voids having a porosity of 0.5 or more are formed in gaps having an interval of 0.5 μm or less among the gaps formed by the first wiring layer.

[0057]

(First Embodiment) A first embodiment of the present invention.
Will be described with reference to FIGS. FIG.
FIGS. 2A to 2D and FIGS. 2A to 2C are process flow charts showing a method for manufacturing a semiconductor device according to the present embodiment. First, as shown in FIG. 1A, a semiconductor substrate 101 on which a semiconductor active element (not shown) is formed in advance,
An insulating film 102 (0.8 μm in thickness), a first metal layer 103 (0.5 μm in thickness) having a laminated structure of aluminum and a titanium alloy, and a first interlayer insulating film 104 (1.0 μm in thickness)
m) are sequentially deposited. Thereafter, an interlayer connection resist pattern 105 is formed, and an interlayer connection hole 106 is opened by dry etching.

Next, as shown in FIG. 1B, an adhesion layer 107 made of, for example, TiN / Ti is deposited on the surface having the interlayer connection holes 106 after the interlayer connection resist pattern 105 is peeled off. Then, an interlayer connection material 108 made of tungsten is deposited by blanket W-CVD. The adhesion layer 107 and the interlayer connection material 1 existing outside the interlayer connection hole 106 by dry etching or CMP.
08 is removed. The adhesion 107 and the interlayer connection material 108 that exist only inside the interlayer connection hole 106 together form a metal 109 for interlayer connection.

Next, as shown in FIG. 1C, the first interlayer insulating film 104 and the metal
The wiring resist pattern (masking layer defining the first wiring layer pattern) 110 is formed. Consider a case where the first wiring resist pattern 110 is formed with a misalignment by a misalignment dimension 111. For example, when the diameter of the interlayer connection hole 106 is 0.3 μm and the width of the first wiring resist pattern 110 is 0.3 μm,
Metal 10 for interlayer connection buried in interlayer connection hole 106
The allowable deviation dimension 111 between the first wiring pattern 9 and the first wiring resist pattern 110 is 0.1 μm at the maximum.

FIG. 3A is a plan view showing a relationship between the displacement of the first wiring resist pattern 110 and the metal 109 for interlayer connection. The position of the first wiring resist pattern 110 is located below the wavy line in FIG.
The position of the first wiring resist pattern 110 and the position of the interlayer connection metal 109 match on the upper side of the wavy line.

Next, as shown in FIG. 1D, a first wiring is formed by using a CF-based etching gas for patterning an oxide film and a Cl-based etching gas for patterning an aluminum film. Resist pattern 11
0, the first wiring resist pattern 11
Dry etching is sequentially performed using 0 as a mask. First, the first interlayer insulating film 104 in the opening of the first wiring resist pattern 110 is removed by dry etching using a CF-based etching gas at a low temperature. In this case, the metal 109 for interlayer connection in the misaligned portion 112 is hardly etched by the CF-based etching gas. Further, the insulating film 10 is formed by dry etching using a Cl-based etching gas.
2 until the first wiring resist pattern 110 is exposed.
The first metal layer 103 in the opening is removed. Thus, a first wiring 113A is formed. Also in this case, the metal 109 for interlayer connection in the misaligned portion 112 is not etched by the Cl-based etching gas. In the etching for forming the first wiring 113A, both the first wiring resist pattern 110 and the interlayer connection metal 109 function as an etching mask.

FIG. 3B is a perspective view showing the positional relationship between the first wiring 113 and the metal for interlayer connection 109 corresponding to the presence or absence of misalignment. First, the first metal layer 10
From 3, the case of the wiring 113B formed by dry etching without any misalignment will be considered. In this case, an interlayer connection metal 109 having the same diameter as the width of the wiring 113B is formed on the upper surface of the wiring 113B. On the other hand, consider the case of the wiring 113C formed out of alignment with the first metal layer by dry etching. In this case, the first metal layer located below the interlayer connection metal 109 is not etched during the dry etching. Therefore, in the misaligned portion 112 in FIG. 8A, the first metal layer located under the interlayer connection metal 109 remains without being etched by self-alignment, and thus has a shape as shown in FIG. Is formed. Accordingly, the first wiring 113A including the wiring 113B or the wiring 113C is always formed on the entire lower surface of the interlayer connection metal 109. In addition, since the portion below the first wiring resist pattern 110 in FIG. 8A is not etched, the portion above the first wiring 113A where the interlayer connection metal 109 does not exist is the first portion. The interlayer insulating film 104 remains. As a result, the first interlayer insulating film 1 is formed on the first wiring 113A.
04 or the metal 109 for interlayer connection is always present. Therefore, the first metal layer 103 under the interlayer connection metal 109 or the first wiring resist pattern 110 forms the first wiring 113A. The total thickness of the first wiring 113A formed from the first metal layer 103 and the first interlayer insulating film 104 is 1.5 μm.
Therefore, the aspect ratio of the groove 115 formed in the portion having the minimum width of 0.3 μm in the wiring gap 114 which is a region between the adjacent first wirings 113A is about 5.
Note that the field portion 116 where the first wiring does not exist is provided.
Alternatively, a wiring dummy pattern may be formed.

As described above, according to this embodiment, the plane pattern of both the first interlayer insulating film 104 and the metal for interlayer connection 109 defines the plane pattern of the first wiring 113A.

Next, as shown in FIG. 2A, the insulating film 102 and the first interlayer insulating film 1 of the semiconductor substrate 101 after the first wiring resist pattern 110 is released.
04, a second interlayer insulating film 117 is deposited on the interlayer connection metal 109 using a plasma CVD apparatus. Part or all of the region of the wiring gap 114 in the groove formed in the wiring gap 114 becomes a hole 118 without being filled with the second interlayer insulating film 117.
In particular, in a groove having a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118.

Next, as shown in FIG. 2B, the surfaces of the first interlayer insulating film 104, the metal 109 for interlayer connection, and the second interlayer insulating film 117 are substantially the same by using the CMP method. The second interlayer insulating film 117 is planarized so as to be flat. First interlayer insulating film 104 and second interlayer insulating film 117
Are made of different materials, and the CM of the first interlayer insulating film 104 is
The etching rate at P is lower than the second interlayer insulating film 11.
7 is set to be smaller than the etching rate. Thus, the first interlayer insulating film 104 is used as an etching stopper. Second interlayer insulating film 11
7 is buried to some extent in the upper part of the groove having a high aspect ratio, so that the hole 118 does not form an opening in the surface of the second interlayer insulating film 117 after the CMP.

Next, as shown in FIG. 2C, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 119 is formed using photolithography and dry etching. .

As described above, according to the present embodiment, a part or the whole of the region of the wiring gap 114 becomes the air hole 118 made of air, so that the space between the first wirings 113A sandwiching the wiring gap 114 is formed. The relative dielectric constant can be reduced. In particular, when the groove 115 formed in the wiring gap 114 has a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118, so that the relative dielectric constant between the first wirings 113A is minimized. can do.

Also, since the first wiring 113A is formed after the formation of the interlayer connection metal 109, the first wiring 11A must be formed over the entire lower surface of the interlayer connection metal 109.
3A is formed. Therefore, poor connection between the first wiring 113A and the metal for interlayer connection 109 can be prevented.

After the metal 109 for interlayer connection is formed in the interlayer connection hole 106 of the first interlayer insulating film 104, the first
Of the wiring 113A and the second interlayer insulating film 117 are sequentially formed. As a result, even if the misalignment occurs during the formation of the first wiring, either the metal 109 for interlayer connection or the first interlayer insulating film 104 always exists on the upper surface of the first wiring 113A, and The metal for interlayer connection 109 is not buried in the hole 118 formed simultaneously with the second interlayer insulating film 117. Therefore, short-circuit failure between the first wirings 113A and short-circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109 can be prevented.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. 4 (a) to 4 (c)
FIG. 2 is a process flow chart showing a method for manufacturing a semiconductor device according to the embodiment. The steps leading up to FIG.
Since these are the same as (a) to (d), the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. In the present embodiment, the second interlayer insulating film 217 is formed by a coating method instead of depositing the second interlayer insulating film 117 by the plasma CVD apparatus in the first embodiment. Second interlayer insulating film 217
For example, an organic film made of a material such as an organic polysiloxane or an organic material containing fluorine, an inorganic porous film, or the like can be considered. Many of these materials have fluidity.

First, as shown in FIG. 4A, the first interlayer insulating film 104, the metal for interlayer connection 109, the wiring gap 21
4 is coated with the above material. Accordingly, the second interlayer insulating film 217 can be formed by filling the material having the fluidity into the groove in the wiring gap 214 without generating a hole. As a material of the second interlayer insulating film 217, a material having a lower relative dielectric constant than that of the first interlayer insulating film 104 is selected. Therefore, the first wiring 1 sandwiching the wiring gap 214
The relative dielectric constant between 13A can be reduced. Next, FIG.
As shown in (b), the second interlayer insulating film 104, the metal for interlayer connection 109, and the second interlayer insulating film 217 are formed using the CMP method so that the surfaces of the second interlayer insulating film 104 and the second interlayer insulating film 217 are flush with each other. Is flattened. First interlayer insulating film 104
And the second interlayer insulating film 217 are made of different materials,
Is set such that the etching rate of the interlayer insulating film 104 in CMP is lower than the etching rate of the second interlayer insulating film 217. Thus, the first interlayer insulating film 104 is used as an etching stopper. Next, as shown in FIG. 4C, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second layer is formed using photolithography and dry etching.
Is formed.

As described above, according to the present embodiment, the entire area of the wiring gap 214 is formed by the second interlayer insulating film 217 using a material having a lower relative dielectric constant than the first interlayer insulating film 104. Embed Therefore, the relative dielectric constant between the first wirings 113A sandwiching the wiring gap 214 can be reduced, and the relative dielectric constant can be determined by the material of the second interlayer insulating film 217.

Further, since the first wiring 113A is formed after the formation of the metal for interlayer connection 109, the first wiring 11A must be formed over the entire lower surface of the metal for interlayer connection 109.
3A is formed. Therefore, poor connection between the first wiring 113A and the metal for interlayer connection 109 can be prevented.

After the metal 109 for interlayer connection is formed in the interlayer connection hole of the first interlayer insulating film 104, the first wiring 113A and the second interlayer insulating film 217 are sequentially formed.
As a result, even if misalignment occurs during the formation of the first wiring, either the metal 109 for interlayer connection or the first interlayer insulating film 104 must be present on the upper surface of the first wiring 113A, and The second interlayer insulating film 217 always exists in the gap 214. Therefore, short-circuit failure between the first wirings 113A and short-circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109 can be prevented.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 4D is a process flow chart illustrating the method for manufacturing the semiconductor device according to the embodiment. Steps up to FIG. 5A are the same as those of the first embodiment, that is, FIGS. 1A to 1A, except that the thickness (2.5 μm) of the first interlayer insulating film 304 is increased.
2D and FIGS. 2A and 2B, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 5A, a second wiring inversion resist pattern 320 is formed on the first interlayer insulating film 304, the metal 309 for interlayer connection, and the second interlayer insulating film 317. It is formed by photolithography. The second wiring inversion resist pattern 320 has a displacement dimension 3
A case where the alignment is formed by 11 is considered. For example, the diameter of the interlayer connection hole is 0.3 μm, and the width of the groove of the second wiring inversion resist pattern 320 is 0.1 μm.
In the case of 3 μm, the allowable deviation 311 between the interlayer connection metal 309 buried in the interlayer connection hole and the groove of the second wiring inverted resist pattern 320 is:
The maximum is 0.1 μm. Next, as shown in FIG. 5B, the first interlayer insulating film 304 and the second interlayer insulating film 317 are formed.
To form a wiring groove 3 having a depth of 0.5 μm.
21A is formed. Next, as shown in FIG. 5C, an adhesion layer (not shown) made of a titanium alloy
Is deposited, a second metal layer 322 made of aluminum, an alloy of aluminum and copper, copper, or the like is formed.
In order to form the second metal layer 322, a vacuum evaporation method or C
The VD method or the like is used. Next, as shown in FIG. 5D, the second metal layer existing outside the wiring groove is removed by a CMP method to form a second wiring 323.

The second wiring inversion resist pattern 320
The relationship between the displacement of the second wiring 323 due to the displacement and the metal 309 for interlayer connection will be described with reference to FIGS. 6 and 5B to 5D. FIG. 6 is a perspective view showing the positional relationship between the wiring groove in which the second wiring is to be formed and the metal for interlayer connection, corresponding to the presence or absence of misalignment. In FIG. 6, the case of a wiring groove 321B formed without a misalignment by dry etching will be considered. In this case, a wiring groove 321B having the same width as the diameter of the interlayer connection metal 309 is formed. The second wiring is the wiring groove 32
1B, the interlayer connection metal 309 and the second metal 309 are almost entirely formed on the side surfaces of the interlayer connection metal 309.
Contacts with other wiring. On the other hand, by dry etching,
Consider the case of a wiring groove 321C formed with misalignment. In this case, the wiring groove 321C having the same width as the diameter of the interlayer connection metal 309 is formed shifted by the shift dimension 311 in FIG. 5B. Since the metal 309 for interlayer connection is not etched, the portion of the side surface of the metal 309 for interlayer connection other than the portion that has been cut into the first interlayer insulating film 304 by the deviation dimension 111 is exposed to the wiring groove 321C. Therefore, most of the side surfaces of the metal 309 for interlayer connection correspond to the second metal layer 32 in FIG.
2 and also contacts the second wiring 323 in FIG. 5D after the CMP.

As described above, according to the present embodiment, even if the second wiring inversion resist pattern 320 for forming the second wiring 323 is misaligned, the side surface of the interlayer connection metal 309 can be removed. Most contacts the second wiring 323. Therefore, in addition to the same effects as in the first embodiment, even when the second wiring inversion resist pattern 320 is misaligned, the reliability of the connection between the interlayer connection metal 309 and the second wiring 323 is improved. Can be improved.

(Fourth Embodiment) A semiconductor according to this embodiment will be described with reference to FIGS. 7A to 7D, FIGS. 8A to 8C and FIGS. 9A and 9B. A method for manufacturing the device will be described.

First, as shown in FIG. 7A, an insulating film 102 (thickness 0.8 μm), an aluminum alloy and a titanium alloy are formed on a semiconductor substrate 101 on which a semiconductor active element (not shown) is formed in advance. Metal layer 103 having a laminated structure of
(Thickness: 0.5 μm) and a first interlayer insulating film 104 (thickness: 1.0 μm) are sequentially deposited. Thereafter, an interlayer connection resist pattern 105 is formed, and an interlayer connection hole 106 is opened by dry etching.

Next, as shown in FIG. 7B, an adhesion layer 107 made of, for example, TiN / Ti is deposited on the surface having the interlayer connection holes 106 after the interlayer connection resist pattern 105 has been peeled off. Then, an interlayer connection material 108 made of tungsten is deposited by blanket W-CVD. The adhesion layer 107 and the interlayer connection material 1 existing outside the interlayer connection hole 106 by dry etching or CMP.
08 is removed. The adhesion 107 and the interlayer connection material 108 that exist only inside the interlayer connection hole 106 together form a metal 109 for interlayer connection.

Next, as shown in FIG. 7C, the first interlayer insulating film 104 is etched back by about 0.5 μm,
The remaining film thickness of the interlayer insulating film 104 is adjusted to 0.5 μm. At this time, the metal for interlayer connection 109 protrudes upward from the surface of the first interlayer insulating film 104.

Next, as shown in FIG. 7D, the first interlayer insulating film 104 and the metal
The wiring resist pattern 110 is formed. Consider a case where the first wiring resist pattern 110 is formed with a misalignment by a misalignment dimension 111. For example, when the diameter of the interlayer connection hole 106 is 0.3 μm and the width of the first wiring resist pattern 110 is 0.3 μm, the first metal 110 for the interlayer connection embedded in the interlayer connection hole 106 and the first The allowable deviation dimension 111 from the wiring resist pattern 110 is 0.1 μm at the maximum.

FIG. 3A is a plan view showing the relationship between the displacement of the first wiring resist pattern 110 and the metal 109 for interlayer connection. The position of the first wiring resist pattern 110 is located below the wavy line in FIG.
The position of the first wiring resist pattern 110 and the position of the interlayer connection metal 109 match on the upper side of the wavy line.

Next, as shown in FIG. 8A, a CF-based etching gas for removing an oxide film and a Cl-based etching gas for removing aluminum are used.
The surface having the first wiring resist pattern 110 is sequentially dry-etched. First, the first interlayer insulating film 104 in the opening of the first wiring resist pattern 110 is removed by dry etching using a CF-based etching gas at a low temperature. In this case, the interlayer connection metal 109 in the misaligned portion 112 is
It is not etched by the CF-based etching gas.
Further, the first metal layer 103 in the opening of the first wiring resist pattern 110 is removed by dry etching using a Cl-based etching gas until the insulating film 102 is exposed. As a result, the first wiring 11
Form 3A. Also in this case, the metal 109 for interlayer connection in the misaligned portion 112 is not etched by the Cl-based etching gas.

FIG. 3B is a perspective view showing the positional relationship between the first wiring 113 and the metal 109 for interlayer connection corresponding to the presence or absence of misalignment. First, the first metal layer 10
From 3, the case of the wiring 113B formed by dry etching without any misalignment will be considered. In this case, an interlayer connection metal 109 having the same diameter as the width of the wiring 113B is formed on the upper surface of the wiring 113B. On the other hand, consider the case of the wiring 113C formed out of alignment with the first metal layer by dry etching. In this case, the first metal layer located below the interlayer connection metal 109 is not etched during the dry etching. Therefore, in the misaligned portion 112 in FIG. 8A, the first metal layer located under the interlayer connection metal 109 remains without being etched by self-alignment, and thus has a shape as shown in FIG. Is formed. Accordingly, the first wiring 113A including the wiring 113B or the wiring 113C is always formed on the entire lower surface of the interlayer connection metal 109. In addition, since the portion below the first wiring resist pattern 110 in FIG. 8A is not etched, the portion above the first wiring 113A where the interlayer connection metal 109 does not exist is the first portion. The interlayer insulating film 104 remains. As a result, the first interlayer insulating film 1 is formed on the first wiring 113A.
04 or the metal 109 for interlayer connection is always present.

Next, as shown in FIG. 8B, the insulating film 102 is carved by about 0.5 μm by dry etching using a CF-based etching gas. As a result, the first wiring 113A having a shape sandwiched between the upper and lower insulating films is formed. The non-engraved insulating film immediately below the first wiring 113A is referred to as 112A. Therefore, the first metal layer 103 under the interlayer connection metal 109 or the first wiring resist pattern 110 forms the first wiring 113A.

The total thickness of the first wiring 113A formed from the first metal layer 103, the first interlayer insulating film 104, and the insulating film 112A is 1.5 μm. Therefore, the aspect ratio of the groove 115 formed in the portion having the minimum width of 0.3 μm in the wiring gap 114 which is a region between the adjacent first wirings 113A is about 5. Note that a wiring dummy pattern may be formed on the field portion 116 where the first wiring does not exist.

Next, as shown in FIG. 8C, after the first wiring resist pattern 110 is released, the insulating film 102 and the first interlayer insulating film 1 of the semiconductor substrate 101 are removed.
04, a second interlayer insulating film 117 is deposited on the interlayer connection metal 109 using a plasma CVD apparatus. The wiring gap 1 in the groove formed in the wiring gap 114
Part or all of the region 14 is formed by the second interlayer insulating film 117.
In some cases, the holes 118 are not filled. In particular, in a trench having a high aspect ratio, the wiring gap 11
The entirety of the region 4 becomes the hole 118. Next, FIG.
As shown in FIG.
The second interlayer insulating film 117 is planarized so that the surface of the second interlayer insulating film 117 and the surface of the second interlayer insulating film 117 are flush with each other. Since the second interlayer insulating film 117 is buried to some extent in the upper part of the trench having the high aspect ratio, the void 118 forms an opening in the surface of the second interlayer insulating film 117 after the CMP. There is no. Next, as shown in FIG. 3B, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and the second wiring 119 is formed using photolithography and dry etching.
To form

Here, with reference to FIGS. 10A and 10B and FIGS. 11A and 11B, what is the form of the holes formed by the method of depositing the second interlayer insulating film 117? Will be described.

First, reference is made to FIG. FIG.
(A) shows an ideal form in which the second interlayer insulating film 117 does not enter the groove 115 at all, and the holes occupy the whole of the groove 115. In this case, since there is no insulating film between the adjacent wirings 113A, the capacitance C1 between the wirings is extremely small. In the case shown in FIG. 10A, the upper ends of the holes do not extend above the upper surface of the first interlayer insulating film 104. Therefore, the second interlayer insulating film 1
Even if 17 is polished by the CMP method, there is a small possibility that holes are exposed. If the second interlayer insulating film 117 is formed by CMP
If holes are communicated to the outside through the polished surface when polished by the method, the function as an interlayer insulating film may be impaired, and a short circuit between wirings may occur.

FIG. 10B shows the second interlayer insulating film 117.
Are deposited on the bottom surface and the side surfaces of the groove 115, and holes are formed in the groove 115.
The figure occupies a small part of the inside. Such a mode is obtained when the second interlayer insulating film 117 is deposited under conditions of good coverage. For example, in the case of the plasma CVD method using TEOS as a raw material, before the second interlayer insulating film 117 in the deposition process closes the upper part of the groove 115,
An insulating film having a certain thickness is deposited on the bottom and side surfaces of the groove 115. As a result, the capacitance C2 between the wirings 113A increases.

FIG. 11A shows the second interlayer insulating film 117.
Does not enter the inside of the groove 115 at all, and the upper portion 118 of the hole extends above the upper surface of the first interlayer insulating film 104. Such a form is the second
Is obtained when the interlayer insulating film 117 is formed under conditions by a deposition method having poor coverage and high directivity. For example, from a film called a high-density plasma (HDP) film to a second
When the interlayer insulating film 117 is formed, holes having a form as shown in FIG. 11A are obtained. In this case, since no insulating film is deposited inside the groove 115, the capacitance C3 between the wirings 113A is reduced.

The high density plasma (HDP) film is
It is formed using an HDP device. In this HDP device, when an HDP film is deposited while applying a bias voltage to the substrate, an etching phenomenon occurs during the deposition so as to compete with the deposition. No longer extends above the upper surface of the first interlayer insulating film 104. FIG. 11B shows a hole having such a form. HDP deposited while applying bias voltage to substrate
When the second interlayer insulating film is formed of a film, an insulator slightly deposits on the bottom surface of the groove. However, when the insulating film which is a lower layer of the first wiring layer is etched, the deposited insulator is the first insulator. Of the wiring 113A.
Is kept low.

Therefore, as shown in FIG. 8B, when the step of etching the insulating film 102 is performed, even if a slight amount of insulating material is deposited on the bottom of the groove, the capacitance C between the wiring 113A is reduced.
4 is kept low. This will be described with reference to FIGS. FIG. 12A illustrates one form of a hole when performing a step of not etching the insulating film 102, and FIG. 12B illustrates one form of a hole when performing the step of etching the insulating film 102. Is shown. In the case of FIG. 12A, if an insulator is deposited on the bottom surface of the groove, the insulator exists between the wirings.
The capacitance C5 is larger than the capacitance C4. For this reason, when forming the second interlayer insulating film by a deposition method that forms holes as shown in FIGS. 10B and 11B, the step of etching the insulating film 102 is omitted. Do
It is preferable that the bottom surface of the groove be lower than the lower surface of the first wiring layer 113A.

From the viewpoint of reducing the capacitance between wirings, FIG.
Although it is most preferable that a hole having the form shown in FIG. 1A is formed, when the second interlayer insulating film is planarized by CMP, the second interlayer insulating film reaches a level where the upper end of the hole is located. There is a high possibility that the film will be etched. But,
If the metal for interlayer connection 109 is projected above the level of the upper surface of the first interlayer insulating film 104, polishing formed by CMP can be stopped at the level of the upper surface of the metal for interlayer connection 109. That is, the metal 1 for interlayer connection
09 functions as a kind of etching stop layer. In this case, it is easy to control the polished surface to be at a position higher than the upper end of the hole, so that even if the hole shown in FIG. Also,
In the case of forming a hole having the form shown in FIG. 11A, the necessity of etching the insulating film 102 is low. However, the inter-wiring capacitance C3 when the insulating film 102 is etched is lower than the inter-wiring capacitance when the insulating film 102 is not etched at all. This is because the inter-wiring capacitance is determined by the physical properties of a space having a certain extent located between two adjacent wirings, so that the dielectric constant of the space above and below the space beside the wiring is also affected. To receive.

As described above, when the insulating film 102 located in the region between the first wiring layers 113A is partially etched, it is necessary to reduce the wiring capacitance when forming various holes. It turns out to be effective.

As described above, according to the present embodiment, a part or all of the area of the wiring gap 114 becomes the air hole 118 made of air, so that the space between the first wirings 113A sandwiching the wiring gap 114 is formed. The relative dielectric constant can be reduced. In particular, when the groove 115 formed in the wiring gap 114 has a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118, so that the relative dielectric constant between the first wirings 113A is minimized. can do.

Also, since the first wiring 113A is formed after the formation of the interlayer connection metal 109, the first wiring 11A must be formed over the entire lower surface of the interlayer connection metal 109.
3A is formed. Therefore, poor connection between the first wiring 113A and the metal for interlayer connection 109 can be prevented.

After the metal 109 for interlayer connection is formed in the interlayer connection hole 106 of the first interlayer insulating film 104, the first
Of the wiring 113A and the second interlayer insulating film 117 are sequentially formed. As a result, even if the misalignment occurs during the formation of the first wiring, either the metal 109 for interlayer connection or the first interlayer insulating film 104 always exists on the upper surface of the first wiring 113A, and The metal for interlayer connection 109 is not buried in the hole 118 formed simultaneously with the second interlayer insulating film 117. Therefore, short-circuit failure between the first wirings 113A and short-circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109 can be prevented.

(Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to FIGS. FIGS. 13A to 13D are process flow charts showing the method for manufacturing the semiconductor device according to the present embodiment. The steps leading to FIG. 13 (a) are the same as those in FIGS. 1 (a) to (d) and FIGS. 8 (a) and (b), so that the same components as those in the first embodiment are the same. The reference numerals are attached and the description is omitted. In the present embodiment, the second interlayer insulating film 212 is formed by a coating method instead of depositing the second interlayer insulating film 117 by the plasma CVD apparatus in the first embodiment. As the second interlayer insulating film 212, for example, organic polysiloxane,
An organic film made of a material such as an organic material containing fluorine, an inorganic porous film, and the like are conceivable. Many of these materials have fluidity.

First, as shown in FIG. 13A, a first interlayer insulating film 204 formed on a semiconductor substrate 201 is formed.
The above-mentioned material is applied on the metal for interlayer connection 208 and the wiring gap 215. Accordingly, the second interlayer insulating film 212 can be formed by filling the material having the fluidity into the groove in the wiring gap 215 without generating a hole. Second
As a material of the interlayer insulating film 212, the first interlayer insulating film 2
A material having a relative dielectric constant lower than 04 is selected. Therefore, the relative dielectric constant between the first wirings 203 sandwiching the wiring gap 215 can be reduced. Next, as shown in FIG.
Using a CMP method, the second interlayer insulating film 212 is planarized so that the surfaces of the first interlayer insulating film 204, the metal for interlayer connection 208, and the second interlayer insulating film 212 are flush with each other. I do. First interlayer insulating film 204 and second interlayer insulating film 2
12 is made of a different material so that the etching rate of the first interlayer insulating film 204 in the CMP is lower than the etching rate of the second interlayer insulating film 212. Thus, the first interlayer insulating film 204 is used as an etching stopper.

Further, as shown in FIG. 13C, after only the second interlayer insulating film 212 is selectively etched in the depth direction by about 0.3 μm, the third interlayer insulating film 214 is etched by about 0.1 μm. Deposit 5 μm. Again, the third interlayer insulating film 214 is planarized by using the CMP method so that the surfaces of the first interlayer insulating film 204, the metal for interlayer connection 208, and the third interlayer insulating film 214 are flush with each other. .

Next, as shown in FIG. 13D, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 216 is formed using photolithography and dry etching. .

As described above, according to the present embodiment, the entire area of the wiring gap 215 is formed by the second interlayer insulating film 212 using a material having a lower relative dielectric constant than the first interlayer insulating film 204. Embed Therefore, the relative dielectric constant between the first wirings 203 sandwiching the wiring gap 215 can be reduced, and the relative dielectric constant can be determined by the material of the second interlayer insulating film 212.

Since the first wiring 203 is formed after the formation of the interlayer connection metal 208, the interlayer connection metal 2 is formed.
08, the first wiring 203
Is formed. Therefore, poor connection between the first wiring 203 and the metal for interlayer connection 208 can be prevented.

After forming the metal for interlayer connection 208 in the interlayer connection hole of the first interlayer insulating film 204, the first wiring 203 and the second interlayer insulating film 212 are sequentially formed. As a result, even if the misalignment occurs during the formation of the first wiring, either the metal for interlayer connection 208 or the first interlayer insulating film 204 must be present on the upper surface of the first wiring 203, and In the gap 215, the second interlayer insulating film 2
12 are always present. Therefore, the metal for interlayer connection 20
8, short-circuit failure between the first wirings 203 and short-circuit failure between the wiring and the semiconductor substrate 201 can be prevented.

Also in this embodiment, the first wiring 203
The insulating film 202 located in the region between the portions is partially etched. For this reason, the capacitance between wirings is substantially governed by the relative dielectric constant of the second interlayer insulating film. If the insulating film 202 located in the region between the first wirings 203 is not etched, the insulating film 202 located in the vicinity of the region between the first wirings 203 may increase the wiring capacitance to some extent. Become.

In this embodiment, since the third interlayer insulating film 214 is provided, even if a film made of a material having low etching resistance or low plasma resistance is used as the second interlayer insulating film 212, The second interlayer insulating film is not damaged by the step of forming the wiring. It is preferable to use a film made of a material having high etching resistance or plasma resistance as the third interlayer insulating film. Therefore, even if the relative dielectric constant of the third interlayer insulating film 214 increases, the capacitance between the first wirings 203 does not increase.

In the embodiment shown in FIGS. 13A to 13D,
Although no holes are formed in the wiring gap 215, the wiring gap 2
A hole may be formed in 15.

(Sixth Embodiment) In the present embodiment, the second
The steps up to the formation of the interlayer insulating film are the same as in the fifth embodiment. This embodiment is characterized in the step of forming a second interlayer insulating film. Hereinafter, the step of forming the second interlayer insulating film will be described in detail with reference to FIGS. 14 (a), (b) and (c).

FIGS. 14A to 14C show that the width is 0.5 μm.
m, a relatively narrow groove (first gap) 115a having a width of not more than 0.5 μm and a relatively wide groove (for example, 0.8 μm or more, second gap) having a width of more than 0.5 μm are formed. Is shown. Here, the first wiring layer 113A is
The first wiring includes first to third wirings, and a first gap 115a is formed between the first wiring located at the center in the drawing and the second wiring located on the left side, and the first wiring 115a and the right side are formed. The second gap 115b is formed between the second wiring 115b and the third wiring located at the second position.

FIGS. 14A and 14B show cross sections when the second interlayer insulating film 117 is formed from the same type of insulating film. In the example of FIG. 14A, an insulating film having relatively poor coverage is deposited. As a film having such poor coverage, for example, a plasma oxide film formed using a silane / N ₂ O-based gas plasma in a parallel plate type plasma CVD apparatus can be used. When such a film is used, the grooves 115a and 11
Holes are formed in both of 5b. Large holes are formed in the relatively wide grooves 115b. For this reason, the upper portion of the hole in the groove 115b may exceed the level indicated by the line to be polished by CMP. If such large holes are formed, the holes may be exposed from the polished surface after polishing by CMP. When the holes are exposed by polishing, there is a risk of disconnection failure or short-circuit failure of the second layer wiring.

On the other hand, in the example of FIG. 14B, an insulating film having good filling performance is deposited as the second interlayer insulating film 117. For example, a plasma oxide film formed using high-density plasma (HDP) can be used as such a film having good burying performance.
When such a film is used, the second interlayer insulating film 117
Is also deposited on the bottom and side surfaces of the groove 115a having a relatively small width. As a result, a hole smaller than the size of the groove is formed in the groove 115a. Relatively wide groove 1
The inside of 15b is filled with the second interlayer insulating film 117, and no holes are observed therein. The HDP layer is HDP
It is formed using an apparatus. In this HDP device,
When the HDP film is deposited while applying a bias voltage to the substrate, an etching phenomenon occurs during the deposition so as to compete with the deposition, so that the insulating film is deposited on the bottom surface of the groove and the filling performance is improved. In this case, the upper end of the hole does not reach the level indicated by the CMP polishing line. However, since the holes in the groove 115a are small, the effect of reducing the capacitance between the wirings is small.

In the present embodiment shown in FIG. 14C, both advantages can be taken. That is, the second interlayer insulating film 117 is formed from insulating layers formed by at least two different forming methods. More specifically, first,
After the upper portion of the relatively narrow groove 115a is substantially covered with the interlayer insulating layer 117a, the second interlayer insulating layer 117b is formed.
Fills another wide groove 115b. Specifically, after a first interlayer insulating layer 117a is formed using a silane / N ₂ O-based gas plasma in a parallel plate type plasma CVD apparatus, a _second interlayer insulating layer 117a is applied while applying a bias voltage to a substrate in an HDP apparatus. The insulating layer 117b may be deposited.

Although the first interlayer insulating layer 117a and the second interlayer insulating layer 117b can be typically formed of a silicon oxide film, the second interlayer insulating layer 117b is formed of a low dielectric constant organic coating film such as polyallyl ether. May be formed.
Note that the first interlayer insulating layer 117a is made of, for example, silane gas,
Pressure 5mTorr using oxygen gas and argon gas
Can be deposited under

According to the embodiment shown in FIG. 14C, a large hole is formed in the first gap 115a and the second gap 11a is formed.
5b is buried by the second interlayer insulating layer 117b,
No holes are exposed by polishing by MP.

When the size of the hole (the ratio of the hole to the wiring gap) is increased, the upper end of the hole becomes higher. The size of the holes and the height of the holes can be optimized by adjusting the thicknesses of the first interlayer insulating film 117a and the second interlayer insulating film 117b.

Next, the evaluation results of the multilayer wiring structure manufactured according to the present embodiment will be shown. First, FIG.
See (b) and 15 (c).

FIG. 15A shows the positional relationship between wiring gaps and holes. Here, “H” indicates the distance from the upper surface of the first wiring layer to the top of the hole, and “D” indicates the distance from the lower surface of the first wiring layer to the bottom point of the hole. The hole occupancy “R” indicates the ratio of the hole width W to the wiring gap S.

FIG. 15B shows the dependence of the hole occupancy R on the wiring gap S. The occupancy R of the vacancy is expressed as S =
When the thickness is 0.8 μm or less, a positive value exceeding 0 is shown. The occupancy R increases as the wiring gap S decreases.
When S = 0.3 μm, the occupation ratio R shows a value of about 0.9.

FIG. 15C shows the dependence of H and D on the wiring gap. The value of H is 50 at any wiring gap.
It does not reach the planned CMP polishing line (800 to 1000 nm above the wiring) without exceeding 0 nm. That is, even after the interlayer insulating film 117 is planarized by CMP, the holes are not exposed. Therefore, the yield of the second-layer wiring does not decrease.

Next, the effect of reducing the capacitance between wirings of the multilayer wiring manufactured according to the present embodiment will be described with reference to FIG. FIG. 16 shows, as a comparative example, data in the case where no holes were formed between the wirings by using a circle. In the case of the comparative example, the inter-wiring capacitance per unit length increases as the wiring gap decreases, whereas the inter-wiring capacitance of the present embodiment decreases rather as the wiring gap decreases. It is considered that the decrease in the capacitance between the wirings is caused by an increase in the occupation ratio R of the holes to the wiring gap as the wiring gap becomes smaller.

Next, reference will be made to FIGS. 17 (a) and (b).

The effect of reducing the capacitance between wirings according to the present embodiment will be compared with the effect of reducing the capacitance between wirings when a low dielectric constant interlayer film is used.

FIG. 17A is a sectional view showing the structure of a model used for calculation (simulation). FIG.
(B) shows the dependency of the effective relative permittivity on the wiring interval. This effective relative permittivity is obtained by calculating the capacitance (per unit length) between wirings when a uniform medium having a certain relative permittivity is used as an interlayer insulating film, and the capacitance obtained by actual measurement. Was determined by comparing with In this embodiment, as indicated by the square marks in FIG. 17B, the effective relative permittivity decreases as the wiring gap decreases. When the wiring gap becomes 0.8 μm or less, holes are formed in the wiring gap. When the holes are formed, the effective relative permittivity sharply decreases. When the wiring gap is 0.3 μm, the effective relative permittivity drops to about 1.8.

FIG. 18 shows the relationship between the resistance value of the metal for interlayer connection (via) and the diameter of the metal for interlayer connection (via diameter). Even when the present embodiment is compared with the comparative example in which no holes are formed, there is no large difference between the via resistance values.

FIG. 19 shows the dependence of the via resistance value on the amount of alignment shift between the first wiring layer and the metal for interlayer connection. The alignment shift amount indicates a magnitude of misalignment between the metal for interlayer connection and the first wiring layer. In the pattern used for the measurement, since the width of the first wiring layer and the via diameter are the same, there is no overlapping margin between the first wiring layer and the metal for interlayer connection. FIG.
As can be seen from the above, in the conventional example, the via resistance value increases as the alignment shift amount increases,
In the present embodiment, the via resistance maintains a constant value regardless of the alignment shift. This is because the contact area between the first wiring and the metal for interlayer connection always has a maximum value because the metal for interlayer connection is surely present on the upper surface of the first wiring layer even if the misalignment occurs. Because it is maintained.

Since the second interlayer insulating film 117 is deposited after the formation of the metal 109 for interlayer connection, holes formed at the same time as the deposition of the second interlayer insulating film 117 are in contact with the metal 109 for interlayer connection. I will not do it. Therefore, neither a short-circuit failure between the first wirings 113A via the interlayer connection metal 109 nor a short-circuit failure between the wiring and the semiconductor substrate 101 occurs.

The material of the first wiring layer is not limited to Al. For example, it may be Cu. Instead of using a plasma oxide film as the second interlayer insulating layer 117b constituting the second interlayer insulating film 117, a coating insulating film having good filling performance may be used. Further, the method of forming the second interlayer insulating film described with reference to FIG. 14C has an effect that can be applied to other embodiments.

In each of the above embodiments, the present invention has been described with respect to a semiconductor device using a normal silicon substrate, but the present invention is not limited to this. As long as the semiconductor device has a multilayer wiring structure, a semiconductor substrate other than silicon or an SOI substrate may be used.
A substrate using an insulating substrate such as glass or plastic may be used.

[0132]

According to the present invention, the first wiring is always formed on the entire lower surface of the metal for interlayer connection. Therefore, even if the first wiring is misaligned, the first wiring is formed. Poor connection between the first wiring and the metal for interlayer connection can be reliably prevented. Further, the metal for interlayer connection is not buried in the holes formed simultaneously with the second interlayer insulating film. Therefore, a short circuit between the first wirings and a short circuit between the wiring and the semiconductor substrate via the metal for interlayer connection can be prevented.

If a part or the whole of the wiring gap forms a hole made of air, or if the entire wiring gap is filled with a material having a low relative dielectric constant, the first wiring sandwiching the wiring gap is formed.
Can be reduced. Therefore,
A semiconductor device with a wide operation margin and less malfunction can be realized by suppressing signal delay between the first wirings.

Further, since most of the side surfaces of the metal for interlayer connection are in contact with the second wiring, even when the second wiring is misaligned when forming the second wiring, the second wiring and the metal for the interlayer connection are not connected. Reliability in connection with metal can be improved.

Even if an alignment shift occurs during the formation of the first wiring, either the metal for interlayer connection or the first interlayer insulating film must exist on the upper surface of the first wiring, and
The metal for interlayer connection is not buried in the holes formed simultaneously with the second interlayer insulating film. Therefore, a short circuit between the first wirings and a short circuit between the wiring and the semiconductor substrate via the metal for interlayer connection can be prevented.

[Brief description of the drawings]

FIGS. 1A to 1D are process flow charts showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are process flow charts showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3A is a plan view showing a positional relationship between a first wiring and an interlayer connection metal corresponding to the presence or absence of an alignment shift in the semiconductor device according to the first embodiment of the present invention;
(B) is a perspective view thereof.

FIGS. 4A to 4C are process flow charts showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5D are process flow charts showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a perspective view showing a positional relationship between a wiring groove corresponding to the presence or absence of an alignment shift and a metal for interlayer connection in a semiconductor device according to a third embodiment of the present invention.

FIGS. 7A to 7D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 8A to 8C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 9A and 9B are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views showing a form of a hole.

11A and 11B are cross-sectional views showing other forms of holes.

FIGS. 12A and 12B are cross-sectional views showing still another form of a hole.

13A to 13D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIGS. 14A to 14C are process cross-sectional views illustrating a sixth embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIGS. 15A to 15C are diagrams showing respective dimensions of holes in another embodiment of the semiconductor device according to the present invention.

FIG. 16 is a diagram showing a relationship between a wiring interval and a capacitance between wirings per unit length in an embodiment of the semiconductor device according to the present invention.

17A is a cross-sectional view of a wiring structure for calculating a capacitance between wirings of a semiconductor device, and FIG. 17B is a graph showing a relationship between a wiring gap and an effective relative permittivity.

FIG. 18 is a graph showing the relationship between via diameter and via resistance in one embodiment of the semiconductor device of the present invention.

FIG. 19 is a graph showing a relationship between an alignment shift amount between a first wiring layer and a via and a via resistance in an embodiment of the semiconductor device of the present invention.

FIG. 20 is a cross-sectional view showing a structure of a conventional semiconductor device.

FIGS. 21A and 21B are process flow charts showing a conventional method for manufacturing a semiconductor device.

FIGS. 22A to 22C are process flow charts showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 101 semiconductor substrate 102 insulating film 103 first metal layer 104 first interlayer insulating film 105 interlayer connection resist pattern 106 interlayer connection hole 107 adhesion layer 108 interlayer connection material 208 interlayer connection metal 110 first wiring resist Pattern (first wiring pattern) 111 Misalignment dimension 112 Misalignment part 114 Wiring gap 115 Groove 116 Field part without first wiring 117 Second interlayer insulating film 118 Vacancy 119 Second wiring

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[Procedure amendment]

[Submission date] May 7, 1999 (1999.5.7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Semiconductor device having multilayer wiring and method of manufacturing the same

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art A remarkable progress in semiconductor processing technology in recent years has made it possible to make wirings and devices ultra-fine and highly integrated, so that the performance of ULSI has been improved. However, with the integration of wiring, the delay of a signal in the wiring determines the speed of the device. Therefore, in the ULSI of the so-called 0.25 μm generation or later, as the material of the interlayer insulating film, a material having a low relative dielectric constant, for example, a material having a low relative dielectric constant instead of the conventional SiO ₂ (relative dielectric constant ε = 4.3) is used. SiOF doped with fluorine (ε =
3.5) and SiO: C (ε = 2.8 to 3.2) containing organic substances are being used. However, these materials have problems in terms of hygroscopicity and heat resistance, so that it is difficult to construct a process using the materials.

Further, in order to reduce a delay between wirings, which is a particularly large delay, a hole formed by air (ε = 1.0) is intentionally provided in an insulating material between wirings. A technique for lowering the relative dielectric constant between wirings has been proposed (Japanese Patent Application Laid-Open No. 62-5643). Hereinafter, this technique will be described with reference to FIG. FIG. 20 is a cross-sectional view showing the structure of a conventional semiconductor device.
In FIG. 20, a hole 6 is provided between the wirings 3 and 4 and a hole 7 is provided between the wirings 4 and 5 in the insulating substance 2 provided on the semiconductor substrate 1 of the semiconductor device. As a material of the insulating substance 2, SiO ₂ is used. The capacitance between the wiring 3 and the wiring 4 is equal to the capacitance between the wiring 3 and the hole 6, the capacitance of the hole 6 itself, and the capacitance between the hole 6 and the wiring 4 connected in series. Can be considered. Material of insulating substance 2 which is a portion other than the holes SiO
Compared to the relative dielectric constant of _2, the relative dielectric constant of the void formed by air is about 1/4. Therefore, by providing the holes, the capacitance between adjacent wirings can be reduced. As a result, a signal delay between adjacent wirings can be suppressed, so that a semiconductor device having a wide operation margin and hardly malfunctioning can be realized, and a low-cost process can be achieved because there is no need to use a new material.

[0004]

However, according to the above conventional structure, the wiring and the interlayer connection hole are designed so as to be borderless, that is, designed so that the wiring width and the diameter of the interlayer connection hole have the same dimensions, and When the misalignment occurs in the photolithography process, the following problem occurs. First, since the interlayer connection hole and the hole are integrated when the interlayer connection hole is opened, a short circuit failure of the wiring occurs due to the metal for interlayer connection entering the integrated region. Second, the connection area between the metal for interlayer connection in the interlayer connection hole and the wiring is small, so that a connection failure occurs.

[0005] These defects will be described with reference to FIGS. 21 and 22. 21 (a), 21 (b) and 22
(A) to (c) are process flow diagrams showing a conventional method for manufacturing a multilayer wiring included in a semiconductor device. First, as shown in FIG. 21A, an insulating film 12, a first wiring 13, and an interlayer insulating film 14 are sequentially formed on a semiconductor substrate 11. Since SiO ₂ deposited by the plasma CVD method is used as the interlayer insulating film 14, the step coverage is poor. That is, the ratio of the deposited film thickness in the wiring gap 15 which is a region between the first wirings 13 to the deposited film thickness in the flat portion is low. As a result, the wiring gap 1
5, holes 16 are formed in the interlayer insulating film 14. However, since the step coverage does not become 0%, not all of the wiring gaps 15 become voids, and the interlayer insulating film 14 exists between the wirings. Therefore, for the purpose of reducing the relative dielectric constant between the wirings, a method of further lowering the deposition rate of the interlayer insulating film 14 in the wiring gap 15 to lower the relative dielectric constant can be considered. In this case,
The holes 16 occupy a larger area. Next, FIG.
As shown in (b), the interlayer insulating film 14 is planarized by removing a part of the interlayer insulating film 14 by using a resist etch back method, a chemical mechanical polishing (CMP) method, or the like.

Next, as shown in FIG. 22A, an interlayer connection hole 17 is formed by using photolithography and dry etching. Here, the wiring width of the first wiring 18
And the diameter 19 of the interlayer connection hole are the same size, and
Consider a case where an alignment shift of only the shift size 20 occurs in photolithography. In this case,
The interlayer connection hole 17 at a position shifted from the upper surface of the first wiring 13 due to the alignment shift is formed deeper than the position of the upper surface. Therefore, the interlayer connection hole 17 is
Integrate with Next, as shown in FIG. 22B, an interlayer connection metal 21 made of tungsten is formed in the interlayer connection hole 17 by using a CVD method. Since the tungsten 21 formed by the CVD method has good step coverage, it fills not only the interlayer connection holes 17 in FIG. As a result, via the interlayer connection metal 21 formed in the portion that was the hole 16,
Short-circuit failure in which adjacent first wirings 13 are connected to each other occurs. If an attempt is made to lower the relative dielectric constant in the wiring gap 15, the holes 16 occupy a larger area, so that short-circuit defects are more likely to occur. On the other hand, FIG.
If the deviation dimension 20 in (a) is further increased, the connection area between the first wiring 13 and the metal 21 for interlayer connection buried in the interlayer connection hole 17 becomes smaller. A connection failure with the metal for interlayer connection 21 occurs. In particular, when an organic material is used as the material of the interlayer insulating film 14, the connection failure easily occurs. When the etching is performed deeper in the interlayer connection hole 17, the first metal 21 for interlayer connection is formed.
Short-circuit failure in which the wiring 13 and the semiconductor substrate 11 are connected to each other occurs. Next, as shown in FIG. 22C, a second wiring 22 to be connected to the first wiring 13 via the metal 21 for interlayer connection is formed by the metal 21 for interlayer connection and the interlayer insulating film 14. Formed on

The present invention has been made in view of the above-mentioned conventional problems, and provides a semiconductor device and a method of manufacturing the same, which minimizes inter-wiring capacitance and hardly causes short-circuit failure or connection failure even when an alignment shift occurs. The purpose is to:

[0008]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, comprising the steps of: covering a surface of a substrate with an insulating film; Depositing, forming a first interlayer insulating film on the conductive film, forming an interlayer connection hole reaching the conductive film in the first interlayer insulating film, Embedding a metal for interlayer connection into the first wiring layer; and forming a masking layer defining a first wiring layer pattern on the first interlayer insulating film so as to cover at least a part of the metal for interlayer connection. The first interlayer insulating film is etched using the masking layer as a mask, and the conductive film is etched using the masking layer and the interlayer connection metal as a mask.
Forming a wiring layer, removing the masking layer, and depositing a second interlayer insulating film on the substrate to cover the interlayer connection metal and a first wiring layer;
Exposing at least a portion of the metal for interlayer connection by flattening the second interlayer insulating film; and forming a second wiring layer electrically connected to an upper portion of the metal for interlayer connection. Forming.

According to another method of manufacturing a semiconductor device of the present invention, a step of covering the surface of a substrate with an insulating film, a step of depositing a conductive film on the insulating film, and a step of forming a first interlayer insulating film on the conductive film Forming an interlayer connection hole reaching the conductive film in the first interlayer insulating film; embedding a metal for interlayer connection in the interlayer connection hole; Partially etching the upper surface of the metal for interlayer connection from the first interlayer insulating film, and forming a masking layer for defining a first wiring layer pattern with the metal for interlayer connection. Forming on the first interlayer insulating film so as to cover at least a part of the first interlayer insulating film; and etching the first interlayer insulating film using the masking layer as a mask to remove the masking layer and the interlayer connecting metal. Make a mask Etching the conductive film, thereby forming a first wiring layer from the conductive film, removing the masking layer, and forming a second interlayer so as to cover the interlayer connection metal and the first wiring layer. Depositing an insulating film on the substrate, flattening the second interlayer insulating film to expose at least a part of the metal for interlayer connection, and an upper portion of the metal for interlayer connection. Forming a second wiring layer electrically connected to the second wiring layer.

It is preferable that the etching of the conductive film is performed so that the interlayer connection metal is not substantially etched.

The step of forming the second interlayer insulating film includes:
It is preferable that voids formed of a closed region where the second interlayer insulating film does not exist are also formed in the wiring gap between the first wirings.

In the step of flattening the second interlayer insulating film, it is preferable that the holes are not exposed.

It is preferable that the dielectric constant of the material used for the second interlayer insulating film is smaller than the dielectric constant of the material used for the first interlayer insulating film.

The step of forming the second interlayer insulating film includes:
Forming a first interlayer insulating layer forming a part of the second interlayer insulating film, and forming a second interlayer insulating layer forming another part of the second interlayer insulating film into the first interlayer insulating film; Forming the first interlayer insulating layer, wherein in the step of forming the first interlayer insulating layer, voids are formed in a gap of 0.5 μm or less among gaps formed by the first wiring layer. In the step of substantially covering the gap of 0.5 μm or less with the first interlayer insulating layer and forming the second interlayer insulating layer, the step of forming the second interlayer insulating layer may include: A part of the second interlayer insulating layer may enter a gap that is not substantially covered by the first interlayer insulating layer.

As the first interlayer insulating layer, silane / N ₂
First plasma CV formed using O-based gas plasma
D membranes can be used.

As the second interlayer insulating layer, a second plasma CVD film formed by using high-density plasma to which a substrate bias voltage is applied can be used.

In the step of forming the first wiring layer, the first interlayer insulating film and the conductive film are etched using the masking layer as a mask, and then a part of a base insulating film of the conductive film is etched. And forming a groove on the surface of the insulating film.

In the step of forming the second wiring layer, a groove is formed on the surface of the first interlayer insulating film by etching at least the first interlayer insulating film using the groove forming pattern as a mask. Forming a second metal layer on the metal for interlayer connection, the first interlayer insulating film, and the second interlayer insulating film; and forming a second metal layer inside the trench in the second metal layer. Forming a second wiring by removing a portion other than the above.

According to still another method of manufacturing a semiconductor device of the present invention, there is provided a lower wiring layer including a plurality of wirings formed on the same insulating film, wherein the plurality of wirings include a first wiring,
A lower wiring layer including a second wiring adjacent to the first wiring at a first gap and a third wiring adjacent to the first wiring at a second gap wider than the first gap; Forming a structure having a first interlayer insulating film formed on the first wiring, the second wiring, and the third wiring; and substantially blocking the space above the first gap. , The first
Depositing a first interlayer insulating layer forming a lower portion of the second interlayer insulating film so as to form a hole in the gap between the first interlayer insulating film, and forming an upper portion of the second interlayer insulating film. Depositing a second interlayer insulating layer having better coverage than the interlayer insulating layer to fill the second gap and completely cover the holes.

Preferably, the method further includes a step of flattening the second interlayer insulating film so as not to expose the holes.

It is preferable that the second interlayer insulating layer is formed of an organic film having a lower dielectric constant than the first interlayer insulating layer.

The semiconductor device according to the present invention is a lower wiring layer comprising a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are a first wiring and a first wiring from the first wiring. A lower wiring layer including a second wiring adjacent with a gap therebetween, and a third wiring adjacent with a second gap from the first wiring, the first wiring, the second wiring, and the third wiring A first interlayer insulating film formed on the first wiring, a connection metal formed in the first interlayer insulating film and in contact with an upper surface of the first wiring, the first gap and the second gap. A second interlayer insulating film formed above the gap and forming a hole in each of the first gap and the second gap;
And an upper wiring layer electrically connected to the metal for interlayer connection.

The upper wiring layer may be a wiring having a buried structure, and the upper wiring layer may be formed in the second interlayer insulating film.

The lower insulating film of the lower wiring layer has a groove formed below the first gap and the second gap, and a groove is formed in the groove from an upper surface of the lower insulating film. And a part of the second interlayer insulating film having a height that does not protrude upward.

The upper end portion of the metal for interlayer connection is the first
It is preferable to project above the upper surface of the interlayer insulating film.

The first wiring has a side surface portion locally protruding toward the second wiring and / or the third wiring, and the upper surface of the side surface portion is covered with the metal for interlayer connection. It may be. Further, it is preferable that the side surface portion of the first wiring is formed in a self-aligned manner with respect to the metal for interlayer connection.

A semiconductor device according to the present invention is a lower wiring layer composed of a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are a first wiring and a first wiring from the first wiring. A lower wiring layer including a second wiring adjacent with a gap therebetween, and a third wiring adjacent with a second gap from the first wiring, the first wiring, the second wiring, and the third wiring A first interlayer insulating film formed thereon and a second interlayer insulating film covering the lower wiring layer and having an upper surface planarized, wherein the second gap is larger than the first gap. Broadly, the second interlayer insulating film includes a first interlayer insulating layer and a second interlayer insulating layer formed on the first interlayer insulating layer.
The first interlayer insulating layer and the second interlayer insulating layer block the upper part of the first gap, and a hole is formed in the first gap, The second gap is filled with the first interlayer insulating layer and the second interlayer insulating layer.

It is preferable that the second interlayer insulating layer has better coverage than the first interlayer insulating layer.

The first interlayer insulating layer is formed from a silicon oxide film, and the second interlayer insulating layer is formed from an organic coating film having a dielectric constant lower than that of the first interlayer insulating layer. Is preferred.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, comprising: forming a first interlayer insulating film on a first wiring layer; Forming an interlayer connection hole in the interlayer insulating film, embedding an interlayer connection metal in the opened interlayer connection hole, and using the first wiring pattern as a mask to form the first interlayer insulating film and the first interlayer insulating film. By sequentially etching the wiring layer, the first
Forming the first wiring, and forming the first interlayer insulating film and the first
Forming a second interlayer insulating film on the semiconductor substrate on which the wiring is formed, and removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed. Flattening the surfaces of the second interlayer insulating film, the first interlayer insulating film, and the metal for interlayer connection so as to be on the same plane, and forming a second metal layer on the same plane Forming a second wiring by etching the second metal layer using the second wiring pattern as a mask.

Another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring,
A first interlayer insulating film is formed on the first wiring layer, an interlayer connection hole is opened in the formed first interlayer insulating film, and a metal for interlayer connection is buried in the opened interlayer connection hole. Process and
Forming a first wiring by sequentially etching the first interlayer insulating film and the first wiring layer using the first wiring pattern as a mask; Forming a second interlayer insulating film on the semiconductor substrate on which the first wiring is formed, and removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed; Flattening the surfaces of the second interlayer insulating film, the first interlayer insulating film, and the metal for interlayer connection so as to be flush with each other; and using at least the first Forming a groove having a predetermined depth from the surface of the first interlayer insulating film by etching the interlayer insulating film; and forming the interlayer connection metal, the first interlayer insulating film and the second interlayer insulating film. Forming a second metal layer on the insulating film; And a step of forming a second wiring by removing a portion present outside the interior of the groove of the metal layer.

Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, wherein a first interlayer insulating film is formed on a first wiring layer formed on an insulating film. Forming a film, forming an interlayer connection hole in the formed first interlayer insulating film, embedding a metal for interlayer connection in the opened interlayer connection hole, and masking the first wiring resist pattern. Forming a first wiring by sequentially etching the first interlayer insulating film, the first wiring layer, and at least a part of the insulating film using the first interlayer insulating film;
Forming a second interlayer insulating film on the semiconductor substrate on which the first wiring is formed, and removing the second interlayer insulating film until the surface of the metal for interlayer connection is exposed; Flattening the surfaces of the two interlayer insulating films and the metal for interlayer connection so as to be on the same plane, forming a second metal layer on the same plane, and forming a second wiring resist pattern. Forming a second wiring by etching the second metal layer using masking for masking.

Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, wherein a first interlayer insulating film is formed on a first wiring layer formed on an insulating film. Forming a film, opening an interlayer connection hole in the formed first interlayer insulating film, and embedding a metal for interlayer connection in the opened interlayer connection hole; and forming a film from the surface of the first interlayer insulating film. Forming a first wiring by etching a part of the first interlayer insulating film and the first wiring layer sequentially using a first wiring resist pattern for masking; Forming a second interlayer insulating film on the semiconductor substrate on which the first wiring has been formed; and forming the second interlayer insulating film on the semiconductor substrate until the surface of the metal for interlayer connection is exposed.
Removing the interlayer insulating film to planarize the surfaces of the second interlayer insulating film and the metal for interlayer connection so as to be flush with each other;
Forming a second wiring by etching the second metal layer using the second wiring resist pattern for masking.

Still another method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multi-layer wiring, wherein a first interlayer insulating film is formed on a first wiring layer formed on an insulating film. Forming a film, forming an interlayer connection hole in the formed first interlayer insulating film, embedding a metal for interlayer connection in the opened interlayer connection hole, and masking the first wiring resist pattern. Forming a first wiring by sequentially etching the first interlayer insulating film, the first wiring layer, and the insulating film using the first wiring, and forming the first wiring on the semiconductor substrate on which the first wiring is formed. Forming the second interlayer insulating film and removing the second interlayer insulating film until the surface of the first interlayer insulating film is exposed, thereby forming the second interlayer insulating film and the first interlayer insulating film. So that the surfaces of the interlayer insulating film and the surface of each have the same plane Carrying out the step of supporting, selectively etching the surface of the second interlayer insulating film, and then depositing a third interlayer insulating film; and forming the third interlayer insulating film until the surface of the first interlayer insulating film is exposed. Removing the third interlayer insulating film to flatten the surfaces of the third interlayer insulating film, the first interlayer insulating film, and the interlayer connection metal so as to be flush with each other. Forming a second metal layer on the flat surface and forming the second wiring by etching the second metal layer using the second wiring resist pattern for masking. .

It is preferable that the semiconductor device further includes a void formed of a closed region where the second interlayer insulating film does not exist in the wiring gap between the first wirings.

It is preferable that the dielectric constant of the second interlayer insulating film is smaller than the dielectric constant of the first interlayer insulating film.

[0037] Before the step of forming the first wiring, the method may further include a step of partially etching the surface of the first interlayer insulating film.

As a method of forming the second interlayer insulating film, high-density plasma CVD may be used.

As a method of forming the second interlayer insulating film, a high-density plasma CV with a bias voltage applied to a substrate is used.
D may be used.

It is preferable that the dielectric constant of the material used for the second interlayer insulating film is smaller than the dielectric constant of the material used for the first interlayer insulating film.

In the step of flattening the second interlayer insulating film, it is preferable to use chemical mechanical polishing.

The step of forming the second interlayer insulating film includes:
Forming a first interlayer insulating layer forming a part of the second interlayer insulating film, and forming a second interlayer insulating layer forming another part of the second interlayer insulating film into the first interlayer insulating film; A step of forming on a layer may be included.

In the step of forming the first interlayer insulating layer, an interval of the gap formed by the first wiring layer is set to 0.
In the step of forming the second interlayer insulating layer, the first interlayer insulating layer substantially covers the gap of 0.5 μm or less by the first interlayer insulating layer so as to form a hole in the gap of 5 μm or less. In the gap formed by the first wiring layer, a part of the second interlayer insulating layer may enter a gap that is not substantially covered by the first interlayer insulating layer.

As the first interlayer insulating layer, silane / N ₂
First plasma CV formed using O-based gas plasma
A D film may be used.

As the second interlayer insulating layer, a second plasma CVD film formed using high-density plasma to which a substrate bias voltage is applied may be used.

In the step of flattening the second interlayer insulating film, the second interlayer insulating layer may be removed without removing the first interlayer insulating layer.

The step of forming the second interlayer insulating film includes:
It is preferable that the height of the upper end of the hole measured from the upper surface of the first wiring be 500 nm or less.

The step of forming the second interlayer insulating film includes:
The gap formed by the first wiring layer is 0.8 μm.
It is preferable to form holes in gaps of m or less.

The step of forming the second interlayer insulating film includes:
The gap formed by the first wiring layer is 0.5 μm.
It is preferable to form pores having a porosity of 0.5 or more in gaps of m or less.

In the step of flattening the second interlayer insulating film, the second interlayer insulating layer may be removed without removing the first interlayer insulating layer.

A semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, which is used for connecting a first wiring formed on a semiconductor substrate to the first wiring and a wiring of another layer. A metal for interlayer connection formed on the first wiring, and the first metal other than the portion where the metal for interlayer connection is present;
A first interlayer insulating film formed in all regions of the wiring, and a second interlayer insulating film formed in all regions other than the first wiring when the semiconductor substrate is viewed in a plan view; A second wiring formed at least on the metal for interlayer connection and connected to the first wiring via the metal for interlayer connection.

Another semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, and comprises a plurality of first wiring layers arranged on an insulating film, and a plurality of first wiring layers on each of the plurality of first wiring layers. A first interlayer insulating film formed in the first interlayer insulating film, an interlayer connecting hole opened in the first interlayer insulating film and located on the plurality of first wiring layers, and embedded in the interlayer connecting hole; A metal for interlayer connection in contact with a first wiring layer, a second interlayer insulating film formed so as to cover the plurality of first wiring layers, and the plurality of first wiring layers; A concave portion formed on the surface of the insulating film.

Still another semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring, and comprises a plurality of first wiring layers arranged on an insulating film, and each of the plurality of first wiring layers. A first interlayer insulating film formed thereon, an interlayer connection hole opened in the first interlayer insulating film, located on the plurality of first wiring layers, and buried in the interlayer connection hole; A metal for interlayer connection in contact with the first wiring layer;
And a second interlayer insulating film provided on a region where the wiring layer is not formed, wherein the upper surface of the metal for interlayer connection protrudes above the upper surface of the first interlayer insulating film.

The second interlayer insulating film is formed of the plurality of first interlayer insulating films.
A wiring layer, a first interlayer insulating layer forming part of the second interlayer insulating film, and a second interlayer insulating layer forming another part of the second interlayer insulating film. The first interlayer insulating layer has a gap of 0.1 mm among gaps formed by the first wiring layer.
The gap substantially covers the gap of 0.5 μm or less so as to form a void in the gap of 5 μm or less, and a part of the second interlayer insulating layer is a gap formed by the first wiring layer. Of these, it is preferable that the semiconductor device enters into a gap that is not substantially covered by the first interlayer insulating layer.

It is preferable that the height of the upper end of the hole measured from the upper surface of the first wiring is 500 nm or less.

It is preferable that voids are formed in gaps having an interval of 0.8 μm or less among the gaps formed by the first wiring layer.

It is preferable that voids having a porosity of 0.5 or more are formed in gaps having an interval of 0.5 μm or less among the gaps formed by the first wiring layer.

[0058]

(First Embodiment) A first embodiment of the present invention.
Will be described with reference to FIGS. FIG.
FIGS. 2A to 2D and FIGS. 2A to 2C are process flow charts showing a method for manufacturing a semiconductor device according to the present embodiment. First, as shown in FIG. 1A, a semiconductor substrate 101 on which a semiconductor active element (not shown) is formed in advance,
An insulating film 102 (0.8 μm in thickness), a first metal layer 103 (0.5 μm in thickness) having a laminated structure of aluminum and a titanium alloy, and a first interlayer insulating film 104 (1.0 μm in thickness)
m) are sequentially deposited. Thereafter, an interlayer connection resist pattern 105 is formed, and an interlayer connection hole 106 is opened by dry etching.

Next, as shown in FIG. 1B, an adhesion layer 107 made of, for example, TiN / Ti is deposited on the surface having the interlayer connection hole 106 after the resist pattern 105 for interlayer connection is peeled off. Then, an interlayer connection material 108 made of tungsten is deposited by blanket W-CVD. The adhesion layer 107 and the interlayer connection material 1 existing outside the interlayer connection hole 106 by dry etching or CMP.
08 is removed. The adhesion 107 and the interlayer connection material 108 that exist only inside the interlayer connection hole 106 together form a metal 109 for interlayer connection.

Next, as shown in FIG. 1C, the first interlayer insulating film 104 and the metal
The wiring resist pattern (masking layer defining the first wiring layer pattern) 110 is formed. Consider a case where the first wiring resist pattern 110 is formed with a misalignment by a misalignment dimension 111. For example, when the diameter of the interlayer connection hole 106 is 0.3 μm and the width of the first wiring resist pattern 110 is 0.3 μm,
Metal 10 for interlayer connection buried in interlayer connection hole 106
The allowable deviation dimension 111 between the first wiring pattern 9 and the first wiring resist pattern 110 is 0.1 μm at the maximum.

FIG. 3A is a plan view showing the relationship between the displacement of the first wiring resist pattern 110 and the metal 109 for interlayer connection. The position of the first wiring resist pattern 110 is located below the wavy line in FIG.
The position of the first wiring resist pattern 110 and the position of the interlayer connection metal 109 match on the upper side of the wavy line.

Next, as shown in FIG. 1D, a first wiring is formed by using a CF-based etching gas for patterning an oxide film and a Cl-based etching gas for patterning an aluminum film. Resist pattern 11
0, the first wiring resist pattern 11
Dry etching is sequentially performed using 0 as a mask. First, the first interlayer insulating film 104 in the opening of the first wiring resist pattern 110 is removed by dry etching using a CF-based etching gas at a low temperature. In this case, the metal 109 for interlayer connection in the misaligned portion 112 is hardly etched by the CF-based etching gas. Further, the insulating film 10 is formed by dry etching using a Cl-based etching gas.
2 until the first wiring resist pattern 110 is exposed.
The first metal layer 103 in the opening is removed. Thus, a first wiring 113A is formed. Also in this case, the metal 109 for interlayer connection in the misaligned portion 112 is not etched by the Cl-based etching gas. In the etching for forming the first wiring 113A, both the first wiring resist pattern 110 and the interlayer connection metal 109 function as an etching mask.

FIG. 3B is a perspective view showing the positional relationship between the first wiring 113 and the metal 109 for interlayer connection corresponding to the presence or absence of misalignment. First, the first metal layer 10
From 3, the case of the wiring 113B formed by dry etching without any misalignment will be considered. In this case, an interlayer connection metal 109 having the same diameter as the width of the wiring 113B is formed on the upper surface of the wiring 113B. On the other hand, consider the case of the wiring 113C formed out of alignment with the first metal layer by dry etching. In this case, the first metal layer located below the interlayer connection metal 109 is not etched during the dry etching. Therefore, in the misaligned portion 112 in FIG. 8A, the first metal layer located under the interlayer connection metal 109 remains without being etched by self-alignment, and thus has a shape as shown in FIG. Is formed. Accordingly, the first wiring 113A including the wiring 113B or the wiring 113C is always formed on the entire lower surface of the interlayer connection metal 109. In addition, since the portion below the first wiring resist pattern 110 in FIG. 8A is not etched, the portion above the first wiring 113A where the interlayer connection metal 109 does not exist is the first portion. The interlayer insulating film 104 remains. As a result, the first interlayer insulating film 1 is formed on the first wiring 113A.
04 or the metal 109 for interlayer connection is always present. Therefore, the first metal layer 103 under the interlayer connection metal 109 or the first wiring resist pattern 110 forms the first wiring 113A. The total thickness of the first wiring 113A formed from the first metal layer 103 and the first interlayer insulating film 104 is 1.5 μm.
Therefore, the aspect ratio of the groove 115 formed in the portion having the minimum width of 0.3 μm in the wiring gap 114 which is a region between the adjacent first wirings 113A is about 5.
Note that the field portion 116 where the first wiring does not exist is provided.
Alternatively, a wiring dummy pattern may be formed.

As described above, according to the present embodiment, the plane pattern of both the first interlayer insulating film 104 and the metal for interlayer connection 109 defines the plane pattern of the first wiring 113A.

Next, as shown in FIG. 2A, the insulating film 102 and the first interlayer insulating film 1 of the semiconductor substrate 101 after the first wiring resist pattern 110 is released.
04, a second interlayer insulating film 117 is deposited on the interlayer connection metal 109 using a plasma CVD apparatus. Part or all of the region of the wiring gap 114 in the groove formed in the wiring gap 114 becomes a hole 118 without being filled with the second interlayer insulating film 117.
In particular, in a groove having a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118.

Next, as shown in FIG. 2B, the surfaces of the first interlayer insulating film 104, the metal 109 for interlayer connection, and the second interlayer insulating film 117 are substantially the same by using the CMP method. The second interlayer insulating film 117 is planarized so as to be flat. First interlayer insulating film 104 and second interlayer insulating film 117
Are made of different materials, and the CM of the first interlayer insulating film 104 is
The etching rate at P is lower than the second interlayer insulating film 11.
7 is set to be smaller than the etching rate. Thus, the first interlayer insulating film 104 is used as an etching stopper. Second interlayer insulating film 11
7 is buried to some extent in the upper part of the groove having a high aspect ratio, so that the hole 118 does not form an opening in the surface of the second interlayer insulating film 117 after the CMP.

Next, as shown in FIG. 2C, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 119 is formed using photolithography and dry etching. .

As described above, according to the present embodiment, a part or all of the area of the wiring gap 114 becomes the air hole 118 made of air, so that the space between the first wirings 113A sandwiching the wiring gap 114 is formed. The relative dielectric constant can be reduced. In particular, when the groove 115 formed in the wiring gap 114 has a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118, so that the relative dielectric constant between the first wirings 113A is minimized. can do.

Since the first wiring 113A is formed after the formation of the metal for interlayer connection 109, the first wiring 11A must be formed over the entire lower surface of the metal for interlayer connection 109.
3A is formed. Therefore, poor connection between the first wiring 113A and the metal for interlayer connection 109 can be prevented.

After forming the metal 109 for interlayer connection in the interlayer connection hole 106 of the first interlayer insulating film 104,
Of the wiring 113A and the second interlayer insulating film 117 are sequentially formed. As a result, even if the misalignment occurs during the formation of the first wiring, either the metal 109 for interlayer connection or the first interlayer insulating film 104 always exists on the upper surface of the first wiring 113A, and The metal for interlayer connection 109 is not buried in the hole 118 formed simultaneously with the second interlayer insulating film 117. Therefore, short-circuit failure between the first wirings 113A and short-circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109 can be prevented.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. 4 (a) to 4 (c)
FIG. 2 is a process flow chart showing a method for manufacturing a semiconductor device according to the embodiment. The steps leading up to FIG.
Since these are the same as (a) to (d), the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. In the present embodiment, the second interlayer insulating film 217 is formed by a coating method instead of depositing the second interlayer insulating film 117 by the plasma CVD apparatus in the first embodiment. Second interlayer insulating film 217
For example, an organic film made of a material such as an organic polysiloxane or an organic material containing fluorine, an inorganic porous film, or the like can be considered. Many of these materials have fluidity.

First, as shown in FIG. 4A, the first interlayer insulating film 104, the metal for interlayer connection 109, the wiring gap 21
4 is coated with the above material. Accordingly, the second interlayer insulating film 217 can be formed by filling the material having the fluidity into the groove in the wiring gap 214 without generating a hole. As a material of the second interlayer insulating film 217, a material having a lower relative dielectric constant than that of the first interlayer insulating film 104 is selected. Therefore, the first wiring 1 sandwiching the wiring gap 214
The relative dielectric constant between 13A can be reduced. Next, FIG.
As shown in (b), the second interlayer insulating film 104, the metal for interlayer connection 109, and the second interlayer insulating film 217 are formed using the CMP method so that the surfaces of the second interlayer insulating film 104 and the second interlayer insulating film 217 are flush with each other. Is flattened. First interlayer insulating film 104
And the second interlayer insulating film 217 are made of different materials,
Is set such that the etching rate of the interlayer insulating film 104 in CMP is lower than the etching rate of the second interlayer insulating film 217. Thus, the first interlayer insulating film 104 is used as an etching stopper. Next, as shown in FIG. 4C, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second layer is formed using photolithography and dry etching.
Is formed.

As described above, according to the present embodiment, the entire area of the wiring gap 214 is formed by the second interlayer insulating film 217 using a material having a lower relative dielectric constant than the first interlayer insulating film 104. Embed Therefore, the relative dielectric constant between the first wirings 113A sandwiching the wiring gap 214 can be reduced, and the relative dielectric constant can be determined by the material of the second interlayer insulating film 217.

Since the first wiring 113A is formed after the formation of the interlayer connection metal 109, the first wiring 11A must be formed over the entire lower surface of the interlayer connection metal 109.
3A is formed. Therefore, poor connection between the first wiring 113A and the metal for interlayer connection 109 can be prevented.

After forming the interlayer connection metal 109 in the interlayer connection hole of the first interlayer insulating film 104, the first wiring 113A and the second interlayer insulating film 217 are formed sequentially.
As a result, even if misalignment occurs during the formation of the first wiring, either the metal 109 for interlayer connection or the first interlayer insulating film 104 must be present on the upper surface of the first wiring 113A, and The second interlayer insulating film 217 always exists in the gap 214. Therefore, short-circuit failure between the first wirings 113A and short-circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109 can be prevented.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 4D is a process flow chart illustrating the method for manufacturing the semiconductor device according to the embodiment. Steps up to FIG. 5A are the same as those of the first embodiment, that is, FIGS. 1A to 1A, except that the thickness (2.5 μm) of the first interlayer insulating film 304 is increased.
2D and FIGS. 2A and 2B, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as shown in FIG. 5A, a second wiring inversion resist pattern 320 is formed on the first interlayer insulating film 304, the interlayer connecting metal 309, and the second interlayer insulating film 317. It is formed by photolithography. The second wiring inversion resist pattern 320 has a displacement dimension 3
A case where the alignment is formed by 11 is considered. For example, the diameter of the interlayer connection hole is 0.3 μm, and the width of the groove of the second wiring inversion resist pattern 320 is 0.1 μm.
In the case of 3 μm, the allowable deviation 311 between the interlayer connection metal 309 buried in the interlayer connection hole and the groove of the second wiring inverted resist pattern 320 is:
The maximum is 0.1 μm. Next, as shown in FIG. 5B, the first interlayer insulating film 304 and the second interlayer insulating film 317 are formed.
To form a wiring groove 3 having a depth of 0.5 μm.
21A is formed. Next, as shown in FIG. 5C, an adhesion layer (not shown) made of a titanium alloy
Is deposited, a second metal layer 322 made of aluminum, an alloy of aluminum and copper, copper, or the like is formed.
In order to form the second metal layer 322, a vacuum evaporation method or C
The VD method or the like is used. Next, as shown in FIG. 5D, the second metal layer existing outside the wiring groove is removed by a CMP method to form a second wiring 323.

Second Inverted Resist Pattern 320 for Wiring
The relationship between the displacement of the second wiring 323 due to the displacement and the metal 309 for interlayer connection will be described with reference to FIGS. 6 and 5B to 5D. FIG. 6 is a perspective view showing the positional relationship between the wiring groove in which the second wiring is to be formed and the metal for interlayer connection, corresponding to the presence or absence of misalignment. In FIG. 6, the case of a wiring groove 321B formed without a misalignment by dry etching will be considered. In this case, a wiring groove 321B having the same width as the diameter of the interlayer connection metal 309 is formed. The second wiring is the wiring groove 32
1B, the interlayer connection metal 309 and the second metal 309 are almost entirely formed on the side surfaces of the interlayer connection metal 309.
Contacts with other wiring. On the other hand, by dry etching,
Consider the case of a wiring groove 321C formed with misalignment. In this case, the wiring groove 321C having the same width as the diameter of the interlayer connection metal 309 is formed shifted by the shift dimension 311 in FIG. 5B. Since the metal 309 for interlayer connection is not etched, the portion of the side surface of the metal 309 for interlayer connection other than the portion that has been cut into the first interlayer insulating film 304 by the deviation dimension 111 is exposed to the wiring groove 321C. Therefore, most of the side surfaces of the metal 309 for interlayer connection correspond to the second metal layer 32 in FIG.
2 and also contacts the second wiring 323 in FIG. 5D after the CMP.

As described above, according to this embodiment, even when the second wiring inversion resist pattern 320 for forming the second wiring 323 is misaligned, the side surface of the interlayer connection metal 309 can be formed. Most contacts the second wiring 323. Therefore, in addition to the same effects as in the first embodiment, even when the second wiring inversion resist pattern 320 is misaligned, the reliability of the connection between the interlayer connection metal 309 and the second wiring 323 is improved. Can be improved.

(Fourth Embodiment) A semiconductor according to this embodiment will be described with reference to FIGS. 7A to 7D, FIGS. 8A to 8C, and FIGS. 9A and 9B. A method for manufacturing the device will be described.

First, as shown in FIG. 7A, an insulating film 102 (thickness 0.8 μm), an aluminum alloy and a titanium alloy are formed on a semiconductor substrate 101 on which a semiconductor active element (not shown) is formed in advance. Metal layer 103 having a laminated structure of
(Thickness: 0.5 μm) and a first interlayer insulating film 104 (thickness: 1.0 μm) are sequentially deposited. Thereafter, an interlayer connection resist pattern 105 is formed, and an interlayer connection hole 106 is opened by dry etching.

Next, as shown in FIG. 7B, an adhesion layer 107 made of, for example, TiN / Ti is deposited on the surface having the interlayer connection hole 106 after the resist pattern 105 for interlayer connection has been peeled off. Then, an interlayer connection material 108 made of tungsten is deposited by blanket W-CVD. The adhesion layer 107 and the interlayer connection material 1 existing outside the interlayer connection hole 106 by dry etching or CMP.
08 is removed. The adhesion 107 and the interlayer connection material 108 that exist only inside the interlayer connection hole 106 together form a metal 109 for interlayer connection.

Next, as shown in FIG. 7C, the first interlayer insulating film 104 is etched back by about 0.5 μm,
The remaining film thickness of the interlayer insulating film 104 is adjusted to 0.5 μm. At this time, the metal for interlayer connection 109 protrudes upward from the surface of the first interlayer insulating film 104.

Next, as shown in FIG. 7D, the first interlayer insulating film 104 and the metal
The wiring resist pattern 110 is formed. Consider a case where the first wiring resist pattern 110 is formed with a misalignment by a misalignment dimension 111. For example, when the diameter of the interlayer connection hole 106 is 0.3 μm and the width of the first wiring resist pattern 110 is 0.3 μm, the first metal 110 for the interlayer connection embedded in the interlayer connection hole 106 and the first The allowable deviation dimension 111 from the wiring resist pattern 110 is 0.1 μm at the maximum.

FIG. 3A is a plan view showing the relationship between the displacement of the first wiring resist pattern 110 and the metal 109 for interlayer connection. The position of the first wiring resist pattern 110 is located below the wavy line in FIG.
The position of the first wiring resist pattern 110 and the position of the interlayer connection metal 109 match on the upper side of the wavy line.

Next, as shown in FIG. 8A, a CF-based etching gas for removing an oxide film and a Cl-based etching gas for removing aluminum are used.
The surface having the first wiring resist pattern 110 is sequentially dry-etched. First, the first interlayer insulating film 104 in the opening of the first wiring resist pattern 110 is removed by dry etching using a CF-based etching gas at a low temperature. In this case, the interlayer connection metal 109 in the misaligned portion 112 is
It is not etched by the CF-based etching gas.
Further, the first metal layer 103 in the opening of the first wiring resist pattern 110 is removed by dry etching using a Cl-based etching gas until the insulating film 102 is exposed. As a result, the first wiring 11
Form 3A. Also in this case, the metal 109 for interlayer connection in the misaligned portion 112 is not etched by the Cl-based etching gas.

FIG. 3B is a perspective view showing the positional relationship between the first wiring 113 and the metal for interlayer connection 109 corresponding to the presence or absence of misalignment. First, the first metal layer 10
From 3, the case of the wiring 113B formed by dry etching without any misalignment will be considered. In this case, an interlayer connection metal 109 having the same diameter as the width of the wiring 113B is formed on the upper surface of the wiring 113B. On the other hand, consider the case of the wiring 113C formed out of alignment with the first metal layer by dry etching. In this case, the first metal layer located below the interlayer connection metal 109 is not etched during the dry etching. Therefore, in the misaligned portion 112 in FIG. 8A, the first metal layer located under the interlayer connection metal 109 remains without being etched by self-alignment, and thus has a shape as shown in FIG. Is formed. Accordingly, the first wiring 113A including the wiring 113B or the wiring 113C is always formed on the entire lower surface of the interlayer connection metal 109. In addition, since the portion below the first wiring resist pattern 110 in FIG. 8A is not etched, the portion above the first wiring 113A where the interlayer connection metal 109 does not exist is the first portion. The interlayer insulating film 104 remains. As a result, the first interlayer insulating film 1 is formed on the first wiring 113A.
04 or the metal 109 for interlayer connection is always present.

Next, as shown in FIG. 8B, the insulating film 102 is carved by about 0.5 μm by dry etching using a CF-based etching gas. As a result, the first wiring 113A having a shape sandwiched between the upper and lower insulating films is formed. The non-engraved insulating film immediately below the first wiring 113A is referred to as 112A. Therefore, the first metal layer 103 under the interlayer connection metal 109 or the first wiring resist pattern 110 forms the first wiring 113A.

The total thickness of the first wiring 113A formed from the first metal layer 103, the first interlayer insulating film 104, and the insulating film 112A is 1.5 μm. Therefore, the aspect ratio of the groove 115 formed in the portion having the minimum width of 0.3 μm in the wiring gap 114 which is a region between the adjacent first wirings 113A is about 5. Note that a wiring dummy pattern may be formed on the field portion 116 where the first wiring does not exist.

Next, as shown in FIG. 8C, after the first wiring resist pattern 110 is released, the insulating film 102 and the first interlayer insulating film 1 of the semiconductor substrate 101 are removed.
04, a second interlayer insulating film 117 is deposited on the interlayer connection metal 109 using a plasma CVD apparatus. The wiring gap 1 in the groove formed in the wiring gap 114
Part or all of the region 14 is formed by the second interlayer insulating film 117.
In some cases, the holes 118 are not filled. In particular, in a trench having a high aspect ratio, the wiring gap 11
The entirety of the region 4 becomes the hole 118. Next, FIG. 9 (a)
As shown in FIG.
The second interlayer insulating film 117 is planarized so that the surface of the second interlayer insulating film 117 and the surface of the second interlayer insulating film 117 are flush with each other. Since the second interlayer insulating film 117 is buried to some extent in the upper part of the trench having the high aspect ratio, the void 118 forms an opening in the surface of the second interlayer insulating film 117 after the CMP. There is no. Then figure
9 (b), a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and the second wiring 119 is formed using photolithography and dry etching.
To form

Here, referring to FIGS. 10A and 10B and FIGS. 11A and 11B, the shape of the holes formed by the method of depositing the second interlayer insulating film 117 is as follows. Will be described.

First, reference is made to FIG. FIG.
(A) shows an ideal form in which the second interlayer insulating film 117 does not enter the groove 115 at all, and the holes occupy the whole of the groove 115. In this case, since there is no insulating film between the adjacent wirings 113A, the capacitance C1 between the wirings is extremely small. In the case shown in FIG. 10A, the upper ends of the holes do not extend above the upper surface of the first interlayer insulating film 104. Therefore, the second interlayer insulating film 1
Even if 17 is polished by the CMP method, there is a small possibility that holes are exposed. If the second interlayer insulating film 117 is formed by CMP
If holes are communicated to the outside through the polished surface when polished by the method, the function as an interlayer insulating film may be impaired, and a short circuit between wirings may occur.

FIG. 10B shows the second interlayer insulating film 117.
Are deposited on the bottom surface and the side surfaces of the groove 115, and holes are formed in the groove 115.
The figure occupies a small part of the inside. Such a mode is obtained when the second interlayer insulating film 117 is deposited under conditions of good coverage. For example, in the case of the plasma CVD method using TEOS as a raw material, before the second interlayer insulating film 117 in the deposition process closes the upper part of the groove 115,
An insulating film having a certain thickness is deposited on the bottom and side surfaces of the groove 115. As a result, the capacitance C2 between the wirings 113A increases.

FIG. 11A shows the second interlayer insulating film 117.
Does not enter the inside of the groove 115 at all, and the upper portion 118 of the hole extends above the upper surface of the first interlayer insulating film 104. Such a form is the second
Is obtained when the interlayer insulating film 117 is formed under conditions by a deposition method having poor coverage and high directivity. For example, from a film called a high-density plasma (HDP) film to a second
When the interlayer insulating film 117 is formed, holes having a form as shown in FIG. 11A are obtained. In this case, since no insulating film is deposited inside the groove 115, the capacitance C3 between the wirings 113A is reduced.

The high density plasma (HDP) film is
It is formed using an HDP device. In this HDP device, when an HDP film is deposited while applying a bias voltage to the substrate, an etching phenomenon occurs during the deposition so as to compete with the deposition. No longer extends above the upper surface of the first interlayer insulating film 104. FIG. 11B shows a hole having such a form. HDP deposited while applying bias voltage to substrate
When the second interlayer insulating film is formed of a film, an insulator slightly deposits on the bottom surface of the groove. However, when the insulating film which is a lower layer of the first wiring layer is etched, the deposited insulator is the first insulator. Of the wiring 113A.
Is kept low.

Therefore, as shown in FIG. 8B, when the step of etching the insulating film 102 is performed, even if a small amount of insulating material is deposited on the bottom of the groove, the capacitance C between the wirings 113A is reduced.
4 is kept low. This will be described with reference to FIGS. FIG. 12A illustrates one form of a hole when performing a step of not etching the insulating film 102, and FIG. 12B illustrates one form of a hole when performing the step of etching the insulating film 102. Is shown. In the case of FIG. 12A, if an insulator is deposited on the bottom surface of the groove, the insulator exists between the wirings.
The capacitance C5 is larger than the capacitance C4. For this reason, when forming the second interlayer insulating film by a deposition method that forms holes as shown in FIGS. 10B and 11B, the step of etching the insulating film 102 is omitted. Do
It is preferable that the bottom surface of the groove be lower than the lower surface of the first wiring layer 113A.

From the viewpoint of reducing the capacitance between wirings, FIG.
Although it is most preferable that a hole having the form shown in FIG. 1A is formed, when the second interlayer insulating film is planarized by CMP, the second interlayer insulating film reaches a level where the upper end of the hole is located. There is a high possibility that the film will be etched. But,
If the metal for interlayer connection 109 is projected above the level of the upper surface of the first interlayer insulating film 104, polishing formed by CMP can be stopped at the level of the upper surface of the metal for interlayer connection 109. That is, the metal 1 for interlayer connection
09 functions as a kind of etching stop layer. In this case, it is easy to control the polished surface to be at a position higher than the upper end of the hole, so that even if the hole shown in FIG. Also,
In the case of forming a hole having the form shown in FIG. 11A, the necessity of etching the insulating film 102 is low. However, the inter-wiring capacitance C3 when the insulating film 102 is etched is lower than the inter-wiring capacitance when the insulating film 102 is not etched at all. This is because the inter-wiring capacitance is determined by the physical properties of a space having a certain extent located between two adjacent wirings, so that the dielectric constant of the space above and below the space beside the wiring is also affected. To receive.

As described above, when the insulating film 102 located in the region between the first wiring layers 113A is partially etched, it is necessary to reduce the wiring capacity when forming various holes. It turns out to be effective.

As described above, according to the present embodiment, a part or all of the area of the wiring gap 114 becomes the air hole 118 made of air, so that the space between the first wirings 113A sandwiching the wiring gap 114 is formed. The relative dielectric constant can be reduced. In particular, when the groove 115 formed in the wiring gap 114 has a high aspect ratio, the entire area of the wiring gap 114 becomes a hole 118, so that the relative dielectric constant between the first wirings 113A is minimized. can do.

Further, since the first wiring 113A is formed after the formation of the metal for interlayer connection 109, the first wiring 11A must be formed over the entire lower surface of the metal for interlayer connection 109.
3A is formed. Therefore, poor connection between the first wiring 113A and the metal for interlayer connection 109 can be prevented.

After forming the metal 109 for interlayer connection in the interlayer connection hole 106 of the first interlayer insulating film 104,
Of the wiring 113A and the second interlayer insulating film 117 are sequentially formed. As a result, even if the misalignment occurs during the formation of the first wiring, either the metal 109 for interlayer connection or the first interlayer insulating film 104 always exists on the upper surface of the first wiring 113A, and The metal for interlayer connection 109 is not buried in the hole 118 formed simultaneously with the second interlayer insulating film 117. Therefore, short-circuit failure between the first wirings 113A and short-circuit failure between the wiring and the semiconductor substrate 101 via the interlayer connection metal 109 can be prevented.

(Fifth Embodiment) A fifth embodiment of the present invention will be described with reference to FIGS. FIGS. 13A to 13D are process flow charts showing the method for manufacturing the semiconductor device according to the present embodiment. The steps leading to FIG. 13 (a) are the same as those in FIGS. 1 (a) to (d) and FIGS. 8 (a) and (b), so that the same components as those in the first embodiment are the same. The reference numerals are attached and the description is omitted. In the present embodiment, the second interlayer insulating film 212 is formed by a coating method instead of depositing the second interlayer insulating film 117 by the plasma CVD apparatus in the first embodiment. As the second interlayer insulating film 212, for example, organic polysiloxane,
An organic film made of a material such as an organic material containing fluorine, an inorganic porous film, and the like are conceivable. Many of these materials have fluidity.

First, as shown in FIG. 13A, a first interlayer insulating film 204 formed on a semiconductor substrate 201 is formed.
The above-mentioned material is applied on the metal for interlayer connection 208 and the wiring gap 215. Accordingly, the second interlayer insulating film 212 can be formed by filling the material having the fluidity into the groove in the wiring gap 215 without generating a hole. Second
As a material of the interlayer insulating film 212, the first interlayer insulating film 2
A material having a relative dielectric constant lower than 04 is selected. Therefore, the relative dielectric constant between the first wirings 203 sandwiching the wiring gap 215 can be reduced. Next, as shown in FIG.
Using a CMP method, the second interlayer insulating film 212 is planarized so that the surfaces of the first interlayer insulating film 204, the metal for interlayer connection 208, and the second interlayer insulating film 212 are flush with each other. I do. First interlayer insulating film 204 and second interlayer insulating film 2
12 is made of a different material so that the etching rate of the first interlayer insulating film 204 in the CMP is lower than the etching rate of the second interlayer insulating film 212. Thus, the first interlayer insulating film 204 is used as an etching stopper.

Further, as shown in FIG. 13C, after only the second interlayer insulating film 212 is selectively etched in the depth direction by about 0.3 μm, the third interlayer insulating film 214 is etched by about 0.1 μm. Deposit 5 μm. Again, the third interlayer insulating film 214 is planarized by using the CMP method so that the surfaces of the first interlayer insulating film 204, the metal for interlayer connection 208, and the third interlayer insulating film 214 are flush with each other. .

Next, as shown in FIG. 13D, a metal layer having a laminated structure of aluminum and a titanium alloy is deposited, and a second wiring 216 is formed by using photolithography and dry etching. .

As described above, according to the present embodiment, the entire area of the wiring gap 215 is formed by the second interlayer insulating film 212 using a material having a lower relative dielectric constant than the first interlayer insulating film 204. Embed Therefore, the relative dielectric constant between the first wirings 203 sandwiching the wiring gap 215 can be reduced, and the relative dielectric constant can be determined by the material of the second interlayer insulating film 212.

Since the first wiring 203 is formed after the formation of the interlayer connection metal 208, the interlayer connection metal
08, the first wiring 203
Is formed. Therefore, poor connection between the first wiring 203 and the metal for interlayer connection 208 can be prevented.

After forming the metal for interlayer connection 208 in the interlayer connection hole of the first interlayer insulating film 204, the first wiring 203 and the second interlayer insulating film 212 are sequentially formed. As a result, even if the misalignment occurs during the formation of the first wiring, either the metal for interlayer connection 208 or the first interlayer insulating film 204 must be present on the upper surface of the first wiring 203, and In the gap 215, the second interlayer insulating film 2
12 are always present. Therefore, the metal for interlayer connection 20
8, short-circuit failure between the first wirings 203 and short-circuit failure between the wiring and the semiconductor substrate 201 can be prevented.

Also in this embodiment, the first wiring 203
The insulating film 202 located in the region between the portions is partially etched. For this reason, the capacitance between wirings is substantially governed by the relative dielectric constant of the second interlayer insulating film. If the insulating film 202 located in the region between the first wirings 203 is not etched, the insulating film 202 located in the vicinity of the region between the first wirings 203 may increase the wiring capacitance to some extent. Become.

In this embodiment, since the third interlayer insulating film 214 is provided, even if a film made of a material having low etching resistance or low plasma resistance is used as the second interlayer insulating film 212, The second interlayer insulating film is not damaged by the step of forming the wiring. It is preferable to use a film made of a material having high etching resistance or plasma resistance as the third interlayer insulating film. Therefore, even if the relative dielectric constant of the third interlayer insulating film 214 increases, the capacitance between the first wirings 203 does not increase.

In the embodiment shown in FIGS. 13A to 13D,
Although no holes are formed in the wiring gap 215, the wiring gap 2
A hole may be formed in 15.

(Sixth Embodiment) In the present embodiment, the second
The steps up to the formation of the interlayer insulating film are the same as in the fifth embodiment. This embodiment is characterized in the step of forming a second interlayer insulating film. Hereinafter, the step of forming the second interlayer insulating film will be described in detail with reference to FIGS. 14 (a), (b) and (c).

FIGS. 14A to 14C show that the width is 0.5 μm.
m, a relatively narrow groove (first gap) 115a having a width of not more than 0.5 μm and a relatively wide groove (for example, 0.8 μm or more, second gap) having a width of more than 0.5 μm are formed. Is shown. Here, the first wiring layer 113A is
The first wiring includes first to third wirings, and a first gap 115a is formed between the first wiring located at the center in the drawing and the second wiring located on the left side, and the first wiring 115a and the right side are formed. The second gap 115b is formed between the second wiring 115b and the third wiring located at the second position.

FIGS. 14A and 14B show cross sections when the second interlayer insulating film 117 is formed from the same type of insulating film. In the example of FIG. 14A, an insulating film having relatively poor coverage is deposited. As a film having such poor coverage, for example, a plasma oxide film formed using a silane / N ₂ O-based gas plasma in a parallel plate type plasma CVD apparatus can be used. When such a film is used, the grooves 115a and 11
Holes are formed in both of 5b. Large holes are formed in the relatively wide grooves 115b. For this reason, the upper portion of the hole in the groove 115b may exceed the level indicated by the line to be polished by CMP. If such large holes are formed, the holes may be exposed from the polished surface after polishing by CMP. When the holes are exposed by polishing, there is a risk of disconnection failure or short-circuit failure of the second layer wiring.

On the other hand, in the example shown in FIG. 14B, an insulating film having good burying performance is deposited as the second interlayer insulating film 117. For example, a plasma oxide film formed using high-density plasma (HDP) can be used as such a film having good burying performance.
When such a film is used, the second interlayer insulating film 117
Is also deposited on the bottom and side surfaces of the groove 115a having a relatively small width. As a result, a hole smaller than the size of the groove is formed in the groove 115a. Relatively wide groove 1
The inside of 15b is filled with the second interlayer insulating film 117, and no holes are observed therein. The HDP layer is HDP
It is formed using an apparatus. In this HDP device,
When the HDP film is deposited while applying a bias voltage to the substrate, an etching phenomenon occurs during the deposition so as to compete with the deposition, so that the insulating film is deposited on the bottom surface of the groove and the filling performance is improved. In this case, the upper end of the hole does not reach the level indicated by the CMP polishing line. However, since the holes in the groove 115a are small, the effect of reducing the capacitance between the wirings is small.

In the present embodiment shown in FIG. 14C, both advantages can be taken. That is, the second interlayer insulating film 117 is formed from insulating layers formed by at least two different forming methods. More specifically, first,
After the upper portion of the relatively narrow groove 115a is substantially covered with the interlayer insulating layer 117a, the second interlayer insulating layer 117b is formed.
Fills another wide groove 115b. Specifically, after a first interlayer insulating layer 117a is formed using a silane / N ₂ O-based gas plasma in a parallel plate type plasma CVD apparatus, a _second interlayer insulating layer 117a is applied while applying a bias voltage to a substrate in an HDP apparatus. The insulating layer 117b may be deposited.

Although the first interlayer insulating layer 117a and the second interlayer insulating layer 117b can be typically formed of a silicon oxide film, the second interlayer insulating layer 117b is formed of a low dielectric constant organic coating film such as polyallyl ether. May be formed.
Note that the first interlayer insulating layer 117a is made of, for example, silane gas,
Pressure 5mTorr using oxygen gas and argon gas
Can be deposited under

According to the embodiment of FIG. 14C, a large hole is formed in the first gap 115a, and the second gap 11a is formed.
5b is buried by the second interlayer insulating layer 117b,
No holes are exposed by polishing by MP.

When the size of the hole (the ratio of the hole to the wiring gap) is increased, the upper end of the hole becomes higher. The size of the holes and the height of the holes can be optimized by adjusting the thicknesses of the first interlayer insulating film 117a and the second interlayer insulating film 117b.

Next, the evaluation results of the multilayer wiring structure manufactured according to the present embodiment will be shown.

First, FIGS. 15 (a), 15 (b) and 1
See FIG. 5 (c). FIG. 15A shows a wiring gap and a positional relationship between holes. Here, “H” indicates the distance from the upper surface of the first wiring layer to the top of the hole, and “D” indicates the distance from the lower surface of the first wiring layer to the bottom point of the hole. The hole occupancy “R” indicates the ratio of the hole width W to the wiring gap S.

FIG. 15B shows the dependence of the hole occupancy R on the wiring gap S. The occupancy R of the vacancy is expressed as S =
When the thickness is 0.8 μm or less, a positive value exceeding 0 is shown. The occupancy R increases as the wiring gap S decreases.
When S = 0.3 μm, the occupation ratio R shows a value of about 0.9.

FIG. 15C shows the dependence of H and D on the wiring gap. The value of H is 50 at any wiring gap.
It does not reach the planned CMP polishing line (800 to 1000 nm above the wiring) without exceeding 0 nm. That is, even after the interlayer insulating film 117 is planarized by CMP, the holes are not exposed. Therefore, the yield of the second-layer wiring does not decrease.

Next, the effect of reducing the inter-wiring capacitance of the multilayer wiring manufactured according to the present embodiment will be described with reference to FIG. FIG. 16 shows, as a comparative example, data in the case where no holes were formed between the wirings by using a circle. In the case of the comparative example, the inter-wiring capacitance per unit length increases as the wiring gap decreases, whereas the inter-wiring capacitance of the present embodiment decreases rather as the wiring gap decreases. It is considered that the decrease in the capacitance between the wirings is caused by an increase in the occupation ratio R of the holes to the wiring gap as the wiring gap becomes smaller.

Next, reference is made to FIGS. 17 (a) and (b).

The effect of reducing the capacitance between wirings according to the present embodiment will be compared with the effect of reducing the capacitance between wirings when a low dielectric constant interlayer film is used.

FIG. 17A is a sectional view showing the structure of a model used for calculation (simulation). FIG.
(B) shows the dependency of the effective relative permittivity on the wiring interval. This effective relative permittivity is obtained by calculating the capacitance (per unit length) between wirings when a uniform medium having a certain relative permittivity is used as an interlayer insulating film, and the capacitance obtained by actual measurement. Was determined by comparing with In this embodiment, as indicated by the square marks in FIG. 17B, the effective relative permittivity decreases as the wiring gap decreases. When the wiring gap becomes 0.8 μm or less, holes are formed in the wiring gap. When the holes are formed, the effective relative permittivity sharply decreases. When the wiring gap is 0.3 μm, the effective relative permittivity drops to about 1.8.

FIG. 18 shows the relationship between the resistance value of the metal for interlayer connection (via) and the diameter of the metal for interlayer connection (via diameter). Even when the present embodiment is compared with the comparative example in which no holes are formed, there is no large difference between the via resistance values.

FIG. 19 shows the dependence of the via resistance value on the amount of alignment shift between the first wiring layer and the metal for interlayer connection. The alignment shift amount indicates a magnitude of misalignment between the metal for interlayer connection and the first wiring layer. In the pattern used for the measurement, since the width of the first wiring layer and the via diameter are the same, there is no overlapping margin between the first wiring layer and the metal for interlayer connection. FIG.
As can be seen from the above, in the conventional example, the via resistance value increases as the alignment shift amount increases,
In the present embodiment, the via resistance maintains a constant value regardless of the alignment shift. This is because the contact area between the first wiring and the metal for interlayer connection always has a maximum value because the metal for interlayer connection is surely present on the upper surface of the first wiring layer even if the misalignment occurs. Because it is maintained.

Since the second interlayer insulating film 117 is deposited after the formation of the metal 109 for interlayer connection, the holes formed simultaneously with the deposition of the second interlayer insulating film 117 are in contact with the metal 109 for interlayer connection. I will not do it. Therefore, neither a short-circuit failure between the first wirings 113A via the interlayer connection metal 109 nor a short-circuit failure between the wiring and the semiconductor substrate 101 occurs.

Note that the material of the first wiring layer is not limited to Al. For example, it may be Cu. Instead of using a plasma oxide film as the second interlayer insulating layer 117b constituting the second interlayer insulating film 117, a coating insulating film having good filling performance may be used. Further, the method of forming the second interlayer insulating film described with reference to FIG. 14C has an effect that can be applied to other embodiments.

In each of the above embodiments, the present invention has been described for a semiconductor device using a normal silicon substrate, but the present invention is not limited to this. As long as the semiconductor device has a multilayer wiring structure, a semiconductor substrate other than silicon or an SOI substrate may be used.
A substrate using an insulating substrate such as glass or plastic may be used.

[0133]

According to the present invention, the first wiring is always formed on the entire lower surface of the metal for interlayer connection. Therefore, even if the first wiring is misaligned, the first wiring is formed. Poor connection between the first wiring and the metal for interlayer connection can be reliably prevented. Further, the metal for interlayer connection is not buried in the holes formed simultaneously with the second interlayer insulating film. Therefore, a short circuit between the first wirings and a short circuit between the wiring and the semiconductor substrate via the metal for interlayer connection can be prevented.

If a part or the whole of the wiring gap forms a hole made of air, or if the whole of the wiring gap is filled with a material having a low relative dielectric constant, the first wiring sandwiching the wiring gap is formed.
Can be reduced. Therefore,
A semiconductor device with a wide operation margin and less malfunction can be realized by suppressing signal delay between the first wirings.

Further, since most of the side surfaces of the metal for interlayer connection are in contact with the second wiring, even if the second wiring is misaligned when forming the second wiring, the second wiring and the metal for the interlayer connection may be displaced. Reliability in connection with metal can be improved.

Even if an alignment error occurs during the formation of the first wiring, either the metal for interlayer connection or the first interlayer insulating film must be present on the upper surface of the first wiring, and
The metal for interlayer connection is not buried in the holes formed simultaneously with the second interlayer insulating film. Therefore, a short circuit between the first wirings and a short circuit between the wiring and the semiconductor substrate via the metal for interlayer connection can be prevented.

[Brief description of the drawings]

FIGS. 1A to 1D are process flow charts showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are process flow charts showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3A is a plan view showing a positional relationship between a first wiring and an interlayer connection metal corresponding to the presence or absence of an alignment shift in the semiconductor device according to the first embodiment of the present invention;
(B) is a perspective view thereof.

FIGS. 4A to 4C are process flow charts showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5D are process flow charts showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a perspective view showing a positional relationship between a wiring groove corresponding to the presence or absence of an alignment shift and a metal for interlayer connection in a semiconductor device according to a third embodiment of the present invention.

FIGS. 7A to 7D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 8A to 8C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 9A and 9B are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views showing a form of a hole.

11A and 11B are cross-sectional views showing other forms of holes.

FIGS. 12A and 12B are cross-sectional views showing still another form of a hole.

13A to 13D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIGS. 14A to 14C are process cross-sectional views illustrating a sixth embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIGS. 15A to 15C are diagrams showing respective dimensions of holes in another embodiment of the semiconductor device according to the present invention.

FIG. 16 is a diagram showing a relationship between a wiring interval and a capacitance between wirings per unit length in an embodiment of the semiconductor device according to the present invention.

17A is a cross-sectional view of a wiring structure for calculating a capacitance between wirings of a semiconductor device, and FIG. 17B is a graph showing a relationship between a wiring gap and an effective relative permittivity.

FIG. 18 is a graph showing the relationship between via diameter and via resistance in one embodiment of the semiconductor device of the present invention.

FIG. 19 is a graph showing a relationship between an alignment shift amount between a first wiring layer and a via and a via resistance in an embodiment of the semiconductor device of the present invention.

FIG. 20 is a cross-sectional view showing a structure of a conventional semiconductor device.

FIGS. 21A and 21B are process flow charts showing a conventional method for manufacturing a semiconductor device.

FIGS. 22A to 22C are process flow charts showing a conventional method for manufacturing a semiconductor device.

DESCRIPTION OF SYMBOLS 101 semiconductor substrate 102 insulating film 103 first metal layer 104 first interlayer insulating film 105 interlayer connection resist pattern 106 interlayer connection hole 107 adhesion layer 108 interlayer connection material 208 interlayer connection metal 110 1 wiring resist pattern (first wiring pattern) 111 misalignment dimension 112 misaligned portion 114 wiring gap 115 groove 116 field portion without first wiring 117 second interlayer insulating film 118 void 119 second wiring

Claims (23)

[Claims] 1. A method of manufacturing a semiconductor device having a multi-layer wiring, comprising: a step of covering a surface of a substrate with an insulating film; a step of depositing a conductive film on the insulating film; Forming an interlayer insulating film; forming an interlayer connecting hole reaching the conductive film in the first interlayer insulating film; embedding an interlayer connecting metal in the interlayer connecting hole; Forming a masking layer defining a layer pattern on the first interlayer insulating film so as to cover at least a part of the metal for interlayer connection; and forming the first interlayer insulating film using the masking layer as a mask. Etching the conductive film using the masking layer and the interlayer connection metal as a mask, thereby forming a first wiring layer from the conductive film; and removing the masking layer. Second so as to cover the interlayer connecting metal and a first wiring layer
Depositing an interlayer insulating film on the substrate, flattening the second interlayer insulating film to expose at least a part of the metal for interlayer connection, and an upper portion of the metal for interlayer connection. Forming a second wiring layer electrically connected to the semiconductor device. A step of covering a surface of the substrate with an insulating film; a step of depositing a conductive film on the insulating film; a step of forming a first interlayer insulating film on the conductive film; Forming a reaching interlayer connection hole in the first interlayer insulating film, embedding a metal for interlayer connection in the interlayer connecting hole, partially etching the first interlayer insulating film from its surface, A step of projecting an upper end portion of the metal for interlayer connection from the first interlayer insulating film; and forming a masking layer defining a first wiring layer pattern so as to cover at least a part of the metal for interlayer connection. Forming on the first interlayer insulating film, etching the first interlayer insulating film using the masking layer as a mask, etching the conductive film using the masking layer and the interlayer connecting metal as a mask, It Forming a first wiring layer from the conductive film; removing the masking layer; depositing a second interlayer insulating film on the substrate so as to cover the interlayer connection metal and the first wiring layer. Exposing at least a portion of the interlayer connection metal by flattening the second interlayer insulating film; and a second wiring electrically connected to an upper portion of the interlayer connection metal. Forming a layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching of the conductive film is performed such that the interlayer connection metal is not substantially etched. Method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said step of forming said second interlayer insulating film is performed in a wiring gap between said first wiring layers. A method for manufacturing a semiconductor device, wherein holes including closed regions where no interlayer insulating film exists are also formed. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of planarizing the second interlayer insulating film does not expose the holes. 6. The method for manufacturing a semiconductor device according to claim 1, wherein a dielectric constant of a material used for the second interlayer insulating film is smaller than a dielectric constant of a material used for the first interlayer insulating film. Is a method of manufacturing a semiconductor device having a smaller size. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the step of forming the second interlayer insulating film includes: forming a first interlayer forming a part of the second interlayer insulating film. Forming an insulating layer; and forming a second interlayer insulating layer, which forms another part of the second interlayer insulating film, on the first interlayer insulating layer. In the step of forming an insulating layer, the first
The first interlayer insulating layer substantially covers the gaps of 0.5 μm or less so as to form voids in the gaps of 0.5 μm or less among the gaps formed by the wiring layers; In the step of forming the second interlayer insulating layer, in the gap formed by the first wiring layer, the second wiring layer is inserted into a gap substantially not covered by the first interlayer insulating layer.
A method for manufacturing a semiconductor device, wherein a part of an interlayer insulating layer is made to enter. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a first plasma CVD film formed by using plasma of a silane / N ₂ O-based gas is used as the first interlayer insulating layer. A method for manufacturing a semiconductor device, comprising: 9. The method for manufacturing a semiconductor device according to claim 7, wherein the second interlayer insulating layer is formed using high-density plasma to which a substrate bias voltage is applied.
A method for manufacturing a semiconductor device, comprising using a film. 10. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the first wiring layer comprises: using the masking layer as a mask to form the first interlayer insulating film and the conductive layer. A method of manufacturing a semiconductor device, comprising: forming a groove on a surface of an insulating film by etching a part of a base insulating film of the conductive film after etching the film. 11. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the second wiring layer comprises forming at least the first interlayer insulating film using a groove forming pattern as a mask. Forming a groove in the surface of the first interlayer insulating film by etching; and forming a second metal layer on the metal for interlayer connection, the first interlayer insulating film, and the second interlayer insulating film. Forming a second wiring by removing a portion of the second metal layer other than the inside of the groove. 12. A lower wiring layer comprising a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are adjacent to a first wiring with a first gap from the first wiring. A lower wiring layer including a second wiring to be formed, a third wiring adjacent to the first wiring with a second gap wider than the first gap, and the first wiring, the second wiring, and the second wiring. Forming a structure comprising: a first interlayer insulating film formed on the three wirings; and substantially blocking an upper part of the first gap to form a hole in the first gap. Depositing a first interlayer insulating layer that forms a lower portion of the second interlayer insulating film, and has better coverage than the first interlayer insulating layer that forms an upper portion of the second interlayer insulating film. The second gap is filled by depositing a second interlayer insulating layer, and The method of manufacturing a semiconductor device including a step of covering the whole. 13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of planarizing said second interlayer insulating film so as not to expose said holes. Manufacturing method. 14. The method of manufacturing a semiconductor device according to claim 12, wherein the second interlayer insulating layer is formed from an organic film having a lower dielectric constant than the first interlayer insulating layer. Method. 15. A lower wiring layer comprising a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are adjacent to a first wiring with a first gap from the first wiring. A second wiring, a lower wiring layer including a third wiring adjacent to the first wiring at a second gap from the first wiring, and formed on the first wiring, the second wiring, and the third wiring. A first interlayer insulating film, a connecting metal formed in the first interlayer insulating film and in contact with an upper surface of the first wiring, and formed above the first gap and the second gap. A second interlayer insulating film that forms holes in each of the first gap and the second gap; and a second interlayer insulating film formed on the second interlayer insulating film and electrically connected to the metal for interlayer connection. A semiconductor device comprising: an upper wiring layer to be connected. 16. The semiconductor device according to claim 15, wherein said upper wiring layer is a wiring having a buried structure, and wherein said upper wiring layer is formed in said second interlayer insulating film. . 17. The semiconductor device according to claim 15, wherein the base insulating film of the lower wiring layer has a groove formed below the first gap and the second gap. A semiconductor device in which a portion of the second interlayer insulating film having a height that does not protrude above the upper surface of the base insulating film exists in the groove. 18. The semiconductor device according to claim 15, wherein an upper end portion of said metal for interlayer connection protrudes above an upper surface of said first interlayer insulating film. 19. The semiconductor device according to claim 15, wherein the first wiring is the second wiring and / or the third wiring.
It has side portions that protrude locally toward the wiring,
A semiconductor device in which an upper surface of the side portion is covered with the metal for interlayer connection. 20. The semiconductor device according to claim 19, wherein the side surface of the first wiring is formed in a self-aligned manner with respect to the metal for interlayer connection. 21. A lower wiring layer comprising a plurality of wirings formed on the same insulating film, wherein the plurality of wirings are adjacent to a first wiring with a first gap from the first wiring. A second wiring, a lower wiring layer including a third wiring adjacent to the first wiring at a second gap from the first wiring, and formed on the first wiring, the second wiring, and the third wiring. A first interlayer insulating film, and a second interlayer insulating film covering the lower wiring layer and having an upper surface planarized, wherein the second gap is wider than the first gap, The second interlayer insulating film includes a first interlayer insulating layer and the first interlayer insulating layer.
The first interlayer insulating layer includes a second interlayer insulating layer formed on the interlayer insulating layer, an upper surface of the second interlayer insulating film is planarized, and the first interlayer insulating layer and the second interlayer insulating layer are formed on the first gap. A hole is formed in the first gap to block the upper part, and the second gap is formed between the first interlayer insulating layer and the second gap.
A semiconductor device embedded with an interlayer insulating layer. 22. The semiconductor device according to claim 21, wherein the second interlayer insulating layer has better coverage than the first interlayer insulating layer. 23. The semiconductor device according to claim 21, wherein said first interlayer insulating layer is formed of a silicon oxide film, and said second interlayer insulating layer is formed by a dielectric constant of said first interlayer insulating layer. A semiconductor device formed from an organic coating film having a low dielectric constant.