JPH10154940A - Decoding circuit for reed solomon code - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the decoding circuit that is in parallel operation in time division with respect to an arithmetic operation for a reed Solomon code so as to continuously accept data. SOLUTION: Since it is not yet required to conduct time division parallel processing for the processing of a first reception word, an m0-1 register 118 being a component of the decoding circuit calculates a syndrome from each basic cell. After the reception of a succeeding received word is started, the processing of the first reception word and the syndrome calculation of the succeeding reception word are conducted in time division. In the case of conducting chain search and syndrome calculation in time division, since an evaluation arithmetic operation for an error value polynomial (omega) and an error position polynomial (lambda) is conducted alternately in the chain search operation, the error position polynomial (lambda) is latched by the m1 register 118 and the error value polynomial (omega) is calculated by using an m0-1 register 114.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error correction decoding of Reed-Solomon codes used for correcting random errors, and more particularly to high-order Reed-Solomon codes having excellent error correction capability. The present invention relates to a high-speed operation circuit used for high-speed decoding.

[0002]

2. Description of the Related Art Reed-Solomon codes are used for error and correction of digital codes. In decoding a higher-order Reed-Solomon code, (1) calculation of a syndrome polynomial (2) calculation of an error position / error value polynomial (3) Chein Search (an error position / error value polynomial evaluation method, Usually, three steps are required. Since the calculation of the syndrome polynomial requires all of the codewords, it cannot be completed without receiving or reading out the codewords. In general, the calculation of the error position / error value polynomial cannot be started unless the calculation of the syndrome polynomial has been completed. Since the calculation of the error position / error value polynomial and the Chien search require a large amount of calculation, the processing often takes time.

[0003] For this reason, in an application that requires continuous reproduction of code words, for example, Japanese Patent Laid-Open No.
Like the error correction device described in Japanese Patent No. 7844, it has a syndrome polynomial generator, an error position / error value polynomial calculation unit, and three circuits for Chien search, and the code word error position / error value polynomial During the calculation or the Chien search calculation, the syndrome of the next code word must be calculated.

[0004] In Japanese Patent Application No. Hei 6-273526, filed by the applicant of the present invention, a generator of a syndrome polynomial, generation of a modified syndrome polynomial / erasure polynomial, a calculator of an error position / error value polynomial, and Chen It has been shown that the search circuit can be efficiently configured as a single circuit and high-speed processing is possible. However, Japanese Patent Application No. 6-27
In No. 3526, when a certain codeword is being processed, another codeword cannot be processed. Therefore, when data needs to be continuously reproduced, a system configuration in which a buffer memory is provided in front of an error correction circuit is required. Was.

[0005] Furthermore, Reed-Solomon codes, such as magneto-optical disks, are generally used in an interleaved form in order to increase the ability to correct burst errors. However, in the past, each codeword had to be processed separately in the decoding operation, and thus had to be temporarily stored in a buffer memory to deinterleave. That is, the data is written to the buffer memory in the order of reception, the codeword of each interleave is read, and supplied to the decoding circuit. Then, it is necessary to write the correction result in the buffer memory and read the corrected data in the order of reception.

[0006]

Problems to be Solved by the Invention Japanese Patent Application No. Hei 6-106 shown above.
In the case of 273526, when a certain codeword is being processed, another codeword cannot be processed. Therefore, when data needs to be continuously reproduced, a buffer memory needs to be placed before the error correction circuit.

In the case of an interleaved code, it is necessary to place a buffer memory before the decoding circuit in order to process the interleave.

[0008] Further, in this buffer memory, all received data is written, all received data is read in the interleave direction, an error portion is read, and a correction result is written.
A step of finally reading all data is required. For this reason, all data has to be moved in and out at least three times, and the buffer memory used needs to be high speed.

[0009]

In order to solve the above-mentioned problem, the present invention is directed to a decoding circuit for a 2t-order Reed-Solomon code, which comprises 2t basic cells and 1t connected in cascade. Number of term cells, a control circuit for controlling the basic cells and the term cells, the basic cells comprising at least three sets of registers, a multiplexer for controlling the registers and operations, and an operation on a Galois field. The term cell has a circuit for performing an operation on the Galois field and a register, and the control circuit uses a set of registers of the basic cell to generate a code word. Calculate the syndrome polynomial of
Using the other two sets of registers, calculate the error position / error value polynomial of another codeword or evaluate the error position / error value polynomial, and perform the syndrome polynomial and other operations in a time-division manner. It is characterized by controlling.

This makes it possible to concurrently generate the syndrome polynomial for the next codeword while calculating the error position / error value polynomial for a certain codeword or evaluating the error position / error value polynomial. Therefore, the decoding circuit can always receive the data, and it is not necessary to temporarily store the data in the buffer memory.

The decoding circuit for Reed-Solomon codes according to claim 1, wherein each of the three registers of the basic cell is constituted by one register.

A register for holding an intermediate value in the middle of calculation is provided in each basic cell so that a syndrome polynomial can be generated in a time-division parallel manner when calculating or evaluating an error position / error value polynomial.

Thus, the decoding circuit can always receive the data, and does not need to temporarily store the data in the buffer memory.

Further, in the circuit for decoding a Reed-Solomon code according to the first aspect, the three sets of registers of the basic cell are each constituted by a register having a number of interleaving depths.

In order to decode the interleaved code, in each basic cell, registers for storing the intermediate values of the calculations are provided by the number of interleaves, so that the calculation of the interleaved code can be performed in a time-division parallel manner. Things.

As a result, even in the case of an interleaved code, the decoding circuit can always accept the data and can accept the data with the interleaved state. Therefore, it is not necessary to temporarily store the data in the buffer memory in order to release the interleave.

Further, in the Reed-Solomon decoding circuit according to claim 1, two of the three registers of the basic cell are each constituted by a register having a number of interleaving depths. Features.

With this configuration, although the output order of the correction results does not match the order of the input data, the number of registers can be reduced.

[0019]

Embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a circuit configuration of a basic cell according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a circuit configuration of a term cell. The term cell circuit is described in Japanese Patent Application No. 6-27.
The configuration is the same as that shown in No. 3526. FIG. 3 is an overall connection diagram. This is the same as Japanese Patent Application No. 6-273526.

In the basic cell 100 shown in FIG. 1, 132 is a multiplier on a Galois field, and 134 is an adder on a Galois field. The multiplier 132 and the adder 134 can be replaced by a single multiplier / adder. Reference numerals 102, 104, and 106 denote multiplexers, which switch inputs of the multiplier 132 and the adder 134, respectively. The switching control lines of the multiplexers 102, 104 and 106 are s2, s0 and s1, respectively. 114, 116 and 118 are a group of registers called m registers. 120
And 122 are register groups called n registers. Each register 114, 116, 118, 120 and 122
Are write control lines wm0-1, wm0-2,
wm1, wn0, wn1. The output of the m register group is selected by the multiplexer 110. Similarly, the outputs of the n registers are selected by the multiplexer 112. Multiplexers 110 and 112 are connected to control line sm
3, sn3. Qbus is a common bus. Mi _-1 is an input, which is connected to the Mi output of the preceding basic cell. M _i is an output and is connected to the input M _i-1 of the succeeding basic cell. 108 is a multiplexer,
s4 is the control line. As inputs to the multiplexer 104, a constant input (syndrome constant) for calculating a syndrome polynomial, a constant input (lambda constant) for evaluating an error locator polynomial, and a constant input (omega constant) for evaluating an error value polynomial are provided. Has been entered.

In the term cell shown in FIG. 2, 202 is a latch and lk2 is its control line. 204 is an adder on the Galois field, and SUM _odd ,
And it outputs the SUM to SUM _even as input. 218 is S
UM is a zero detection circuit, and sumzero is its output. Reference numeral 220 denotes a zero detection circuit for the input M _2t−1 ,
Is its output. 206 is a register, and wf is its write control line. 208 is an inverse function operation circuit on the Galois field, and 210 is a multiplier on the Galois field.
222, 224 and 226 are multiplexers;
si1, si2, and si3 are the control signals. 212
Is a latch, and lk1 is its control signal. 214
Is a Galois field sequencer, 216 and 217 are 2t deep
FIFO register.

FIG. 3 shows a decoding circuit for error detection / correction of a 2t-order Reed-Solomon code. The decoding circuit shown in FIG. 3 is obtained by interconnecting the 2t basic cells shown in FIG. 1 and the TERM cells shown in FIG. 100 is
2t basic cells BU0, BU1,... BU2t-1. 302 is a multiplexer, and s1 is its control line. 304 is a control circuit. Control signals to the control lines of the basic cell and the term cell are output from the control circuit. Note that the control signals to the control lines of all the basic cells are common, and the mzero output in FIG. 2 is an input to the control circuit. A correction unit 306 receives the corrected output of the term cell and sumzero,
The codeword has been corrected.

The multiplexer 302 switches between constants 0 and 1 and inputs the same to Mi _{-1 of the} 0th basic cell BU0. 0 is input to the SUM _i-1 input of the 0th and _1st basic cells BU0 and BU1. 2i-th basic cell B
The input of SUM _{i-1 of} U _2i is the basic cell BU of 2i-2.
connected to SUM _i output of _i-2 , 2i + 1th basic cell B
The SUM _i-1 input of U _2i +1 is the 2i-1 basic cell BU
Connect to _2i -1 SUM _i output. SUM _odd input terms cell 200 is connected to the SUM _i output of the basic cell of 2t-1 th, SUM _{the even} inputs are connected to the SUM _i output of the basic cell of 2t-2 th.

The algebraic procedure for decoding the Reed-Solomon code with the configuration shown in FIGS. 1, 2 and 3 is the same as that of the decoding circuit shown in Japanese Patent Application No. 6-273526. is there.

Now, in the decoding circuit of FIG. 3, the processing of the first received word does not have to be performed by time-division parallel processing yet, so that it operates in the same manner as in Japanese Patent Application No. 6-273526. That is, the basic cells are set such that the multiplexer 104 of each basic cell selects the syndrome constant, the multiplexer 106 selects Qbus, and the multiplexer 102 selects Mi. Then, on Qbus, Term Cell 200
, M0 in each basic cell
The calculation of the syndrome polynomial is accumulated in the -1 register 114 or the m0-2 register 116. Here, it is assumed that the syndrome is calculated in the m0-1 register 116 for convenience.

When performing the erasure calculation, Japanese Patent Application No. 6-273 is disclosed.
Galois body sequencer 21 for each vanishing position as in No. 526
6 is written to FIFO-1 216.

When all the first received words have been received,
Similar to Japanese Patent Application No. 6-273526, the erasure polynomial is calculated and the Euclidean mutual elimination operation is performed, and the error position / error value polynomial is calculated.

As described above, until the reception of the next received word is started, the process proceeds in the same manner as in Japanese Patent Application No. 6-273526.

After the reception of the next received word is started, the processing of the first received word and the syndrome operation of the next received word are performed by time division. The time-division processing differs depending on the stage at which the processing of the first received word has progressed and the processing of the next received word is started.

FIG. 4 shows, for example, the first received word Chen.
The state of the control signal for performing the search and the calculation of the syndrome polynomial of the next received word in time division parallel is shown.

In FIG. 4, an operation is alternately performed every three cycles for two received words, that is, three cycles of the Chien search (lambda / omega) and three cycles of calculating the syndrome polynomial are alternately performed. A timing example will be described.

Now, in the configuration of FIGS. 1 to 3, the operation of each basic cell and the term cell in the Chien search operation is the same as that of Japanese Patent Application No. 6-273526. That is, FIG.
As shown in (1), during the first received word Chien search operation, the evaluation calculation of the error value polynomial (Omega) and the error position polynomial (lambda) are performed alternately.

During the operation of the Chien search, the multiplexer 104 of the basic cell shown in FIG. 1 alternately selects a lambda / omega constant. The multiplexer 106 selects Qbus, and the multiplexer 102 selects Mbus.
i is selected. Qbus outputs 0 through the term cell multiplexer 226.

Since the evaluation operation of the error value polynomial (Omega) and the error locator polynomial (lambda) are performed alternately, the error locator polynomial (lambda) is placed in the m1 register 118, and the error value polynomial (Omega) is placed in the m0-1 register. 114 is used.
Therefore, in the cycle for performing the evaluation calculation of the error locator polynomial (lambda), the multiplexer 104 selects the lambda constant, enables the control line wm1, and the multiplexer 110 outputs the error locator polynomial (lambda) from the m1 register 118. In the cycle in which the evaluation operation of the error value polynomial (Omega) is performed, the cycle in which the multiplexer 104 selects the Omega constant enables the control line wm0-1 and the multiplexer 110 controls the m0-1 register 1
14 outputs an error value polynomial (Omega).

The error position polynomial and the value of the error value polynomial are sequentially output to SUMi of the last stage. The operation of the term cell receiving the request is the same as that of Japanese Patent Application No. 6-273526.

The operation when calculating the syndrome polynomial of the next received word is the same except that the control line wm0-2 is enabled and the syndrome polynomial is integrated in the register m0-2116. That is, the multiplexer 1
04 selects a syndrome constant, and the multiplexer 10
6 selects Qbus, and the multiplexer 102 selects Mi. The control line wm0-2 is enabled, and the multiplexer 110 outputs the register m0-2. Qbu
By inputting the received word to s, the syndrome polynomial is integrated in the registers m0-2.

When performing the erasure calculation, F is used for each erasure calculation.
Write the output of the Galois field sequencer to IFO-2 217.

In the above description, the Chien search for the first received word and the calculation of the syndrome polynomial for the next received word are performed in a time-division parallel manner. Next, a description will be given of a case where the generation of the modified syndrome polynomial / erasure polynomial for calculating the error position polynomial / error value polynomial or the operation of the Euclidean mutual division method and the calculation of the syndrome are performed in time division parallel. In this case, the operations of the generation of the erasure polynomial and the Euclidean mutual division method are respectively described in Japanese Patent Application No. 6-273.
526, using the same method as in No. 526.
The m1 register 118 and the n0 register 120, the n1 register 122, and the term cell FIFO-1 216 are used. Then, in the syndrome calculation cycle, the syndrome calculation and the erasure position recording are performed using the m0-2 register 116 and the term cell FIFO-2 217 in the same procedure as described above.

Subsequently, when the processing of the next received word is further performed, the syndrome calculation and the disappearance position recording of the received word are performed by the m0-1 register 114 and the FIFO-1221.
6, the m0-2 register 116, the m1 register 118 and the n0 register 120, the n1 register 12
2 and FIFO-2 217 to perform processing after generation of the altered syndrome polynomial / erasure polynomial. Or later,
M0-1 register 114 and m0-2 register 11 alternately
6 can be used to configure an error correction circuit capable of continuously receiving data.

As described above, the operation can be performed in a time-division parallel manner by switching the register to be used.

FIG. 4 shows an example of the timing in which the received word is alternately performed every three cycles, that is, for example, the Chen search (lambda / omega) and the syndrome calculation are performed alternately every three cycles. However, this can be switched by rules optimized according to the speed of the data. For example, it is also possible to interrupt the Chien search operation each time a received word is detected and perform the control performed when the syndrome operation is performed.

When the erasure correction function is not required, it is possible to construct an embodiment in which the components for the function are omitted.

As in the case of Japanese Patent Application No. Hei 6-273526, it is possible to add a function of an encoding operation.

(Embodiment 2) Embodiment 2 is a circuit for decoding a code interleaved by time division. FIG.
Indicates an extended basic cell corresponding to the interleaved code. FIG. 6 is a term cell corresponding to the interleaved code.

The extended basic cell of FIG. 5 has a configuration in which registers m0-1 and m0-2 are multiplexed by the interleave depth (N) with respect to the configuration of the basic cell shown in FIG. Has become. 5, the same components as those in FIG. 1 are denoted by the same reference numerals. Now, 514, 516 and 51
Reference numeral 8 denotes a group of N registers corresponding to the interleave depth (N), and the registers to be written and read are control lines wm0-1 (j) and wm0-1 respectively.
(J), rm0-2 (j) and wm0-2 (j) and r
selected by m1 (j) and wm1 (j) (j: 1 to 1)
N).

The term cell shown in FIG. 6 is composed of FIFO-1 216 and F-1 in the configuration of the term cell shown in FIG.
FIFO-2 217 is multiplexed into N FIFOs 217 each.
1 (N) 616 and FIFO-2 (N) 617.

The overall configuration used for the interleaved Reed-Solomon decoding circuit is the same as that of FIG. 3 of the first embodiment.

Now, a description will be given of a syndrome operation when the extended basic cell of FIG. 5 is combined with the term cell of FIG. 6 to have a configuration similar to the entire configuration shown in FIG. FIG.
Will be described based on the timings of FIGS. 7 to 9.

FIGS. 7 to 9 show successive timings in the three figures. Similarly, the decoding circuit for the interleaved Reed-Solomon code, which is composed of the extended basic cells shown in FIG. This shows that the calculation of the syndrome polynomial and the Chien search are operated in a time-division parallel manner.

7 and 9, a case in which the operation of calculating a syndrome polynomial is performed will be described. In FIG. 5, as in the first embodiment, the multiplexer 104 of each extended basic cell selects a syndrome constant, the multiplexer 106 selects Qbus, and the multiplexer 102 selects Mi. The received word is input to Qbus. The multiplexer 110 selects the output of the m0-2 (j) register (j: 1 to N).

When the input data of the received word is the first in the interleave, the control line wm0 for the register group 516
-2 (1) and rm0-2 (1) are enabled to select the m0-2 (1) register. Thereafter, the control lines wm0-2 (j) and rm0-2 (j) are similarly enabled in accordance with the interleaving of the input data of the received word, and the m0-2 (j) register is selected (j: 1 to 1).
N). By using the selected register, the syndrome polynomial can be calculated independently for each interleave.

Similarly, the chain search process shown in FIG. 8 can be performed for each interleave.
That is, when the j-th (j: 1 to N) interleave processing is performed, the control lines wm0-1 (j) and rm0-1
(J), wm1 (j) and rm1 (j) are enabled, and the other control lines perform the same control as in Japanese Patent Application No. 6-273526, and execute all steps of the Chien search. The Chien search operation is performed using the m1 (j) register for the error locator polynomial (lambda) and the m0-1 (j) register for the error value polynomial (Omega). By using a register selected from the register group, a Chien search can be performed independently for each interleave.

As shown in FIGS. 7 to 9, when the extended basic cell of FIG. 5 is used, the calculation of the syndrome polynomial and the Chien search are performed on the interleaved Reed-Solomon code in a time division manner. Can be processed in parallel.

Similarly, for the erasure polynomial generation / Euclidean mutual division method, by using the selected register,
The calculation can be performed independently for each interleave.

In the generation of the erasure polynomial, m0-1
(J) The erasure polynomial is generated using the polynomial stored in the register as an initial value. The resulting modified syndrome polynomial and erasure polynomial are m0-1 (j) for each elementary cell.
Registers and m1 (j) registers.

The Euclidean algorithm executes the Euclidean algorithm using the polynomials stored in the registers m0-1 (j) and m1 (j) as initial values. The resulting error locator polynomial (lambda) is stored in the m1 (j) register and the error value polynomial (omega) is stored in m0-1 (j).

Referring to FIG. 10, a case will be described in which the error locator polynomial (lambda) and the error value polynomial (omega) are obtained by the Euclidean algorithm. FIG. 9 shows registers m0-1 (j) 514 and register m0 of each extended basic cell.
-2 (j) 516, register m1 (j) 517, register n0 120 and register n1 121 are shown.

FIG. 10 shows an example in which the error locator polynomial and the error value polynomial are directly calculated from the syndrome polynomial without performing the erasure calculation.

In FIG. 9, in the time division period in which the Euclidean mutual division method is performed, the register m0-
Using 1 (j) and n0 and registers m1 (j) and n1 as (j: 1 to N), using the syndrome polynomial of each interleave stored in the register m0-1 (j) as an initial value, an error occurs. Operations corresponding to each interleave of the value polynomial (Omega) and the error locator polynomial (lambda) are performed independently. Then, the result is obtained in the registers m0-1 (j) and m1 (j).

FIG. 11 shows the operation when erasure correction is performed. FIG. 11 is the same as FIG. 10 except that the generation cycle of the modified syndrome polynomial / erasure polynomial is inserted before the Euclidean operation of each interleave. In the generation of the modified syndrome polynomial / erasure polynomial, based on the syndrome polynomial of each interleave stored in the register m0-1 (j) and the erasure information stored in the FIFO-1 (j) of the term cell,
By the same procedure as in Japanese Patent Application No. 6-273526, m0-1
A metamorphic syndrome polynomial is obtained in (j) and an erasure polynomial is obtained in m1 (j). The subsequent Euclidean algorithm is
This is executed with m0-1 (j) and m1 (j) as initial values.

As described above, during the operations of generating the erasure polynomial, Euclidean mutual division method, and Chien search, all multiplexers operate in the same manner as in Japanese Patent Application No. 6-273526, and m0 corresponding to the interleave to be processed. -1
(J), m0-2 (j) and m1 (j).

Therefore, the multiplexing of the syndrome operation and other decoding operations can be performed on the interleaved received words in the same manner as in the first embodiment. That is, the syndrome of the current received word is obtained in the m0-2 register. The value of the decoding operation of the previous received word is m0-
It exists in one register. At the time of the syndrome operation, all the multiplexers operate in the same manner as in the first embodiment, and a register corresponding to the interleaving of the received word is selected.

The switching of the time-division parallel operation may be controlled appropriately according to the speed and distribution of the received data.

Further, it is also possible to adopt a configuration in which an encoding operation function is added as in the first embodiment.

(Embodiment 3) When it is not necessary to output the correction results in the same order as the data input order, the number of registers can be reduced. That is, if a series of operations of the erasure polynomial, the Euclidean mutual division method, and the chain search are continuously performed for each interleave, it is not necessary to leave both the Omega and lambda polynomials of each interleave, so the m1 register may be single. At this time, the correction result is output in the order of all error values / positions of interleave 1, all error values / positions of interleave 1,... All error values / positions of interleave N. This case will be described with reference to FIGS.

FIG. 12 shows a circuit of a basic cell in a case where it is not necessary to output a correction result in the same order as data input. In this figure, registers m0-1 (j) 1
014 and the registers m0-2 (j) 1016 have the number N of interleaving depths, and the registers m1 1018
Is one. Another configuration is the second embodiment shown in FIG.
Is similar to the extended basic cell. By combining this with the term cell of FIG. 3, a Reed-Solomon code decoding circuit is configured as in the second embodiment.

In the Reed-Solomon decoding circuit of this embodiment, the operation during the syndrome operation of the time division operation is as follows:
As in the second embodiment, the register m0-1 (j) 1014
Alternatively, this is performed using m0-2 (j) 1016.

The time division operation of the Reed-Solomon decoding circuit for an interleaved received word using the extended basic cell will be described with reference to FIGS.

In FIG. 13, after the syndrome operation for a certain received word is completed, the syndrome polynomial of each interleave is stored in each register of m0-1 (j) 1014, and each syndrome of the next received word is stored in the register m. 2 (j) 1016 is calculated in each register.

The decoding operation using the interleaved Euclidean algorithm is performed in the register m0-1 (j).
Is performed using the registers m1, n1, and n0 as initial values. After completion of the Euclidean algorithm, an error value polynomial (Omega) and an error location polynomial (lambda) are calculated in the registers m0-1 (j) and m1.

Thereafter, a Chien search is performed using the registers m0-1 and m1 based on the error value polynomial (Omega) and error location polynomial (lambda) obtained by the Euclidean algorithm.

When the erasure operation is performed, a cycle of the erasure polynomial may be inserted before the Euclidean operation as in FIG.

FIG. 14 is an enlarged view of FIG. 13 showing the switching operation between interleave 0 and interleave 1 in the decoding operation.

Each operation is performed in synchronization with the clock pulse CLK. When the operation of the Euclidean algorithm with respect to interleave 0 is completed, the error value polynomial (omega) and error location polynomial (lambda) of interleave 0 become
It is determined for the registers m0-1 (0) and m1. The interleave 0 chain search is performed using this.

When the Chien search is being performed on interleave 0, registers m0-1
The intermediate result of the error value polynomial (Omega) is stored in (0). The register m1 stores an intermediate result of the error locator polynomial (lambda) of interleave 0.

When the time division operation is switched from interleave 0 to interleave 1, the Chien search performs the register m0-1 (1) while the intermediate result of the error value polynomial (Omega) is stored in the register m0-1 (0). Using the interleave 1 syndrome polynomial stored in
The interleave 1 Euclidean operation is performed using the register m1, the register n0, and the register n1.

As in the first embodiment, an encoding operation can be added.

[0079]

As described above, the decoding circuit of the present invention can continuously receive data because the operation for the Reed-Solomon code can be performed in a time-division parallel manner.

Also, the interleaved read
The Solomon code can be extended to one that can continuously receive data.

In addition, this configuration eliminates the need to temporarily store data in the buffer memory before giving data to the decoding circuit, and reduces the load on the buffer memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a basic cell.

FIG. 2 is a block diagram showing a configuration of a term cell.

FIG. 3 is a block diagram illustrating a configuration of a decoding circuit.

FIG. 4 is a time chart illustrating an operation of the decoding circuit.

FIG. 5 is a block diagram showing a configuration of an extended basic cell.

FIG. 6 is a block diagram showing a configuration of a term cell.

FIG. 7 is a part of a time chart showing the operation of the decoding circuit of the second embodiment.

FIG. 8 is a part of a time chart illustrating the operation of the decoding circuit according to the second embodiment.

FIG. 9 is a part of a time chart showing the operation of another decoding circuit.

FIG. 10 is a time chart illustrating an operation of the decoding circuit according to the second embodiment in the Euclidean mutual division method.

FIG. 11 is a time chart illustrating an operation of the decoding circuit according to the second embodiment in the Euclidean mutual division method.

FIG. 12 is a block diagram showing a configuration of another extension cell.

FIG. 13 is a time chart illustrating the operation of the decoding circuit according to the third embodiment.

FIG. 14 is a partially enlarged view of the time chart of FIG. 12;

[Explanation of symbols]

100 Basic cell 102, 104, 106, 108, 110, 112 Multiplexer 114, 116, 118 m register 120, 122 n register 132 Multiplier on Galois field 134, 136 Adder on Galois field 200 Term cell 202, 212 Register (latch) 204 Adder on Galois field 208 Inverse function operation circuit on Galois field 210 Multiplier on Galois field 214 Galois field sequencer 216 FIFO with 2t depth 218,220 Zero detection circuit 222,224,226 Multiplexer 302 Multiplexer 304 Control circuit 306 Correction unit 514, 516, 518 m register of number (N) of interleaving depth

Claims (4)

[Claims] 1. A decoding circuit for a 2t-order Reed-Solomon code, comprising: 2t basic cells and one term cell connected in cascade; and a control circuit for controlling the basic cells and the term cells. The basic cell has at least three sets of registers, a multiplexer for controlling the registers and operations, and a circuit for performing operations on Galois fields, and the term cell includes operations on Galois fields. And a register. The control circuit calculates a syndrome polynomial of a certain code word using one set of registers of the basic cell, and uses another two sets of registers. Calculates the error position / error value polynomial of another codeword or evaluates the error position / error value polynomial, and controls the calculation of the syndrome polynomial and other operations in a time-division manner A Reed-Solomon decoding circuit. 2. The Reed-Solomon code decoding circuit according to claim 1, wherein each of the three sets of registers of the basic cell comprises one register. 3. The Reed-Solomon decoding circuit according to claim 1, wherein each of the three sets of registers of the basic cell is constituted by a register having a number of interleaving depths. Solomon code decoding circuit. 4. The decoding circuit for a Reed-Solomon code according to claim 1, wherein two of the three registers of the basic cell are each formed of registers having a number of interleaving depths. A Reed-Solomon code decoding circuit.