JPH11168392A - Data error correction device and data error correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data error correction device and a data error correction method capable of accelerating repetitive correction. SOLUTION: This data error correction device is provided with a syndrome calculation circuit 4 for calculating the syndrome of the Q sequence and P sequence of sector data, a syndrome storage device 5 for storing the calculated syndrome of the respective sequences and an error correction circuit 6 for calculating an error position on the sequence and the correction value of error data based on the syndrome of one sequence stored in the syndrome storage device 5, obtaining a vector number and the error position on the other sequence corresponding to the calculated error position on one sequence and correcting the syndrome of the vector number on the other sequence based on the correction value and the error position on the other sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data error correction device and a data error correction method used for a CD-ROM decoder or the like.

[0002]

2. Description of the Related Art Error correction of sector data of a CD-ROM is processed based on "JIS X6281-1992 Appendix A (Regulation) Encoding for Error Correction by RSPC". In this conventional error correction, the syndrome of each of the 0th to 42nd vectors on the P sequence and the syndrome of each of the 0th to 23rd vectors on the Q sequence in the sector data encoding format are calculated, and the syndrome value S0 is calculated. , S1
If both are "0", it is determined that there is no error. If both syndromes S0 and S1 are not "0", an error correction process is executed. In the error correction process, an error position on each stream and a correction value of the error data are calculated, and the value of the byte data of the sector address converted by the address converter is corrected. Until both of the syndrome values S0 and S1 become "0", the error correction process of the Q sequence and the P sequence is repeated, such as Q correction → P correction → Q correction → P correction.

[0003]

However, in the above-mentioned conventional data error correction method, when performing repetitive correction, it is necessary to alternately read the data of each series from the sector buffer by the number of repetitions of the correction processing. There has been a problem that the correction process takes much time. An object of the present invention is to solve such a problem, and an object of the present invention is to provide a data error correction device and a data error correction method capable of increasing the speed of repeated correction.

[0004]

In order to achieve the above object, a data error correction apparatus according to the present invention comprises: syndrome calculating means for calculating a Q-sequence and a P-sequence of input sector data; A syndrome storage means for storing the syndromes of the Q and P sequences, and means for calculating an error position on the sequence and a correction value of error data based on the syndrome of one of the sequences stored in the syndrome storage means. Means for calculating a vector number and an error position on the other sequence corresponding to the calculated error position on one of the sequences, and based on the calculated correction value and the obtained error position on the other sequence. Means for correcting the syndrome of the vector number on the other series.

In the data error correction device of the present invention, by repeatedly performing correction through access to the syndrome storage means, access to the sector buffer does not occur except during data correction, and high-speed error correction can be performed even in a storage device having a small bandwidth. Correction processing can be performed.

Further, the data error correction device of the present invention stores a syndrome calculating means for calculating a Q-sequence and a P-sequence of the input sector data, and stores the calculated Q-sequence and the P-sequence syndrome. Syndrome storage means, means for calculating an error position on the sequence and a correction value of error data based on the syndrome of one of the sequences stored in the syndrome storage device, and an error position on the calculated one of the sequences Means for determining a vector number and an error position on the other sequence corresponding to, and means for determining whether to perform error correction based on the value of the syndrome of the obtained vector number on the other sequence,
Means for correcting a syndrome of a vector number on the other stream based on the calculated correction value and the obtained error position on the other stream.

In the data error correction apparatus of the present invention, whether to perform error correction is determined on the basis of the value of the syndrome of the vector number on the other stream corresponding to the error position on one stream. Since the repetitive correction is not performed, the speed of the error correction process can be increased, and the probability of occurrence of a correction error is reduced to improve reliability.

Further, the data error correction device of the present invention
The data error correction device according to claim 1 or 2,
The syndrome storage means has a plurality of storage areas capable of storing sector data, and further includes means for alternately transferring a syndrome calculation result for each sector data to the storage areas by the syndrome calculation means. I do. According to the present invention, syndrome calculation and error correction for a plurality of continuous sector data can be performed in parallel, and the speed of error correction can be increased.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an overall configuration of a data error correction device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an 8-bit input port to which descrambled sector data is input. Reference numeral 2 denotes a synchronization signal indicating the start timing of sector data. A data write request signal 3 indicates the write timing of the sector data. Reference numeral 4 denotes a syndrome calculation circuit for calculating a syndrome of sector data. 5
Is a syndrome storage device for storing syndrome calculation results. Reference numeral 8 denotes arbitration and switching of transfer requests such as data input, error correction, data transfer to the host, and DR.
It is a memory controller that controls the AM9. The memory controller 8 writes sector data to the DRAM 9 according to the address generated by the address counter 7. Reference numeral 6 denotes an error correction circuit that corrects data errors based on the value of the syndrome stored in the syndrome storage device 5. Reference numeral 10 denotes output data to the host interface. A signal 11 indicates the end of the sector data output from the address counter 7 to the syndrome storage device 5.

Next, the details of the main part of the data error correction device will be described.

The syndrome memory in the syndrome storage device 5 is constituted by two SRAMs having a width of 256 words of 16 bits, ie, two banks. As shown in Table 1 below, the two banks are switched for syndrome calculation and error correction in accordance with the NBANK signal switched by the synchronization signal SYNC.

[0014]

[Table 1] FIG. 2 shows the operation timing of the syndrome storage device 5.

The value (NBANK) of the syndrome memory bank selection register is inverted by the sector synchronization signal SYNC. In the period when the value of NBANK is "1" (sector time), in bank 0, the syndrome calculation is performed on the input data. On the other hand, in the bank 1, the error correction is repeatedly performed using the syndromes S0 and S1 of each vector calculated in the previous sector time. Next sector synchronization signal S
When YNC is input, the value (NBANK) of the syndrome memory bank selection register is inverted, and in bank 0,
Iterative correction is performed using the syndromes S0 and S1 of each vector calculated in the immediately preceding sector time, and the bank 1
In, the syndrome calculation for the input data is performed.

FIG. 3 shows the structure of the syndrome storage device 5.

The memories in the syndrome storage device 5 include two SRAM banks 0 (11) and 1 (1).
2). Each bank (11) (12)
Can hold the syndrome values S0 and S1 of 43 vectors of the P sequence and 26 vectors of the Q sequence for each of the MSB byte and the LSB byte. The syndrome memory chip selection circuit 13 selects the selection signal XSC in accordance with the value (NBANK) of the bank selection signal.
S, decodes the write signal XSWR and outputs the decoded result to the selected bank (11) (12).

The multiplexer 14 receives the address input SA [7: 0] from the syndrome calculation circuit 4 and the error correction circuit 6
Of the bank 0 (11) via the multiplexer 16 is selected. That is, when the value of the bank selection signal NBANK is “0”, the address input SA [7: 0] from the syndrome calculation circuit 4 is used as the address input of the bank 0 (11).
And when the bank selection signal NBANK is H, the address input CA [7: 0] from the error correction circuit 6 is selected as the address input of the bank 0 (11).

The multiplexer 15 receives the address input SA [7: 0] from the syndrome calculation circuit 4 and the error correction circuit 6
Of the bank 1 (12) via the multiplexer 17 is input to the address input CA [7: 0]. That is, when the value of the bank selection signal NBANK is “1”, the address input SA [7: 0] from the syndrome calculation circuit 4 is selected as the address input of the SRAM bank 1 (12), and the value of the bank selection signal NBANK is When "0", the address input CA [7: from the error correction circuit 6 as the address input of the SRAM bank 1 (12):
Select [0]. The multiplexer 16 is an address input multiplexer for bank 0 diagnosis, and can switch to the address input MA [7: 0] from the microprocessor when the MTEST input is “1”. Multiplexer 1
Reference numeral 7 denotes an address input multiplexer for bank 1 diagnosis, which can be switched to the address input MA [7: 0] from the microprocessor when the MTEST input is "1".

The multiplexer 18 is a multiplexer for selecting bank 0 data input, and has a bank selection signal NBA.
When NK is "0", the input SDI [7: 0] from the syndrome calculation circuit 4 is selected, and when the bank selection signal NBANK is "1", the input CDI [7: 0] from the error correction circuit 6 is selected.
Is selected and input to the multiplexer 20.

The multiplexer 19 is a multiplexer for selecting bank 1 data input, and has a bank selection signal NBA.
When the value of NK is "1", the input SDI [7: 0] from the syndrome calculation circuit 4 is selected, and the bank selection signal NBANK is selected.
Is "1", the input CDI from the error correction circuit 6
[7: 0] is selected and input to the multiplexer 21.

The multiplexer 20 is a data input multiplexer for bank 0 diagnosis. When the MTEST input is "1", a data input MD from the microprocessor is provided.
It can be switched to I [7: 0]. Multiplexer 21
Is a data input multiplexer for bank 1 diagnosis,
When the MTEST input is "1", it is possible to switch to the data input from the microprocessor.

The multiplexer 22 is a multiplexer for selecting the data output of the syndrome calculation circuit 4. When the value of the bank selection signal NBANK is "0", the bank 0 (1
1) Data output is selected and the bank selection signal NBANK
Is "1", the data output of the bank 1 (12) is selected.

The multiplexer 23 is a multiplexer for selecting data output to the error correction circuit 6, and when the value of the bank selection signal NBANK is "1", the bank 0 (11)
And the data output of the bank 1 (12) is selected when the value of the bank selection signal NBANK is "0".

The multiplexer 24 is a multiplexer for selecting the data output MDO [15: 0] from the syndrome memory to the microprocessor. When the value of the signal MA [9] is "0", the multiplexer 24 is connected to the bank 0 (11). Select data output,
When the value of the signal MA [9] is "1", the data output of the bank 1 (12) is selected.

Next, the details of the syndrome calculation circuit 4 will be described.

FIG. 4 shows the timing of syndrome calculation.
FIG. 5 shows the configuration of the syndrome calculation circuit 4.

In FIG. 5, reference numeral 31 denotes a syndrome memory series pointer generation circuit for generating an address pointer of the syndrome memory corresponding to the input sector data. The address pointer is initialized by the sector synchronization signal, and is updated according to the data write timing. 3
2 is for writing the input sector data to a write signal (WRIT).
This is a latch held at the timing of E).

Reference numeral 33 denotes a coefficient register for calculating the syndrome S1 of the P series holding α ^25-i . Numeral 34 denotes a coefficient register for calculating the syndrome S1 of the Q sequence holding ^α44-i . A Galois field multiplier 35 multiplies α ⁻¹ . Reference numeral 36 denotes a multiplexer for switching between a P-series coefficient and a Q-series coefficient. A Galois field multiplier 37 multiplies the input data by the coefficient. 38
Is a Galois field adder for calculating the syndrome S0. 39 is a Galois field adder for calculating the syndrome S1.

Reference numeral 40 denotes the timing of the last syndrome calculation of each vector of the P sequence and the Q sequence (SMEM LAS
This is a syndrome determination circuit that writes the calculation result in the syndrome memory at T) and simultaneously stores the determination result in the syndrome determination register. That is, the syndrome determination circuit 40 sets the value of the signal FSDOK to "1" when the values of the syndromes S0 and S1 of all the streams are "0", and sets "0" otherwise to set the syndrome to 0. Store it in the judgment register. If the value of any of the syndromes S0 and S1 is not "0", the value of the signal FSDRC is set to "1". Otherwise, the value is set to "0" and stored in the syndrome determination register.

Next, the configuration of the error correction circuit 6 will be described. FIG. 6 shows the configuration of the error correction circuit 6.

In the figure, reference numeral 41 denotes an 8-bit input port CDI [15: 8] to which the syndrome S0 from the syndrome memory is input. Reference numeral 42 denotes an 8-bit wide input port CDI [17: 0] to which the syndrome S1 from the syndrome memory is input. 43 is syndrome S0,
This is a syndrome determination circuit that outputs NOERROR (44) and CORRECT (45) as determination results from the value of S1. The judgment conditions are shown below.

NOERROR = (S0 [7: 0] == 0) && (S1 [7: 0] == 0) CORRECT = (S0 [7: 0]! = 0) && (S1 [7: 0]! = 0) Here, when the value of NOERROR is “1”, it indicates that error correction is unnecessary. When the value of CORRECT is “1”, it indicates that error correction is necessary. N
When the value of OERROR is “0” and the value of CORRECT is “0”, it means that either S0 or S1 is “0”, indicating that error correction is impossible.

Reference numeral 46 denotes a register FS0 T0 [7: 0] that holds the value of the syndrome S0. 47 is state T0
Register FS1 T holding the value of syndrome S1
0 [7: 0]. 48 is a register 46 and a register 47
Is an error calculation circuit that calculates an error position in a vector from the value of. An error position determination circuit 49 determines whether or not the error position in the vector obtained by the error calculation circuit 48 falls within a valid range. The determination result is output to the output port IRANGOK (50). 51
Is an inter-sequence vector number and error position conversion circuit for calculating a vector number and an error position of another sequence from a vector number and an error position of a sequence currently being corrected specified by the signal QMODE. The conversion circuit 51 outputs the signal QM
When the value of ODE is "0", the correction of the P sequence
When the value of ODE is "1", the Q sequence is corrected. 52
Is a corrected data sector address generation circuit for generating an address in a sector from a vector number and an error position according to the value of the signal QMODE.

Reference numeral 53 denotes a register for holding a vector number of another system. Reference numeral 54 denotes a register for holding an error position of another system. 56 is a register for holding a correction data sector address. 57 is an output port BAD [10: 0] for the correction data sector address. Reference numeral 58 denotes an output port KK [5: 0] for outputting an inter-sequence vector number.

Reference numeral 59 denotes a converter for converting an exponential expression of a Galois field into a vector expression. When the value of QMODE is “0”, the converter 59 calculates α
Outputs ^25-II . Α when QMODE is “1”
Outputs ^44-II . A Galois field multiplier 60 multiplies the syndrome S0 by the Galois field of α ^N-II .

Using the vector numbers of the other series output from the output ports KK [5: 0] (58) as addresses, the syndromes S0 and S1 of the other series are stored in the input port CDI [15: 8] (41) from the syndrome memory. Input port CDI [7: 0]
(42) is input.

Reference numeral 61 denotes a register for holding another series of syndromes S0. Reference numeral 62 denotes a register for holding another series of syndromes S1. Reference numeral 63 denotes a Galois field adder for correcting the syndrome S0 of another system. Reference numeral 64 denotes a Galois field adder for correcting the syndrome S1 of another series. The corrected value S0 'of the syndrome is output from the Galois field adder 63, and the corrected value S1' of the syndrome is output from the Galois field adder 64. Modified syndrome value S generated when the value of QMODE is "0"
0 'and S1' are shown below.

[0039] _{S0 q '= S0' q +} δ p S1 q '= S1' q + δ p α 44-iq where [delta] _p is the value to be added by the error correction of P sequence. iq
Is the inter-sequence vector number, the vector number of the P sequence output from the error position conversion circuit 51, and the error position of the Q sequence corresponding to the error position.

A multiplexer 65 switches the output to the output port CDI [15: 8] (67) for the syndrome memory. Reference numeral 66 denotes a multiplexer for switching the output to the output port CDI [7: 0] (68) for the syndrome memory. When the input signal from the input port T5 (69) is "1", the multiplexers 65 and 66 respectively output the modified syndrome values S0 'and S1' to the output ports [15: 8] (67) and the output port CDI [ 7: 0] (68). Thereby, the value S of the syndrome in which the vector number of the other series corresponding to the error position is corrected
0 'and S1' are written back to the syndrome memory.

Next, the details of the inter-sequence vector number and error position conversion circuit 51 will be described.

In the Reed-Solomon product code (RSPC) on a CD-ROM, the sequence number of the P sequence is k _p , the error position is i _p , Assuming that the sequence number of the Q sequence is k _Q and the error position is i _Q , (k _p , i _p ) and (k _Q , i _Q )
The following relationship holds between.

[0043] - conversion from P series to the Q series _{k Q = mod 26 (52-} k p + i p) i Q = k conversion from _p ······ (2) · Q series to the P series k _p = illustrating a configuration example of a _{i Q i p = mod 26 (} k Q + i Q) ······ (3) between sequences in Figure 8 vector number and the error position conversion circuit 51. "0" is applied to input port QMODE (73).
Is set, the conversion from the vector number and the error position in the vector of the P sequence to the vector number and the error position in the vector of the Q sequence is performed.

Reference numeral 71 denotes an input port K [5: 0] to which the vector number of the syndrome is input. Reference numeral 72 denotes an input port I [5: 0] to which an error position in the vector is input. When "0" is input to the input port QMODE (73), P
Conversion of the vector number and error position from the sequence to the Q sequence is performed, and when "1" is input, conversion of the vector number and error position from the Q sequence to the P sequence is performed. The converted vector number is output to the output port KK [5: 0] (74), and the error position in the converted vector is output to the output port II [5: 0] (75).

[0045] 76 is a subtractor for calculating the 52-K _p. 77 is a selector, if QMODE value is "0" (73), selects the output of the subtractor 76 (52-K _p), if the value of QMODE (73) is "1" K
Select [5: 0]. 78 denote adders, if the value of QMODE is _{"0", 52-K p} + I p from the adder 78
Is output, and when the value of QMODE is “1”, K _Q + I
_Q is output.

[0046] 79 is a calculator for calculating a remainder of 26, when the value of QMODE is _{"0", k Q = mod} 26 (52-k p + i p) is output from the arithmetic unit 79, QM
If the value of UDE is _{"1", i p = mod} 26 (K Q + I
_Q ) is output.

The output KK [5: 0] of the selector 80 is QM
When the value of the ODE is “0”, k _Q = mod ₂₆ (52−k
_p + i _p) next, if the value of QMODE is "1" k
_p = i _Q. The output II [5: 0] of the selector 81 is
When the value of QMODE is “0”, i _Q = k _p and Q
If the value of MODE is _{"1" i p = mod 26} (K Q +
_IQ ).

Next, the error correction sequence will be described.

First, each series of syndromes stored in the syndrome memory is scanned to determine whether or not it is necessary to execute error correction. If the result of this determination is that there is an error and error correction is possible, an error correction process is performed. If there is no error or the error cannot be corrected, the error correction process is not executed.

FIG. 9 is a timing chart of the error correction sequence.

CLK is a system clock, QMODE is a signal indicating a series of syndromes to be processed, and K [5: 0] is a vector number of the syndrome. The MSB is a signal for selecting an even address plane and an odd address plane of sector data. When the value of the MSB is "0", the syndrome of the even address plane is selected. When the value of the MSB is "1", the odd address plane is selected. Is selected. KK [5: 0] is the inter-sequence vector number and the vector number of the other series output from the error position conversion circuit 51 shown in FIG. CA [7: 0] is an address input to the syndrome memory.

As shown below, the following addresses are output to the syndrome memory according to the state of the correction process.

CA [7: 0] = {QMODE, K [5: 0], MSB} for states T0, T1, T2, T5 CA [7: 0] = {! QMODE, KK [5: 0], MSB｝ XCCS are syndrome memory selection signals. When the value is “0”, the syndrome memory is selected. X
CWR is a write signal of the syndrome memory. CD
O [15: 8] is the syndrome S0 of the address specified by the upper 8 bits of the data output from the syndrome memory. CDO [7: 0] is the syndrome S1 of the address specified by the lower 8 bits of the data output from the syndrome memory. These syndromes S0 and S1 are shown in FIG.
Is input to the syndrome determination circuit 40. CDI [15:
8] is a data output port to the syndrome memory,
The corrected syndrome S0 is written. CDI
[7: 0] is a data output port to the syndrome memory, in which the corrected syndrome S1 is written. NO
ERROR is an output of the syndrome determination circuit 40, and both the syndromes S0 and S1 are "0", indicating that there is no error. CORRECT is an output of the syndrome judging circuit 40, and both syndromes S0 and S1 are not "0" but 1;
Indicates that individual correction is possible.

In this figure, a syndrome error has occurred in the vector number 1 (KK [5: 0] = 1) of the syndrome check of the Q sequence and the odd-numbered plane (MSB = 1).
When the value of CORRECT is “1”, the state transits to the state T1 at the rise of the system clock.

The operation of each state will be described below.

State T0: The syndromes S0 [K] and S1 [K] are read from the syndrome memory. S0
If both [K] and S1 [K] are not “0”, the process proceeds to state T1.

State T1: An error position I on the series K and a correction value δ are calculated. If the error position I is within the range of the RSPC encoding format, the state T2
Proceed to. If the error position I is out of the range, the sequence counter is updated.

State T2: Vector number and error position II on other series KK corresponding to error position I on series K
Is calculated.

State T3: The values S0 and S1 of the syndrome of the vector number on the other series KK are read. S0, S
If both 1 are "0", the sequence counter is updated; otherwise, the process proceeds to state T4.

State T4: (1) The syndromes S0 and S1 on the other series KK are corrected by the correction value δ obtained in the state T1. The corrected syndrome value is S0 ',
S1 '= S0 [KK] + δ S1' = S1 [KK] + α ** (N-II) δ where δ = S0 [K]. (2) Activate a sub-sequence for correcting sector data.

State T5: Syndrome S0 of series K
"0" is written to [K] and S1 [K], and the sequence counter is updated.

[0062] The above error correction, whether the value of all of the syndromes S0, S1 becomes "0", or the error correction of a predetermined number of times N _MAX is repeated until completion.

The operation when error correction is actually started from the Q sequence will be described below with reference to the flowchart of FIG.

First, the syndromes S0 _Q and S1 _Q of each vector of the Q sequence are read from the syndrome memory (step S1), and it is checked whether both S0 _Q and S1 _Q are “0” (step S2). If both the syndromes S0 _Q and S1 _Q of a certain vector number are not “0”, the error position calculation circuit 48 of FIG. 6 calculates an error position in the vector on the Q sequence and its correction value (step S3). ).

Here, it is assumed that the error position is i _Q and the correction value is δ. When the error position i _Q is within the range (0 to 44) of the encoding format of the sector data, the following error correction processing is performed. When the error position i _Q is out of the range, the error processing is determined as an error position due to erroneous correction and the correction processing is skipped. (Step S4).

In the error correction step, first, the inter-sequence vector number and error position conversion circuit 51 determines the vector number k _P and error position i _P of the P sequence corresponding to the error position i _Q of the Q sequence ( Step S5).

Next, the syndromes S0 _P and S1 _P of the P series vector number k _P are read from the syndrome memory (step S6), and it is determined whether both S0 _P and S1 _P are “0” (step S6). S7).

When both S0 _P and S1 _P are “0”, the error position i _Q obtained from the syndromes S0 _Q and S1 _{Q of} the Q sequence is determined to be due to erroneous correction, and no correction is performed. On the other hand, Agego either S0 _P, S1 _P is not "0", the corrected data sector address generation circuit 5 shown in FIG. 6
2, the vector number k _P on the P sequence and the error position i _Q
, The corresponding byte data is read from the sector buffer based on the sector address, the byte data is corrected by the correction value δ, and written back to the syndrome memory, thereby obtaining the vector number k of the P sequence. modifying the syndromes S0 _P, S1 _P in _P (step S8).

Thereafter, the syndrome of each vector of the P sequence is read from the syndrome memory, and the error correction from the P sequence is performed in the same manner as the error correction from the Q sequence.

The case where the syndromes S0 and S1 of the vector number k _Q = 2 are not “0” in the error correction of the Q sequence will be described below.

FIG. 11 shows the RS of the CD-ROM sector data.
2 shows an encoding format by a PC. Q series vector number k _Q = 2 vector syndrome S0 (k _Q =
2), an error position calculation circuit from S1 (k _Q = 2), the error location i _Q = 14, correction value [delta] _Q is output. This error position i _Q corresponds to address 702 in the sector address. The byte data at address 702 of the sector data is δ _Q
, The P-sequence vector number k _P = 14
Syndrome _{S0 (k P = 14),} S1 (k P = 1
4) is modified to the following value.

[0072] where _{d i (i = 0,1,2 ...,} 2
5) is vector data of a _P -sequence vector number k _P = 14, and d ₁₆ is equivalent to byte data at address 702 of sector data.

S0 '(k _P = 14) = d ₀ + d ₁ +...
_{· + D 15 + d 16 '} + d 17 + ··· + d 24 + d 25 S1' (k P = 14) = α 25 d 0 + α 24 d 1 + ··· +
^{_{α 10 d 15 + α 9 d}} '16 + α 8 d' 17 + ··· + α 1 d 24
'Because it is ₁₆ = d ₁₆ + _{δ Q,} the value S0 syndrome after the error _{^{correction' + d 25 d (k P}} = 14), S1 '(k P
= 14) becomes the following value.

S 0 ′ (k _P = 14) = S 0 (k _P = 14) + δ _Q S 1 ′ (k _P = 14) = S 1 (k _P = 14) + α ⁹ δ _Q Therefore, the vector number k _P = 14 Syndrome S
The corrected values of 0 (k _P = 14) and S1 (k _P = 14) are δ _Q and α ⁹ δ _Q , respectively.

Next, the configuration of an information processing apparatus having a CD-ROM decoder using the data error correction device of this embodiment will be described with reference to FIG.

In the figure, a signal processed by a CD processor 101 is input to a CD processor interface 103 of a CD-ROM decoder 102. The CD processor interface 103 performs processing such as synchronization detection, descrambling, and serial-to-parallel conversion on the input signal, and outputs byte data, a sector synchronization signal,
Outputs a byte data write enable signal.

In the CD-ROM decoder 102, the syndrome calculation circuit 105 and the syndrome storage device 10
6. The data error correction device according to the above-described embodiment, which includes the error correction circuit 107 and the like, is provided. Also, 10
Reference numeral 8 denotes an address counter for counting addresses in the sector.

The byte data output from the CD processor interface 103 is stored in the IO bus controller 10.
9, the data is transferred to a buffer on the main storage device 112 via the IO bus 110 and the memory controller / bus bridge 111.

Reference numeral 113 denotes a microprocessor for controlling the information processing device, and reference numeral 114 denotes an input / output device. Also, 115
Is a decode completion interrupt signal, which is generated by the error correction circuit 107 when decoding of one sector or a designated number of sectors is completed, and sent to the microprocessor 113 through the memory controller / bus bridge 111. The microprocessor 113 can read the decoded sector data by accessing the sector data on the main storage device 112 in synchronization with this interrupt.

The sector data is stored in the syndrome calculation circuit 10.
In step 5, the syndrome of each vector of the P sequence and the Q sequence is calculated, and the result is output to the syndrome storage device 106. If the syndrome is not "0", the value of the syndrome determination register is set to "1". The error correction circuit 107 performs error correction based on the information stored in the syndrome storage device 106. Since the sector data exists in the sector buffer on the main storage device 112, the error correction processing is realized as a read cycle and a write cycle for the error position of the sector buffer on the main storage device 112 via the IO bus controller 109.

According to the present embodiment, the number of times of access to the sector buffer when performing repetitive correction between streams can be reduced as compared with the related art, and the correction processing speed can be improved. In addition, since the occupancy of the main storage device and the I / O bus is reduced by accessing the main storage device including the sector buffer in the data error correction processing, a DRAM or the like dedicated to a CD-ROM decoder conventionally required is used. Is unnecessary, and the cost of the CD-ROM decoder can be reduced.

[0082]

As described above, according to the present invention, by repeatedly performing correction through access to the syndrome storage means, access to the sector buffer does not occur except during data correction, and a storage device having a small bandwidth. However, high-speed error correction processing can be performed. Further, in the present invention, it is determined whether or not to perform error correction based on the value of the syndrome of the vector number on the other stream corresponding to the error position on the other stream, so that unnecessary repetitive correction is not performed. Therefore, the speed of the error correction process can be increased, and the probability of occurrence of a correction error is reduced, thereby improving the reliability.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an overall configuration of a data error correction device according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation timings of the syndrome storage device 5 of the present embodiment.

FIG. 3 is a diagram showing a configuration of the syndrome storage device 5;

FIG. 4 is a diagram showing a syndrome calculation timing by the syndrome calculation circuit 4 of the present embodiment.

FIG. 5 is a diagram showing a configuration of the syndrome calculation circuit 4.

FIG. 6 is a diagram illustrating a configuration of an error correction circuit 6 of the present embodiment.

FIG. 7: CD-ROM Reed-Solomon product code (RSP)
It is a figure which shows the geometric relationship of P vector and Q vector in C).

FIG. 8 is a diagram illustrating a configuration of an inter-sequence vector number and error position conversion circuit 51 according to the present embodiment.

FIG. 9 is a diagram showing an error correction timing according to the embodiment.

FIG. 10 is a flowchart showing a procedure of the error correction.

FIG. 11 is a diagram showing an RSPC encoding format of CD-ROM sector data.

FIG. 12 illustrates C using the data error correction device of the present embodiment.
FIG. 2 is a diagram illustrating a configuration of an information processing apparatus having a D-ROM decoder.

[Explanation of symbols]

 4 Syndrome calculation circuit 5 Syndrome storage device 6 Error correction circuit 40 Syndrome determination circuit 48 Error position calculation circuit 51 Inter-sequence vector number and error position conversion circuit

Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11B 20/18 572 G11B 20/18 572F

Claims (6)

[Claims] 1. A method for inputting a Q sequence and P
Syndrome calculation means for calculating a syndrome of a series; syndrome storage means for storing the calculated syndromes of each series; and error positions on the series based on the syndromes of one of the series stored in the syndrome storage means. Means for calculating a correction value of the error data, and means for calculating a vector number and an error position on the other sequence corresponding to the calculated error position on the one sequence, and the calculated correction value and the calculation Means for correcting a syndrome of a vector number on the other stream based on the obtained error position on the other stream. 2. The system according to claim 1, further comprising:
Syndrome calculation means for calculating a syndrome of a series; syndrome storage means for storing the calculated syndromes of the respective series; and an error position on the series based on the syndrome of one of the series stored in the syndrome storage means. Means for calculating a correction value of error data, and means for calculating a vector number and an error position on the other sequence corresponding to the calculated error position on one of the sequences, and Means for determining whether or not to perform error correction based on the value of the syndrome of the vector number; and a vector on the other sequence based on the calculated correction value and the obtained error position on the other sequence. Means for correcting a syndrome of a number. 3. The data error correction device according to claim 1, wherein said syndrome storage means has a plurality of storage areas capable of storing sector data, and said syndrome calculation means stores a syndrome calculation result for each sector data. A data error correction device, further comprising means for alternately transferring data to each of the storage areas. 4. The Q sequence and P of input sector data
Calculating a sequence syndrome and writing a calculation result to a memory; calculating an error position on the sequence and a correction value of error data on the basis of the syndrome of one of the sequences stored in the memory; Obtaining a vector number and an error position on the other sequence corresponding to the error position on one of the obtained sequences, based on the calculated correction value and the obtained error position on the other sequence. Correcting the syndrome of the vector number on the sequence of (i). 5. The system according to claim 5, wherein the Q sequence and P
Calculating a sequence syndrome and writing a calculation result to a memory; calculating an error position on the sequence and a correction value of error data on the basis of the syndrome of one of the sequences stored in the memory; Obtaining a vector number and an error position on the other sequence corresponding to the error position on one of the obtained sequences, and performing error correction based on the syndrome value of the obtained vector number on the other sequence. Judging whether or not, comprising a step of correcting the syndrome of the vector number on the other series based on the calculated correction value and the obtained error position on the other series, Data error correction method. 6. The data error correction method according to claim 4, wherein the memory has a plurality of storage areas for storing at least sector data, and stores the calculated syndrome calculation result for each sector in each of the storage areas. A data error correction method characterized by alternately transferring data.