JPH10154667A - Plate wiring and its method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a substrate of feeding electrode layer from being damaged under etching process of plate wiring. SOLUTION: A barrier metal layer 23 having Ti and Au layers of 50nm thickness each corresponding to a plate wiring area is formed on a semiconductor substrate 21 coated with a protective film 22. An opening 25 is made in a barrier metal layer 23 by coating with a lower layer, a resist film 24. A feeding electrode layer 27 is filmed all over its surface. An opening 29 smaller than the opening 25 is formed by corresponding to the opening 25. An Au plating layer 30 is formed in the opening 29 by an electrolytic plating with voltage supplied to the feeding electrode layer 27. When the feeding electrode layer 27 is etched after stripping the upper layer resist film 28, the protective film 22 will not be etched of as the barrier metal layer 23 lying in the lower layer close to the opening 25 prevents an etching liquid from reaching the film 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plating wiring suitable for being formed on a semiconductor device such as a microwave monolithic IC or a field effect transistor by a selective plating method, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a wiring material used for semiconductor devices such as high-frequency transistors and ICs, a low-resistance material such as a noble metal such as Au is often used to suppress high-frequency propagation loss. Regarding the formation method, since the material itself is expensive, a selective plating method that uses the material more efficiently and is advantageous for thickening the film should be used rather than the metal lift-off method that wastes a large amount of the material. Is common.

A general example of such a selective plating method will be described with reference to FIG. First, as shown in FIG.
A lower resist film 3 is formed by photolithography on a protective film 2 laminated on a semiconductor substrate 1 to form an opening 4 at a specific portion. Then, the opening 4
Is performed so that the cross section of the lower resist film 3 has a tapered shape. Thereafter, a power supply electrode layer 5 for performing electrolytic plating is applied to the entire surface.

Next, as shown in FIG. 1B, a lower resist 3 corresponding to the lower resist 3 is provided on the power supply electrode layer 5.
An upper resist film 6 having an opening 6a narrower than that is formed by photolithography. Thereafter, by performing an electrolytic plating process, the exposed wiring portion of the power supply electrode layer 5 is selectively plated with Au to form a plated portion 7. Thereafter, the upper resist film 6 used for patterning is formed.
And unnecessary power supply electrode layer 5 remaining other than the plating portion 7
Is removed. Thus, it is possible to selectively perform Au plating wiring only on a necessary portion without wasting material.

[0005]

However, in the above-described forming process, the following problems may occur. That is, when the upper resist film 6 is removed by performing a wet process using an organic solvent-based release agent, the release agent permeates the lower layer resist 3 and is simultaneously removed. Problems such as leaving the upper power supply electrode layer 5 or leaving burrs 5a of the power supply electrode layer 5 in the wiring portion of the plated portion 7 occur. In this case, The treatment is performed by a dry process such as an oxygen ashing treatment (see FIG. 3C).

In this case, if the thickness of the power supply electrode layer 5 is not appropriate, the following problems occur. That is,
When the power supply electrode layer 5 is formed to be thin, the power supply electrode layer 5 is formed at a step portion of the opening 4 of the lower resist 3 in a film forming process.
Of the power supply electrode layer 5 in the stepped portion, and a pinhole is apt to occur. Therefore, if the above-described oxygen ashing or the like is performed in this state, the lower layer resist 3 of the step portion 8 is removed through the stepped portion or the pinhole portion, and the base is exposed. As a result, when an etching process is performed to remove the power supply electrode layer 5, as shown in FIG.
Will be damaged (portion indicated by A in the figure).

In order to prevent disconnection and pinholes at the step 8 of the power supply electrode layer 5, when the power supply electrode layer 5 is formed to have a large thickness, as shown in FIG. In some cases, the power supply electrode layer 5 remains without being etched due to such factors (see FIG. 3A). After that, when the lower resist film 3 is peeled off, as shown in FIG. As described above, a problem arises in that the power supply electrode layer 5 is left fragmentarily at both ends of the plating portion 7 and the like, and burrs 5a are generated.

[0008] This means that even when only the wiring pattern is formed does not cause a serious problem,
If such a problem occurs in a portion where the wiring portion is dense or a portion where a contact is formed, a problem such as a short-circuit between the wiring patterns occurs.

FIGS. 13 and 14 show an HEMT (high electron mobility tra) as an actual field effect transistor.
nsistor (high electron mobility transistor). FIG. 13 showing the cross-sectional configuration of the HEMT
, An active layer 12 is laminated on an insulating semiconductor substrate, for example, an InP substrate 11 to form a mesa, a source electrode 13a and a drain electrode 13b are formed thereon, and a Schottky gate electrode 14 is formed. A protective film 15 is formed so as to cover the whole from above.

Next, the source electrode 13a and the drain electrode 1
3b and electrical contact with gate electrode 14 (contact)
Is formed by plating wiring. First,
An opening is formed in the protective film 15, a resist is applied over the entire surface, the first resist is removed corresponding to a portion where a contact is to be formed, and then a power supply electrode layer 16 is formed over the entire surface. .

Next, an opening is formed (not shown) so that the power supply electrode layer 16 is exposed corresponding to a portion where a plating resist is formed by applying a second resist. Subsequently, electrolytic plating is performed while applying a voltage via the power supply electrode layer 16 to form a plating wiring 17 on the power supply electrode layer 16 exposed from the opening. Thereafter, the second resist is removed, the exposed and unnecessary power supply electrode layer 16 is removed by etching, and the first resist is removed to obtain a plated wiring 17 formed in a predetermined pattern. .

By the way, when the power supply electrode layer 16 is etched, if there is a step or a pinhole in the power supply electrode layer 16 due to the step at the boundary between the resist film and the inner part of the resist film, as described above, the portion is removed. The etchant penetrates into the lower layer through the lower protective film 15.
May be etched off.

FIG. 14 is an enlarged view of a portion in the vicinity of the gate electrode 14. As described above, when the etchant infiltrates as described above, the protection film 15 shown in FIG. When the active layer 13b is partially exposed and the active layer 13b is exposed, the etchant further penetrates into the inside through the interface between the active layer 13b and the protective film 15, and the active layer 13b itself is damaged. Will be lost. Further, when the protective film 15 is further damaged, the active layer 13a is directly exposed to the etchant as shown by a portion D (bold line) in the figure, and is further damaged. As a result, the characteristics as a semiconductor element may fluctuate greatly, making it impossible to obtain desired characteristics.

The present invention has been made in view of the above circumstances, and an object of the present invention is to effectively prevent damage to an underlying protective film and a substrate and to prevent burrs on a power supply electrode layer, thereby improving the reliability of a semiconductor device. An object of the present invention is to provide a plating wiring that can be secured and a method for manufacturing the same.

[0015]

According to the first or eighth aspect of the present invention, a metal layer is provided below a power supply electrode layer for electrolytic plating when performing plating wiring. After selectively performing electrolytic plating using the power supply electrode layer, when etching for removing the power supply electrode layer after removing the upper layer resist, even if the coverage of the power supply electrode layer is poor, the oxygen for removing the upper layer resist is removed. When the lower resist is removed at the lower resist step by ashing or the like, the protective layer or the substrate is not directly damaged because the metal layer covers the base.

Along with this, even if the power supply electrode layer at the lower resist step portion has a slight step or a pinhole, there is no damage to the base, so that the power supply electrode layer can be made thinner, thereby improving the processing accuracy. . At the same time, since a metal layer is also provided under the power supply electrode layer immediately below the plating portion, stress applied to the plating portion is reduced, leading to improvement in adhesion. Further, since there is a margin for the etching time of the power supply electrode layer, generation of burrs due to insufficient etching can be prevented by setting the etching time long in advance.

Therefore, a microwave monolithic IC
In the case where it is used for plating wiring of a field effect transistor or the like, high reliability can be ensured also for an IC or a transistor itself.

According to the second or ninth aspect of the present invention, a metal layer is provided when a plated wiring is formed on an insulating film. The film is not damaged, and the quality can be improved.

According to the third or tenth aspect of the present invention, when a plated wiring is formed on a conductor pattern layer to make electrical contact, a metal layer is provided and formed. In addition, when the power supply electrode layer is removed, the conductor pattern layer is not damaged, and when a pattern having a predetermined resistance value is formed by the conductor pattern, the resistance value does not fluctuate with high accuracy. It can be formed and the quality can be improved.

According to the invention as set forth in claim 4 or the invention as set forth in claim 11, when an insulating film is formed on a conductor pattern layer and a plated wiring is partially formed through an opening thereof, an upper layer of the insulating film is formed. Since the power supply electrode layer is removed, the insulating film and the conductor pattern are not damaged when the power supply electrode layer is removed, and the quality can be improved.

According to the fifth or twelfth aspect of the present invention, when an insulating film is formed on a conductive pattern layer and a plated wiring is partially formed through an opening thereof, a lower layer of the insulating film is formed. Since a metal layer is provided and formed, the conductive pattern is not damaged when the power supply electrode layer is removed, and the quality can be improved.

According to the invention of claim 6 or the invention of claim 13, the capacitance value of the capacitance element formed between the lower electrode layer and the upper electrode layer can be set with high accuracy. Can be improved.

According to the invention of claim 7 or the invention of claim 14, since the metal layers are formed by laminating different metals, they can be removed by different etching treatments, and the underlying film can be removed. Can be improved.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment showing a basic structure of the present invention and a method of manufacturing the same will be described below with reference to FIG. 1 (a) to 1 (e) show steps of forming a plating wiring such as a signal line of a microwave monolithic IC, and FIG. 1 (e) shows a cross section of the plating wiring formed by employing the present invention. 1 schematically shows the structure.

First, as shown in FIG. 1A, an element such as a transistor (not shown) is formed on a semi-insulating semiconductor substrate 21, and a surface thereof is formed of Si as an insulating film.
A protective film 22 of N (silicon nitride) or the like is formed by lamination. On the protective film 22, a portion where a plated wiring is to be formed includes:
For example, two types of metal films of Ti (titanium) and Au (gold) are sequentially coated by 50 nm each as a different metal for the barrier metal layer 23 as a metal layer, and unnecessary portions are removed by a normal metal lift-off method to perform plating wiring. Is formed.

Next, a lower resist film 24 as a first resist film is applied on the entire surface by photolithography, and the barrier metal layer 2 is formed on the barrier metal layer 23.
The opening 25 is smaller than the size of the pattern 3.
Is formed so that the edge of the pattern of the barrier metal layer 23 is not exposed to the surface. At this time, the step 26 around the opening 25 is formed by a post bake or the like so as to have a tapered surface in which the lower part is narrower than the upper part. Thereafter, a power supply electrode layer 27 for electrolytic plating for applying a plating voltage when performing selective plating is formed on the entire surface including the opening 25. The power supply electrode layer 27 is made of, for example, Ti 30 nm, A
It is formed in the order of u30 nm by means such as electron beam evaporation.

Next, as shown in FIG. 2B, an upper resist film 28 as a second resist film is applied on the entire surface by photolithography, and is placed at the same position as the opening 25 of the lower resist film 24. Opening 2 smaller than opening 25
9 is formed. As a result, only the portion corresponding to the opening 29 of the power supply electrode layer 27 is exposed on the surface. When the selective plating pattern is formed by the openings 29 of the upper resist 28 as described above, for example, A
The selective plating of u is performed. By this selective plating, the plating layer 30 by Au plating is formed corresponding to the pattern of the opening 29 of the upper resist film 28.

Next, as shown in FIG. 2C, the upper resist film 28 is removed by, for example, an oxygen ashing process, and the power supply electrode layer 27 located in a portion other than the lower portion of the plating layer 30 is formed.
To expose. Further, as shown in FIG. 3D, the power supply electrode layer 27 is removed by wet etching. By using an etching solution composed of, for example, iodine and ammonium iodide for removing the Au film, and using, for example, dilute hydrofluoric acid for removing the Ti film, the respective etching times are set with a margin more than the just etching. Step 26
Of the power supply electrode layer 27 is left unetched.
Finally, as shown in FIG.
Is removed with an organic release agent to form a plated wiring.

In the plating wiring process formed in this manner, since the etching time for removing the power supply electrode layer 27 can be set with a margin, there is no etching residue of the power supply electrode layer 27, and the power supply electrode layer is formed on the plating wiring. 27 can be prevented from remaining. In addition, the coverage of the power supply electrode layer 27 is poor, and part of the power supply electrode layer 27 is cut off or has a pinhole in the step portion 26 of the lower resist film 24. In the case where the lower resist film 24 is removed in the above, the protective film 22 which is a base at the end of the lower resist film 24
Is covered with the barrier metal layer 23 and is not exposed, so that it can be prevented from being damaged by the etching solution.

In order to improve the workability, the power supply electrode layer 2
Even if the film thickness of 7 is reduced, the thickness of the barrier metal layer 23 immediately below the plating layer 30 is ensured, so that the stress applied to the plating wiring is reduced, and the adhesion does not decrease. Therefore, the reliability of the plated wiring, IC and the like can be ensured.

(Second Embodiment) FIG. 2 and FIG.
FIG. 6 shows a second embodiment of the present invention, in which an MIM (metal insulator meas) used for a microwave monolithic IC is shown.
tal) shows an embodiment applied to a capacitor. FIG. 2 is a plan view of the MIM capacitor, and FIG. 3 is a cross-sectional view taken along line AA of FIG. In this embodiment, the lower electrode 32, the protective film 33, and the upper electrode
It is a capacitor. Hereinafter, a method for manufacturing a MIM capacitor in a microwave monolithic IC will be described.

On the semi-insulating semiconductor substrate 31 after element isolation such as mesa etching, for example, Ti / Pt /
Au films having a thickness of 60 nm, 20 nm and 150 nm, respectively.
The lower electrode 32 is formed by metal lift-off so as to have a thickness of nm. Next, after forming a gate electrode and the like (not shown), a protective film 33 such as silicon nitride (SiN) is formed as an insulating film also serving as a dielectric of the MIM capacitor.

Next, although not shown, after a step of forming a contact hole in a pad portion such as an ohmic electrode or a gate electrode, the upper electrode portion of the MIM capacitor and the upper wiring portion of the MIM capacitor on the protective film 33 are provided with Ti / Au. 50 membranes each
The barrier metal layer 35 as a metal layer is formed by forming the barrier metal layer 35 in units of nm. Thereafter, a lower resist film (not shown) having an opening inside the barrier metal layer 35 is formed on the barrier metal layer 35. At this time, the step around the opening is tapered such that the lower part is narrower than the upper part by post baking or the like. Thereafter, the power supply electrode layer 36 for applying a plating voltage at the time of selective plating is formed on the entire surface including the opening by, for example, electron beam evaporation or the like so that the thickness of the Ti film is 30 nm and the thickness of the Au film is 30 nm. It is formed by means.

Next, an upper resist film is applied over the entire surface, and an opening smaller than the opening of the lower resist film is formed at the same position as the opening of the lower resist film by photolithography (not shown). Accordingly, only the portion corresponding to the opening of the upper resist film is exposed in the power supply electrode layer 36. In the state where the selective plating pattern is formed by the openings of the upper resist film in this way, a predetermined voltage is applied to the power supply electrode layer 36 to perform Au plating to form the plating layer 37, and thereby, the plating layer 37 is formed. Electrode 34
Is configured.

Next, the upper resist film is removed, for example, by performing an oxygen ashing process to expose the power supply electrode layer 36 other than the upper electrode 34. Further exposed power supply electrode layer 36
Is removed by wet etching. At this time, Au
An etching solution composed of, for example, iodine and ammonium iodide is used for the etching of the film, and dilute hydrofluoric acid is used for the etching of the Ti film. Finally, the lower resist film is removed with an organic release agent to form a MIM capacitor.

In this case, the barrier metal layer 35 of the conventional configuration
In the case of the MIM capacitor having no MIM capacitor, when the power supply electrode layer 36 is removed, if the etchant for the power supply electrode layer 36 goes under the lower resist film, the protective film which is a dielectric of the MIM capacitor may be etched. As a result, when the capacitance value of the MIM capacitor becomes smaller than the design value, or when the etchant reaches the lower electrode, a problem occurs that a leak occurs between the upper electrode and the lower electrode. There was a fear.

In order to cope with such a problem, in the MIM capacitor to which the present invention is applied, even if the etching solution flows under the lower resist film when the power supply electrode layer 36 is removed, the gap between the lower resist film and the protective film 33 is increased. Has a barrier metal layer 35
Are arranged, the protective film 33, which is a dielectric of the MIM capacitor, is not etched, and the characteristics are stable without any change in capacitance or leakage between the upper electrode 34 and the lower electrode 32. An MIM capacitor can be obtained.

(Third Embodiment) In this embodiment, the present invention is applied to a connection portion between a Ti thin film resistor and a signal line used in a microwave monolithic IC. FIG. 4 is a plan view of the Ti thin film resistor, and FIG. 5 is a cross-sectional view taken along the line BB. Hereinafter, a connection portion between the Ti thin film resistor and the signal line will be described.

A 100 nm-thick Ti thin film resistor 42 is formed on the semi-insulating semiconductor substrate 41 after element isolation by a mesa etching process or the like by a metal lift-off method. Thereafter, after forming a gate electrode and the like (not shown), a protective film 43 such as silicon nitride (SiN) is formed as an insulating film, and a contact hole 4 for connecting to a signal line or the like is formed.
4 is formed. Next, in order to cover the contact hole 44 and to correspond to a portion where a signal line or the like is to be formed, the Ti film and the Au film are sequentially laminated so as to have a thickness of 50 nm and a thickness of 50 nm, respectively. The layer 45 is formed.

After that, a lower resist film having an opening inside the barrier metal layer 45 is formed on the barrier metal layer 45. At this time, the step around the opening is tapered such that the lower part is narrower than the upper part by post baking or the like. Thereafter, the power supply electrode layer 46 for applying a plating voltage when selective plating is applied to the entire surface including the opening is formed by means such as electron beam evaporation so that the thickness of the Ti film is 30 nm and the thickness of the Au film is 30 nm. Formed.

Next, an upper resist film is applied to the entire surface (not shown), and an opening smaller than the opening of the lower resist film is formed at the same position as the opening of the lower resist film by photolithography. Thereby, the power supply electrode layer 4
The portion exposed at 6 is only the portion corresponding to the opening of the upper resist film. With the selective plating pattern formed by the opening of the upper resist film in this way,
Au plating is performed by applying a predetermined voltage to the power supply electrode layer 46 to form a plating layer 47.

Thereafter, the upper resist film is removed by, for example, an oxygen ashing process, and the power supply electrode layer 46 other than the lower portion of the plating layer 47 is exposed. Further exposed power supply electrode layer 4
6 is removed by wet etching. In this case, an etching solution composed of, for example, iodine or ammonium iodide is used for removing the Au film, and dilute hydrofluoric acid is used for removing the Ti film. Finally, the lower resist film is removed with an organic stripping agent to form a connection between the signal line and the Ti thin film resistor 42 and the signal line.

In this case, in the conventional method using a plated wiring without the barrier metal layer 45, dilute hydrofluoric acid, which is an etchant for the underlying Ti film, is used to etch the underlying resist film during the etching process for removing the power supply electrode layer 46. There is a case where the protective film 43 goes down and the protective film 43 is etched or the etchant reaches the Ti thin film resistor 42 under the protective film 43. In other words, the Ti thin film resistor 42 is also etched, and as a result, the Ti thin film resistor 42 cannot be formed with high accuracy, resulting in a problem that the resistance value varies and disconnection occurs.

In this regard, when the present invention is applied, even if the diluted hydrofluoric acid flows under the lower resist film when the power supply electrode layer 46 is removed, a barrier metal layer is formed between the lower resist film and the protective film 43. The thin film resistor 45 is provided, and is blocked by the Au film on the barrier metal layer 45. Thus, the diluted hydrofluoric acid does not reach the Ti thin film resistor 42, and the Ti thin film resistor 42 having stable characteristics can be obtained. .

Incidentally, in addition to the Ti thin film resistor 42, a Ti film or A
By applying the present invention also to the connection portion between the pad of the gate electrode and the signal line employing the l film, it is possible to prevent the lead portion and the pad portion of the gate electrode from being damaged.

(Fourth Embodiment) In the fourth embodiment, the signal lines and the like of the microwave monolithic IC cross each other, and an air gap is provided between a wiring passing above and a wiring passing below. The present invention is applied to the lower wiring portion of the air bridge wiring portion to lower the resistance of the lower wiring and stabilize the resistance value.

FIG. 6 is a plan view of the air bridge portion, and FIG. 7 shows a cross section taken along the line CC. In the present embodiment, the lower wiring passing under the air bridge portion is composed of the first wiring 52 and the barrier metal layer 53 formed simultaneously with the ohmic electrode and the like. Hereinafter, a method of manufacturing the air bridge wiring portion will be described.

First, an ohmic electrode of an active element such as a transistor (not shown) is formed on the semi-insulating semiconductor substrate 51 after element isolation by mesa etching or the like, and at the same time, for example, a Ti / Pt / Au film is formed. First wirings 52 having a thickness of 60 nm, 20 nm, and 150 nm are formed by a metal lift-off method. Next, for example, Ti / Au is formed on the first wiring 52 as a metal layer.
A barrier metal layer 53 having a thickness of 50 nm is formed by a metal lift-off method. Further, after forming a gate electrode and the like (not shown), a protective film 54 made of silicon nitride (SiN) is formed as an insulating film by plasma CVD or the like, and contact holes 55 are formed at both ends of the barrier metal layer 53 by dry etching or the like. Form.

At this time, the contact holes 55 do not protrude from the barrier metal layer 53. Next, a lower resist film having an opening in the contact hole 55 formed on the barrier metal layer 53 and an edge thereof and a wiring forming portion on the protective film 54 is formed by photolithography, and the lower resist film and the lower resist film are formed. A power supply electrode layer 56 for electrolytic plating is formed on the entire surface of the opening by electron beam evaporation or the like.

Next, an upper resist film corresponding to the opening of the lower resist film and having an opening smaller than the opening of the lower resist film and larger than the contact hole 55 is formed by photolithography to form a wiring. Pattern. After the wiring formation pattern is thus formed, a predetermined voltage is applied to the power supply electrode layer 56 to perform Au plating to form the plating layer 57.

Next, the upper resist film is removed by, for example, an oxygen ashing process, and the power supply electrode layer 56 other than the lower portion of the plating layer 57 is exposed. Further, the exposed power supply electrode layer 56 is removed by wet etching. In this case, an etching solution composed of, for example, iodine or ammonium iodide is used for removing the Au film, and dilute hydrofluoric acid is used for removing the Ti film. Finally, the lower resist film is removed with an organic release agent to form an air bridge.

In the lower wiring portion of the air bridge wiring formed in this manner, when the Ti film of the power supply electrode layer 56 is etched, the dilute hydrofluoric acid goes under the lower resist film to form the protective film 54. Is etched to reach the lower wiring, almost no etching is performed because the upper layer of the surface of the barrier metal layer 53 laminated thereon is formed of the Au film regardless of the material of the first wiring 52. And a lower wiring having a stable resistance value can be obtained. Further, since the barrier metal layer 53 is formed on the first wiring 52, it is easy to increase the thickness of the lower wiring, so that the resistance of the lower wiring can be reduced.

(Fifth Embodiment) In the fifth embodiment, GaAs is used as an active element used in the microwave band.
FET and HEMT (high electron mobility transisto)
r; high electron mobility transistor)
The present invention is applied to a case where plating wiring is formed as a conductor pattern connected to the source, drain or gate electrodes of these elements, whereby stable plating wiring can be performed. FIG. 8 shows H
FIG. 10 is a plan view of the EMT, and FIG. 9 shows a cross section along the line D-D, and FIG.

An active layer 62 having a six-layer structure including a buffer layer, a channel layer, an electron supply layer, a gate contact layer, a cap layer, and the like is laminated on an insulating semiconductor substrate, for example, an InP substrate 61, and an etching process is performed. And a source electrode 6 as an ohmic electrode.
3 and a drain electrode 64 are formed, and a Schottky gate electrode 65 is formed in the recessed portion. A protective film 66 is formed as an insulating film so as to cover the whole from above.

Next, the source electrode 63 and the drain electrode 64
A conductor for making electrical contact with the gate electrode 65 is formed by plating wiring. First, a contact hole 67 is formed in the protective film 66, and thereafter a barrier metal layer 68 having a Ti / Au film thickness of, for example, 50 nm is formed as a metal layer into a pattern corresponding to the shape of the plated wiring by a metal lift-off method. Form. Next, a first resist film (not shown) is applied to the entire upper surface and patterned by photolithography so that the surface of the barrier metal layer 68 is exposed. At this time, patterning is performed so that at least the end of the barrier metal layer 68 is covered with the first resist film. After this,
A power supply electrode layer 69 for electrolytic plating is formed by electron beam evaporation or the like.

Next, an opening is formed (not shown) so that the power supply electrode layer 69 is exposed corresponding to the portion where the plating resist is formed by applying the second resist film. Subsequently, an electrolytic plating process is performed while applying a voltage through the power supply electrode layer 69 to form a plating layer 70 on the power supply electrode layer 69 exposed from the opening. Thereafter, the second resist film is removed, the exposed and unnecessary power supply electrode layer 69 is removed by etching, and the first resist film is further removed to obtain a plating layer 70 formed in a predetermined pattern. become.

Since the electrolytic plating process is performed with the barrier metal layer 68 provided as described above, the state in which the end of the protective film 66 is covered by the barrier metal layer 68 provided below the power supply electrode layer 69. Therefore, when the power supply electrode layer 69 which becomes unnecessary after the plating process is removed by the etching process, the lower layer portion can be protected by the barrier metal layer 68, and as shown in FIG. It can be manufactured without damaging the protection film 66 for protecting the vicinity of the gate electrode 65.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. The present invention can be applied to plating wiring of other semiconductor elements. Further, the present invention can be applied to all devices using plated wiring other than semiconductor devices. The present invention can be applied to a metal layer other than a barrier metal layer using a Ti / Au layer.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention corresponding to each manufacturing process of plated wiring.

FIG. 2 is a plan view of an MIM capacitor according to a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view (a cross-section taken along line AA in FIG. 2)

FIG. 4 is a plan view of a connection portion between a Ti resistor and a signal line according to a third embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view (a cross-section taken along line BB in FIG. 4).

FIG. 6 is a plan view of an air bridge wiring unit according to a fourth embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view (a cross-section taken along line CC in FIG. 6).

FIG. 8 is a plan view of a HEMT showing a fifth embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view (a cross-section taken along line DD in FIG. 8).

FIG. 10 is an enlarged view showing a gate electrode part of FIG. 9;

FIG. 11 is a diagram corresponding to FIG. 1 showing a conventional example.

FIG. 12 is a diagram corresponding to FIG. 1 for explaining a problem.

FIG. 13 is a diagram corresponding to FIG. 9;

FIG. 14 is a diagram corresponding to FIG. 10;

[Explanation of symbols]

21 is a semi-insulating substrate, 22 is a protective film (insulating film), 23 is a barrier metal layer (metal layer), 24 is a lower resist film (first resist film), 25 is an opening of the lower resist film, 2
6 is a step portion of the lower resist film, 27 is a power supply electrode layer, 28
Denotes an upper resist film (second resist film), 29 denotes an opening of the upper resist film, 30 denotes a plating layer, 31 denotes a semi-insulating substrate, 32 denotes a lower electrode, 33 denotes a protective film (insulating film), and 34 denotes an upper portion. Electrodes, 35 a barrier metal layer (metal layer), 36 a power supply electrode layer, 37 a plating layer, 41 a semi-insulating semiconductor substrate, 42 a Ti thin film resistor, 43 a protective film (insulating film), 4
4 is a contact hole, 45 is a barrier metal layer (metal layer), 46 is a power supply electrode layer, 47 is a plating layer, 51 is a semi-insulating semiconductor substrate, 52 is a first wiring, 53 is a barrier metal layer (metal layer). , 54 are a protective film (insulating film), 55 is a contact hole, 56 is a power supply electrode layer, 57 is a plating layer,
8 is a plating wiring, 61 is an insulating semiconductor substrate, 62 is an active layer, 63 is a source electrode, 64 is a drain electrode, 65 is a gate electrode, 66 is a protective film (insulating film), 67 is a contact hole, and 68 is a barrier. A metal layer (metal layer), 69 is a power supply electrode layer, and 70 is a plating layer.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/812

Claims (14)

[Claims] 1. A plating wiring comprising a plating layer formed on a semiconductor substrate, comprising: a power supply electrode layer for electrolytic plating provided below the plating layer; A metal layer interposed between the semiconductor substrate and a metal layer formed to be wider than the width of the power supply electrode layer for electrolytic plating. 2. The plated wiring according to claim 1, wherein an insulating film is formed on the semiconductor substrate, and the metal layer is formed on the insulating film. 3. The plated wiring according to claim 1, wherein a conductor pattern layer is formed on the semiconductor substrate, and the metal layer is formed on the conductor pattern layer. 4. A conductive pattern layer is formed on the semiconductor substrate, and an insulating film having an opening is formed so as to expose a portion of the conductive pattern layer excluding at least an end. The metal layer is formed so as to be in electrical contact with the conductor pattern layer while being formed so as to cover an opening of the insulating film.
The described plating wiring. 5. An insulating film provided with an opening on the metal layer so as to expose at least a portion excluding an end of the metal layer, wherein the power supply electrode layer for electrolytic plating is formed on the metal layer with respect to the metal layer. 4. The plating wiring according to claim 3, wherein the plating wiring is formed so as to be in an electrical contact state while being formed so as to cover the opening of the insulating film. 6. A lower electrode layer is formed between the semiconductor substrate and the insulating film, and the plating layer is formed as an upper electrode constituting a capacitor between the lower electrode layer and the lower electrode layer. 3. The plated wiring according to claim 2, wherein: 7. The plated wiring according to claim 1, wherein the metal layer has a multilayer metal film structure in which different metals are stacked. 8. A metal layer forming step of forming a metal layer corresponding to a wiring forming part on a semiconductor substrate, and a first step of forming an opening to expose a portion excluding an end of the metal layer. A first resist forming step of forming a resist film; a power supply electrode layer forming step of forming a power supply electrode layer for electrolytic plating so as to cover the metal layer and the first resist film; Second to cover from top
And applying a plating opening so as to expose the power supply electrode layer for electrolytic plating located in an inner region except for the end corresponding to the opening of the first resist film. A second resist forming step of forming; an electroplating step of selectively electroplating a plating conductor in the plating opening while applying an electroplating voltage via the electrolytic plating power supply electrode layer; And a resist removing step of removing the second resist film. 9. An insulating film forming step of forming an insulating film on the semiconductor substrate, which is performed prior to the metal layer forming step, wherein the metal layer is formed on a wiring forming portion on the insulating film. 9. The method for manufacturing a plated wiring according to claim 8, wherein the plating wiring is formed. 10. A conductor pattern forming step for forming a conductor pattern layer on the semiconductor substrate, which is performed prior to the metal forming step, wherein the metal layer is formed on a wiring forming portion on the conductor pattern. 9. The method as claimed in claim 8, wherein
A method for manufacturing the plated wiring according to the above. 11. An insulating film which is formed prior to the metal layer forming step and has an opening provided on the conductive pattern layer so as to expose at least a portion excluding an end thereof, following the conductive pattern forming step. Forming an insulating film, wherein in the metal layer forming step, the metal layer is formed so as to cover the opening of the insulating film with respect to the conductor pattern layer so as to be in an electrical contact state. The method for producing a plated wiring according to claim 10, wherein: 12. An insulating film forming step, which is performed prior to the first resist forming step, and forms an insulating film provided with an opening on the metal layer so as to expose at least a portion excluding an end of the metal layer. In the power supply electrode layer forming step, the power supply electrode layer for electrolytic plating is formed so as to be in electrical contact with the metal layer so as to cover the opening of the insulating film. The method for manufacturing a plated wiring according to claim 10, wherein: 13. A lower electrode layer forming step of forming a lower electrode layer on the semiconductor substrate prior to the insulating film forming step, wherein the metal layer formed in the metal layer forming step is used as an upper electrode layer. A method for manufacturing a plated wiring, comprising forming a capacitive element having an insulating film as a dielectric. 14. The method according to claim 8, wherein in the metal layer forming step, a metal layer having a multilayer metal film structure in which different metal films are sequentially laminated is formed. .