JPH10144853A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10144853A
JPH10144853A JP29496496A JP29496496A JPH10144853A JP H10144853 A JPH10144853 A JP H10144853A JP 29496496 A JP29496496 A JP 29496496A JP 29496496 A JP29496496 A JP 29496496A JP H10144853 A JPH10144853 A JP H10144853A
Authority
JP
Japan
Prior art keywords
bed
lead frame
package
resin
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29496496A
Other languages
Japanese (ja)
Inventor
Mitsunari Takano
晃成 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP29496496A priority Critical patent/JPH10144853A/en
Publication of JPH10144853A publication Critical patent/JPH10144853A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with an increased manufacturing yield by suppressing vertical movement of a bed fixing a semiconductor element in the case of resin molding a package. SOLUTION: A semiconductor element 16 is fixed on the top face of a square bed 13 formed on a lead frame 12 so as to resin mold a package 21 using a molding die to resin seal. Next, the lead frame 12 is continuously recessed in a specific depth so as to encircle the bed 13 to form an angle circular bed support protrusion 23 as well as making the outer bottom face of this protrusion 23 abut against the inner face of the molding die in the case of the resin molding so as to make the outer bottom face expose in the outer face of the package 21 after the molding step. Through these procedures, even if the bed 13 is moving in the vertical direction by the umbalanced state of the resin injected along the surface of the lead frame 12 in the case of molding the package 21, the movement is restricted and suppressed by the bed support protrusion 23 abutting against the inner face of the molding die.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、樹脂封止された半
導体装置に関する。
The present invention relates to a resin-sealed semiconductor device.

【0002】[0002]

【従来の技術】周知の通り、半導体装置にはリードフレ
ームのベッドに半導体素子を固着し、熱硬化性樹脂を成
形型内に注入してパッケージを形成し樹脂封止を行うよ
うにしたものがある。以下、従来の樹脂封止された半導
体装置を図7を参照して説明する。図7は断面図で、図
7において半導体装置1は、リードフレーム2のベッド
3の上表面に半導体素子4を固着し、半導体素子4の端
子5とリードフレーム2のリード6の内端部とをボンデ
ィングワイヤ7で電気的に接続し、さらに図示しない成
形型を用いた熱硬化性樹脂による樹脂成形によりパッケ
ージ8を形成し、図示しないベッド3を吊り支持する図
示しない吊りピンと、パッケージ8から外部に延出した
リード6の外端部を所定長さとなるように切断し、同時
に延出したリード6を所定形状となるよう成形加工する
ことによって構成されている。
2. Description of the Related Art As is well known, a semiconductor device has a semiconductor element fixed to a bed of a lead frame, and a thermosetting resin is injected into a molding die to form a package and perform resin sealing. is there. Hereinafter, a conventional resin-sealed semiconductor device will be described with reference to FIG. FIG. 7 is a sectional view. In FIG. 7, the semiconductor device 1 has a semiconductor element 4 fixed to the upper surface of the bed 3 of the lead frame 2, and a terminal 5 of the semiconductor element 4 and an inner end of the lead 6 of the lead frame 2. Are electrically connected by a bonding wire 7, and a package 8 is formed by resin molding using a thermosetting resin using a molding die (not shown). The outer ends of the extended leads 6 are cut to have a predetermined length, and at the same time, the extended leads 6 are formed into a predetermined shape.

【0003】そして、成形型を用いてパッケージ8の樹
脂成形を行うモールド工程では、半導体素子4を固着し
たベッド3を成形型内に宙吊りとなるように支持し、そ
の後、成形型内にリードフレーム2の面に沿って熱硬化
性樹脂の注入が行われる。そして成形型内が熱硬化性樹
脂で満たされ、さらに所定の硬化時間を経て成形型から
パッケージ8が形成されたリードフレーム2が取り出さ
れる。
[0003] In a molding step of performing resin molding of the package 8 using a molding die, the bed 3 to which the semiconductor element 4 is fixed is supported so as to be suspended in the molding die, and then the lead frame is placed in the molding die. A thermosetting resin is injected along the surface of No. 2. Then, the inside of the mold is filled with the thermosetting resin, and after a predetermined curing time, the lead frame 2 on which the package 8 is formed is taken out from the mold.

【0004】しかしながら上記の従来技術においては、
パッケージ8の樹脂成形の際にリードフレーム2の面に
沿うよう成形型内に熱硬化性樹脂の注入が行われるが、
リードフレーム2の上面側と下面側とでは半導体素子4
が固着されている上面側での流動抵抗が下面側よりも大
きく樹脂が流れ難くいことによって、またリードフレー
ム2によって2分された成形型内の上側と下側の熱硬化
性樹脂の量に差がある場合にはその樹脂量の差によっ
て、半導体素子4及びベッド3を上下方向に移動させて
しまうことになる。これにより、パッケージ8の外面に
ボンディングワイヤ7が露出したり、半導体素子4上に
ボイドが生じたり、パッケージ8内に封止されるよう設
計されているベッド3が下面に露出し外観上好ましくな
い状態になる等の虞があった。
However, in the above prior art,
When the resin of the package 8 is molded, a thermosetting resin is injected into the molding die along the surface of the lead frame 2.
The semiconductor element 4 is provided between the upper and lower sides of the lead frame 2.
The flow resistance on the upper surface side where the resin is fixed is larger than that on the lower surface side, so that the resin does not easily flow, and the amount of the upper and lower thermosetting resin in the molding die divided by the lead frame 2 is reduced. If there is a difference, the semiconductor element 4 and the bed 3 are moved up and down due to the difference in the amount of resin. As a result, the bonding wires 7 are exposed on the outer surface of the package 8, voids are generated on the semiconductor element 4, and the bed 3 designed to be sealed in the package 8 is exposed on the lower surface, which is not preferable in appearance. There was a risk of becoming a state.

【0005】[0005]

【発明が解決しようとする課題】上記のような状況に鑑
みて本発明はなされたもので、パッケージを成形型を用
いて樹脂成形する際、リードフレームのベッド及びベッ
ドに固着した半導体素子が上下方向に移動するのを抑制
し、ボンディングワイヤのパッケージ外面への露出、半
導体素子上のボイドの発生等を低減するようにし、製造
歩留を向上させた半導体装置を提供することを目的とす
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above situation. When a package is molded with a resin using a molding die, a bed of a lead frame and a semiconductor element fixed to the bed are vertically moved. It is an object of the present invention to provide a semiconductor device having an improved manufacturing yield by suppressing movement of the bonding wire in the direction, reducing exposure of a bonding wire to an outer surface of a package, generation of a void on a semiconductor element, and the like.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
リードフレームに形成されたベッドと、このベッドに固
着された半導体素子と、この半導体素子をベッドと共に
成形型を用いた樹脂成形によって樹脂封止したパッケー
ジとを備えてなる半導体装置において、リードフレーム
が、パッケージの外面に露出するよう形成されたベッド
支持凸部を具備していることを特徴とするものであり、
さらに、ベッド支持凸部が、ベッドの周縁に連続するよ
うに形成されていることを特徴とするものであり、さら
に、ベッド支持凸部が、ベッドをリードフレーム内に吊
り支持する吊りピンの中間部に形成されていることを特
徴とするものであり、さらに、ベッド支持凸部が、ベッ
ドの半導体素子固着面に対し裏面側方向に凸となるよう
に形成されていることを特徴ものである。
According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device including a bed formed on a lead frame, a semiconductor element fixed to the bed, and a package in which the semiconductor element is resin-sealed together with the bed by resin molding using a molding die, A bed support projection formed to be exposed on the outer surface of the package,
Furthermore, the bed support projection is formed so as to be continuous with the periphery of the bed, and further, the bed support projection is provided between the suspension pins for suspending and supporting the bed in the lead frame. Wherein the bed support projection is formed so as to project in the direction of the back surface side with respect to the semiconductor element fixing surface of the bed. .

【0007】[0007]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0008】先ず、第1の実施形態を図1乃至図3によ
り説明する。図1は断面図であり、図2は樹脂封止前に
おけるリードフレームの要部の斜視図であり、図3はパ
ッケージの裏面図である。図1乃至図3において半導体
装置11は、42アロイ等の金属材料でなるリードフレ
ーム12の方形状に形成されたベッド13のリードフレ
ーム面14より下方に位置する上側表面15に、半導体
素子16を半田あるいは銀ペーストのろう材により固着
するようにして構成されている。そして半導体素子16
の複数の端子17とリードフレーム12に形成された複
数のリード18の内端部19とは、それぞれ対応するも
のがボンディングワイヤ20によって電気的に接続され
ている。また、半導体素子16をベッド13上に固着し
たリードフレーム12は、図示しない成形型にセットさ
れシリカフィラーが混入されたエポキシ樹脂等の熱硬化
性樹脂による樹脂成形によりパッケージ21が形成さ
れ、半導体素子16等の樹脂封止がなされる。
First, a first embodiment will be described with reference to FIGS. 1 is a sectional view, FIG. 2 is a perspective view of a main part of a lead frame before resin sealing, and FIG. 3 is a rear view of the package. 1 to 3, a semiconductor device 11 has a semiconductor element 16 on an upper surface 15 located below a lead frame surface 14 of a bed 13 formed in a square shape of a lead frame 12 made of a metal material such as a 42 alloy. It is configured to be fixed by solder or silver paste brazing material. And the semiconductor element 16
The plurality of terminals 17 and the inner ends 19 of the plurality of leads 18 formed on the lead frame 12 are electrically connected to each other by bonding wires 20. The package 21 is formed on the lead frame 12 in which the semiconductor element 16 is fixed on the bed 13 by resin molding using a thermosetting resin such as an epoxy resin mixed with a silica filler and set in a molding die (not shown). Resin sealing such as 16 is performed.

【0009】一方、ベッド13の4周囲には、このベッ
ド13を取り囲むようリードフレーム12を所定深さと
なるよう凹没加工、すなわち下方に向けて凸となるよう
加工することによって、ベッド13の上側表面15より
も底面22が下方に位置するよう形成されたベッド支持
凸部23が角環状に設けられ、ベッド支持凸部23の外
底面24も同様に角環状の平面を形成している。このた
め、樹脂成形によりパッケージ21を形成した状態で
は、ベッド支持凸部23の外底面24がパッケージ21
の外面に露出する。またベッド支持凸部23の外側壁の
4隅角部の上部には、角部分から外方に放射状に延びる
吊りピン25が設けられ、その外方端がリードフレーム
12に連設されていて、これらの吊りピン25によって
ベッド支持凸部23で取り囲まれたベッド13がリード
フレーム12内の中間部分に吊り支持された状態となっ
ている。
On the other hand, around the bed 13, the lead frame 12 is recessed so as to have a predetermined depth so as to surround the bed 13, that is, the lead frame 12 is formed so as to be convex downward, so that the upper side of the bed 13 is formed. A bed support protrusion 23 formed so that the bottom surface 22 is located below the front surface 15 is provided in a rectangular ring shape, and the outer bottom surface 24 of the bed support protrusion 23 similarly forms a rectangular ring-shaped plane. Therefore, when the package 21 is formed by resin molding, the outer bottom surface 24 of the bed support projection 23 is
Exposed on the outer surface of At the upper part of the four corners of the outer wall of the bed support projection 23, suspension pins 25 extending radially outward from the corners are provided, the outer ends of which are connected to the lead frame 12, and The bed 13 surrounded by the bed support projections 23 is suspended and supported by an intermediate portion in the lead frame 12 by these suspension pins 25.

【0010】そして、パッケージ21が形成され樹脂封
止がなされたリードフレーム12は、パッケージ21か
ら外部に延出した吊りピン25とリード18の外端部2
6とがそれぞれ所定の位置で切断され、同時に所定長だ
け延出した状態のリード18の外端部26が、例えば所
定のガルウイング形状となるよう成形加工され、半導体
装置11が形成される。
The lead frame 12 on which the package 21 is formed and sealed with resin is connected to the suspension pins 25 extending from the package 21 to the outside and the outer ends 2 of the leads 18.
6 are cut at predetermined positions, and the outer ends 26 of the leads 18 extending at the same time by a predetermined length are formed into, for example, a predetermined gull wing shape, and the semiconductor device 11 is formed.

【0011】このように構成されているものでは、成形
型を用いてパッケージ21の樹脂成形を行うモールド工
程で、リードフレーム12を成形型にセットした時にベ
ッド支持凸部23の外底面24が成形型の内面に当接す
る。そしてベッド支持凸部23の外底面24が型内面に
当接した状態で成形型内にリードフレーム12の面に沿
って熱硬化性樹脂の注入が行われると、樹脂はリードフ
レーム12の形状やベッド13に固着された半導体素子
16の影響を受けながらリードフレーム12の面に沿う
方向に流れる。この時、ベッド支持凸部23による流動
抵抗で樹脂の注入が遅れ樹脂量が少くなっている下面側
に向け、ベッド13を押し下げるような力がリードフレ
ーム12には加わる。しかし、ベッド13はベッド支持
凸部23が型内面に当接しているために上下方向の移動
が阻止され、ベッド13に固着された半導体素子16は
パッケージ21内の所定位置に樹脂封止される。
In the above-described configuration, in the molding step of performing resin molding of the package 21 using a molding die, the outer bottom surface 24 of the bed support projection 23 is formed when the lead frame 12 is set in the molding die. Contact the inner surface of the mold. When the thermosetting resin is injected into the mold along the surface of the lead frame 12 in a state where the outer bottom surface 24 of the bed support projection 23 is in contact with the inner surface of the mold, the resin becomes It flows in a direction along the surface of the lead frame 12 under the influence of the semiconductor element 16 fixed to the bed 13. At this time, a force that pushes down the bed 13 is applied to the lead frame 12 toward the lower surface side where the resin injection is delayed due to the flow resistance by the bed support protrusion 23 and the resin amount is reduced. However, the bed 13 is prevented from moving in the vertical direction because the bed support projection 23 is in contact with the inner surface of the mold, and the semiconductor element 16 fixed to the bed 13 is resin-sealed at a predetermined position in the package 21. .

【0012】以上のように本実施形態によれば、ベッド
支持凸部23を外底面24がパッケージ21の外面に露
出するよう設けているので、注入された樹脂の流れる部
分の断面積が小さく、リードフレーム12に下方向の力
が働くものの、ベッド13が上下に移動せずを押し下げ
るような力が働いてもリードフレーム12は変形するこ
とがなく、パッケージ21の外面にボンディングワイヤ
20が露出したり、半導体素子16上にボイドが生じた
りするのが低減し、ベッド支持凸部23の外底面24が
パッケージ21外面に露出する設計にすることで外観上
の不具合の発生も低減する等して製造歩留が向上する。
As described above, according to the present embodiment, since the bed support protrusion 23 is provided so that the outer bottom surface 24 is exposed to the outer surface of the package 21, the cross-sectional area of the flowing portion of the injected resin is small. Although a downward force acts on the lead frame 12, the lead frame 12 is not deformed even if a force such as pushing down the bed 13 does not move up and down, and the bonding wire 20 is exposed on the outer surface of the package 21. And the occurrence of voids on the semiconductor element 16 is reduced, and the outer bottom surface 24 of the bed support protrusion 23 is designed to be exposed on the outer surface of the package 21 so that appearance defects are reduced. Manufacturing yield is improved.

【0013】また、ベッド支持凸部23の形状を適正に
設定すること等によってリードフレーム12の上下面に
おける樹脂量の比を変えることができ、パッケージ21
の反り量の調節が容易に行え、パッケージ21の薄型化
を実現することができる。さらに、半導体素子16で発
生した熱をパッケージ21の外面に露出するベッド支持
凸部23の外底面24から外部に放出させることができ
る。なお、外底面24を別に設けた放熱器に接触させる
よう構成すれば、より効果的な冷却を行うことができ
る。
The ratio of the amount of resin on the upper and lower surfaces of the lead frame 12 can be changed by appropriately setting the shape of the bed support projection 23, and the like.
The amount of warpage can be easily adjusted, and the thickness of the package 21 can be reduced. Further, the heat generated by the semiconductor element 16 can be released to the outside from the outer bottom surface 24 of the bed support projection 23 exposed on the outer surface of the package 21. If the outer bottom surface 24 is configured to be in contact with a separately provided radiator, more effective cooling can be performed.

【0014】次に、第2の実施形態を図4乃至図6によ
り説明する。図4は吊りピン部分における断面図であ
り、図5は樹脂封止前におけるリードフレームの要部の
斜視図であり、図6はパッケージの裏面図である。図4
乃至図6において半導体装置31は、42アロイ等の金
属材料でなるリードフレーム32の方形状に形成された
ベッド13のリードフレーム面33より下方に位置する
上側表面15に、半導体素子16を半田あるいは銀ペー
ストのろう材により固着するようにして構成されてい
る。そして半導体素子16の複数の端子17とリードフ
レーム32に形成された複数のリード18の内端部19
とは、それぞれ対応するものがボンディングワイヤ20
によって電気的に接続されている。また、半導体素子1
6をベッド13上に固着したリードフレーム32は、図
示しない成形型にセットされシリカフィラーが混入され
たエポキシ樹脂等の熱硬化性樹脂による樹脂成形により
パッケージ34が形成され、半導体素子16等の樹脂封
止がなされる。
Next, a second embodiment will be described with reference to FIGS. 4 is a cross-sectional view of the suspension pin portion, FIG. 5 is a perspective view of a main part of the lead frame before resin sealing, and FIG. 6 is a rear view of the package. FIG.
In FIG. 6 to FIG. 6, a semiconductor device 31 is formed by soldering or mounting a semiconductor element 16 on an upper surface 15 located below a lead frame surface 33 of a bed 13 formed in a square shape of a lead frame 32 made of a metal material such as a 42 alloy. It is configured to be fixed by a brazing material of silver paste. The plurality of terminals 17 of the semiconductor element 16 and the inner ends 19 of the plurality of leads 18 formed on the lead frame 32
Means that the corresponding one is a bonding wire 20
Are electrically connected by In addition, the semiconductor element 1
6 is fixed on a bed 13, a lead frame 32 is set in a molding die (not shown), and a package 34 is formed by resin molding with a thermosetting resin such as an epoxy resin mixed with a silica filler. Sealing is performed.

【0015】一方、ベッド13は、4隅角部から外方に
放射状に延びる吊りピン35の外方端がリードフレーム
32に連設され、これによってリードフレーム32内の
中間部分に吊り支持された状態となっている。また、吊
りピン35は中間部分に、所定深さとなるよう台形状に
凹没加工、すなわち下方に向けて凸となるよう加工する
ことによって形成されたベッド支持凸部36が設けられ
ている。ベッド支持凸部36は、底面37がベッド13
の上側表面15よりも下方に位置するよう形成され、樹
脂成形によりパッケージ34を形成した状態では、ベッ
ド支持凸部36の外底面38がパッケージ34の外面に
露出する。
On the other hand, the outer ends of the suspension pins 35 extending radially outward from the four corners of the bed 13 are connected to the lead frame 32, and the bed 13 is suspended and supported by an intermediate portion in the lead frame 32. It is in a state. Further, the suspension pin 35 is provided with a bed support convex portion 36 formed in a middle portion by forming a trapezoidal concave or concave process to have a predetermined depth, that is, by processing the convex portion downward. The bed support projection 36 has a bottom 37
When the package 34 is formed by resin molding, the outer bottom surface 38 of the bed support projection 36 is exposed to the outer surface of the package 34.

【0016】そして、パッケージ34が形成され樹脂封
止がなされたリードフレーム32は、パッケージ34か
ら外部に延出した吊りピン35とリード18の図示しな
い外端部とがそれぞれ所定の位置で切断され、同時に所
定長だけ延出した状態のリード18の外端部が、例えば
所定のガルウイング形状となるよう成形加工され、半導
体装置31が形成される。
In the lead frame 32 in which the package 34 is formed and sealed with resin, the suspension pins 35 extending outside from the package 34 and the outer ends (not shown) of the leads 18 are cut at predetermined positions. At the same time, the outer ends of the leads 18 extending by a predetermined length are formed into, for example, a predetermined gull wing shape, and the semiconductor device 31 is formed.

【0017】このように構成されているものでは、成形
型を用いてパッケージ34の樹脂成形を行うモールド工
程で、リードフレーム32を成形型にセットした時に吊
りピン35に形成したベッド支持凸部36の外底面38
が成形型の内面に当接する。そしてベッド支持凸部36
の外底面38が型内面に当接した状態で成形型内にリー
ドフレーム32の面に沿って熱硬化性樹脂の注入が行わ
れると、樹脂はリードフレーム32の形状やベッド13
に固着された半導体素子16の影響を受けながらリード
フレーム32の面に沿う方向に流れる。この時、ベッド
支持凸部36による流動抵抗で樹脂の注入が遅れ樹脂量
が少くなっている下面側に向け、ベッド13を押し下げ
るような力がリードフレーム32には加わる。しかし、
ベッド13はベッド支持凸部36が型内面に当接してい
るために上下方向の移動が阻止され、ベッド13に固着
された半導体素子16はパッケージ34内の所定位置に
樹脂封止される。
With the above-described structure, in the molding step of performing resin molding of the package 34 using the molding die, the bed support projection 36 formed on the suspension pin 35 when the lead frame 32 is set in the molding die. Outer bottom surface 38
Abuts against the inner surface of the mold. And the bed support protrusion 36
When the thermosetting resin is injected into the molding die along the surface of the lead frame 32 in a state where the outer bottom surface 38 is in contact with the inner surface of the die, the resin becomes the shape of the lead frame 32 and the bed 13.
Flows in the direction along the surface of the lead frame 32 under the influence of the semiconductor element 16 fixed to the lead frame 32. At this time, a force that pushes down the bed 13 is applied to the lead frame 32 toward the lower surface side where the injection of the resin is delayed due to the flow resistance by the bed support protrusion 36 and the resin amount is reduced. But,
The bed 13 is prevented from moving up and down because the bed support projection 36 is in contact with the inner surface of the mold, and the semiconductor element 16 fixed to the bed 13 is sealed with a resin at a predetermined position in the package 34.

【0018】この結果、本実施形態においても、上記の
第1の実施形態と同様の作用、効果が得られる。
As a result, the same operation and effect as in the first embodiment can be obtained in this embodiment.

【0019】[0019]

【発明の効果】以上の説明から明らかなように、本発明
は、リードフレームにパッケージの外面に外底面が露出
するようベッド支持凸部を設けることにより、パッケー
ジを樹脂成形する際に生じる虞のあるベッド及びベッド
に固着した半導体素子の上下方向の移動が抑制でき、ボ
ンディングワイヤのパッケージ外面への露出や半導体素
子上のボイドの発生等が低減でき、製造歩留を向上させ
ることができるなどの効果を奏する。
As is apparent from the above description, according to the present invention, by providing the lead frame with the bed support protrusion so that the outer bottom surface is exposed on the outer surface of the package, there is a possibility that the package may be formed when the resin is molded. The vertical movement of a certain bed and a semiconductor element fixed to the bed can be suppressed, the exposure of bonding wires to the outer surface of the package and the occurrence of voids on the semiconductor element can be reduced, and the manufacturing yield can be improved. It works.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態を示す断面図である。FIG. 1 is a cross-sectional view illustrating a first embodiment of the present invention.

【図2】本発明の第1の実施形態の樹脂封止前における
リードフレームの要部の斜視図である。
FIG. 2 is a perspective view of a main part of the lead frame before resin sealing according to the first embodiment of the present invention.

【図3】本発明の第1の実施形態のパッケージの裏面図
である。
FIG. 3 is a back view of the package according to the first embodiment of the present invention.

【図4】本発明の第2の実施形態の吊りピン部分におけ
る断面図である。
FIG. 4 is a cross-sectional view of a suspension pin according to a second embodiment of the present invention.

【図5】本発明の第2の実施形態の樹脂封止前における
リードフレームの要部の斜視図である。
FIG. 5 is a perspective view of a main part of a lead frame before resin sealing according to a second embodiment of the present invention.

【図6】本発明の第2の実施形態のパッケージの裏面図
である。
FIG. 6 is a rear view of the package according to the second embodiment of the present invention.

【図7】従来技術の断面図である。FIG. 7 is a sectional view of a conventional technique.

【符号の説明】[Explanation of symbols]

12,32…リードフレーム 13…ベッド 16…半導体素子 21,34…パッケージ 23,36…ベッド支持凸部 24,38…外底面 35…吊りピン 12, 32 ... lead frame 13 ... bed 16 ... semiconductor element 21, 34 ... package 23, 36 ... bed support protrusion 24, 38 ... outer bottom surface 35 ... hanging pin

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 リードフレームに形成されたベッドと、
このベッドに固着された半導体素子と、この半導体素子
を前記ベッドと共に成形型を用いた樹脂成形によって樹
脂封止したパッケージとを備えてなる半導体装置におい
て、前記リードフレームが、前記パッケージの外面に露
出するよう形成されたベッド支持凸部を具備しているこ
とを特徴とする半導体装置。
A bed formed on a lead frame;
In a semiconductor device comprising a semiconductor element fixed to the bed and a package obtained by sealing the semiconductor element with a resin by using a molding die together with the bed, the lead frame is exposed on an outer surface of the package. A semiconductor device comprising a bed support projection formed to perform the following.
【請求項2】 ベッド支持凸部が、ベッドの周縁に連続
するように形成されていることを特徴とする請求項1記
載の半導体装置。
2. The semiconductor device according to claim 1, wherein the bed support projection is formed so as to be continuous with the periphery of the bed.
【請求項3】 ベッド支持凸部が、ベッドをリードフレ
ーム内に吊り支持する吊りピンの中間部に形成されてい
ることを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the bed support projection is formed at an intermediate portion of a suspension pin for suspending and supporting the bed in the lead frame.
【請求項4】 ベッド支持凸部が、ベッドの半導体素子
固着面に対し裏面側方向に凸となるように形成されてい
ることを特徴とする請求項1記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the bed supporting projection is formed so as to project toward the back surface side with respect to the semiconductor element fixing surface of the bed.
JP29496496A 1996-11-07 1996-11-07 Semiconductor device Pending JPH10144853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29496496A JPH10144853A (en) 1996-11-07 1996-11-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29496496A JPH10144853A (en) 1996-11-07 1996-11-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10144853A true JPH10144853A (en) 1998-05-29

Family

ID=17814588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29496496A Pending JPH10144853A (en) 1996-11-07 1996-11-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10144853A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1032037A3 (en) * 1999-02-24 2001-04-25 Matsushita Electronics Corporation Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
KR20010045637A (en) * 1999-11-05 2001-06-05 마이클 디. 오브라이언 Semiconductor package
US7192808B2 (en) 2003-02-21 2007-03-20 Yamaha Corporation Semiconductor device having a lead frame smaller than a semiconductor chip and manufacturing method therefor
US7245004B2 (en) 2003-05-20 2007-07-17 Rohm Co., Ltd. Semiconductor device
JPWO2011064817A1 (en) * 2009-11-26 2013-04-11 パナソニック株式会社 Semiconductor device and manufacturing method thereof
WO2013084842A1 (en) * 2011-12-06 2013-06-13 Kato Nobukazu Led package and production method for led package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1032037A3 (en) * 1999-02-24 2001-04-25 Matsushita Electronics Corporation Resin-moulded semiconductor device, method for manufacturing the same, and leadframe
EP1335427A3 (en) * 1999-02-24 2003-10-08 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device
EP1335428A3 (en) * 1999-02-24 2003-10-08 Matsushita Electric Industrial Co., Ltd. Resin-moulded semiconductor device and method for manufacturing the same
KR20010045637A (en) * 1999-11-05 2001-06-05 마이클 디. 오브라이언 Semiconductor package
US7192808B2 (en) 2003-02-21 2007-03-20 Yamaha Corporation Semiconductor device having a lead frame smaller than a semiconductor chip and manufacturing method therefor
US7245004B2 (en) 2003-05-20 2007-07-17 Rohm Co., Ltd. Semiconductor device
JPWO2011064817A1 (en) * 2009-11-26 2013-04-11 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP5566296B2 (en) * 2009-11-26 2014-08-06 パナソニック株式会社 Manufacturing method of semiconductor device
WO2013084842A1 (en) * 2011-12-06 2013-06-13 Kato Nobukazu Led package and production method for led package

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