JPH10133943A5 - - Google Patents

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Publication number
JPH10133943A5
JPH10133943A5 JP1997264305A JP26430597A JPH10133943A5 JP H10133943 A5 JPH10133943 A5 JP H10133943A5 JP 1997264305 A JP1997264305 A JP 1997264305A JP 26430597 A JP26430597 A JP 26430597A JP H10133943 A5 JPH10133943 A5 JP H10133943A5
Authority
JP
Japan
Prior art keywords
item
memory
additional
computing system
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997264305A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10133943A (ja
JP4065586B2 (ja
Filing date
Publication date
Priority claimed from US08/734,003 external-priority patent/US5995967A/en
Application filed filed Critical
Publication of JPH10133943A publication Critical patent/JPH10133943A/ja
Publication of JPH10133943A5 publication Critical patent/JPH10133943A5/ja
Application granted granted Critical
Publication of JP4065586B2 publication Critical patent/JP4065586B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP26430597A 1996-10-18 1997-09-29 リンクリスト形成方法 Expired - Fee Related JP4065586B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US734-003 1996-10-18
US08/734,003 US5995967A (en) 1996-10-18 1996-10-18 Forming linked lists using content addressable memory

Publications (3)

Publication Number Publication Date
JPH10133943A JPH10133943A (ja) 1998-05-22
JPH10133943A5 true JPH10133943A5 (cg-RX-API-DMAC7.html) 2005-06-16
JP4065586B2 JP4065586B2 (ja) 2008-03-26

Family

ID=24949967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26430597A Expired - Fee Related JP4065586B2 (ja) 1996-10-18 1997-09-29 リンクリスト形成方法

Country Status (2)

Country Link
US (2) US5995967A (cg-RX-API-DMAC7.html)
JP (1) JP4065586B2 (cg-RX-API-DMAC7.html)

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US6772300B1 (en) * 2000-08-30 2004-08-03 Intel Corporation Method and apparatus for managing out of order memory transactions
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US6721856B1 (en) 2000-10-26 2004-04-13 International Business Machines Corporation Enhanced cache management mechanism via an intelligent system bus monitor
US6629210B1 (en) * 2000-10-26 2003-09-30 International Business Machines Corporation Intelligent cache management mechanism via processor access sequence analysis
US6601144B1 (en) * 2000-10-26 2003-07-29 International Business Machines Corporation Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis
US6763433B1 (en) 2000-10-26 2004-07-13 International Business Machines Corporation High performance cache intervention mechanism for symmetric multiprocessor systems
US6704843B1 (en) 2000-10-26 2004-03-09 International Business Machines Corporation Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
US6868481B1 (en) * 2000-10-31 2005-03-15 Hewlett-Packard Development Company, L.P. Cache coherence protocol for a multiple bus multiprocessor system
US6941427B2 (en) * 2002-12-20 2005-09-06 Lsi Logic Corporation Method and apparatus for improving queue traversal time
US6996645B1 (en) * 2002-12-27 2006-02-07 Unisys Corporation Method and apparatus for spawning multiple requests from a single entry of a queue
US7222222B1 (en) * 2003-06-20 2007-05-22 Unisys Corporation System and method for handling memory requests in a multiprocessor shared memory system
JP2005173788A (ja) * 2003-12-09 2005-06-30 Ibm Japan Ltd オートノミック・コンピューティングシステム、実行環境制御方法及びプログラム
US8418127B2 (en) * 2003-12-09 2013-04-09 International Business Machines Corporation Autonomic computing system, execution environment control program
US7529800B2 (en) * 2003-12-18 2009-05-05 International Business Machines Corporation Queuing of conflicted remotely received transactions
US7774374B1 (en) * 2004-03-02 2010-08-10 Qlogic Corporation Switching systems and methods using wildcard searching
US7418543B2 (en) * 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7467256B2 (en) * 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
JP4856444B2 (ja) * 2005-03-07 2012-01-18 株式会社リコー 情報処理装置及び情報処理方法
US8275976B2 (en) * 2005-08-29 2012-09-25 The Invention Science Fund I, Llc Hierarchical instruction scheduler facilitating instruction replay
US8296550B2 (en) * 2005-08-29 2012-10-23 The Invention Science Fund I, Llc Hierarchical register file with operand capture ports
US9176741B2 (en) * 2005-08-29 2015-11-03 Invention Science Fund I, Llc Method and apparatus for segmented sequential storage
US7644258B2 (en) * 2005-08-29 2010-01-05 Searete, Llc Hybrid branch predictor using component predictors each having confidence and override signals
US20070083735A1 (en) * 2005-08-29 2007-04-12 Glew Andrew F Hierarchical processor
US20160098279A1 (en) * 2005-08-29 2016-04-07 Searete Llc Method and apparatus for segmented sequential storage
US7437373B2 (en) * 2006-03-06 2008-10-14 The Real Time Matrix Corporation Method and system for correlating information
US7539030B2 (en) * 2006-03-28 2009-05-26 Applied Wireless Identification Group, Inc. Attribute cache memory
JP4867451B2 (ja) * 2006-04-19 2012-02-01 日本電気株式会社 キャッシュメモリ装置及びそれに用いるキャッシュメモリ制御方法並びにそのプログラム
US8078657B2 (en) * 2007-01-03 2011-12-13 International Business Machines Corporation Multi-source dual-port linked list purger
US20080240227A1 (en) * 2007-03-30 2008-10-02 Wan Wade K Bitstream processing using marker codes with offset values
CN102347882B (zh) * 2010-07-29 2014-06-11 高通创锐讯通讯科技(上海)有限公司 Atm信元重组共享缓存系统及其实现方法
US9752105B2 (en) 2012-09-13 2017-09-05 Ecolab Usa Inc. Two step method of cleaning, sanitizing, and rinsing a surface
US10042764B2 (en) * 2016-06-27 2018-08-07 International Business Machines Corporation Processing commands in a directory-based computer memory management system
US11537319B2 (en) * 2019-12-11 2022-12-27 Advanced Micro Devices, Inc. Content addressable memory with sub-field minimum and maximum clamping
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