JPH10130856A - Glass circuit substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a glass circuit substrate which allows the formation of wirings by wet process plating without formation of special under costing layers on a glass surface and without impairment of the smoothness of the glass surface with reduced deterioration in adhesion property in spite of the thermal influence from outside. SOLUTION: This glass circuit substrate has a catalyst nucleus layer 2 consisting of metal Pd formed on a glass substrate 1 and an amorphous Pd-P plating layer 3 formed on this catalyst nucleus layer 2. The film thickness of this amorphous Pd-P plating layer 3 is 0.015 to 0.500μm. The content of the phosphorus in the amorphous Pd-P plating layer 3 is 3.0 to 10.0(wt.%).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a glass circuit board in which wiring, electrodes and the like are formed by metallizing glass by wet plating. More specifically, the present invention relates to a glass substrate having a smooth surface. While maintaining the
The present invention relates to a glass circuit board on which wiring, electrodes and the like are formed with good adhesion by wet plating.

[0002]

2. Description of the Related Art Conventionally, the following method has been known for metallizing an insulating substrate glass by wet plating. That is, after the surface of the glass is degreased and washed, the surface is roughened by etching, and the surface is immersed in a Sn / Pd colloid solution to capture the colloid particles on the rough surface, and then the tin protective film of tin / palladium colloid is formed. Removal by acid to obtain Pd metal nuclei for plating.

[0003] By immersing the substrate thus treated in an electroless nickel-phosphorus plating (hereinafter referred to as Ni-P) solution, the above-mentioned Pd metal nucleus is used as a catalyst nucleus to form Ni-
A conductive metal layer made of a P plating film is formed on the surface of the base.

[0004] As a known example, a glass is roughened with 10% hydrofluoric acid, and then a Pd nucleus is provided.
A research paper for forming i-P plating has been published by Homma et al. (Surface Technology vol. 44, No. 10, 19).
93).

When a metal wiring pattern is formed on an insulating substrate by plating, the Ni-P plating film is usually applied to the surface of the insulating substrate by about 1 μm, and then a low-resistance metal such as Cu plating is formed thereon. The layers are laminated from several μm to several tens μm.

[0006] In this case, the Ni-P plating film plays a role of an underlayer for laminating a low-resistance metal plating film on the surface of the insulating substrate.

In addition to the metallization method described above, an aminosilane coupling agent having a functional group having an affinity for the surface of an insulating substrate at one end and an amino group at the other end is applied to the surface of the substrate, and then a chloride is applied. Contact with aqueous palladium solution
There is known a method in which d ions are captured by an amino group, and the Pd ions are reduced to metal Pd with a reducing agent such as sodium hypophosphite. A metal layer can be formed on the catalyst nucleus thus formed by using electroless nickel plating or the like.

As another known example, after a semiconductor layer made of either ZnO or WO ₃ is formed on an insulator, Pd, Pt, Au, Ag, etc. are deposited thereon, and then Cu
A method of forming a conductive layer on an insulator by laminating conductive layers such as these has been filed by Fujishima et al.
No. 619, JP-A-4-17211).

When a desired metal pattern is to be formed on these insulating substrates, a required metal layer is first formed on the entire surface of the metal substrate by plating, and then a photoresist process or the like is used. There is known a subtractive method in which a necessary portion of a metal layer is protected by an etching method and an unprotected portion is removed by an etchant.

[0010]

However, the conventional plating film formed on a glass substrate has the following problems.

In other words, in the case where a metal layer is to be plated on a glass surface with good adhesion, it has been necessary in the prior art to roughen the surface with hydrofluoric acid or the like. Next, chloride 1
The sensitizing solution containing about 0.1 g / l of tin (SnCl ₂ ) is subjected to a sensitizing treatment in which the roughened substrate is immersed, so that the roughened surface captures Sn ²⁺ ions.

This substrate is immersed in an activation solution (containing about 0.1 g / l of palladium chloride) to replace the captured Sn ²⁺ ions and Pd ²⁺ ions, thereby forming Pd contact nuclei for electroless plating. Form. In addition to this pretreatment method, an alkaline catalyst method of adsorbing an organic complex compound of Pd on a glass substrate surface at pH 9 to 13 is known.

Next, about 0.5 (μm) of electroless Ni—P plating is deposited on the catalyst core, and further, Cu plating is laminated to a required thickness (usually about 3 to 20 μm).
The upper layer is plated with Ni and Au as an antioxidant layer for Cu. In the circuit board having such a configuration, the adhesion between the electroless Ni-P plating layer and the glass substrate is as follows.
It is manifested by the anchor effect caused by the plating layer entering the roughened glass surface having a complicated shape.

However, when an adhesion effect that can be used as a circuit pattern is to be developed by an anchor effect,
It is necessary to roughen the glass until the average surface roughness Ra becomes about 0.2 μm, which not only impairs the characteristics of the glass substrate, such as transparency and smoothness, but also causes microcracks on the entire surface. In many cases, the strength of the substrate is reduced, and the precision of a fine line pattern required for an electronic device or the like is not easily obtained. In addition, the probability of disconnection when patterning the fine line increases. .

The Ni—P plating film has a heating temperature of 10
From around 0 ° C., it begins to be affected by crystallization due to the formation of nickel phosphide. At around 400 ° C., it is converted to Ni ₃ P, causing distortion between the Pd catalyst nucleus and the Ni plating layer, resulting in deterioration of adhesion. There's a problem.

Although there is a method of applying a coupling agent between the glass substrate and the plating layer so as not to impair the smoothness of the substrate surface, annealing can be performed only at a temperature lower than the decomposition temperature of the coupling agent, and There is a problem that the ambient temperature for use is also limited to the decomposition temperature of the coupling agent or lower.

Further, there is a method of forming a circuit pattern by printing a metal paste on glass. However, the patterned metal paste needs to be fired at a high temperature, in which case the substrate is easily deformed, Not only can crystalline glass having high properties be used, which causes a cost increase, but also has the drawback that it is difficult to obtain the flatness of the pattern surface by printing.

Here, by using the methods disclosed in JP-A-6-61619 and JP-A-4-17211, it is possible to laminate a plating film on a glass substrate with good adhesion. There is a problem that a ZnO or WO ₃ film forming process is required, and the film forming cost is high. In addition, since a ZnO or WO ₃ film forming process requires a high temperature, a low-melting glass substrate such as blue sheet glass is required. If used, problems such as warpage and distortion of the glass substrate occur.

[Object of the Invention] The present invention has been filed in view of the above problems, and does not form a special undercoat layer on the glass surface, and further impairs the smoothness of the glass surface. In addition, the present invention proposes a configuration for forming a wiring on glass by wet plating, which causes little deterioration in adhesion even with respect to external thermal effects.

[0020]

The present invention has the following means to solve the above-mentioned problems.

*** (FIG. 1, Examples 1 to 3) *** [1] A catalyst core layer made of metal Pd formed on a glass substrate and an amorphous P formed on the catalyst core layer
and a d-P plating layer.

[2] The glass circuit board, wherein the thickness of the amorphous Pd-P plating layer is 0.015 to 0.500 μm.

[3] The glass circuit board, wherein the amorphous Pd-P plating layer has a phosphorus content of 3.0 to 10.0 (wt%).

*** (FIGS. 2-7, Examples 2-15) **
* [4] The plating layer is made of Cu, Ni, Ni-P, A
A glass circuit board comprising one kind of metal selected from g, Pd, Pd-P, Au, and Pt or two or more kinds of alloys.

*** (FIG. 2, Example 4) *** [5] A catalyst core layer made of metal Pd formed on a glass substrate and an amorphous P formed on the catalyst core layer
d-P plating layer, Cu plating layer, Ni plating layer,
A glass circuit board, comprising: an Au plating layer.

*** (FIG. 3, Example 5) *** [6] A catalyst core layer made of metal Pd formed on a glass substrate and an amorphous P formed on the catalyst core layer
d-P plating layer, Ag plating layer, Au plating layer,
A glass circuit board comprising:

*** (FIG. 4, Examples 6, 7, 8) *** [7] A catalyst core layer made of metal Pd formed on a glass substrate, and an amorphous layer formed on the catalyst core layer P
A glass circuit board having a dP plating layer and a crystalline Pd-P plating layer.

*** (FIG. 5, Examples 9 and 15) *** [8] A catalyst core layer made of metal Pd formed on a glass substrate and an amorphous P formed on the catalyst core layer
A glass circuit board comprising: a dP plating layer, a crystalline Pd-P plating layer, a Cu plating layer, a Ni plating layer, and an Au plating layer.

*** (FIG. 6, Example 10) *** [9] A catalyst core layer made of metal Pd formed on a glass substrate and an amorphous P formed on the catalyst core layer
A glass circuit board comprising: a dP plating layer, a crystalline Pd-P plating layer, an Ag plating layer, and an Au plating layer.

*** (FIG. 7, Examples 11, 12, 13,
14) *** [10] A catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, and a crystalline Pd-P plating layer, Pt
A glass circuit board comprising: a plating layer.

[11] A glass circuit substrate, wherein the thickness of the crystalline Pd-P layer is 0.015 to 0.250 μm.

[12] A glass circuit substrate characterized in that the crystallinity is inclinedly changed at an interface between the amorphous Pd-P plating layer and the crystalline Pd-P layer.

[13] From the a-Pd plating layer, c
-A glass circuit board having a film structure in which the content of P decreases continuously and gradually in a Pd plating layer.

[14] The glass circuit board according to any one of claims 7 to 13, wherein the c-Pd plating layer has a thickness of 0.015 to 0.25 µm.

[15] The glass circuit board, wherein the c-Pd plating layer has a phosphorus content of 0 to 1 (wt%).

**** The present invention relates to a method for preparing a first layer on a palladium-based catalyst nucleus provided on a glass substrate as a first layer containing a certain amount of P
By forming the Pd plating layer to an appropriate thickness, a plating layer having sufficient adhesion can be formed without performing an extreme roughening treatment on the glass substrate.

Further, according to the present invention, a c-Pd plating layer close to crystallinity is laminated on this a-Pd layer,
Changing the content of P in the Pd laminated film in a gradient manner,
When patterning fine lines on a smooth glass substrate,
It is possible to obtain a metallized glass substrate having wiring / electrodes formed by wet plating and having excellent film stability, adhesion, and resolution.

According to the present invention, the average surface roughness Ra is 0.5.
0010 to 0.10 (μm), preferably 0.0012 to
A catalyst nucleus mainly composed of metal Pd is formed on the entire surface or a part of the glass substrate having a thickness of 0.050 (μm), and a film thickness of 0.015 to 0.50 ( μ
m), preferably 0.020 to 0.40 (μm), and the phosphorus content is 3.0 to 10.0 (wt%), preferably 3.5 to 9.0 (wt%). By forming the a-Pd plating layer, the smoothness of the glass surface is not impaired,
A glass circuit board having plated wiring with little degradation of adhesion even with external thermal influences can be obtained.

At this time, the pretreatment step performed prior to the catalyst nucleus providing step needs to be performed using a chemical and a condition that do not cause microcracks on the surface of the glass substrate. In addition, as a process for providing a catalyst nucleus to a glass substrate, a sensitizer activator method in which Sn adsorbed on the substrate surface is replaced with Pd, and a catalyst accelerator method in which Sn · Pd colloid is adsorbed on the substrate surface. Further, an alkaline catalyst method or the like in which an alkaline Pd complex is adsorbed on the substrate surface and then reduced to zero-valent metal Pd can be suitably used.

The thickness of the a-Pd plating layer deposited on the catalyst nuclei and the phosphorus content greatly affect the adhesion of the circuit pattern to be formed to the glass substrate.

That is, the average surface roughness Ra of the glass substrate
But 0.0010 to 0.10 (μm), preferably 0.0
In the range of 012 to 0.050 (μm), 0.00
If it is smaller than 10 (μm), the adhesion will deteriorate, and
If it is larger than (μm), defects tend to occur when the thin film is patterned.

Similarly, the thickness of the a-Pd plating layer is set to 0.
015-0.50 (μm), preferably 0.020-0.
In the range of 40 (μm), if it is less than 0.015 (μm), it tends to become a film having many defects, and 0.50 (μm)
If it is larger than this, film peeling tends to occur.

Further, the phosphorus content in the a-Pd plating layer is 3.0 to 10 (wt%), preferably 3.5 to 9.0.
In the range of (wt%), if it is smaller than 3.0 (wt%), the film stress increases, and the film is easily peeled off, and 10 (wt%).
%), Plating must be performed under conditions in which the plating solution is easily decomposed, such as when the plating temperature must be set high when performing electroless Pd plating, and this is not suitable for mass production.

Also, according to the present invention, after patterning is performed on the a-Pd plating layer by photolithography or etching if necessary, Cu, Ni, Ni-P, A
g, Pd, Pd-P, Au, Pt, by laminating a plating layer composed of at least one or more metals or two or more alloys selected from among alloys, without impairing the smoothness of the glass surface. In addition, a glass circuit board having plated wiring with less deterioration of adhesion even with external thermal influence can be obtained.

Further, according to the present invention, after forming an a-Pd plating layer on a glass substrate, if necessary,
The plating film is subjected to patterning by performing photolithography, etching, and the like, and the P content is 0 to 1 wt%, preferably 0 to 0.5 wt% on the entire surface or a part thereof, and the film thickness is further reduced. , 0.015 to 0.25 (μm)
By laminating a c-Pd plating layer preferably having a thickness of 0.020 to 0.20 (μm), excellent adhesion to a glass substrate can be exhibited without impairing the smoothness of the glass surface. Alternatively, as compared with the case where the a-Pd plated film of the present invention is plated with a single film, a glass circuit board having plated wiring with less change in resistance when subjected to heat history and having a stable surface is obtained. Can be

The change in resistance during heating is a-Pd of the present invention.
The reason why the size of the plating film is smaller than when a single film is formed is that the a-Pd plating film has a film structure close to non-crystal, whereas the c-Pd plating film has a film structure close to polycrystal. Because.

Actually, such a laminated structure {glass / a}
−Pd (0.04 μm) / c−Pd (0.04 μm)}
A line width of 200 μm was formed on a metallized glass substrate
A line pattern having a length of 8 cm was prepared, baked in an oxidizing atmosphere at 450 ° C. for 40 minutes, and the change in volume resistivity before and after heating was measured by a four-terminal method.

At this time, the average value of the volume resistivity measurement results of the laminated film before and after firing was 6.5 × 10 ⁻⁵ (Ωc) before firing.
m) and after firing was 4 × 10 ⁻⁵ (Ωcm) (100 samples).

Further, by adopting such a two-layer structure, P is diffused from the a-Pd layer into the c-Pd layer by an appropriate heat treatment, and the P-layer is changed from the a-Pd plating layer to the c-Pd plating layer. , P can be reduced. By forming a film in which the P content is inclined over two layers, stress generated when layers having different crystal structures are stacked can be reduced, the film stress can be reduced, and the adhesion to the substrate can be improved.

Further, by forming a thin film having a two-layer structure having a c-Pd plating film on the surface, it is difficult to directly laminate Pt or Au on the a-Pd plating thin film due to film damage due to replacement. It is possible to stack a metal having a higher oxidation-reduction potential than Pd without using a metal other than Pd.

Here, the thickness of the c-Pd plating film is
If it is smaller than 0.015 (μm), the effect of the diffusion of P into the film will have no effect on the improvement of the electrical properties at the time of heating, and 0.2
When it is larger than 5 (μm), the film stress increases and the film is liable to be peeled off.
If it is larger than (wt%), no remarkable improvement in electric characteristics and film stability is observed as compared with the single film of the a-Pd plating layer.

According to the present invention, a-Pd / c-P
Cu, Ni, Ni-
By laminating plating layers made of at least one kind of metal or two or more kinds of alloys selected from P, Ag, Au, and Pt, the glass substrate surface does not lose its original smoothness, and In addition to being able to laminate the film while minimizing the damage of the film and the damage of the catalyst nuclei in the subsequent surface treatment, it is advantageous in terms of the resistance value when performing electroplating.

Hereinafter, the present invention will be described in more detail with reference to the drawings. Conventionally, there has been known a method of providing a Pd catalyst nucleus on glass and forming a chemical Ni-P plating film thereon, and performing wiring by laminating Cu or the like on the Ni-P plating film. Are also known.

FIG. 10 is a schematic view showing a layer structure of a wet plating known as a conventional example. In this figure, 1 is a roughened glass substrate, 2 is a catalyst core layer mainly composed of metal Pd, Reference numeral 10 denotes a non-crystalline electroless Ni-P plating film plated on the catalyst core layer 2.

Generally, c- is smaller than that of the Ni-P plating film.
It is considered that the Pd plating film has a large film stress and has a problem in adhesion, but the Ni-P plating layer has a heating temperature of 10%.
Around 0 ° C., there is a problem with heat resistance such as starting to be affected by the formation of nickel phosphide and crystallization of nickel and having a clear diffraction peak at 300 ° C.

When the plating substrate receives heat, the Ni—P plating layer provided on the metal Pd catalyst core layer, or
Part of P in the a-Pd plating layer diffuses into the metal Pd catalyst nucleus to form a palladium-phosphorus alloy.

At this time, it is considered that when the a-Pd plating layer is formed on the catalyst core layer, the stress applied to the catalyst core layer is smaller, and the adhesion of the plating layer to the glass substrate is improved. Moreover, by plating the a-Pd plating film having the film thickness and the P content as described in the present invention on the Pd catalyst core layer, it is extremely excellent even if the glass surface is not extremely roughened. A circuit board having plated wiring and electrodes having adhesion to a glass substrate can be produced.

FIG. 1 is a schematic diagram of this, in which 1 is a glass substrate, 2 is a catalyst core layer mainly composed of metal Pd, and 3 is an a-Pd plating layer.

In the conventional Ni-P plating on glass,
In order to cover the insufficient adhesion, the glass surface was roughened until the average surface roughness Ra became about 0.4 μm. However, according to the present invention, the glass substrate had a surface roughness Ra of 0.002 μm.
Even in a smooth state of about m, adhesion equal to or higher than that of a roughened substrate can be obtained.

FIG. 2 and FIG. 3 are schematic views showing an example of the layer structure of the present invention, which is a glass substrate having a circuit formed by laminating a metal on an a-Pd plating layer.

In FIG. 2, 1 is a glass substrate, 2 is the above-described catalyst core layer, 3 is an a-Pd plating layer, 4 is a Cu plating layer for low resistance wiring, and 5 is a Ni plating layer for preventing diffusion. And 6 are Au plating layers for preventing oxidation.

As shown in FIG. 3, an Ag plating layer can be used in place of the Cu plating layer 4 described above.
In this figure, 1 is a glass substrate, 2 is the above-described catalyst core layer,
3 is an a-Pd plating layer, 8 is an Ag plating layer for low resistance wiring, and 6 is an Au plating layer for preventing oxidation.

Here, instead of the a-Pd plating film, a conventionally used Ni-P plating layer is laminated,
FIG. 10 is a schematic diagram when u, Ni, and Au are sequentially laminated.
When stacking is performed in such a layer configuration, peeling of the film is likely to occur due to an increase in stress due to stacking, and further, peeling of the film is often promoted by external heating.

However, when the a-Pd plating layer is formed as the first layer on the catalyst nucleus as in the present case, the stress due to lamination can be obtained without performing the treatment for improving the adhesion such as roughening the glass surface or applying a coupling agent. Not only can be absorbed, but also good adhesion can be maintained during heating.

Further, according to the present invention, when a c-Pd plating layer is laminated on an a-Pd plating layer, P diffuses from the a-Pd plating layer into the c-Pd plating layer, and the
Can be formed in a film structure in which the content decreases while continuously tilting. In order to incline the P content in this manner, the above-mentioned laminated film may be annealed at an appropriate temperature.

By making the plating film formed on the catalyst nucleus layer a gradient film as described above, the adhesion strength of the a-Pd plating layer is hardly reduced and the a-Pd single film is more thermally and chemically treated than the a-Pd single film. A stable surface state can be obtained.

That is, Pd having a structure close to non-crystallinity
Compared to the case of the single P-plated film, not only the substitution reaction at the time of laminating different kinds of metals and the stability of the film against the attack of the chemical solution are increased, but also the resistance change due to heating is smaller than that of the Pd-P single film. , Cu, Ni, Ni-P, Ag, Pd, Pd-
This is particularly effective when electroplating metals such as P, Au, and Pt.

Here, graph 1 shown in FIG. 11 shows that a plating layer according to the present invention is laminated on float glass (blue sheet glass), subjected to an appropriate heat treatment, and then the film is subjected to Auger electron spectroscopy. (Hereinafter abbreviated as AES), and is a result of examining the distribution intensity of P in the depth direction.

The plating film thickness of the substrate used in the analysis was determined to be about 0.30 μm for the a-Pd plating layer and about 0.25 μm for the c-Pd plating layer from the results of observation with a transmission electron microscope (hereinafter referred to as TEM). (See Photo 1 shown in FIG. 12).

The measurement conditions of AES and TEM are shown below.

[TEM observation conditions] Apparatus used H-9000NAR (manufactured by Hitachi, Ltd.) Acceleration voltage 300 kV [AES analysis conditions] Apparatus used: PHI-660 manufactured by PERKIN-ELMER Inc. Electron gun acceleration voltage 3 kv Sample current Approx. 100 nA Ion gun ion species Ar ⁺ beam voltage 0.7 kv Sputter rate Approx. 2 nm / min (SiO ₂ conversion) The reason why the P content is different, in other words, the Pd plating layers each having a film quality close to amorphous and polycrystalline are plated into two layers is that the c-Pd plating film close to polycrystalline is formed on the first layer on the catalyst core layer. This is because, when formed in a layer, there is a high risk of peeling due to film stress. Therefore, first, an a-Pd plating film having a relatively small film stress was formed, and a c-Pd plating film was laminated thereon, and the stress was relaxed by positively utilizing the diffusion of P.

That is, the film stress due to the difference in crystallinity between the two layers can be caused by diffusing P in the a-Pd plating layer into the c-Pd plating layer in an inclined manner and reducing the total film thickness. It was relaxed to minimize the decrease in adhesion to the glass substrate. Since the c-Pd plating layer close to polycrystalline is not only low in electric resistivity but also excellent in the stability of the plating film surface as compared with the a-Pd plating layer close to non-crystalline,
As described above, Cu, Ni, Ni-P, Ag, Pd, Pd-
This is particularly effective when one metal selected from P, Au, and Pt or a metal such as two or more alloys is subjected to electric pattern plating.

FIG. 4 schematically shows the above-described Pd plating film having a two-layer structure, in which 1 is a glass substrate, 2 is a catalyst core layer mainly composed of metal Pd, and 3 is a -Pd plating layer, 7 is a c-Pd plating layer.

FIG. 5, FIG. 6, and FIG. 7 are schematic views showing an example of the layer structure of the present invention.
It is an example of a glass substrate on which a circuit is formed by further laminating a metal.

First, in FIG. 5, 1 is a glass substrate, 2
Is the above-mentioned catalyst core layer, 3 is a-Pd plating layer, 7 is c-P
d plating layer, 4 is a Cu plating layer for low resistance wiring, 5
Is a Ni plating layer for preventing diffusion, and 6 is an Au plating layer for preventing oxidation.

Next, in FIG. 6, 1 is a glass substrate, 2
Is the above-mentioned catalyst core layer, 3 is a-Pd plating layer, 7 is c-P
d plating layer, 8 is an Ag plating layer for low resistance wiring, 6
Is an Au plating layer for preventing oxidation.

Further, in FIG. 7, 1 is a glass substrate,
2 is the above-mentioned catalyst core layer, 3 is an a-Pd plating layer, 7 is c-
A Pd plating layer 9 is a Pt plating layer.

As described above, by forming a Pd-plated layer containing a certain amount of P as a first layer on the catalyst core layer to an appropriate thickness, the glass substrate is hardly roughened. However, sufficient adhesion can be obtained. Moreover, by laminating a Pd plating layer close to crystallinity on this, a Pd plating layer having a tilted P content can be formed, and both film stability and adhesion to the substrate can be achieved. Becomes

Here, the evaluation of the adhesion of the plating layer on the glass circuit board in the present invention was performed as follows.
That is, a plating pattern having a size of 2 mm □ is formed on a glass substrate of 100 mm × 100 mm × 1.1 mm in thickness, and a metal wire having a diameter of 1 mm is soldered to the pattern, and then vertically drawn using the metal wire. By conducting the test,
The adhesion between the glass substrate and the laminated plating film was evaluated.

The evaluation of adhesion by the vertical tensile test was 20
Based on the average value of the tensile test results at the points, the evaluation was performed based on the following criteria. Adhesion evaluation Average value of measurement results at 20 points Good 2.5 kg / 2 mm □ or more Normal 1.0 to 2.5 kg / 2 mm □ Poor 1.0 kg / 2 mm □ or less However, the above average value is 1.0 kg / 2 mm Even if it exceeds □, a sample in which the substrate was frequently broken due to microcracks generated in the glass substrate was judged unsuitable for the comprehensive evaluation. Table 1 shows the test results.

The heat resistance test described in the present invention was carried out according to the following method.

In the heat resistance test, the line width was 80 μm and the length was 60 mm.
Of 50 line patterns prepared on the above glass substrate were put into a belt furnace which was baked in an oxidizing atmosphere while constantly blowing fresh air onto the substrate surface, and the maximum temperature was 420 ° C. and the holding time was 15 minutes. The heating was performed under such conditions.

At this time, a sample in which even one pattern peeling or disconnection occurred was determined to be defective, and one in which no pattern was generated was regarded as good. Table 2 shows the test results.

Further, Photo 3 shown in FIG. 14 shows a glass obtained by subjecting a conventional roughened glass substrate (surface roughness Ra: 0.4 μm) to Ni—P plating with a thickness of 0.1 μm and patterning. FIG. 15 is a SEM photograph of the circuit board, and photograph 4 shown in FIG. 15 shows a glass substrate (surface roughness Ra: 0.002 μm) whose surface was not roughened according to the present invention.
It is a SEM photograph of the glass circuit board which performed patterning by giving a-Pd plating of thickness 0.1 micrometers.

In the SEM photograph, the portion that looks black is the glass substrate, and the portion that looks whitish is where plating has been applied. The patterning method was common to both substrates. After plating was performed on the entire surface of the glass substrate, the portion where the plating pattern was to be left was protected with a resist, and etching was performed to form a pattern.

As apparent from these photographs, FIG.
In the Ni-P plating pattern formed on the glass substrate subjected to the roughening treatment shown in Photo 3 shown in FIG. 3, the lack of plating is noticeable in the shape of the roughened pattern, and in some cases, this leads to continuous disconnection.

On the other hand, in the a-Pd plating pattern formed on the glass substrate which has not been subjected to the roughening treatment as shown in Photo 4 shown in FIG. 15, no chipping or disconnection is observed, and stable patterning is performed. Can be.

The SEM measurement conditions are shown below. Apparatus used S-3000 (manufactured by Hitachi, Ltd.) Acceleration voltage 10 kV Direct magnification × 100 Table 3 evaluates the resolving power of the line pattern formed based on the present invention in comparison with the prior art.

As a conventional technique, the average surface roughness Ra is set at 0.
A catalyst nucleus was formed on a glass substrate that had been subjected to a roughening treatment to a thickness of 4 μm, and an electroless Ni—P plating film was formed thereon. A glass circuit board which has not been subjected to extreme roughening on the surface prepared according to the present invention on this substrate shows excellent resolution even when the pattern line width is small.

The evaluation of the resolving power was performed by applying a photo-etching process to each of the plated products at 20 μm and 5 μm.
The patterning was performed based on the number of patterning defects when 50 line patterns of 0 μm and 100 μm were formed.

From Table 3, it can be seen from the table that the pattern formed by the prior art has a sharp increase in the number of breaks when the line width is smaller than 50 μm, whereas the pattern formed based on the present invention has a line width. It can be seen that patterning is possible without disconnection even at 20 μm.

As is clear from the results of Tables 1, 2 and 3, the catalyst nuclei formed with the a-Pd plating film on the first layer on the catalyst nuclei were formed after the glass substrate was roughened. In addition to a glass circuit board having a Ni-P plating film as the first layer formed thereon, it not only exhibits excellent adhesion, but also has sufficient adhesion without extreme roughening treatment. As a result, there is no problem such as the occurrence of microcracks on the surface of the glass substrate which occurs during the roughening treatment, and the patterning of fine wires can be performed in a manner that is incomparable to the roughened substrate.

[0093]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples, but the present invention is not limited to these.

In the present invention, the gas used for the glass circuit board is
The material of the glass substrate 1 is generally known as blue sheet glass.
Alkali-containing glass (an example of a trade name UFF
Glass Nippon Sheet Glass) and borosilicate glass
Almost no alkali (example of brand name #
7059 Corning) and SiO on the glass surface _Two 
(Example of trade name H-coated glass
 Nippon Sheet Glass) or the like can be used.

In plating a glass substrate, the substrate is first washed with a degreasing agent or the like, and then a catalyst nucleus for plating is applied to the surface. The catalyst nucleus provided on the glass substrate is preferably made of a metal mainly composed of metal Pd, and a known method can be used. This catalyst nucleus can be uniformly and densely provided on the glass substrate surface. preferable.

For degreasing the substrate, any of a solvent system and an aqueous system can be used. As water-based glass cleaners, trade names P ₃ siliron HS, P ₃ sili
ronL (manufactured by Henkel Hakusui), trade name OPC-38
0 Condiclean M (manufactured by Okuno Pharmaceutical Co., Ltd.), trade name: Mercleaner ITO-170 (manufactured by Meltex Corporation), and
Others can be used appropriately.

For forming a catalyst nucleus on a substrate, a method in which Sn adsorbed on the substrate surface is replaced with Pd to form a catalyst nucleus,
A method of removing Sn after adsorbing a Pd-Sn colloid on a substrate surface to form a catalyst nucleus, and a method of forming a zero-valent metal Pd catalyst nucleus by adsorbing and reducing an Sn-free Pd complex on the substrate surface, Others are known, and the process can be selected according to the state of the substrate.

The details of an example of the actual pretreatment process will be described in more detail below.

First, as a cleaning step, a glass substrate is immersed in an organic solvent such as isopropyl alcohol (hereinafter referred to as IPA), and then immersed in a water-soluble degreasing agent (trade name: Mercleaner ITO-170 manufactured by Meltex Co., Ltd.). And immersion washing for 5 minutes under the conditions of a liquid concentration of 15 g / l, a liquid temperature of 50 ° C. and ultrasonic irradiation, and further, washing the substrate with ion-exchanged water, followed by a water having a concentration of 70 g / l and a liquid temperature of 70 ° C. It was immersed in a potassium oxide aqueous solution for 5 minutes while performing ultrasonic irradiation, and washed with ion-exchanged water.

Next, in forming the metal Pd nucleus,
The sensitivity of PH1 containing 0.06 g / l of stannous chloride
Immerse in a solution for 3 minutes at 25 ° C.
Sn ²⁺Is adsorbed.

After washing with water, 0.1 g / d of PdCl ₂ was added.
l for 5 minutes at 25 ° C.
After replacing Sn on the substrate with Pd, the substrate is washed with water and immersed in an electroless Pd plating solution.

Here, an electroless Pd plating solution using sodium hypophosphite as a reducing agent is used for forming the a-Pd plating layer formed as the first layer on the Pd catalyst core layer in the present invention. be able to.

By appropriately setting the composition of the electroless Pd plating solution and the plating conditions, a plating layer having the thickness and the P content as shown in the present invention can be formed.

As the above electroless Pd plating solution, a plating solution having a known composition can be used, or a commercially available product can be used. Specific examples of commercially available chemicals include trade name Muden Noble PD (manufactured by Okuno Pharmaceutical), trade name Unicon electroless palladium-phosphorus APP plating bath (manufactured by Ishihara Chemical)
Etc. can be suitably used.

Further, as an example of a basic bath having a known composition, the following are known.

That is, it contains PdCl ₂ as a metal salt, ethylenediamine as a complexing agent, thioglycolic acid as a stabilizer, and sodium hypophosphite as a reducing agent.

In addition, electroless P using sodium phosphite, hydrazine, dimethylamine borane as a reducing agent and triethylenetetramine as a complexing agent.
d plating solutions are known.

Under these circumstances, according to the present invention, the entire surface of a glass substrate having an average surface roughness Ra of 0.0010 to 0.10 (μm), preferably 0.0012 to 0.050 (μm). Alternatively, a catalyst nucleus mainly composed of metal Pd is formed, and a film thickness of 0.015 mm is formed on the catalyst nucleus.
0.50 (μm), preferably 0.020 to 0.40
(Μm), and the phosphorus content is 3.0 to 10.0 (w
t%) Preferably, by selecting a plating solution and selecting plating conditions so as to be preferably 3.5 to 9.0 (wt%), a glass circuit board having excellent characteristics can be obtained.

Under these conditions, an a-Pd plating layer was formed on one surface of a blue sheet glass manufactured by the float method, and an example of the result of observing the cross section by TEM is shown in FIG. Shown in

In Photo 2 shown in FIG. 13, (a) is a blue sheet glass, (b) is a catalyst core layer mainly composed of metal Pd,
(C) is an a-Pd plating layer, and it can be observed from the photograph that the glass substrate is kept smooth after the formation of the plating layer.

Further, according to the present invention, if necessary, patterning, a-Pd plating layer formed on a glass substrate,
A pattern of wiring, electrodes, etc. is formed by etching or the like, and Cu, Ni, Ni-P, Ag, Pd, P
By laminating one or more plating films selected from dP, Au, and Pt, a glass circuit board having excellent characteristics can be obtained.

Further, according to the present invention, the average surface roughness R
a is 0.0010 to 0.10 (μm), preferably 0.1 to 0.10 (μm).
A catalyst nucleus mainly composed of metal Pd is formed on the entire surface or a part of the glass substrate having a thickness of 0012 to 0.050 (μm).
50 (μm), preferably 0.020 to 0.40 (μm)
And forming an a-Pd plating layer having a P content of 3.0 to 10 (wt%), preferably 3.5 to 9.0 (wt%), and performing photolithography and etching if necessary. After patterning by applying to this, the film thickness is further increased to 0.015 to 0.25 on the entire surface or a part thereof.
(Μm), preferably 0.020 to 0.20 (μm), and the P content is 0 to 1.0 (wt%), preferably 0 to
By laminating a 0.5 wt% c-Pd plating layer, a glass circuit board having excellent characteristics can be obtained.

Based on these conditions, an example of a cross-sectional observation result by TEM of a substrate having an a-Pd plating layer and a c-Pd plating layer formed on one surface of a blue sheet glass manufactured by a float method is shown in FIG. 12 is a photograph 1 shown in FIG.

In the photograph 1 shown in FIG. 12, (a) is a blue sheet glass, (b) is a catalyst core layer mainly composed of metal Pd,
(C) is an a-Pd plating layer, (d) is a c-Pd plating layer, and it can be observed from the photograph that the glass substrate is kept smooth after the formation of the plating layer.

Next, according to the present invention, after wiring, electrodes and the like are formed on the c-Pd plating layer formed on the glass substrate by performing patterning, etching and the like, if necessary, Cu, Ni, Ni -P, Ag, Pd, Pd-P,
By laminating at least one or more types of plating layers selected from Au and Pt on the entire surface or on a part thereof, a glass circuit board having plated wiring and electrodes can be produced.

Thus, on the Pd-containing Pd plating layer,
By laminating a Pd plating layer containing almost no P,
The stability of the Pd film against a substitution reaction, a chemical, or the like can be increased without deteriorating the adhesion of the Pd film.

For example, when a metal species nobler than Pd such as Pt is laminated on the a-Pd plating layer, a substitution reaction easily occurs between the two and damages not only to the a-Pd plating layer but also to the catalyst core layer. In many cases, the adhesion is extremely reduced.

That is, since the a-Pd plating layer is in a very active state, the a-Pd plating layer is susceptible to such substitution in the plating solution and attack by the complexing agent in the plating bath. In such a case, if the a-Pd plating layer is a thin film as shown in the present invention, the damage often extends not only to the a-Pd plating layer but also to the underlying catalyst core layer.

In order to prevent this damage from reaching the catalytic core layer without increasing the thickness of the Pd plating layer extremely, the c-Pd plating layer as shown in the present invention should be a-Pd.
It is effective to laminate on the d plating layer.

This is because the c-Pd plating layer containing almost no P and having a film quality close to crystalline is a
This is because the resistance to the above-mentioned attack in the plating solution is higher than that of the Pd plating layer. That is, the total thickness of the case where the c-Pd plating layer is laminated on the a-Pd plating layer is smaller than the case where the thickness of the a-Pd plating layer is increased to prevent damage to the catalyst nucleus. Since the film becomes thinner and the film stress can be reduced, the adhesion is hardly deteriorated.

Further, by laminating a c-Pd plating layer whose film quality is close to crystalline, P diffused from the a-Pd plating layer during the heat treatment step can be trapped in this c-Pd plating layer.

Further, by selecting appropriate heat treatment conditions, the diffusion of P is positively utilized, so that P continuously changes over the above two layers, that is, the P content gradually increases toward the upper part. It is possible to obtain a laminated film in which a-Pd in which amorphousness is dominant is obtained.
The stress caused by the lamination of the plating layer and the c-Pd plating layer, which is dominant in crystallinity and contains almost no P, can be alleviated and the film stress can be reduced.

Chemical plating solution usable in the present invention,
In addition, known electroplating solutions can be suitably used.

The following is an example.

Commercial product name Product name Sales company name Electroless Pd-P plating solution Electroless Noble PD Okuno Pharmaceutical Co., Ltd. Electroless Pd plating solution (does not contain P) Pallet (PARED) Kojima Chemical Co., Ltd. Electric Pd plating solution K-Pure Palladium Kojima Chemical Co., Ltd. Electroless Ni-P plating solution Melplate Ni-422 Meltex Co., Ltd. Electroless Cu plating solution Enplate Cu-406 Meltex Co., Ltd. Electric Ag plating Silver glow 3K Japan Lilonal Co., Ltd. Electroless Au plating solution OH III Electroless Au plating solution Kojima Chemical Co., Ltd. Electroless Pt plating solution EL-PLATINUM • 206 N-Echemcat Co., Ltd. Electric Pt plating solution Pt-255 N-Echemcat Electrolytic copper plating solution Copper sulfate 75 g / l Sulfuric acid 190 g / l Chloride ion 50ppm Copperglyme CLX-A 5ml / l Nippon Leelonal Co., Ltd. Copperglyme CLX-C 5ml / l Nippon Leelonal Co., Ltd. Electric nickel plating solution Nickel sulfamate 410g / l Nickel chloride 30g / l Boric acid 37g / l Nical PC-3 30ml / l Nippon Leelonal Co., Ltd. Nycal-W 0.3ml / l Nippon Leelonal Co., Ltd. Electric nickel plating solution Nickel sulfate 350g / l Nickel chloride 45g / l Boric acid 47g / l Nycal PC-3 30ml / l Nippon Leronal Co., Ltd. Nikal-W 0.3 ml / l Nippon Lelonal Co., Ltd. A plating solution prepared using a known composition other than a commercially available product can also be used.

As an example, the surface technology vol. 40, N
o3, 1989, p123-126, an electroless Pd-P plating solution using ethylenediamine as a complexing agent and sodium hypophosphite as a reducing agent.

However, the above is only an example, and the chemicals / plating solutions usable in the present invention are not limited to the above.

References Printed Circuit Society of Japan "Circuit Technology" 7
(4), pp. 363-271 (1992) 7
(6), P369-376 (1992) Surface technology vol. 44, No5, P425-429
(1993) Surface technology vol. 44, No12, P136-139
(1993) Surface technology vol. 42, No11, P90-95 (1
991) Surface technology vol. 40, No3, P477-480
(1989) (Example 1) 100 mm × 100 m as a glass substrate
A float blue sheet glass (manufactured by Nippon Sheet Glass) having a mx 1.1 mm thickness is prepared, immersed in IPA for 5 minutes while irradiating ultrasonic waves, and a water-soluble degreasing agent, Meltexx, a Mel Cleaner. ITO-170 (liquid concentration 15 g /
immersion for 5 minutes in a liquid temperature of 50 ° C.) while irradiating with ultrasonic waves, washing with ion-exchanged water, and further immersing in an aqueous potassium hydroxide solution (concentration 70 g / l, liquid temperature 70 ° C.). It is immersed for 5 minutes while irradiating a sound wave, washed with ion exchanged water, and the degreasing step is completed.

Subsequently, stannous chloride (SnCl ₂ )
Which contained 0.06 g / l PH1, immersed bath temperature in 25 ° C. in an aqueous solution for 3 minutes, after washing with deionized water, at 25 ° C. palladium chloride (PdCl ₂₎ in an aqueous solution containing 0.1 g / l It is immersed for 5 minutes and washed with ion-exchanged water to complete the catalyst nucleus forming step.

This substrate is subjected to electroless plating using Muden Noble PD (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.).

The plating was performed at a bath temperature of 55 ° C., and immersed in the solution until the layer thickness became 0.1 μm, thereby forming an a-Pd full surface plating film on the glass substrate.

At this time, other plating conditions were set such that the P content in the a-Pd plating layer was 8 wt%.

[0133] The plating film formed as described above is shown in FIG.
The film had a nearly amorphous film structure as seen in the cross-sectional TEM photograph of Photo 2 shown in FIG.

Next, a resist pattern is formed on the plating layer by using a photo process, and further immersed in an etching solution prepared at a ratio of 70% nitric acid: 35% hydrochloric acid: acetic acid = 9: 9: 1. , A heat resistance test, and a pattern for a resolution test.

The plating layer obtained as described above did not show film peeling even when subjected to a peeling test using a tape, and had good heat resistance and good resolving power. The test results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0020 μm, and the Ra of the glass substrate after the plating film was removed by etching was the same as the above value. . Example 2 A Pd-P plating film pattern was formed in the same manner as in Example 1 except that Corning Co., Ltd. product name # 7059 was used as the glass substrate.

The plating layer obtained as described above did not show film peeling even when subjected to a peeling test using a tape, and had good heat resistance and good resolving power. The test results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0013 μm, and the Ra of the glass substrate after removing the plating film by etching was the same as the above value. .

Example 3 As a glass substrate, H-coated glass manufactured by Nippon Sheet Glass having SiO ₂ coated on a blue sheet glass was used. Other conditions were the same as in Example 1 to form a pattern of the laminated film.

The plating layer obtained as described above did not show film peeling even when subjected to a peel test with a tape, and had good heat resistance and good resolving power. The test results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0025 μm, and the Ra of the glass substrate after the plating film was removed by etching was the same as the above value. .

Example 4 Using the same glass substrate as in Example 1, the same pretreatment as in Example 1 was performed on the substrate, and then a film having a thickness of 0.07 μm and a P content of 7 wt% was obtained. a-
A Pd plating layer was formed, and this was formed into a line pattern by using the same photo-etching process as in Example 1. Further, by electroplating, Cu was 5 μm and Ni was 3 μm.
Au and 0.03 μm of Au were laminated by displacement plating.

The results of the tensile test and the heat resistance test of the plating layer obtained as described above are good, and the results are shown in Tables 1 and 2.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0020 μm, and the Ra of the glass substrate after removing the plating film by etching was the same as the above value. .

Example 5 Using the same glass substrate as in Example 1, the same pretreatment as in Example 1 was performed on the substrate, and then a film having a thickness of 0.11 μm and a P content of 8 wt% was obtained. a-
A Pd plating layer was formed, and was formed into a line pattern by using the same photo-etching process as in Example 1.
3 μm of Ag and 1.5 μm of Au were laminated on this pattern by electroplating.

The results of the tensile test and the heat resistance test of the plating layer obtained as described above are good. The results are shown in Tables 1 and 2.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0027 μm, and the Ra of the glass substrate after the plating film was removed by etching was the same as the above value. .

(Example 6) Using the same glass substrate, pretreatment and plating solution as in Example 1, an a-Pd plating layer was formed as the first layer on the catalyst core layer. -Pd
A c-Pd plating layer containing neither phosphorus nor boron was formed on the plating layer.

The plating solution used herein is PARED (trade name) manufactured by Kojima Chemical Co., Ltd.
Was formed. A line pattern was formed on this laminated film using the same photo-etching process as in Example 1, and after cleaning, the film was held at the maximum temperature of 150 ° C. for 3 hours in the above-mentioned belt furnace.

At this time, the P content in the a-Pd plating layer was 8 wt%, the film thickness was 0.03 μm, and the film thickness of the c-Pd plating layer laminated thereon was 0.03 μm.

The laminated film is shown in Photo 1 shown in FIG.
Has a layered structure as seen in the cross-sectional TEM observation, and a P-depth profile analysis of the layered film using AES confirmed a P-gradient structure as shown in Graph-1.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

The average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0023 μm, and the Ra of the glass substrate after removing the plating film by etching was the same as the above value.

Example 7 A laminated film pattern was formed in the same manner as in Example 4 except that Corning's trade name # 7059 was used as the glass substrate.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0018 μm, and the Ra of the glass substrate after removing the plating film by etching was the same as the above value. .

Example 8 As a glass substrate, H-coated glass manufactured by Nippon Sheet Glass having SiO ₂ coated on a blue sheet glass was used. Other conditions were the same as in Example 6 to form a pattern of the laminated film.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0025 μm, and the Ra of the glass substrate after the plating film was removed by etching was the same as the above value. .

(Embodiment 9) Cu was deposited on a line pattern formed in the same manner as in Embodiment 6 by electroplating.
μm, 3 μm of Ni, and 0.03 μm of Au by displacement plating.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0022 μm, and the Ra of the glass substrate after the plating film was removed by etching was the same as the above value. .

(Example 10) Ag was applied to 3 μm and Au was applied to 1 μm on a line pattern having a laminated structure of a-Pd / c-Pd formed in the same manner as in Example 6.
m.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0017 μm, and the Ra of the glass substrate after the plating film was removed by etching was the same as the above value. .

(Example 11) The same pretreatment step and catalyst nucleus forming step as in Example 1 were applied to the same float blue plate glass substrate as in Example 1. As an electroless palladium plating solution for plating the entire surface of the substrate, an APP process manufactured by Ishihara Chemical Co., Ltd. was used. At this time, at a bath temperature of 50 ° C., a
-The glass substrate was plated until the Pd plating layer thickness became 0.06 µm. The P content in the a-Pd plating layer thus formed was 4 wt%.

Next, P was added to the a-Pd plating layer by adding 0.
A 0.1 μm c-Pd plating layer containing 07 wt% was laminated. An electroless Pd plating solution using ethylenediamine as a complexing agent and sodium phosphite as a reducing agent was used for this lamination, and the plating temperature was 67 ° C.

The P content in the plating film was 0.0
It was 8 wt%.

Then, a line pattern was formed by using the same photo-etching process as in the first embodiment.
Platinum was laminated by electroplating.

Examples of the electroplating solution include N.I. E. FIG. Using the product name Pt-270 manufactured by Chemcat, PH6.
3. Energization was performed at a bath temperature of 70 ° C. until the Pt film thickness became 0.1 μm.

Next, an annealing treatment was applied to the pattern plated substrate prepared as described above.

The annealing treatment is performed at a maximum temperature of 1 while constantly blowing fresh air to the substrate surface in a belt furnace.
The test was performed at 80 ° C. or lower.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0020 μm.

The Ra of the glass substrate after removing the plating film by etching was the same as the above value.

Example 12 The above-mentioned electroless palladium plating solution (trade name: PARED) manufactured by Kojima Chemical Co., Ltd. was c-P
A lamination and a pattern were formed under the same conditions as in Example 11 except that they were used for forming a d-plated layer.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0020 μm. Ra of the glass substrate after removing this plating film by etching
Were also the same as above.

Example 13 A laminated film pattern was formed under the same conditions as in Example 12 except that the above-mentioned product (trade name: # 7059) was used as a glass substrate.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0018 μm. Ra of the glass substrate after removing this plating film by etching
Were also the same as above.

Example 14 A laminated film pattern was formed under the same conditions as in Example 12, except that the above-mentioned Nippon Sheet Glass product (trade name: H-coated glass) was used as the glass substrate.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step was 0.0025 μm. Ra of the glass substrate after removing this plating film by etching
Were also the same as above.

(Embodiment 15) The electric C was also applied on the entire plating of a-Pd formed on the substrate in the same manner as in Embodiment 1.
u plating was laminated on the entire surface. After the laminated film was formed into a line pattern by using a photo-etching process, Ni was laminated by 3 μm by electroplating and Au was laminated by 0.03 μm by displacement plating.

The evaluation results of the plating layers obtained as described above are good, and the results are shown in Tables 1, 2 and 3.

At this time, the average surface roughness Ra of the glass substrate at the end of the degreasing step is 0.0023 μm, and the Ra of the glass substrate after removing the above-mentioned laminated plating film by etching is the same as the above value. there were.

Comparative Example 1 The same glass substrate as in Example 1 was subjected to the same degreasing treatment, and the substrate was immersed in a hydrofluoric acid solution to reduce the surface roughness Ra of the glass substrate to 0.41 μm.
m. This roughened substrate was subjected to the same catalyst nucleus forming treatment as in Example 1, and electroless Ni-P alloy plating using sodium hypophosphite as a reducing agent was formed thereon.

At this time, the plating film thickness was 0.7 μm, and the P content was 8 wt%.

Next, a desired pattern was formed on this substrate by using the same photo-etching process as in the first embodiment.

In the plating layer obtained as described above, in the peeling test using a tape, film peeling was 1% of the test area.
Within, evaluation results were normal. In addition, a large number of film peelings occurred after the heat test, and the evaluation result was poor. Similarly, in the patterning test, many pattern disconnections occurred, and the evaluation result was poor. The evaluation results are shown in Tables 1, 2 and 3.

(Comparative Example 2) Ni-P formed in Comparative Example 1
5 μm Cu, N
i was laminated at 3 μm, and Au was laminated at 0.03 μm.

A tensile test of the plating layer obtained as described above showed that the average tensile strength was 0.3 kg.
/ 2mm □, and the evaluation result was poor.

After the heat resistance test, a large number of film peelings occurred, and the evaluation results were poor.

Further, in the patterning test, a large number of pattern breaks occurred, and the evaluation result was poor. The evaluation results are shown in Tables 1, 2 and 3.

(Comparative Example 3) Except that the roughening treatment of the substrate with hydrofluoric acid was omitted, 0.4 μm N
After an i-P plating film was formed and subjected to the same patterning treatment, electric Cu plating and electric Ni plating were laminated in the same manner as in Example 3, and the pattern was a glass substrate and a Ni-P plating film. , And the evaluation test as described above could not be performed.

The above embodiment is merely an example of the glass circuit board having the plated wiring manufactured based on the present invention, and the present invention is not limited to the above specific embodiment. Of course, various modifications are possible within the technical scope of the present invention.

[0198]

[Table 1]

[0199]

[Table 2]

[0200]

[Table 3]

[0201]

As shown in the present invention, the first palladium-based catalyst nucleus provided on the glass substrate is used.
By forming an a-Pd plating layer containing a certain amount of P as a layer to an appropriate thickness, a plating layer having sufficient adhesion can be formed without performing extreme roughening treatment on the glass substrate. it can.

Further, by laminating a c-Pd plating layer close to the crystallinity on the a-Pd layer, a Pd plating laminated film in which the P content changes gradiently can be formed.
Even when forming thick thin lines on a smooth glass substrate,
It is possible to produce a metallized glass substrate having wiring / electrodes formed by wet plating and having both film stability and adhesion.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a metallized glass substrate having a layer configuration shown in Embodiments 1, 2, and 3 of the present invention.

FIG. 2 is a schematic sectional view of a metallized glass substrate having a layer configuration shown in Example 4 of the present invention.

FIG. 3 is a schematic sectional view of a metallized glass substrate having a layer configuration shown in Embodiment 5 of the present invention.

FIG. 4 is a schematic cross-sectional view of a metallized glass substrate having a layer configuration shown in Examples 6, 7, and 8 of the present invention.

FIG. 5 is a schematic sectional view of a metallized glass substrate having the layer configuration shown in Examples 9 and 15 of the present invention.

FIG. 6 is a schematic sectional view of a metallized glass substrate having a layer configuration shown in Embodiment 10 of the present invention.

FIG. 7 shows Embodiments 11, 12, and 1 of the present invention.
FIG. 3 is a schematic cross-sectional view of a metallized glass substrate having the layer configuration shown in Example 14.

FIG. 8 is a schematic sectional view of a metallized glass substrate having a layer configuration shown in Comparative Example 1 of the present invention.

FIG. 9 is a schematic sectional view of a metallized glass substrate having a layer configuration shown in Comparative Example 2 of the present invention.

FIG. 10 is a schematic cross-sectional view of a metallized glass substrate having a layer configuration shown in Comparative Example 3 of the present invention.

FIG. 11 is a diagram illustrating a method of laminating a plating layer of the present invention on a float glass (blue sheet glass) and subjecting it to an appropriate heat treatment, and analyzing the film by Auger electron spectroscopy (AES). It is a figure showing the result of having investigated distribution intensity.

FIG. 12 is a diagram showing an example of a metal structure of a cross section of a substrate having an a-Pd plating layer and a c-Pd plating layer formed on one surface of a blue sheet glass manufactured by a float method, which is obtained by TEM.

[FIG. 13] An a-Pd plating layer is formed on one surface of a blue sheet glass manufactured by a float method, and the cross section is observed by TEM.
FIG. 5 is a diagram showing an example of a metal structure obtained as a result of the above.

FIG. 14 shows a prior art roughened glass substrate (surface roughness R
a: 0.4 μm) is a diagram showing a metal structure by a SEM photograph of a glass circuit board patterned by applying a 0.1 μm-thick Ni—P plating on the top of the glass circuit board.

FIG. 15 is a diagram showing a glass obtained by subjecting a glass substrate (surface roughness Ra: 0.002 μm) whose surface has not been roughened according to the present invention to a-Pd plating with a thickness of 0.1 μm and patterning the same. FIG. 3 is a diagram showing a metal structure of a circuit board by an SEM photograph.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Catalyst core layer 3 Non-crystalline palladium plating layer 4 Copper plating layer 5 Nickel plating layer not containing phosphorus 6 Gold plating layer 7 Crystalline palladium plating layer 8 Silver plating layer 9 Platinum plating layer 10 Nickel containing phosphorus Plating layer a Blue sheet glass b Catalyst core layer c a-Pd plating layer d c-Pd plating layer

Claims (15)

[Claims] 1. A glass circuit board comprising: a catalyst core layer made of metal Pd formed on a glass substrate; and an amorphous Pd-P plating layer formed on the catalyst core layer. 2. The glass circuit board according to claim 1, wherein the thickness of the amorphous Pd-P plating layer is 0.015 to 0.500 μm. 3. The amorphous Pd-P plating layer,
The glass circuit board according to claim 1, wherein the content of phosphorus is 3.0 to 10.0 (wt%). 4. The method according to claim 1, wherein the plating layer is formed of Cu, Ni, Ni-
1 selected from P, Ag, Pd, Pd-P, Au, Pt
2. The glass circuit board according to claim 1, wherein the glass circuit board is made of at least one kind of metal or at least two kinds of alloys. 5. A catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, a Cu plating layer, a Ni plating layer, and Au plating The glass circuit board according to claim 4, comprising a layer. 6. A catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, an Ag plating layer, and an Au plating layer. The glass circuit board according to claim 4, wherein: 7. It has a catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, and a crystalline Pd-P plating layer. The glass circuit board according to claim 4, wherein: 8. A catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, a crystalline Pd-P plating layer, and a Cu plating layer The glass circuit board according to claim 4, comprising: a Ni plating layer; an 8Ni plating layer; and an Au plating layer. 9. A catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, a crystalline Pd-P plating layer, and an Ag plating layer The glass circuit board according to claim 4, comprising: an Au plating layer. 10. A catalyst core layer made of metal Pd formed on a glass substrate, an amorphous Pd-P plating layer formed on the catalyst core layer, a crystalline Pd-P plating layer, and a Pt plating layer The glass circuit board according to claim 4, comprising: 11. The crystalline Pd—P layer has a thickness of 0.
The glass circuit board according to claim 4, wherein the thickness is from 015 to 0.250 µm. 12. The method according to claim 7, wherein at an interface between the amorphous Pd-P plating layer and the crystalline Pd-P layer, crystallinity is inclinedly changed. Glass circuit board. 13. The c-Pd from the a-Pd plating layer.
The glass circuit board according to claim 12, wherein the glass circuit board has a film structure in which the content of P in the plating layer decreases while being continuously inclined. 14. The film thickness of the c-Pd plating layer is set to 0.1.
8. The structure according to claim 7, wherein the thickness is from 015 to 0.25 [mu] m.
14. The glass circuit board according to any one of items 13 to 13. 15. The c-Pd plating layer has a phosphorus content of 0 to 1 (wt%).
15. The glass circuit board according to any one of items 14 to 14.