JPH1012849A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the auto placement and routing of a signal wire, etc., by reducing the number of power source wires among respective cell rows as well as to realize stabilized circuit operation by shortening the layout distance in the row arrangement direction of a counter circuit, etc., even when the auto placement and routing is performed. SOLUTION: This device is formed by arranging a plurality of unit element areas 1 in parallel vertically and horizontally that are comprised on a PMOS area (P) where a P type MOS transistor is formed in advance and an NMOS area (N) where an N type MOS transistor is formed, and a wiring layer connecting the unit element areas 1 is formed at any time so as to obtain a desired integrated circuit. The unit element area 1 has a plurality of cell rows which are arranged in parallel so that the PMOS area may be formed on the side of power source voltage line (VDD) for supplying power to the MOS transistor and the NMOS area be formed on the side of reference potential line (GND), and the respective cell rows are arranged approximately symmetrical with respect to the power source voltage line or reference potential line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a structure of a semiconductor integrated circuit device called a gate array or an embedded array.

[0002]

2. Description of the Related Art In order to form a relatively small amount of semiconductor integrated circuit devices in a short period of time and at a low cost, generally, an A
SIC (Application Specific Integrated Circuit)
In many cases, a semiconductor integrated circuit device called a gate array or an embedded array based on technology is used.

The gate array prepares a circuit library of wiring layers having data such as layout patterns of gate circuits and functional circuits in advance and prepares a semiconductor chip (hereinafter referred to as a "chip") in which only a common layer before a wiring step is formed. A semiconductor integrated circuit device having a desired circuit function by performing a process after the wiring layer using the base chip when an application circuit is determined, which is referred to as a “base chip” (also referred to as a “master”). You can get. Therefore, a semiconductor integrated circuit device having a different circuit can be easily obtained using the same base chip, and the manufacturing time after the circuit is determined is greatly reduced as compared with a case where the semiconductor chip is formed from the first step. It can be shortened. Further, since the mask used for forming the base chip can be commonly used, the manufacturing cost can be reduced.

On the other hand, in the embedded array, a circuit library having data such as a layout pattern of a large-scale circuit such as a CPU and a memory and an evaluation result thereof is prepared in advance, and a gate array is formed as a region for forming a random logic circuit. The semiconductor integrated circuit device can be easily formed by combining libraries of necessary functions. Therefore, the time required for circuit design and evaluation can be greatly reduced as compared to designing and evaluating all circuits, and the degree of circuit integration can be increased as compared with the gate array, so that the chip area of the semiconductor chip can be reduced. As a result, the yield of semiconductor chips can be improved and the unit price can be reduced.

As described above, in the ASIC as described above,
Circuit libraries having various basic circuit layout data and evaluation results are prepared in advance, and by using this circuit library, required circuit operations can be easily verified using a simulation device,
The verified circuit can be automatically converted into a layout pattern using an automatic placement and routing apparatus.
If a mask is created using the data of the automatic placement and routing and a semiconductor integrated circuit device is formed by a general CMOS manufacturing method using the mask, a desired circuit can be obtained in a short period of time and at low cost. . However, with the current automatic placement and routing, the wiring length is often long and the wiring efficiency is not very good, and the operation as simulated cannot be performed due to the increase in wiring resistance and wiring capacitance and the delay time difference in the signal. Was.

The gate array will be further described with reference to FIGS. FIG. 4 is a layout diagram for explaining the overall arrangement thereof, and FIG. 5 is a layout explanatory diagram showing an arrangement of basic cells in a circuit region therein and a circuit example using the same. In FIG. 4, the power supply voltage line (VDD) is used for explanation.
Only the pattern of the main part of the reference potential line (GND) is shown in FIG. 5, and the wiring is schematically shown in FIG.

The gate array 10a shown in FIG. 4 has a plurality of input / output (I / O) units 3 formed on the periphery of a semiconductor chip.
And an internal circuit area 2a formed on the inside thereof. The input / output unit 3 is provided with electrode pads 3a for connecting signals to lead terminals (not shown) of the semiconductor integrated circuit device. The circuit region 2a has a configuration in which a plurality of unit element regions (hereinafter, referred to as “basic cells”) 1 that are basic transistor devices are arranged between power supply lines including a power supply voltage line and a reference potential line.

Then, the basic cell 1 has a P
N-type MOS on the PMOS region (P) where the MOS transistor of the type is formed and the P-well shown by oblique lines falling to the lower right
And a plurality of NMOS regions (N) in which transistors are formed, and are arranged in plural numbers in the horizontal direction of the drawing (hereinafter, this arrangement direction is referred to as “row direction”) (hereinafter, “cell row arrangement”).
). Further, in the vertical direction of the drawing (hereinafter, this arrangement direction is referred to as “column direction”), each MOS transistor region in the cell row is arranged from the upper side to PNPNPNP.
N are repeatedly arranged in the same direction (hereinafter, referred to as “cell row arrangement”).

The basic cell 1 in the internal circuit region shown in FIG. 5A has a PMOS region 1a and a NMOS region 1b serving as a source / drain of a MOS transistor as shown in the layout of a base chip below the diagram. And polysilicon 1c used as a gate or wiring of two MOS transistors formed on a pair of the PMOS region 1a and the NMOS region 1b is formed between power supply lines. Then, as shown on the upper side of FIG. 5A, by forming a first-layer wiring shown by a solid line or a second-layer wiring shown by a dotted line and a contact (connection hole) shown by a black dot (•), Arbitrary circuits can be formed by connecting wiring layers or between each wiring layer and each MOS region.

FIG. 5A shows a circuit diagram of a transistor level shown in FIG. 5B, and FIG. 5C shows a layout of a CMOS inverter circuit as shown in a symbol diagram. In this inverter circuit, a PMOS transistor 1e and an NMOS transistor 1f are connected in series between a power supply voltage line and a reference potential, and four minimum inverter circuits whose gates are commonly connected are connected in parallel.
One large current inverter circuit is formed.

[0011]

In a conventional gate array, embedded array, or the like, all the basic cells 1 are arranged in a plurality in the same direction, and a power supply voltage line is provided above and below the cell row arrangement. And the reference potential lines are arranged, so that the number of power supply lines in the internal circuit area increases, so that a large number of wirings cannot be taken between the cell rows and the basic cells 1 can be arranged at high density. was difficult.

When a circuit such as a counter circuit is formed by automatic placement and routing, the circuits are often arranged using basic cells arranged in the same row, and the row arrangement of the circuits tends to be long. , The position of the lower stage counter output and the upper stage counter output becomes farther, the wiring distance of each output becomes longer, the wiring resistance and the wiring capacitance increase,
In some cases, a delay time difference occurs between the signals on the respective signal lines, resulting in an unexpected mustache-like pulse signal.

Therefore, the present invention solves these problems and makes it easy to automatically arrange and wire signal lines and the like by making it possible to reduce the number of power supply lines between each row of cells.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of performing a stable circuit operation by shortening a layout distance of a counter circuit or the like in a row arrangement direction even when automatic placement and routing is performed.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device, comprising:
A PMOS region (P) in which a P-type MOS transistor is formed in advance and an NMO in which an N-type MOS transistor is formed
A plurality of unit element regions 1 each including an S region (N) are formed in parallel in a matrix, and a semiconductor layer for obtaining a desired integrated circuit by forming a wiring layer connecting the unit element regions 1 as needed. In the integrated circuit device, a plurality of unit element regions 1 are arranged in parallel such that a PMOS region is formed on a power supply voltage line (VDD) side for supplying power to a MOS transistor and an NMOS region is formed on a reference potential line (GND) side. And the cell rows are arranged substantially line-symmetrically with respect to a power supply voltage line or a reference potential line.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device according to the first aspect, wherein a part of a gate circuit or a functional circuit used in the integrated circuit is arranged line-symmetrically. It is characterized by comprising a plurality of unit element regions 1. With the configuration of the semiconductor integrated circuit device according to the present invention, the number of power supply lines between each cell row is reduced, so that it is easy to automatically arrange and route signal lines and the like, and to perform automatic arrangement and wiring. However, the layout distance of the counter circuit and the like in the row arrangement direction is shortened, and the length of the signal line can be shortened.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
This will be described in detail with reference to FIG. 1 and 2 show a layout example of a gate array as a first embodiment of the present invention, and FIG. 3 shows a layout example of an embedded array as a second embodiment of the present invention. In the present specification, the same or similar circuit elements are denoted by the same reference numerals throughout the drawings to simplify the description.

First, a first embodiment will be described.
FIG. 1 is a layout diagram for explaining the overall layout of a semiconductor integrated circuit device 10 having a gate array configuration, and FIG. 2 is a layout explanatory diagram showing the layout of basic cells 1 in an internal circuit area 2 and an example of a circuit library using the same. As in the description of the related art, FIG. 1 illustrates only patterns of main parts of a power supply voltage line and a reference potential line for description, and FIG. 2 schematically illustrates a wiring layer.

This embodiment differs from the configuration of the prior art in that the cell arrangement in the internal circuit region 2 is arranged so as to be substantially line-symmetric with respect to the power supply line, and each MOS transistor region is arranged from the upper side as PNPNPPNNP. .. And the P wells of the two NMOS regions are combined into one. Therefore, only one of the power supply voltage lines or the reference potential lines is provided between the cell rows, so that the number of power supply lines is reduced by half as compared with the prior art, and the internal circuit is reduced. Since the width of the P-well and the semiconductor substrate in the region 2 is increased and the count value of the sheet resistance is reduced, the number of contacts for biasing the P-well and the semiconductor substrate to a predetermined potential can be reduced.

Since such a cell array arrangement is used, the basic cells 1 can be arranged at a higher density when it is desired to secure the same wiring area as in the prior art, and the inverter circuit shown in FIG. When a circuit library of a wiring layer is formed, as shown in FIG. 2, an efficient circuit library is formed by laying out using two basic cells 1 symmetrically opposed with respect to a reference potential line. become able to. In particular, an open drain output circuit using a large number of PMOS or NMOS only,
Alternatively, when laying out a gate circuit or the like set to a special input threshold voltage by changing the number of NMOSs used, it is preferable to use two basic cells 1 symmetrically opposed with respect to the power supply line. Can shorten the total wiring distance. Furthermore, if a desired circuit is formed by using such a circuit library, the number of power supply lines between the signal lines and the like can be reduced, so that the wiring with the second wiring layer can be easily performed. Placement and wiring becomes easy. Although a circuit library can be laid out using two cell rows even in a conventional gate array having cell rows, the present embodiment has a smaller number of power supply lines, and accordingly, wiring is easier. ing.

Further, if the flip-flop circuit and the like are constituted by using a plurality of basic cells 1 arranged in line symmetry, the layout distance between the input and the output can be made shorter than before. Therefore, the position of the lower stage counter output such as the counter circuit using a large number of flip-flop circuits and the position of the upper stage counter output can be easily brought close to each other, and the delay time difference between each output signal is reduced. A stable circuit operation can be performed.

Next, another embodiment of the present invention will be described. The semiconductor integrated circuit device 20 shown in FIG. 3 includes a central processing unit (CPU) unit 21 for controlling operation according to a program, and a ROM for storing a program, data, and the like.
, A memory array provided with storage elements such as a RAM, a gate array unit 23 having the same configuration as the internal circuit area 2 of the first embodiment, and an input / output (I / O) for inputting / outputting signals of each circuit. 1 shows an embedded array type one-chip microcomputer including an I / O section 24.

With such a configuration, a one-chip microcomputer in which peripheral random circuits are incorporated into the gate array unit 23 and external components are reduced can be designed in a short time, and the evaluation time can be shortened. Therefore, development costs can be reduced by shortening the development time. Further, by reducing the number of external components, it is possible to greatly reduce the costs for purchasing and managing the components, and the accompanying costs due to the reduction of the circuit board for mounting the components.

It should be noted that the present invention is not limited to the above-described embodiment, and can be used not only for a CMOS structure using an N-type semiconductor substrate but also for forming a substantially uniform structure in an internal circuit region. Basic cells may be spread to form a gate array of a whole-surface spread type. Further, a basic cell having a configuration in which independent polysilicon is provided above the PMOS region and the NMOS region may be used as a gate, or a gate array using a wiring layer having more than two layers may be used. Further, instead of forming all circuit libraries using two basic cells which are symmetrically opposed to each other with respect to the power supply line, a circuit library using only one cell row similar to the related art is formed. The circuit libraries may be used in combination according to the circuit scale and purpose.

[0024]

As described above, the configuration of the semiconductor integrated circuit device according to the present invention makes it possible to reduce the number of power supply lines between the cell rows and to reduce the number of signal lines and the like. Since the automatic placement and routing becomes easy, there is an effect that the wiring efficiency and the use efficiency of the basic cell at the time of the automatic placement and routing can be improved. In addition, even when automatic placement and routing is performed, the layout distance in the row arrangement direction of the counter circuit and the like can be shortened, so that the total wiring distance of the circuit is shortened, the wiring resistance and the wiring capacitance are reduced, and the signal of each wiring is reduced. The delay time difference is reduced, and unnecessary signal output is reduced due to the delay time difference, so that a stable circuit operation can be performed.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an embodiment of the present invention;

FIG. 2 is a layout explanatory view showing an example of arrangement of basic cells according to the present invention;

FIG. 3 is a layout diagram showing another embodiment of the present invention;

FIG. 4 is a layout diagram showing an arrangement of a conventional semiconductor chip;

FIG. 5 is an explanatory view of a layout showing an example of a conventional arrangement of basic cells.

[Explanation of symbols]

 1: Basic cell 1a: P-type MOS transistor (PMOS) region 1b: N-type MOS transistor (NMOS) region 1c: Gate (polysilicon) 1d: P well (region) 2: Internal circuit region 3: Input / output region (I / O region) 3a: electrode pad 10: semiconductor chip (gate array) 20: semiconductor chip (embedded array)

Claims (2)

[Claims] A plurality of unit element regions each including a PMOS region in which a P-type MOS transistor is formed and an NMOS region in which an N-type MOS transistor is formed are previously formed in parallel in a matrix, and the unit region is formed as needed. In a semiconductor integrated circuit device for obtaining a desired integrated circuit by forming a wiring layer connecting the unit element regions, the unit element region is provided with a power supply voltage line for supplying power to the MOS transistor. A plurality of cell rows are arranged in parallel so that a region is formed and the NMOS region is formed on the side of the reference potential line. The cell row is arranged with respect to the power supply voltage line or the reference potential line. A semiconductor integrated circuit device which is arranged substantially symmetrically with respect to a line. 2. The semiconductor integrated circuit according to claim 1, wherein a part of a gate circuit or a functional circuit used in the integrated circuit is configured by using a plurality of the unit element regions arranged in line symmetry. apparatus.