JPH10107866A - Data receiver and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a receiver to decode data which are received resulting from performing bit spread processing to a convolution code series and 16QAM system digital modulation, using a convolutional code. SOLUTION: Data I', B' outputted from a symbol inverse spread circuit 33 are given to bit inverse spread circuits 101-1 to 101-4, where bit inverse spread processing is applied to 1st to 4th bits of 16QAM data while keeping a coordinate of each symbol. The result is given to metric calculation circuits 102-1 to 102-4, where a metric corresponding to each bit is calculated. A Viterbi decoder 103 apples Viterbi decoding to metric data and provides an output of recovery information 38.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus and method, and more particularly to a data receiving apparatus and method, wherein a punctured code is used as an error correction code, bit spreading is performed on a code sequence, and a multi-level multi-phase method is used. The present invention relates to a data receiving apparatus and method capable of receiving and decoding data which has been digitally modulated and transmitted.

[0002]

2. Description of the Related Art Digital broadcasting has already begun in the United States. In Europe, Digital Video Broadcasti is a standards organization to introduce digital television broadcasting.
ng (DVB) has been formed and its standard method is being finalized. Regarding this digital broadcasting, for example, Nikkei Electronics 1996.1.15 (No. 653)
Pages 139 to 151 introduce "Digital Broadcasting, Practical Use in Europe After the United States".

[0003] In the case of digital broadcasting, it is desired to reduce the power consumption as much as possible. In such a communication channel with severe power restrictions, generally, an attempt is made to reduce power by obtaining a coding gain using an error correction code. In such a system, it is common to perform error correction coding on the transmission side and perform error correction decoding on the reception side. In particular, a convolutional code is advantageous in a communication channel having a small signal power-to-noise power ratio (C / N ratio). This code can easily perform soft decision decoding by using the Viterbi decoding method. Gain can be obtained.

Further, a punctured code which can easily realize a plurality of coding rates by using the same decoder by thinning out a sequence of code outputs of a convolutional encoder according to a certain rule is known. ing. Also, by spreading the code output sequence of the punctured encoder for each bit in accordance with a certain rule, it is possible to improve the resistance to noise superimposed on the transmission path.

FIG. 11 shows an example of the configuration of a transmitter proposed in the standard DVB-T for DVB terrestrial television broadcasting. In this apparatus, a punctured convolutional code, bit spreading, and QPSK modulation are used.

That is, in the example shown in FIG. 11, 1-bit serial data output from the information source 1 is input to the convolutional encoder 2 to generate punctured code mother code sequences X and Y. In this example, the coding rate is １ ／. X and Y each represent a 1-bit code sequence.

The code series X and Y are transmitted to the bit erase circuit 3
, And a bit erasure process is performed according to a predetermined rule. The serialized punctured code sequence output from the bit erasure circuit 3 is input to the serial-to-parallel converter 4 and is converted from one series of data to two series of data.

The two series of data x and y output from the serial / parallel converter 4 are input to bit spreading circuits 5-1 and 5-2, respectively, and are subjected to bit spreading processing in which the bit order is spread (interlaced). Has been made to be done. Bit-spread data x 'and y' output from bit spreading circuits 5-1 and 5-2 are input to signal point assignment circuit 6 and assigned to symbols on the transmission path. The signal point assignment circuit 6 outputs coordinate data I 'and Q' of a signal point represented by an in-phase component (I component) and a quadrature component (Q component) which are orthogonal to each other.

The symbol spreading circuit 7 performs a symbol spreading process for spreading the order of the symbols defined by the coordinate data I 'and Q' output from the signal point allocating circuit 6, and outputs the I component of the spread symbol and the I component. Output the Q component. The modulator 8 is, for example, an OFDM (Orthogonal Frequency Divisi).
On Multiplex), the I component and the Q component are digitally modulated and output as radio waves via the antenna 9.

FIG. 12 shows an example of the configuration of the convolutional encoder 2. However, this configuration example is not defined by DVB-T, but shows a basic configuration for explaining the convolution processing. In this example, the 1-bit serial data output from the information
, And 1 by the delay circuits 22 and 23, respectively.
After being sequentially delayed by the clock, adders 24 and 25
Is output to The output of the terminal 21 and the output of the delay circuit 22 are also supplied to the addition circuit 24, and the addition circuit 24 adds these data (exclusive OR operation).
After that, the data is output from the terminal 26 as data X. The addition circuit 25 adds the output of the terminal 21 and the output of the delay circuit 23 (exclusive OR operation), and
The data is output from the terminal 27 as data Y.

That is, in this embodiment, a 2-bit mother code determined from the internal states of the delay circuits 22 and 23 is output for a 1-bit input. In this example, the constraint length is 3, the number of internal delay elements is 2, the number of states is 4, and the coding rate is 1/2.

FIG. 13 shows a state transition diagram of the convolutional encoder 2. The state transition of the convolutional encoder 2 is as follows.

That is, for example, state 00 (delay element 2
In the state where both the output 2 and the output of the delay element 23 are 0), when 0 is input from the terminal 21, (XY) = (00) is output from the terminals 26 and 27, and the state transits to the state 00. When 1 is input from the state 00, (XY) = (1
1) is output, and the state transits to 10. When 0 is input from the state 01, (XY) = (11) is output, and the state transits to the state 00. When 1 is input from state 01,
(XY) = (00) is output, and the state transits to the state 10.

In other states, as shown in FIG. 13, the input shown in FIG. 13 is output in response to the input of 0 or 1, and the state transits to the illustrated state.

The bit erasing circuit 3 can change the coding rate by erasing data at an appropriate position from the mother code sequence (XY) according to a certain rule. Hereinafter, a case where bits are erased according to an erase map such as X: 10 Y: 11 will be described.

The bit corresponding to 1 in the erasure map is transmitted, and the bit corresponding to 0 is not transmitted (erased). According to the erasure map, the outputs X (= X1) and Y (= Y1) of the convolutional encoder 2 at a certain point in time are X1Y1
At the next point, the output X (= X2) of the convolutional encoder 2 is deleted and not transmitted, and Y (= Y
Only 2) will be transmitted. That is, the bits transmitted at these two times are X1Y1Y2. With this operation, the number of bits input to the convolutional encoder 2 is 2 bits, and the number of bits output from the bit erasure circuit 3 is 3 bits, so that the coding rate R is 2/3. This operation is repeated every two unit times.

The serial-parallel converter 4 converts the input one-series data X1, Y1, Y2,... Into two-series data (x, y).

The bit spreading circuits 5-1 and 5-2 spread bits by changing the order of the input data series x and y according to a predetermined rule. At this time, the spreading method of the bit spreaders 5-1 and 5-2 is generally different.

The following is an example of bit spreading. An M-bit input data is defined as one block, and an appropriate numerical value s is determined.
The bit spreading is performed from a vector (B0, B1,..., Bk,..., BM-1) consisting of an M-bit input sequence to a vector (B'0, B) consisting of an M-bit output sequence after spreading. '1, ..., B'n, ..., B'M-
Means substitution to 1). At this time, B′n = Bk (n
= K + s mod M).

Different s for the bit spreading circuits 5-1 and 5-2
, Different bit spreading circuits can be configured with the same algorithm.

The signal point allocating circuit 6 allocates the input data (x ', y') to symbols on the transmission path. The allocation is performed, for example, as shown in FIG.
It is performed according to the method. That is, when (x ′, y ′) = (0, 0), (I ′, Q ′) =
(1 / √2, 1 / √2), (x ′, y ′) = (0, 1), and (I ′, Q ′) =
(1 / √2, -1 / √2), When (x ′, y ′) = (1, 0), (I ′, Q ′) =
(−1 / √2, 1 / √2), (x ′, y ′) = (1, 1), and (I ′, Q ′) =
The assignment is performed as (−1 / √2, −1 / √2).

The symbol spreading circuit 7 spreads the symbols by changing the order of the symbols S 'represented by (I', Q ') according to a predetermined rule, and obtains the symbols S (I, Q). Thus, a burst-like error received on the transmission path can be spread.

To show a specific example (different from DVB-T), when N-1 symbols are used as a spreading unit block and a number G less than N and relatively prime to N is determined, the spreading is , A vector (S′1,
.., S′k,..., S′N−1), vectors (S1, S2,.
.., Sn,..., SN-1). At this time, Sn = S'k (n = G ＾ k mod N)
It is.

In the modulator 8, the I of the input symbol S
The carrier is modulated according to the component and the Q component, and transmitted via the antenna 9.

FIG. 15 shows an example of the configuration of a receiving device that receives data transmitted from the transmitting device of FIG. The demodulator 32 demodulates a radio wave received via the antenna 31 and outputs an I component signal and a Q component signal. The symbol despreading circuit 33 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 11, that is, a process of returning the order of the symbols exchanged in the symbol spreading circuit 7 to the original order, and the I signal component I ′. And a Q signal component Q ′.

The bit despreading circuits 34-1 and 34-2 are
The I ′ signal and Q ′ output from the symbol despreading circuit 33
For the signal, bit spreading circuits 5-1 and 5-2 shown in FIG.
The process of returning the order of the bits changed in to the original order is executed.

The data x corresponding to the I 'signal component and the data y corresponding to the Q' signal component output from the bit despreading circuits 34-1 and 34-2 are input to the parallel / serial converter 35, The series data (x, y) is converted into one series of data and supplied to the bit insertion circuit 36.

In the bit insertion circuit 36, a bit insertion process is performed in a manner opposite to the bit erasure process in the bit erasure circuit 3 in FIG. By the bit insertion circuit 36,
The data x of the I signal component and the data y of the Q signal component into which the bits have been inserted are input to a Viterbi decoder 37, Viterbi-decoded, and output as reproduction information 38.

Next, the operation will be described.

The received signal received by the antenna 31 is demodulated by the demodulator 32, and data of the I component and the Q component of each symbol is obtained. The data of the I component and the Q component is input to the symbol despreading circuit 33, where the operation reverse to that in the symbol spreading circuit 7 is performed to obtain despread data I 'and Q'.

That is, this despreading operation is represented by using the same values N and G as those used in the symbol spreading circuit 7, and the vector (S1,
S2,..., Sn,..., SN-1) are converted into vectors (S′1, S′2,.
.., S′k,..., S′N−1). At this time, Sn = S'k (n = G ＾ k mod N)
It is.

I supplied from the symbol despreading circuit 33
The component data I ′ and the Q component data Q ′ are supplied to bit despreading circuits 34-1 and 34-2, respectively.

The bit despreading circuits 34-1 and 34-2 are
They correspond to the bit spreading circuits 5-1 and 5-2, respectively, and perform operations opposite to those of the bit spreading circuits 5-1 and 5-2, respectively.

That is, M input data is taken as one block, an appropriate numerical value s is determined, and a vector (B'0, B'1,..., B'n,. ,
B′M−1), a vector (B0, B1,..., Bk,.
1) is required. At this time, B'n = Bk (n = k + s mod M).

Here, the bit despreading circuits 34-1 and 34-1
As the numerical value s used in the bit despreading of −2, the same value as the numerical value s used in the bit spreading circuits 5-1 and 5-2 is used.

The data sequence (x, y) thus bit-despread is supplied to the next-stage parallel-serial converter 35, where the operation reverse to that of the serial-parallel converter 4 is performed, and the two-sequence data (x , Y) is converted into a series of data.

In the bit insertion circuit 36, an operation reverse to that of the bit erasure circuit 3 is performed. That is, in response to the processing of the bit erasure circuit 3 using the erasure map X: 10 Y: 11 in the above-described example, the bit insertion circuit 36 performs the following operations: X1, Y1, Y2 (in this case, x1, y1, y2) , Arbitrary dummy data (here, 0) is inserted at a position corresponding to the erased data X2 (x2), and X data is obtained as X data.
Let 1 (x1), 0 be Y data, and Y1 (y1), Y
2 (y2) are output in this order. Further, an insertion flag indicating the position where the dummy data is inserted is supplied to the Viterbi decoder 37.

The Viterbi decoder 37 performs Viterbi decoding according to the state transition of the convolutional encoder 2 (FIG. 13). FIG. 16 shows an example of the Viterbi decoder 37. Input terminal 62-
Data X and Y output from the bit insertion circuit 36 are input to 1, 62-2, respectively. These data X and Y are supplied to branch metric operation circuits 63-1 to 6-6.
3-4. The branch metric calculation circuit 63-1 calculates the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) shown in FIG. 14 as a branch metric. Similarly, in the branch metric calculation circuits 63-2 to 63-4, the input data (X, Y) and the coordinate points (1 / √2, -1 / √2),
(-1 / √2, 1 / √2) or (-1 / √2, -1 /
√2) is calculated.

Branch metric operation circuits 63-1, 6
The output (branch metric) BM00 of 3-4 is AC
It is input to an S (Add Compare Select) circuit 64-1. Similarly, the output (branch metric) BM01 of the branch metric calculation circuit 63-2 and the output (branch metric) BM of the branch metric calculation circuit 63-3
10 is input to the ACS circuit 64-2, and the output (branch metric) of the branch metric calculation circuit 63-1
The output (branch metric) BM11 of the BM00 and the branch metric calculation circuit 63-4 is converted to the ACS circuit 64-
3, the output (branch metric) BM01 of the branch metric calculation circuit 63-2 and the output (branch metric) B of the branch metric calculation circuit 63-3
M10 is input to the ACS circuit 64-4.

The output (state metric) SM00 of the state metric storage device 66-1 and the output (state metric) SM01 of the state metric storage device 66-2 are input to the ACS circuit 64-1. The output (state metric) SM10 of the state metric storage device 66-3 and the output (state metric) SM11 of the state metric storage device 66-4 are input to -2. Similarly, AC
The S circuit 64-3 includes a state metric storage device 66.
The output (state metric) SM00 of the state metric storage device 66-3 and the output (state metric) SM01 of the state metric storage device 66-2 are input to the ACS circuit 64-4. ) SM10 and the output (state metric) SM11 of the state metric storage device 66-4 are input.

The ACS circuits 64-1 to 64-4 add the input one branch metric BM and the corresponding state metric SM, and also add the other branch metric BM and the corresponding state metric SM. Then, the two addition results are compared, and in accordance with the comparison result, the smaller addition value is output to the state metric storage devices 66-1 to 66-4 as a new state metric SM, and the selection result is output. Are output to the path memory 65. The path memory 65 also has
State metrics SM00 to SM1 stored in state metric storage devices 66-1 to 66-4
1 has been entered.

The state metric storage devices 66-1 to 66-4 are reset by a signal input from a terminal 61. The path memory 65 outputs the decoding result from the terminal 67.

Next, the operation will be described.

In the branch metric calculation circuit 63-1, the input data (X, Y) and the coordinate point (1 / {2,1 /})
2) is calculated as the branch metric BM00. Similarly, in the branch metric calculation circuit 63-2, the input data (X, Y) and the coordinate point (1 / {2, -1 /})
2), the input data (X, Y) and the coordinate point (-1 / {2,1 /}) in the branch metric calculation circuit 63-3.
2), the input data (X, Y) and the coordinate point (−1 / √2, −1 /
√2) is the distance between the branch metrics BM01 and BM
10 and BM11. Here, the distance calculation for the inserted dummy data is omitted according to the insertion flag supplied from the preceding bit insertion circuit 36. That is, the distances between the inserted bits and the coordinates to be compared are all the same (for example, 0).

The ACS circuit 64-1 calculates the following two equations according to the state transition of the convolutional encoder 2, and selects the one with the larger likelihood, that is, the one with the smaller calculation result,
The selection information SEL is stored in the subsequent path memory 65, the calculation result SM is stored in the state metric storage device 66-1, and
Supplied respectively.

SM00 + BM00 (1) SM01 + BM11 (2)

Here, SM00 is the value of the state metric storage device 66-1 one unit time ago, and SM01 is 1
The value of the state metric storage device 66-2 before the unit time, BM00, is stored in the branch metric operation circuit 63-1.
, And BM11 represent the calculation results of the branch metric calculation circuit 63-4, respectively.

If the calculation result of equation (1) is smaller, SE
If L00 = 0 is smaller than the calculation result of equation (2), S
EL00 = 1 is supplied to the path memory 65 at the subsequent stage.
In the former case, SM00 + BM00 is stored. In the latter case, SM01 + BM11 stores the new state metric SM in the state metric storage device 66-1.
00 is stored.

This calculation will be described with reference to FIG. There are two paths that reach state 00, and the first path is 0 in state 00.
Is input, and the calculation formula to be compared in the path that outputs 00 is as shown in Expression (1). The second calculation is a path in which 0 is input in state 01 and output is 11, and the calculation formula to be compared is Equation (2) is obtained. The smaller one of the calculation results is supplied to the state metric storage device 66-1 as a new state metric SM00.

A similar operation is performed by the ACS circuits 64-2 to 6-6.
This is also performed in 4-4. The state metric storage devices 66-1 to 66-4 are reset to 0 at the initial stage when the system operates. This control is performed via a terminal 61 from a control device (not shown).

The path memory 65 selects, stores, and propagates input data, that is, decoded data, using the selection information SEL00 to SEL11 from the ACS circuits 64-1 to 64-4 in accordance with the state transition diagram of FIG.

FIG. 17 shows the branch metric operation circuit 6.
3 illustrates a configuration example of 3-1. The data X input from the terminal 62-1 is input to the subtraction circuit 51,
1 / √2 output by 2 is subtracted. The output of the subtraction circuit 51 is branched and input to the multiplication circuit 53, and is multiplied (that is, squared). The selector 203 receives the output of the multiplication circuit 53 and the output of the generation circuit 202 and selects 0 generated by the generation circuit 202 when the dummy flag for X is input from the bit insertion circuit 36 via the terminal 201. At other times, the output of the multiplication circuit 53 is selected and output to the addition circuit 54.

Similarly, the data Y input from the terminal 62-2 is input to the subtraction circuit 55, and 1 / √2 output from the generation circuit 56 is subtracted. The output of the subtraction circuit 55 is branched and input to the multiplication circuit 57, and is multiplied (squared). Selector 206
Receives the output of the multiplication circuit 57 and the output of the generation circuit 205, and when a dummy flag for Y is input from the bit insertion circuit 36 via the terminal 204,
05 is generated, and at other times, the multiplication circuit 5 is selected.
7 is selected and output to the adding circuit 54. The addition circuit 54 outputs the output of the selector 203 and the selector 206
And outputs the result as a branch metric BM00.

That is, in this example, when the flag is not input, the subtraction circuit 51 outputs X−1 / √2, which is squared in the multiplication circuit 53, and is output from the multiplication circuit 53 by (X−1 / √2) ² is output. Similarly,
The subtraction circuit 55 outputs Y−1 / √2, and this value is squared by the multiplication circuit 57, and the multiplication circuit 57 outputs (Y−1 / √2).
2) Output ² . The addition circuit 54 adds the output of the multiplication circuit 53 and the output of the multiplication circuit 57 (X−1 / √2) ² +
(Y−1 / √2) ² is output as the branch metric BM00. On the other hand, when the dummy flag of X is input, the selector 203 outputs 0,
4 is (Y−1 / √2) ² , and when the dummy data of Y is input, the selector 206 outputs 0, so that the output of the adder circuit 54 is (X−1 /） 2). It becomes ² .

In the branch metric operation circuits 63-2 to 63-4, the same operation is performed by a circuit having the same configuration as that shown in FIG. However, in the branch metric calculation circuit 63-2, the generation circuit 52
Is 1 / √2, and the output of the generating circuit 56 is -1 / √2. In the branch metric calculation circuit 63-3, the outputs of the generation circuits 52 and 56 are respectively -1.
/ √2 and 1 / √2, and in the branch metric operation circuit 63-4, -1 / √2 and -1 / √2, respectively.
It is said.

FIG. 18 is a block diagram of the path memory 65. Terminals 71-1 to 71-4 have an ACS circuit 64-
Selection information SEL00 to SEL11 output from 1 to 64-4 are input. These selection information SEL
00 to SEL11 are input as control signals to the selectors 73-1 to 73-4 having two inputs and one output, respectively. The selector 73-1 has two inputs,
Fixed data 0 is input from the terminal 72-1. Similarly, selectors 73-2 to 73-4 have terminals 72-2.
7 to 72-4, fixed data 0, 1 or 1 is input as two inputs.

The selectors 73-1 to 73-4 select one of the two inputs in accordance with the selection information SEL00 to SEL11, and the registers 81-1 to 81-1 at the subsequent stage.
-4. However, the first column selector 73-
As described above, the same data is input to terminals 12-1 to 73-4 as two inputs from terminals 72-1 to 72-4. , 1 or 1 will be stored.

Hereinafter, similarly, n columns (in the case of the example of FIG. 18,
There is provided a configuration including (four columns) selectors and registers. That is, in the second column, the selector 74-
1 to 74-4 and registers 82-1 to 82-4. The selector 74-1 includes the register 8 in the front row.
The output of 1-1 and the output of register 81-2 are supplied. The output of the register 81-3 and the output of the register 81-4 are input to the selector 74-2.
The output of the register 81-1 and the output of the register 81-2 are input to the selector 74-4.
3 and the output of the register 81-4.
Then, the selectors 74-1 to 74-4 select the selection information S
One of the two inputs is selected according to the values of EL00 to SEL11, and registers 82-1 to 82-4 at the subsequent stage are selected.
Perform processing to output to. For example, register 74-1 has
When the selection information SEL00 is 0, the register 81-1
Is selected, and when the selection information SEL00 is 1,
The output of the register 81-2 is selected and output.

The outputs of the registers 84-1 to 84-4 in the last column are input to a 4-input / 1-output selector 85.

The state metrics SM00 to SM11 output from the state metric storage devices 66-1 to 66-4 in FIG. 16 are input to the minimum value comparison circuit 88 from the terminals 87-1 to 87-4. The minimum value comparison circuit 88 compares the magnitudes of the four state metrics and selects the minimum one. Then, when the state metric SM00 is the minimum, the data 00 is output,
When the state metric SM01 is the minimum, data 01 is output. When the state metric SM10 is the minimum, data 10 is output. When the state metric SM11 is the minimum, data 11 is output.
The selector 85 receives the input from the minimum value comparison circuit 88
, The output of the register 84-1 is selected, when 01, the output of the register 84-2 is selected, when it is 10, the output of the register 84-3 is selected, and when it is 11, the register is output. The output of the terminal 84-4 is selected and output from the terminal 86 as a decoding result. Terminal 72
The fixed values of -1 to 72-4 mean the decoded information corresponding to each state.

Such connection of the path memory 65 is based on the state transition diagram of FIG. In the configuration of the path memory 65, the top row is in state 00, and the second row is in state 01.
The third row corresponds to state 10, and the bottom row corresponds to state 11. The first column captures decoded information. According to FIG. 13, there are two paths from state 00 and state 01 that reach state 00. The input bit corresponding to each path, that is, the decoded information is 0 in each case. Therefore, in the first column in the state 00 (the top row), the input terminals of the selector 73-1 are wired so that the decoding information 0 corresponding to the selection information SEL00 is selected by the selection information SEL00.

In the first column, state 01, state 1
0 and state 11 are similarly connected.

In the second and subsequent columns, selection, propagation, and storage of a decoded sequence are performed. According to FIG. 13, there are two paths that reach state 00 from state 00 and state 01. Therefore, in the second column in the state 00, the input terminals of the selector 74-1 are wired such that the selection information SEL00 selects data from the corresponding state.

The state 01 of the second to third rows in the second column,
In the states 10 and 11, the connection is made in the same manner.

In the last column of the path memory 65, data corresponding to the path with the highest likelihood is output as final decoded data from the four stored decoded data. The “path with the highest likelihood” is a path corresponding to the one having the minimum value among the four state metrics SM00 to SM11, and the selector 85 selects the path corresponding to the minimum value of the state metric at that time. That is, the path with the highest likelihood is selected.

[0066]

In recent years, with the demand for high-speed (high bit rate) transmission, the modulation scheme of the digital data transmission system has been changed from QPSK to 16 bits.
Extension to QAM, 64QAM, 256QAM, etc., is conceivable. In this case, the number of bits that can be transmitted is QP
4 bits, 6 bits, or 8 bits for 2 bits of SK, respectively, 2 times, 3 times for QPSK
It will increase by a factor of six.

FIG. 19 is a block diagram of a data transmitting apparatus using 16QAM. In FIG. 19, portions corresponding to those in FIG. 11 are denoted by the same reference numerals. That is, in this example, in the serial-parallel converter 4,
The serial data output from the bit erase circuit 3 is 4
The data is converted into data u, v, x, y in units of bits. Then, for each data, bit spreading processing is performed in bit spreading circuits 91-1 to 91-4, and as signal u ′, v ′, x ′, y ′, signal point assigning circuit 6
To be supplied. Other configurations are the same as those in FIG.

That is, in this example, in the serial / parallel converter 4, one series of data is converted into four series of data (u, v, x, y) corresponding to 16QAM, and each is converted to a bit spreading circuit 91-. In 1 to 91-4, the bit spreading process is performed by changing the order of the bits according to a predetermined rule. This process is the same as the process in the bit spreading circuits 5-1 and 5-2 in FIG. 11, and performs different bit spreading processes using different numerical values s.

In the signal point assignment circuit 6, the input 4
Bit data (u ′, v ′, x ′, y ′) is assigned to a symbol on the transmission path. The assignment is performed according to, for example, FIG. That is, for example, (u ', v',
x ′, y ′) = (0, 0, 0, 0), (I ′, Q ′) = (3 / √10, 3 / √10), (u ′, v ′, x ′, y When ') = (0,0,0,1), the allocation is performed as follows: (I ′, Q ′) = (3 / √10, 1 / √10).

The assignment is similarly performed for other inputs.

Thereafter, the same processing as in FIG. 11 is performed, and the data is transmitted.

When the transmitting apparatus shown in FIG. 19 performs signal point allocation according to the 16QAM method as shown in FIG. 20 and receives transmitted data, the receiving apparatus performs the processing shown in FIG. 21 corresponding to FIG. It can be considered that However, actually, the configuration cannot be as shown in FIG.

That is, as described above, the data (I, I) input from the demodulator 32 to the symbol despreading circuit 33
Each component I, Q of Q) is, in the case of the QPSK system,
Each of them represents one bit, but in the case of the 16 QAM system, each represents two bits. For example,
In the case of the signal point arrangement shown in FIG. 20, I includes information of the first bit and the third bit, and Q includes the second bit and the fourth bit.
Contains bit information. For example, I is 1 / √1
0, 3 / √10, and Q is also 1
Are two values. Therefore, as shown in FIG.
It cannot be divided into u 'and v' or x 'and y'. As a result, the data receiving device in the case of the 16QAM system is also configured as shown in FIG.

As a result, the processing performed in the bit insertion circuit 36 in FIG. 15 is as follows.

That is, the bit insertion circuit 36 now has:
As shown in FIG. 22A, x1, y1, x2, y2,
If data is input as x3, y3,..., as shown in FIG.
1, Y1, then dummy data d is output as data X2, and data x2 is output as data Y2. Similarly, after the data y2 and x3 are output as the data X3 and Y3, the dummy data d
Is output as data X4, and then data y3 is
It is output as data Y4.

However, this process does not mean that the process is the reverse of the process in the bit erase circuit 3 of FIG. That is, the bit erasing (bit manipulation) processing performed in the bit erasing circuit 3 is performed in units of one bit. In contrast, FIG.
The data x1 and y2 shown in (B) each correspond to 2-bit data, after which 1-bit dummy data d is inserted, and then 2-bit data x2 is output. Then, after all, a data array completely different from the original data array is output.

As a result, the output of the bit insertion circuit 36 is
When Viterbi decoding is performed by the Viterbi decoder 37, the decoding result does not mean that the performance is slightly degraded, and decoding cannot be performed at all.

On the other hand, if the hard decision is performed in the symbol despreading circuit 33 of the data receiving apparatus shown in FIG. 21, for example, as shown in FIG. v ′, x ′, y ′ can be generated.
That is, in this case, the distance between the coordinates of (I, Q) and each signal point shown in FIG. 20 is calculated, and (I, Q) corresponds to the shortest signal point. u ',
It is possible to generate v ', x', y '. However, when such a hard decision is made, it becomes difficult to decode accurate data.

The present invention has been made in view of such a situation, and has been developed for 16 QAM, 64 QAM, and 256 QAM.
It is intended to enable accurate decoding of data even when punctured error correction decoding is transmitted by a multi-level multi-phase modulation method such as that described above.

[0080]

According to a first aspect of the present invention, there is provided a data receiving apparatus, comprising: a bit despreading means for despreading a bit constituting a data symbol while retaining the coordinates of the symbol; , A metric calculating means for calculating a metric for a bit, and a decoding means for performing a data decoding process.

According to a third aspect of the present invention, there is provided a data receiving apparatus comprising: a metric calculating means for calculating a metric for each bit of data; a bit despreading means for despreading a bit constituting a data symbol; And a decoding means for performing the decoding process.

According to a fifth aspect of the present invention, there is provided a data receiving method, comprising: a bit despreading step of despreading a bit constituting a data symbol while keeping the coordinates of the symbol; and calculating a metric for the bit for each data bit. And a decoding step of performing data decoding processing.

According to a sixth aspect of the present invention, in the data receiving method, a metric calculation step of calculating a metric for each bit of data, a bit despreading step of despreading bits constituting a data symbol, And a decoding step of performing a decoding process.

In the data receiving apparatus according to the first aspect, the bits constituting the data symbol are despread by the bit despreading means while retaining the coordinates of the symbol, and the metric for the bit is determined for each bit of the data. The metric calculation means calculates the data, and the decoding means performs data decoding processing. For example, a signal transmitted from the transmitting side is received, and the bits constituting the data symbol are inverted by the reverse operation of the bit despreading means performed on the transmitting side while retaining the symbol coordinates. The spreading is performed, the metric for each bit of the data is calculated by the metric calculation unit, and the obtained metric is decoded by the decoding unit.

In the data receiving apparatus according to the third aspect, for each bit of the data, the metric for the bit is calculated by the metric calculating means, and the bits constituting the data symbol are despread by the bit despreading means. The decoding means performs the data decoding process. For example, a signal transmitted from the transmitting side is received, a metric for the bit is calculated for each bit of the data by the metric calculating means, and the bits constituting the data symbol are despread by the bit despreading means on the transmitting side. Despreading of the bits is performed by the operation opposite to the above, and the obtained data is decoded by the decoding means.

In the data receiving method according to the fifth aspect, the bits constituting the data symbol are despread in the bit despreading step while maintaining the symbol coordinates.
For each bit of data, a metric calculation step calculates a metric for the bit, and the decoding step performs data decoding processing. For example, a signal transmitted from the transmitting side is received, a metric for each bit of data is calculated by a metric calculating step, and bits constituting a data symbol are subjected to a bit despreading step on the transmitting side. Despreading of bits is performed by the reverse operation of the above, and the obtained data is decoded by the decoding step.

In the data receiving method according to the sixth aspect, the metric calculation step calculates a metric for each bit of the data, and the bit despreading step despreads the bits constituting the data symbol.
The decoding step performs data decoding processing. For example, a signal transmitted from the transmitting side is received, a metric for each bit of data is calculated by a metric calculating step, and bits constituting a data symbol are subjected to a bit despreading step on the transmitting side. Despreading of bits is performed by the reverse operation of the above, and the obtained data is decoded by the decoding step.

[0088]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the data transmission apparatus shown in FIG. 11 (19), bit erasure is performed, but data can be transmitted without bit erasure. FIG. 1 is a block diagram showing an example of the configuration of the data transmission device in such a case. In this figure, FIG.
The same parts as those in 9) are denoted by the same reference numerals, and a description thereof will be omitted. In this embodiment, the bit erase circuit 3
And the serial-parallel converter 4 are excluded. Also, the output of the convolutional encoder 2 is changed from two sequences (X, Y) to four sequences (u,
v, x, y). Other configurations are shown in FIG.
1 (19).

FIG. 2 is a block diagram showing an example of a detailed configuration of the convolutional encoder 2 shown in FIG. The convolutional encoder 2 delays the input data by one clock,
Delay circuits 92-1 to 92-3 for outputting, and an adder circuit 93- for calculating exclusive OR of input data
1 to 93-4.

The data I input from the information source 1 is input to the delay circuit 92-1 and the adders 93-1 to 93-4, respectively. The output of the delay circuit 92-1 is input to the delay circuit 92-2 and the adders 93-1 and 93-2. The output of the delay circuit 92-2 is input to the delay circuit 92-3 and the adders 93-1 and 93-3. The delay circuit 92-3 is input to the adders 93-1 to 93-4. The outputs of the adders 93-1 to 93-4 are 4
The data is output as series data (u, v, x, y).

Next, the operation of the embodiment of FIG. 2 will be described with reference to FIG.

FIG. 3 is a state transition diagram of the convolutional encoder 2. The state transition of the convolutional encoder 2 is as follows.

That is, for example, in state 000 (states of the delay circuits 92-1 to 92-3 are all 0), when 0 is input, the addition circuits 93-1 to 93-4 are input.
Output (uvxy) = (0000), and state 0
Transition to 00. When 1 is input from the state 000,
(Uvxy) = (1111) is output, and the state transits to the state 100. When 0 is input from the state 001, (uvx
y) = (1111) is output, and the state transits to the state 000. When 1 is input from the state 001, (uvx
y) = (0000) is output, and the state transits to the state 100.

In other states, as shown in FIG.
For the input of 0 or 1, the signal shown is output,
The state transits to the illustrated state. Therefore, the convolutional encoder 2 shown in FIG. 2 outputs four corresponding data (u, v, x, y) according to the information output from the information source 1.

The four series of data output from the convolutional encoder 2 are subjected to bit spreading processing in the bit spreading circuits 91-1 to 91-4 by changing the order of bits according to a predetermined rule. You. The processing is the same as the processing in the bit spreading circuits 5-1 and 5-2 in FIG.
Bit spreading is performed using a different numerical value s for each of 1-4.

As described with reference to FIG. 11, the signal point allocating circuit 6 allocates the input four series of data (u ', v', x ', y') to the symbols on the transmission path. Other operations are the same as those in FIG.

FIG. 4 is a block diagram showing the configuration of the first embodiment of the data receiving apparatus of the present invention for receiving data transmitted from the data transmitting apparatus shown in FIG. In this figure, parts corresponding to those in FIG. 15 are denoted by the same reference numerals, and the description thereof will be omitted.

The symbol despreading circuit 33 performs symbol despreading by the reverse operation of the symbol spreading circuit 7 shown in FIG. 1, and converts the I and Q components of the received signal into I ′ and Q components, respectively. 'It has been made to convert to components.

Bit despreading circuits 101-1 to 101-
4 performs bit despreading processing on the I ′ signal and the Q ′ signal output from the symbol despreading circuit 33. The bit despreading circuit 101-1 performs a despreading process on the first bit of the symbol defined by the I ′ signal and the Q ′ signal, and performs bit despreading circuits 101-2 to 101-2.
1-4 perform despreading processing of the second to fourth bits, respectively.

Bit despreading circuits 101-1 to 101-
The I signal component and the Q signal component of the first to fourth bits output from the fourth bit are input to the corresponding metric calculation circuits 102-1 to 102-4, respectively, and are respectively converted to the first to fourth bits. A corresponding metric is calculated. Metric calculation circuit 102-1
(Metrics) output from-through 102-4
u, v, x, and y are input to the Viterbi decoder 103. The Viterbi decoder 103 decodes input data (metric) and outputs reproduction information 38.

Note that the metric calculation circuit 102-1 is
It is configured as shown in FIG.

That is, the bit despreading circuit 101-1 of FIG.
The I ′ signal and Q ′ signal output from the above are input to n probability calculation circuits 111-1 to 111-n. In this case, as shown in FIG. 20, since the signal point assignment processing is performed by 16QAM, n is set to 16. The probability calculation circuit 111-1 calculates the 00 of the 16QAM shown in FIG.
The symbol S0000 corresponding to 00 is transmitted, and the probability P (S0000∩R) of receiving the received signal R is calculated. Hereinafter, similarly, in the probability calculation circuit 111-2, the symbol S000 corresponding to 0001 of 16QAM
1 is transmitted, and the probability P (S00
01∩R), and the probability calculation circuit 111-3 calculates a symbol S00 corresponding to 0010 of 16QAM.
10 is transmitted and the probability P (S0
010∩R) is calculated. Then, the probability calculation circuit 11
In 1-16, symbol S1111 corresponding to 1111 of 16QAM is transmitted, and probability P (S1111∩R) of receiving received signal R is calculated.

The adder circuit 112 outputs a symbol whose first bit is 0, that is, S0000, S0001, S0
010, S0011, S0100, S0101, S01
10, the output of the probability calculation circuit 111-i for calculating the probability for S0111 is received, and the sum thereof is calculated. On the other hand, the addition circuit 113 receives the input of the output of the probability calculation circuit 111-i which calculates the probabilities for all the symbols of 16QAM, that is, S0000 to S1111 and calculates the sum thereof. The division circuit 114 divides the output of the addition circuit 112 by the output of the addition circuit 113.

The metric calculation circuits 102-2 to 102-4 are also basically similar to the metric calculation circuit 102-
1 is the same as that of FIG.
12 is configured to calculate the sum of probabilities for the symbols whose second to fourth bits are 0.

FIG. 6 is a block diagram showing an example of the configuration of the Viterbi decoder 103.

The input terminals 62-1 to 62-4 have the configuration shown in FIG.
The data u, v, x, and y output from the metric calculation circuits 102-1 to 102-4 shown in FIG. Inverting circuits 140-1 to 140-4
Is configured to invert all the bits of the input data and output the inverted data. Multiplication circuits 141-1 to 141
-16 is the input terminals 62-1 to 62-4 and the inverting circuit 1
Of the data output from 40-1 to 140-4,
By multiplying predetermined data, BM0000 to B
The data is output as M1111.

The ACS circuits 142-1 through 142-8 are
One of the input branch metrics BM and the corresponding state metric SM are multiplied, and the other branch metric BM and the corresponding state metric SM are multiplied. Then, the two addition results are compared, and the larger multiplication value is stored in the state metric storage devices 143-1 to 143-8 in accordance with the comparison result.
Are output as new state metrics SM and signals SEL000 to SEL representing the selection result.
111 is output to the path memory 144. The path memory 144 also has a state metric storage device 143-
State metrics SM000 to SM111 stored in Nos. 1 to 143-8 are input.

The state metric storage devices 143-1 to 143-8 are reset by a signal input from a terminal 61. Path memory 144
Output the decoding result from the terminal 145.

The multiplying circuit 141-1 has an input terminal 62-1.
Through the input terminals 62-4 to multiply the metrics u, v, x, and y, and output the calculation result as a branch metric BM0000.
The multiplication circuit 141-2 includes input terminals 62-1 to 62-3.
Are multiplied by the metric u, v, x input respectively from, and the metric y inverted by the inverting circuit 140-4, and the calculation result is output as a branch metric BM0001. Similarly, the multiplying circuit 141-3 multiplies the metric u, v, y input from the input terminals 62-1, 62-2, 62-4 by the inverted metric x output from the inverting circuit 140-3. Then, the calculation result is output as the branch metric BM0010, and the multiplication circuit 141-
Reference numeral 16 multiplies the inverted metrics u, v, x, and y output from the inverting circuits 140-1 to 140-4, and outputs the calculation result as a branch metric BM1111.

That is, the inverting circuits 140-1 to 140-1
-4 is (u ', v', x ',
y ′), the outputs BM0000 to BM1111 from the multiplication circuits 141-1 to 141-8 and the input terminal 6
The relationship between data input from 2-1 to 62-4 and data output from inverting circuits 140-1 to 140-4 is as follows.

BM0000 = u · v · x · y BM0001 = u · v · x · y ′ BM0010 = u · v · x ′ · y :: BM1111 = u '· v' · x '· y'

An ACS (Accumulate Compare Select) circuit 142-1 includes an output (branch metric) BM0000 of the multiplication circuit 141-1 and a multiplication circuit 141-16.
(Branch metric) BM 1111 is input. Similarly, the ACS circuit 142-2 includes the output BM0101 of the multiplication circuit 141-6 and the multiplication circuit 141-1.
One output BM 1010 is input. Also, ACS
The circuit 142-3 includes the output BM0 of the multiplication circuit 141-4.
011 and BM1 output from the multiplication circuit 141-13
100 has been entered. Further, the ACS circuit 142-
8, the output BM1001 of the multiplication circuit 141-10;
The output BM0110 of the multiplication circuit 141-7 is input.

The output (state metric) SM000 of the state metric storage device 143-1 and the state metric storage device 143 are also stored in the ACS circuit 142-1.
-2 output (state metric) SM001 is input to the ACS circuit 142-2, and the output (state metric) of the state metric storage device 143-3 is supplied to the ACS circuit 142-2.
SM010 and the output (state metric) SM011 of the state metric storage device 143-4 are input. Similarly, the output (state metric) SM100 of the state metric storage device 143-5 and the state metric storage device 143- are stored in the ACS circuit 142-3.
6, the output (state metric) SM101 of the state metric storage device 143-7 is input to the ACS circuit 142-8.
M110 and the output (state metric) SM111 of the state metric storage device 143-8 are input.

The ACS circuits 142-1 to 142-8 are
One of the inputted branch metrics BM and the corresponding state metric SM are multiplied, and the other branch metric BM is multiplied by the corresponding state metric SM. Then, the two addition results are compared, and the larger multiplication value is stored in the state metric storage devices 143-1 to 143-8 in accordance with the comparison result.
Are output as new state metrics SM and signals SEL000 to SEL representing the selection result.
1111 to the path memory 144. The path memory 144 also has a state metric storage device 143.
State metrics SM000 to SM111 stored in -1 to 143-8 are input.

The state metric storage devices 143-1 to 143-8 receive the signal (RS
T). The path memory 144 outputs the decoding result from the terminal 145.

FIG. 7 is a block diagram showing a detailed configuration example of the path memory 144.

The input terminals 150-1 to 150-8 have
The selection information SEL000 to SEL111 output from the ACS circuits 142-1 to 142-8 are input, respectively. These selection information SEL000 to SEL1
11 is input as a control signal to selectors 151-1 to 151-8 each having two inputs and one output. Also,
The selector 151-1 has two inputs, a terminal 16
Fixed data 0 is input from 1-1. Similarly, the selectors 151-2 to 151-4 have terminals 161-2.
161-4, fixed data 0 is input as two inputs, and the selectors 151-5 to 151-8 receive fixed data 0 as two inputs from terminals 161-5 to 161-8, respectively. 1 has been entered.

The selectors 151-1 to 151-8 select one of the two inputs in accordance with the selection information SEL000 to SEL111, and the register 152-
1 to 152-8. However, since the same data is input to the selectors 151-1 to 151-8 in the first column as two inputs from the terminals 161-1 to 161-8 as described above, the register 152-1
0 to 0, 1, 1 or 1 are stored in Nos. To 152-8, respectively.

Hereinafter, similarly, n columns (4 in the case of the example of FIG. 7)
A configuration including a selector and a register of (column) is provided. That is, in the second column, the selector 153-
1 to 153-8 and registers 154-1 to 154-8
Is provided. The output of the register 152-1 and the output of the register 152-2 in the front row are supplied to the selector 153-1. The selector 153-2 includes the register 1
The output of the register 152-5 and the output of the register 152-6 are input to the selector 153-3, and the output of the register 152-6 is input to the selector 153-3.
53-8 contains the output of register 152-7 and register 1
The output of 52-8 is input. And selector 1
53-1 to 153-8 select one of the two inputs corresponding to the values of the selection information SEL000 to SEL111, and output them to the registers 154-1 to 154-8 at the subsequent stage. For example, the register 153-1 stores the selection information SEL
When 000 is 0, the output of the register 152-1 is selected, and when the selection information SEL000 is 1, the output of the register 152-2 is selected and output.

Last column registers 158-1 to 158-
The output of 8 is input to the selector 159 of 8 inputs and 1 output.

The minimum value comparison circuit (CMP) 160 receives the state metrics SM000 to SM111 output from the state metric storage devices 143-1 to 143-8 of FIG. 6 via terminals 162-1 to 162-8. Has been entered. The minimum value comparison circuit 160 (CMP)
The magnitudes of the eight state metrics are compared, and the smallest one is selected. For example, state metric SM000
Is the minimum, the data 000 is output. If the state metric SM001 is the minimum, the data 001 is output. If the state metric SM010 is the minimum, the data 010 is output, and the state metric SM111 is the minimum. Then, data 111 is output. When the input from the minimum value comparison circuit 160 is 000, the selector 159
-1 is selected, and when it is 001, the register 15
8-2 is selected, and when it is 010, register 1
The output of the register 58-3 is selected, and when it is 111, the output of the register 158-8 is selected and output from the terminal 163 as a decoding result. The same applies to the case where the output of the minimum value comparison circuit 160 is 011 to 110. The fixed values of the input terminals 161-1 to 161-8 mean decoding information corresponding to each state.

The connection of the path memory 144 is based on the state transition diagram of FIG. That is, in the configuration of the path memory 144, the top row corresponds to the state 000, the second row corresponds to the state 001, the third row corresponds to the state 010, and the bottom row corresponds to the state 111. The first column captures decoded information. According to FIG. 3, there are two paths that reach the state 000 from the state 000 and the state 001. The input bit corresponding to each path, that is, the decoded information is 0 in each case. Therefore, state 00
In the first column at 0 (top row), the selection information SEL00
The input terminal of the selector 151-1 is wired so that 0 selects the corresponding decoding information 0.

In the first column, state 001, state 010,.
.., The state 111 is similarly connected.

In the second and subsequent columns, selection, propagation, and storage of a decoded sequence are performed. According to FIG. 3, state 0
There are two paths from state 000 and state 001 that reach 00. Therefore, in the second column in the state 000, the selector 153-selects the data from the corresponding state according to the selection information SEL000.
One input terminal is wired.

In the second column, states 001, 010,...
In the state 111, the connection is made in the same manner.

In the last column of the path memory 144, data corresponding to the path with the highest likelihood is output as final decoded data from the stored eight decoded data.
The “path with the highest likelihood” is a path corresponding to a path having the minimum value among the eight state metrics SM000 to SM111, and a path corresponding to the minimum value of the state metric at that time by the selector 159. That is, the path with the highest likelihood is selected.

Next, the operation will be described.

The received signal received by the antenna 31 is demodulated by the demodulator 32 to obtain data of the I component and the Q component of the symbol. The data of the I component and the Q component is despread by the symbol despreading circuit 33 by performing an operation reverse to that of the symbol spreading circuit 7 of FIG. 1 (a process of returning the reordered symbols to the original order). The obtained I 'and Q' signals are obtained.

This symbol despreading operation uses the same number N, G as that of the symbol spreading circuit 7 and uses vectors (S1, S2,..., S
n,..., SN-1) are converted into vectors (S′1, S′2,..., S′k,.
.., S'N-1). At this time,
Sn = S′k (n = G ＾ k mod N).

The I ′ signal and the Q ′ signal supplied from the symbol despreading circuit 33 are
1-1 to 101-4.

The bit despreading circuit 101 for the first bit
At 1, the operation opposite to that of the first bit bit spreading circuit 91-1 in FIG. 1 is performed while holding the coordinates (the combination of I ′ and Q ′) as symbols. That is, B '
i (I ′, Q ′) as one set, and vectors (B′0, B′1,...) of M sets of B′i data corresponding to the bit spreading circuit 91-1 of FIG.・ ・ 、 B'n 、 ・
.., B′M−1) is a vector (B0, B1,...) Having Bi (I, Q) as one set and M sets of Bi as elements.
.., Bk,..., BM-1).

At this time, B'n = Bk (n = k + s mod
M), and s has the same value as that used in the bit spreading circuit 91-1.

Similarly, another bit despreading circuit 101-2
In steps 101 to 101-4, the bit despreading processing for the second to fourth bits is performed while holding the coordinates of the symbol. At this time, the bit despreading circuit 101-
As the numerical value s used in the bit despreading of 2 to 101-4, the same value as the numerical value s used in the bit spreading circuits 91-2 to 91-4 is used.

The bit despread data sequences (I′u, Q′u), (I′v, Q′v), (I ′) output from the bit despreading circuits 101-1 to 101-4 in this way.
x, Q′x) and (I′y, Q′y) are supplied to the metric calculation circuits 102-1 to 102-4, respectively.

Next, the metric calculation in the metric calculation circuits 102-1 to 102-4 will be described.
Here, the metric means a conditional posterior probability for a bit constituting the received signal when a predetermined received signal is received, which is defined by the following equation. P (bi = 0 | R) = P (bi = 0∩R) / P (R) (3)

Here, P (bi = 0 | R) is the received signal R (Ir, Qr) (Ir = I'u, I'v, I'x, or I'y: Qr = Q'u, Q′v, Q′x, or Q′y), the conditional posterior probability that the i-th bit of the transmission symbol is 0, and P (R) is the received signal R
The probability of receiving (Ir, Qr) is represented by P (bi = 0∩R)
Represents the probability that the symbol whose i-th bit is 0 is transmitted and the received signal R (Ir, Qr) is received.

Similarly, according to the following equation (4), the reception signal R
When (Ir, Qr) is received, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained. P (bi = 1 | R) = P (bi = 1∩R) / P (R) (4)

Here, P (bi = 1 | R) is a conditional posterior probability that the i-th bit of the transmission symbol is 1 when the received signal R (Ir, Qr) is received, and P (R) is , The probability of receiving the received signal R (Ir, Qr) is represented by P (bi =
1∩R) represents the probability that the symbol whose i-th bit is 1 is transmitted and the received signal R (Ir, Qr) is received, respectively.

The following equation (5) also shows that the received signal R
When (Ir, Qr) is received, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained. P (bi = 1 | R) = 1-P (bi = 0 | R) (5)

Metric calculation circuits 102-1 to 102-1
-4, from the input I component Ir and Q component Qr, 16Q
The metric for the first to fourth bits constituting the AM is calculated, and the metric P (b1 = 0 | R) for the first bit is u and the metric P (b2 = 0 | R) for the second bit is v, the metric P (b3 = 0 | R) for the third bit is output as x, and the metric P (b4 = 0 | R) for the fourth bit is output as y.

The calculation of each metric is performed according to the above equation (3). That is, P (bi = 0 | R) = P (bi = 0∩R) / P (R) (6) = ((1/16) ΣP (S _j ∩R)) / ((1/16) ΣP _{(S k ∩R)) (7} ) = (ΣP (S j ∩R)) / (ΣP (S k ∩R)) (8)

Here, P (S _j ∩R) represents the probability that the symbol S _j is transmitted and the received signal R is received.
(S _j ∩R) represents the sum of the probabilities P (S _j ∩R) for all symbols S _j for which the ith bit is 0.

On the other hand, P (S _k ∩R) represents the probability that symbol S _k is transmitted and received signal R is received, and ΣP (S _k ∩R)
_k .andgate.R) represents the sum of the probabilities P (S _k .andgate.R) for all symbols S _k defined in 16QAM.

The metric calculation circuit 102-of the metric (P (b1 = 0 | R)) for the first bit in FIG.
1, the probability calculation circuit 111-1 outputs P (S000
0∩R), that is, the probability of transmitting the symbol S0000 corresponding to 0000 of 16QAM and receiving the received signal R is calculated.

The probability calculation circuit 111-2 calculates P (S000
1∩R), that is, the probability of transmitting the symbol S0001 corresponding to 0001 of 16QAM and receiving the received signal R is calculated.

The probability calculation circuit 111-3 calculates P (S001
0∩R), that is, the probability of transmitting the symbol S0010 corresponding to 0010 of 16QAM and receiving the received signal R is calculated.

In the same manner, the probabilities are calculated for the remaining symbols of 16QAM in the same manner, and a total of 16 symbols are calculated.
Obtain the result of calculating the probabilities.

The addition circuit 112 is a circuit for calculating the numerator of the equation (8), and calculates the probability of the symbol whose first bit is 0, that is, S0000, S0001, S0010, S0011, S0100, S0101, S0110, S0111. Find the sum.

The adder circuit 113 is a block for calculating the denominator of the equation (8). , S1100, S1101, S1110, S1111.

The dividing circuit 114 is a calculator for dividing the output of the adding circuit 112 by the output of the adding circuit 113, and calculates the equation (8).

The calculation of the metric for the second bit can be performed in the same manner. That is, the metric for the second bit is calculated in the metric calculation circuit 102-2. There, a metric calculation circuit 102-corresponding to the addition circuit 112 for calculating the numerator of the equation (8)
As an input to an adder circuit (not shown), all the symbols whose second bit is 0, that is, S0000, S0001, S0010, S0011, S1000, The calculation results of the probabilities for S1001, S1010, and S1011 are selected and added. As an input to an addition circuit (not shown) of the metric calculation circuit 102-2 corresponding to the addition circuit 113 for calculating the denominator of the equation (8), all symbols, That is, the probability calculation results for S0000, S0001, S0010, S0011, S0100, S0101, S0110, S0111, S1000, S1001, S1010, S1011, S1100, S1101, S1110, and S1111 are selected and added.

The same operation is performed on the third bit and the fourth bit.

The operation results u, v, x, and y of the metric calculation circuits 102-1 to 102-4 are supplied to the Viterbi decoder 103.

The multiplication circuit 141-1 shown in FIG. 6 calculates the product of the metrics u, v, x, and y (the probability that the first to fourth bits are 0) and calculates the branch metric BM000.
Output as 0. This branch metric BM000
0 corresponds to the code output 0000 of the convolutional encoder 2.

Similarly, the multiplying circuit 141-2 calculates the metrics u, v, x (the probability that the first to third bits are 0) and the metric y '(the probability that the fourth bit is 1). And the branch metric BM0001
Output as This branch metric BM0001
Corresponds to the code output 0001 of the convolutional encoder 2.

The multiplication circuit 141-3 calculates the metric u,
v, y (the probability that the first bit, the second bit, and the fourth bit are 0) and the metric x ′ (the third bit is 1
Is calculated, and the branch metric BM0 is calculated.
Output as 010. This branch metric BM0
010 corresponds to the code output 0010 of the convolutional encoder 2. Similarly, the multiplication circuit 141-8 outputs the metrics u ′, v ′, x ′, y ′ (first bit to fourth bit).
The product of the probability that the first bit is 1) is calculated and output as the branch metric BM1111. This branch metric BM1111 corresponds to the encoded output 1111 of the convolutional encoder 2.

The ACS circuit 142-1 calculates the following two equations according to the state transition of the convolutional encoder 2 (FIG. 3). SM000 × BM0000 (9) SM001 × BM1111 (10)

Here, SM000 is the value of the state metric storage device 143-1 one unit time ago, SM001
Is the state metric storage device 143 one unit time ago.
The value of −2, BM0000 indicates the operation result of the multiplication circuit 141-1, and BM1111 indicates the operation result of the multiplication circuit 141-8.

The ACS circuit 142-1 selects the one with the larger likelihood, that is, the one with the larger calculation result from the above equations (9) and (10), and selects the selection information SEL.
000 to the subsequent path memory 144,
The larger of the results obtained by calculating Expressions (9) and (10) is stored in the subsequent state metric storage device 143-
1 and stored. That is, if the calculation result of Expression (9) is larger, SEL000 = 0 is set, and Expression (10)
If the calculation result is larger, SEL000 = 1 is set. In the former case, SM000 × BM0000 becomes
In the latter case, SM001 × BM1111 is stored in the state metric storage device 143-1 as a new state metric SM000.

This calculation will be described with reference to FIG. State 0
There are two paths that reach 00, the first is a path in which 0 is input in state 000 and the path that outputs 0000, and the calculation formula to be compared is as shown in equation (9). The second is 0 in state 001. Is input and the path to output 1111 is compared with the calculation equation (10). The larger one of the calculation results is supplied to the state metric storage device 143-1 as a new state metric SM000.

A similar operation is performed in the ACS circuits 142-2 to 142-8. Note that the state metric storage devices 143-1 to 143-8 are reset to 0 at the initial stage when the system operates. This control is performed via a terminal 61 from a control device (not shown).

The path memory 144 selects, stores, and propagates input data, that is, decoded data, using the selection information SEL000 to SEL111 from the ACS circuits 142-1 to 142-8 in accordance with the state transition diagram of FIG.

Next, referring to FIG.
Will be described.

The selection information SEL000 to SEL111 output from the ACS circuits 142-1 to 142-8 are
The signals are input to the terminals 150-1 to 150-8 and supplied as control signals to the selectors in each column.

Selectors 151-1 to 151 in the first column
-4 is input with 0 as two inputs, and selectors 151-5 to 151-8 are input with 1 as two inputs. Therefore, the selector 151
-1 to 151-4 output 0 regardless of the state of the selection information.
From 1-8, 1 is output. In such a configuration, as shown in FIG. 3, in the path from the state 000 to the state 011, all 0s are input, and the state 100 to the state 1
In the path to 11, all 1s are input.

The data output from the selectors 151-1 to 151-8 are stored in the subsequent registers 152-1 to 152-1.
2-8, output after being stored.

The data output from the registers 152-1 to 152-8 is supplied to the second column selectors 153-1 to 153-8. That is, the selector 153-
1 includes the output of the register 152-1 in the front row and the register 1
52-2 is supplied to the selector 153-2.
The output of the register 152-3 and the output of the register 152-4 are input to the selector 153-3.
The output of −5 and the output of the register 152-6 are input, and the output of the register 152-7 and the output of the register 152-8 are input to the selector 153-8. Selector 1
53-4 to 153-7 are as described above.

Each of the selectors 153-1 to 153-8 is
According to the state of the selection information SEL000 to SEL111, one of the two inputs is selected, and the register 15 at the subsequent stage is selected.
4-1 to 154-8. For example, selection information S
If EL000 is 0, the selector 153-1
Selects the output of the register 152-1, and when the selection information SEL000 is 1, the register 152-
2 is selected and output.

Similar processing is performed on the registers in the third and last columns, and selection information SEL000 to SEL000 are selected.
One of the two inputs from the preceding stage is selected according to the state of L111, and is output to the subsequent register.

Registers 158-1 to 158- of the last column
The data output from 8 is input to the selector 159. The selector 159 selects and outputs any of the data output from the registers 158-1 to 158-8 according to the output from the minimum value comparison circuit 160. That is,
The minimum value comparison circuit 160 selects the minimum state metric from the state metrics SM000 to SM111 output from the state metric storage circuits 143-1 to 143-8 shown in FIG. 6, and outputs corresponding data. For example, when the state metric SM000 is the minimum, the data 000 is output. The selector 159 selects and outputs one of the outputs of the registers 158-1 to 158-8 according to the data output from the minimum value comparison circuit 160. For example, the minimum value comparison circuit 16
When the output data from 0 is 000, the selector 15
9 selects and outputs the output of the register 158-1.
When the output data is 001 to 111, the registers 158-2 to 158-8 are selected, respectively.

In other words, the path memory 144 outputs data corresponding to the path with the highest likelihood from the stored eight decoded data as final decoded data. The “path with the highest likelihood” is a path corresponding to a path having the minimum value among the eight state metrics SM000 to SM111, and a path corresponding to the minimum value of the state metric at that time by the selector 159. That is, the path with the highest likelihood is selected.

In FIG. 5, the probability calculation circuit 111
As a calculation method in -1 to 111-16, various calculation methods can be considered depending on the transmission path. When a Gaussian transmission path is assumed, for example, in the probability calculation circuit 111-1, the probability is calculated as follows. can do. P (S0000∩R) = (1 / (2π) ^1/2 σ) exp (− (|| S0000−R || ² ) / (2σ ² )) (11)

Here, σ represents the square root of の of the noise power of the transmission path. That is, 2σ ² represents the noise power of the transmission path. || S0000-R || is the symbol S0000 and R
And the Euclidean distance.

Probability calculation circuits 111-2 to 111-16
Similarly, the probability can be calculated.

FIG. 8 shows a second embodiment of the data receiving apparatus. In this embodiment, the order of the bit despreading circuit and the metric calculation circuit is reversed as compared with the case of FIG. Other configurations are the same as those in FIG.

The I ′ and Q ′ components of the received signal output from the symbol despreading circuit 33 are
After the metric calculation, the metric data is supplied to the bit despreading circuits 95-1 to 95-8 as metric data u ', v', x ', y'.
The bit despreading circuits 95-1 to 95-8 perform operations reverse to those in the bit spreading circuits 91-1 to 91-8 shown in FIG. 1 to perform bit despreading.

The other structures are the same as those in FIG.

Next, the operation will be described. In this embodiment, the I ′ and Q ′ components of the received signal output from the symbol despreading circuit 33 are
20 and a metric corresponding to each of the first to fourth bits is calculated.

That is, the metric calculation circuit 12 shown in FIG.
0 is configured, for example, as shown in FIG. In this embodiment, the probability calculation circuits 111-1 to 111-16
The I ′ and Q ′ output from the symbol despreading circuit 33 are
A component has been entered. Adder circuits 112-1 to 112-1
-8 is a circuit for calculating the numerator of the above equation (8). 8 calculates the sum of the probabilities of the 0 symbol of the second and third bits, respectively. The adder circuit 113 is a circuit that calculates the denominator of the above equation, and calculates the sum of probabilities for all 16QAM symbols. Division circuit 11
4-1 through 114-8 are added circuits 112-1 respectively.
To 112-8 are divided by the output of the adder circuit 113 to calculate the metrics for the first to fourth bits, respectively.
Output as v ', x', y '.

The data (metrics) u ′, v ′, x ′, y ′ output from the metric calculation circuit 120 are supplied to bit despreading circuits 95-1 to 95-8, respectively. The bit despreading circuits 95-1 to 95-8 apply the bit spreading circuits 91-1 to 91- of FIG. 1 to the metric data u ', v', x ', y' output from the metric calculation circuit 120. 8 to perform bit despreading by the reverse operation, and output data u, v, x, and y.

Other operations of the embodiment of FIG. 8 are the same as those of FIG.

FIG. 10 shows a third embodiment of the data receiving apparatus. In this embodiment, the I component and the Q component of the received signal output from the demodulation circuit 32 are supplied to a metric calculation circuit 120, and metric data u ′, v ′, x obtained by performing a metric calculation. ', Y'
Is output to the symbol despreading circuit 140. The symbol despreading circuit 140 performs a process opposite to the symbol spreading process in the symbol spreading circuit 7 of FIG. 1, that is, a process of returning the order of the symbols exchanged in the symbol spreading circuit 7 to the original order, and outputs the output data u ″. , V '',
Output x '', y ''.

The data u ″, v ″, x ″, and y ″ output from the symbol despreader 140 are supplied to bit despreading circuits 95-1 to 95-8, and the bit spreading circuit shown in FIG. The processing reverse to that in the cases 91-1 to 91-8 is executed, and the obtained data u, v, x, y are output. Other configurations are the same as those in FIG. 8, and thus description thereof will be omitted.

Next, the operation will be described.

The I and Q components of the received signal output from demodulator 32 are supplied to metric calculation circuit 120. The metric calculation circuit 120 calculates the metric for the first to fourth bits constituting 16QAM from the input I component and Q component, respectively, sets the metric for the first bit to u ′, and the metric for the second bit. Is output as v ′, the metric for the third bit is x ′, and the metric for the fourth bit is y ′.

This metric calculation circuit 120 is based on FIG.
It has the same configuration as the metric calculation circuit 120 in FIG. 9.

The metric calculation results u ′, v ′, x ′, and metric for the first to fourth bits forming 16QAM
y ′ is input to the symbol despreading circuit 140.

In symbol despreading circuit 140, the reverse operation to that in symbol spreading circuit 7 shown in FIG. 1 is performed, and symbol despreading is performed. That is, despreading is S
i (u ′, v ′, x ′, y ′) as one set in FIG.
(S1, S2,...) Corresponding to the symbol spreading circuit 7 shown in FIG.
, Sn,..., SN-1), S′i (u ″,
v ″, x ″, y ″) as one set, and (N−
1) Despread vector (S ′) having S′i of a set as an element
1, S'2, ..., S'k, ..., S'N-1).

At this time, Sn = S'k (n = G ＾
k mod N).

Then, the obtained data u ″, v ″,
x ″ and y ″ are bit despreading circuits 95-1 to 95
-8 respectively.

Bit despreading circuits 95-1 to 95-8
Performs despreading of bits by an operation reverse to that of the bit spreading circuits 91-1 to 91-8 in FIG. 1 and outputs the obtained data u, v, x, y to the Viterbi decoder 103. I do.

The subsequent processing is the same as in FIG.

As described above, in each of the embodiments, the metric for the bit is calculated for each bit of the data, and the bit insertion process is performed on the bit of the data in accordance with a predetermined rule. A convolutional code is used as an error correction code, bit spreading is performed on a code sequence, and data transmitted by data modulation using the 16QAM method can be subjected to soft-decision processing. Decoding processing can be performed more accurately than when hard decision processing is performed as the closest symbol in coordinates.

In the above embodiment, the Viterbi decoder 1
6, a configuration including multiplication circuits 141-1 to 141-8 as shown in FIG. 6 is used.
It is also possible to adopt a configuration in which og is calculated and the obtained value is multiplied by (−1).

In the above embodiment, the data is modulated and demodulated by the 16QAM method.
The present invention can also be applied to a case where a multi-level multi-phase modulation scheme in which an I component and a Q component each correspond to two or more bits, such as 4QAM and 256QAM, is used.

[0196]

According to the data receiving apparatus of the first aspect or the data receiving method of the fifth aspect, bits constituting a data symbol are despread while retaining the coordinates of the symbol. Since a metric for each bit is calculated for each bit and the data is decoded, a convolutional code is used as an error correction code, bit spreading is performed on a code sequence, and a multi-level multi-phase method is used. It is possible to accurately decode digitally transmitted data.

According to the data receiving apparatus described in claim 3 or the data receiving method described in claim 6, for each bit of data, a metric for the bit is calculated, and the bits constituting the data symbol are despread. Since data decoding is performed, a convolutional code is used as an error correction code, bit spreading is performed on a code sequence, and data transmitted digitally modulated by a multi-level multi-phase method can be accurately calculated. Can be decoded.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a data transmission device.

FIG. 2 is a block diagram showing an example of a detailed configuration of a convolutional encoder 2 shown in FIG.

FIG. 3 is a diagram showing a state transition of the convolutional encoder 2 shown in FIG. 2;

FIG. 4 is a block diagram showing the configuration of a first embodiment of the data receiving apparatus of the present invention.

FIG. 5 is a block diagram illustrating a detailed configuration example of a metric calculation circuit illustrated in FIG. 4;

FIG. 6 is a block diagram illustrating a detailed configuration example of a Viterbi decoder illustrated in FIG. 4;

FIG. 7 is a block diagram showing a detailed configuration example of a path memory 144 shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a second embodiment of the data receiving apparatus of the present invention.

9 is a block diagram illustrating a detailed configuration example of a metric calculation circuit illustrated in FIG. 8;

FIG. 10 is a block diagram showing a configuration of a third embodiment of the data receiving apparatus of the present invention.

FIG. 11 is a block diagram illustrating a configuration example of a conventional data transmission device.

12 is a block diagram illustrating a configuration example of a convolutional encoder in FIG.

13 is a diagram illustrating a state transition of the convolutional encoder in FIG.

FIG. 14 is a diagram illustrating a signal point arrangement of QPSK.

FIG. 15 is a block diagram illustrating a configuration example of a conventional data receiving device.

16 is a block diagram illustrating a configuration example of a Viterbi decoder in FIG.

FIG. 17 is a block diagram illustrating a configuration example of a branch metric calculation circuit in FIG. 16;

FIG. 18 is a block diagram illustrating a configuration example of a path memory of FIG. 16;

FIG. 19 is a block diagram illustrating a configuration example of a data transmission device when 16QAM is used.

FIG. 20 is a diagram illustrating a signal point arrangement of 16QAM.

21 is a diagram illustrating a configuration example of a data receiving device that receives data transmitted by the device of FIG. 19;

FIG. 22 is a diagram for explaining the operation of the embodiment in FIG. 21;

[Explanation of symbols]

32 demodulator, 33 symbol despreading circuit, 38
Reproduction information, 101-1 to 101-4 bit despreading circuits, 102-1 to 102-4 metric calculation circuits, 103 Viterbi decoders, 111-1 to 111
-16 probability calculation circuit, 112, 113 addition circuit,
114 Division circuit

Claims (6)

[Claims] 1. A data receiving apparatus which uses a convolutional code as an error correction code, performs bit spreading on a code sequence, and receives data which has been digitally modulated by a multi-level multi-phase system and transmitted. Bit despreading means for despreading the bits making up the symbol of the symbol while maintaining the coordinates of the symbol; metric calculation means for calculating a metric for the bit for each bit of the data; and performing decoding processing of the data. A data receiving device, comprising: decoding means. 2. The data receiving apparatus according to claim 1, further comprising symbol despreading means for despreading the data symbols. 3. A data receiving apparatus, wherein a convolutional code is used as an error correction code, bit spreading is performed on a code sequence, and data transmitted after being digitally modulated by a multi-level multi-phase system is provided. Metric calculation means for calculating a metric for the bit, bit despreading means for despreading the bits constituting the data symbol, and decoding means for decoding the data. Characteristic data receiving device. 4. The data receiving apparatus according to claim 3, further comprising symbol despreading means for despreading the data symbols. 5. A data receiving method in which a convolutional code is used as an error correction code, bit spreading is performed on a code sequence, and data modulated and transmitted by a multi-level multi-phase system is received. A bit despreading step of despreading the bits forming the symbol of the symbol while retaining the coordinates of the symbol; a metric calculation step of calculating a metric for the bit for each bit of the data; and a decoding process of the data. A data receiving method comprising a decoding step. 6. A data receiving method in which a convolutional code is used as an error correction code, bit spreading is performed on a code sequence, and data modulated and transmitted by a multi-level multi-phase system is received. A metric calculation step of calculating a metric for the bit, a bit constituting a symbol of the data, a bit despreading step of despreading, and a decoding step of decoding the data. Characteristic data receiving method.