JP3606412B2 - Data receiving apparatus and method - Google Patents

Description

【０１３９】
ここで、Ｐ（ＳＩ_ｊ∩ＲＩ）は、集合を表すビット列の第ｉのビットｂ’ｉが０であるシンボルの集合ＳＩ_ｊに属するシンボルが送信され、かつ、受信信号Ｒが受信された確率を表し、ΣＰ（ＳＩ_ｊ∩ＲＩ）は、すべてのシンボルの集合ＳＩ_ｊに対する確率Ｐ（ＳＩ_ｊ∩ＲＩ）の総和を表している。
【０１４０】
ｂ’１＝０の場合（即ち、第１のビットに対するメトリックを算出する場合）、ΣＰ（ＳＩ_ｊ∩ＲＩ）は、Ｐ（ＳＩ００∩ＲＩ）＋Ｐ（ＳＩ０１∩ＲＩ）であり、ｂ’２＝０の場合（即ち、第３のビットに対するメトリックを算出する場合）、ΣＰ（ＳＩ_ｊ∩ＲＩ）は、Ｐ（ＳＩ００∩ＲＩ）＋Ｐ（ＳＩ１０∩ＲＩ）である。
【０１４１】
また、ΣＰ（ＳＩ_ｋ∩ＲＩ）は、シンボルに対する確率Ｐ（ＳＩ_ｋ∩ＲＩ）の総和を表している。今の場合、ΣＰ（ＳＩ_ｋ∩ＲＩ）は、Ｐ（ＳＩ００∩ＲＩ）＋Ｐ（ＳＩ０１∩ＲＩ）＋Ｐ（ＳＩ１１∩ＲＩ）＋Ｐ（ＳＩ１０∩ＲＩ）である。
【０１４２】
従って、図３の確率計算回路１１１−１は、Ｐ（ＳＩ００∩ＲＩ）、即ち、集合ＳＩ００に属するシンボル（１６ＱＡＭの００００、０００１、０１０１、および、０１００のいずれかに対応するシンボル）が送信され、受信信号Ｒを受信した事後確率を計算し、確率計算回路１１１−２は、Ｐ（ＳＩ０１∩ＲＩ）、即ち、集合ＳＩ０１に属するシンボル（１６ＱＡＭの００１０、００１１、０１１１、および、０１１０のいずれかに対応するシンボル）が送信され、受信信号Ｒを受信した事後確率を計算している。
【０１４３】
また、確率計算回路１１１−３は、Ｐ（ＳＩ１１∩ＲＩ）、即ち、集合ＳＩ１１に属するシンボル（１６ＱＡＭの１０１０、１０１１、１１１１、および、１１１０のいずれかに対応するシンボル）が送信され、受信信号Ｒを受信した事後確率を計算し、確率計算回路１１１−４は、Ｐ（ＳＩ１０∩ＲＩ）、即ち、集合ＳＩ１０に属するシンボル（１６ＱＡＭの１０００、１００１、１１０１、および、１１００のいずれかに対応するシンボル）が送信され、受信信号Ｒを受信した事後確率を計算している。
【０１４４】
そして、加算回路１１２−１は、式（６）の分子に対応して、集合ＳＩ００乃至ＳＩ１１のうち、第１のビットｂ’１が０のシンボル、即ち、ＳＩ００およびＳＩ０１に対する上述の事後確率の和を算出し、加算回路１１２−２は、式（６）の分子に対応して、集合ＳＩ００乃至ＳＩ１１のうち、第２のビットｂ’２が０のシンボル、即ち、ＳＩ００およびＳＩ１０に対する上述の事後確率の和を算出する。
【０１４５】
加算回路１１３は、式（６）の分母に対応して、集合ＳＩ００乃至ＳＩ１１に対する上述の事後確率の総和を求める。
【０１４６】
割算回路１１４−１は、式（６）に従って、加算回路１１２−１の出力を加算回路１１３の出力で割算し、シンボルの第１のビットに対するメトリックｕ’を算出し、割算回路１１４−２は、式（６）に従って、加算回路１１２−２の出力を加算回路１１３の出力で割算し、シンボルの第３のビットに対するメトリックｘ’を算出する。
【０１４７】
メトリック計算回路３９−２は、シンボルの第２のビットに対するメトリックｖ’（＝Ｐ（ｂ２＝０｜Ｒ））として、受信信号ＲのＱ成分ＲＱを表すビット列（例えば、集合ＳＱ００における００）の第１のビットｂ’１が０であるときの確率Ｐ（ｂ’１＝０｜ＲＱ）を出力し、シンボルの第４のビットに対するメトリックｙ’（＝Ｐ（ｂ４＝０｜Ｒ））として、受信信号ＲのＱ成分ＲＱを表すビット列の第２のビットｂ’２が０であるときの確率Ｐ（ｂ’２＝０｜ＲＱ）を出力する。
【０１４８】
即ち、１６ＱＡＭのシンボルの第２のビットに対するメトリックは、信号点００００，０００１，００１０，００１１，１０００，１００１，１０１０，１０１１に対応するシンボルＳａ０ｂｃ（ａ，ｂ，ｃは、０または１）に対する条件付き事後確率Ｐ（Ｓａ０ｂｃ｜Ｒ）の総和となるが、本実施例においては、最初に１６個のシンボルを、Ｑ成分の値に応じて４個の集合
ＳＱ００＝｛Ｓ００００，Ｓ００１０，Ｓ１０１０，Ｓ１０００｝，
ＳＱ０１＝｛Ｓ０００１，Ｓ００１１，Ｓ１０１１，Ｓ１００１｝，
ＳＱ１１＝｛Ｓ０１０１，Ｓ０１１１，Ｓ１１１１，Ｓ１１０１｝，
ＳＱ１０＝｛Ｓ０１００，Ｓ０１１０，Ｓ１１１０，Ｓ１１００｝
に分類し、次に、このうち、シンボルの第１のビットが０であるシンボルの集合ＳＱ００，ＳＱ０１（ｂ’１＝０）に対する事後確率Ｐ（ＳＱ００∩ＲＩ），Ｐ（ＳＱ０１∩Ｒ）の総和を、第２のビットに対するメトリックとして算出している。
【０１４９】
即ち、第２のビットに対するメトリックおよび第４のビットに対するメトリックは、次式に従って算出されている。
【０１５０】

【０１５１】
ここで、Ｐ（ＳＱ_ｊ∩ＲＱ）は、集合を表すビット列の第ｉのビットｂ’ｉが０であるシンボルの集合ＳＱ_ｊに属するシンボルが送信され、かつ、受信信号Ｒが受信された確率を表し、ΣＰ（ＳＱ_ｊ∩ＲＱ）は、すべてのシンボルの集合ＳＱ_ｊに対する確率Ｐ（ＳＱ_ｊ∩ＲＱ）の総和を表している。
【０１５２】
ｂ’１＝０の場合（即ち、第２のビットに対するメトリックを算出する場合）、ΣＰ（ＳＱ_ｊ∩ＲＱ）は、Ｐ（ＳＱ００∩ＲＱ）＋Ｐ（ＳＱ０１∩ＲＱ）であり、ｂ’２＝０の場合（即ち、第４のビットに対するメトリックを算出する場合）、ΣＰ（ＳＱ_ｊ∩ＲＱ）は、Ｐ（ＳＱ００∩ＲＱ）＋Ｐ（ＳＱ１０∩ＲＱ）である。
【０１５３】
また、ΣＰ（ＳＱ_ｋ∩ＲＱ）は、シンボルに対する確率Ｐ（ＳＱ_ｋ∩ＲＱ）の総和を表している。今の場合、ΣＰ（ＳＱ_ｋ∩ＲＱ）は、Ｐ（ＳＱ００∩ＲＱ）＋Ｐ（ＳＱ０１∩ＲＱ）＋Ｐ（ＳＱ１１∩ＲＱ）＋Ｐ（ＳＱ１０∩ＲＱ）である。
【０１５４】
なお、メトリック計算回路３９−２は、メトリック計算回路３９−１と同様に動作し、式（７）に従って、第２のビットに対するメトリックｖ’と第４のビットに対するメトリックｙ’の計算を行う。即ち、第２のビットに対するメトリックｖ’は、確率計算回路１２１−１により計算されたＳＱ００に対する事後確率と、確率計算回路１２１−２により計算されたＳＱ０１に対する事後確率の和を、確率計算回路１２１−１乃至１２１−４により計算されたＳＱ００乃至ＳＱ１１に対する事後確率の総和で除算して算出される。
【０１５５】
一方、第４のビットに対するメトリックｙ’は、確率計算回路１２１−１により計算されたＳＱ００に対する事後確率と、確率計算回路１２１−３により計算されたＳＱ１０に対する事後確率の和を、確率計算回路１２１−１乃至１２１−４により計算されたＳＱ００乃至ＳＱ１１に対する事後確率の総和で除算して算出される。
【０１５６】
なお、図３の確率計算回路１１１−１乃至１１１−４および図４の確率計算回路１２１−１乃至１２１−４における計算方法として、伝送路に応じて様々な方法が考えられるが、ガウス伝送路を仮定した場合には、例えば、確率計算回路１１１−１において、以下のように確率を計算することができる。

【０１５７】
ここで、σは伝送路の雑音電力の１／２の平方根を表す。即ち、２σ^２が伝送路の雑音電力を表す。‖ＳＩ００−ＲＩ‖は、シンボルの集合ＳＩ００のＩ成分の値と受信信号のＩ成分ＲＩの値とのユークリッド距離である。この場合、ＳＩ００のＩ成分の値とＲＩは、スカラであるので、‖ＳＩ００−ＲＩ‖は、｜ＳＩ００−ＲＩ｜（絶対値）と同一である。
【０１５８】
なお、式（８）の右辺の係数（１／（２π）^１／２σ）は、ビタビ復号器３７（復号手段）による最尤パスの選択に影響を与えないので、省略してもよい。その場合、確率Ｐ（ＳＩ００∩ＲＩ）は、次のように計算される。

【０１５９】
確率計算回路１１１−２乃至１１１−４においても、同様にして、上述の事後確率を計算することができる。
【０１６０】
以上のようにしてメトリック計算回路３９−１，３９−２により算出されたメトリックｕ’，ｖ’，ｘ’，ｙ’は、ビット逆拡散回路１０１−１乃至１０１−４によりビット逆拡散の処理を施された後、後段の並直列変換器３５で、図１７の直並列変換器４と逆の操作を行い、４系統のデータから１系列のデータに変換される。
【０１６１】
ビット挿入回路３６では、図１７のビット消去回路３と逆の操作が行われる。即ち、前述の例の消去マップ
Ｘ：１０
Ｙ：１１
を用いて、
ｕ１，ｖ１，ｘ１，ｙ１，ｕ２，ｖ２，ｘ２，ｙ２・・・
の順で入力されるデータに対して、３ビットを周期として、最後の３ビット目の直前に、任意のダミーデータ（ここでは０）を挿入して、
データＸとして、ｕ１，０，ｙ１，０，ｘ２，・・・
データＹとして、ｖ１，ｘ１，ｕ２，ｖ２，ｙ２，・・・
を、この順で出力するとともに、ダミーデータを挿入した位置を示す挿入フラグをビタビ復号器３７に供給する。
【０１６２】
ビタビ復号器３７では、畳み込み符号化器２の状態遷移に従ってビタビ復号を行い、再生情報３８を得る。次に、ビタビ復号器３７の動作について詳細に説明する。
【０１６３】
セレクタ１３４−１およびセレクタ１３４−３は、ビット挿入回路３６においてＸとしてダミーデータが挿入され、Ｘに対する挿入フラグが入力された場合、ダミーデータに対するメトリックの確率計算を無効にするため、値１を出力する。
【０１６４】
同様に、セレクタ１３４−２およびセレクタ１３４−４は、ビット挿入回路３６においてＹとしてダミーデータが挿入され、Ｙに対する挿入フラグが入力された場合、ダミーデータに対するメトリックの確率計算を無効にするため、値１を出力する。
【０１６５】
即ち、乗算回路１３２−１乃至１３２−４によるブランチメトリックの算出およびＡＣＳ回路１３３−１乃至１３３−４によりステートメトリックの算出は、すべて乗算によって行われているので（後述）、ダミーデータに対応して値１を出力することにより、メトリックの計算結果に影響を与えないようにしている。
【０１６６】
Ｘとしてダミーデータが挿入されていない場合においては、ビット挿入回路３６より供給された値Ｘが、セレクタ１３４−１を介して乗算回路１３２−１，１３２−２に供給され、値Ｘを反転した値が、乗算回路１３２−３，１３２−４に供給される。
【０１６７】
同様に、Ｙとしてダミーデータが挿入されていない場合においては、ビット挿入回路３６より供給された値Ｙが、セレクタ１３４−２を介して乗算回路１３２−１，１３２−３に供給され、値Ｙを反転した値が、乗算回路１３２−２，１３２−４に供給される。
【０１６８】
乗算回路１３２−１では、シンボルの第１のビットの値が０である確率または第３のビットの値が０である確率に対応するデータＸと、第２のビットの値が０である確率または第４のビットの値が０である確率に対応するデータＹの積（即ち、第１のビットの値が０であり、かつ、第２のビットの値が０である確率、あるいは、第３のビットの値が０であり、かつ、第４のビットの値が０である確率）を計算し、ブランチメトリックＢＭ００として出力する。このブランチメトリックＢＭ００は、畳み込み符号化器２の符号出力００に対応している。
【０１６９】
同様にして、乗算回路１３２−２は、シンボルの第１ビットの値が０である確率または第３のビットの値が０である確率に対応する値Ｘと、第２のビットの値が１である確率または第４のビットの値が１である確率に対応する値（値Ｙを反転した値）の積（即ち、第１のビットの値が０であり、かつ、第２のビットの値が１である確率、あるいは、第３のビットの値が０であり、かつ、第４のビットの値が１である確率）を計算し、ブランチメトリックＢＭ０１として出力する。このブランチメトリックＢＭ０１は、畳み込み符号化器２の符号出力０１に対応している。
【０１７０】
乗算回路１３２−３は、シンボルの第１のビットの値が１である確率または第３のビットの値が１である確率に対応する値（値Ｘを反転した値）と、第２のビットの値が０である確率または第４のビットの値が０である確率に対応する値Ｙの積（即ち、第１のビットの値が１であり、かつ、第２のビットの値が０である確率、あるいは、第３のビットの値が１であり、かつ、第４のビットの値が０である確率）を計算し、ブランチメトリックＢＭ１０として出力する。このブランチメトリックＢＭ１０は、畳み込み符号化器２の符号出力１０に対応している。
【０１７１】
乗算回路１３２−４は、シンボルの第１のビットの値が１である確率または第３のビットの値が１である確率に対応する値（値Ｘを反転した値）と、第２のビットの値が１である確率または第４のビットの値が１である確率に対応する値（値Ｙを反転した値）の積（即ち、第１のビットの値が１であり、かつ、第２のビットの値が１である確率、あるいは、第３のビットの値が１であり、かつ、第４のビットの値が１である確率）を計算し、ブランチメトリックＢＭ１１として出力する。このブランチメトリックＢＭ１１は、畳み込み符号化器２の符号出力１１に対応している。
【０１７２】
なお、ＸまたはＹとしてダミーデータが挿入されている場合、セレクタ１３４−１乃至１３４−４は、そのダミーデータの代わりに、１を選択するので、乗算回路１３２−１乃至１３２−４は、ダミーデータに対応しない入力の値を、そのまま（１を乗じて）、ブランチメトリックとして出力する。
【０１７３】
ＡＣＳ回路１３３−１は、畳み込み符号化器２の状態遷移（図９）に従って、次の２つの式の計算を行う。
ＳＭ００×ＢＭ００ （９）
ＳＭ０１×ＢＭ１１ （１０）
【０１７４】
ここでＳＭ００は、１単位時間前のステートメトリック記憶装置６６−１の値、ＳＭ０１は、１単位時間前のステートメトリック記憶装置６６−２の値、ＢＭ００は、乗算回路１３２−１の演算結果、ＢＭ１１は、乗算回路１３２−４の演算結果をそれぞれ表している。
【０１７５】
そして、ＡＣＳ回路１３３−１は、尤度の大きい方、すなわち、式（９）と式（１０）のうち、計算結果の大きい方を選択し、その選択情報ＳＥＬ００を後段のパスメモリ６５に出力するとともに、式（９）と式（１０）を計算して得られた結果のうち大きい方を、後段のステートメトリック記憶装置６６−１に供給し、記憶させる。すなわち式（９）の計算結果の方が大きければ、ＳＥＬ００＝０とし、式（１０）の計算結果の方が大きければ、ＳＥＬ００＝１とする。また、前者の場合、ＳＭ００×ＢＭ００が、後者の場合、ＳＭ０１×ＢＭ１１が、それぞれステートメトリック記憶装置６６−１に、新たなステートメトリックＳＭ００として記憶される。
【０１７６】
なお、ＡＣＳ回路１３３−２乃至１３３−４も同様に動作し、新たなステートメトリックＳＭ０１乃至ＳＭ１１を計算する。
【０１７７】
ビタビ復号器３７におけるその他の動作は、図１４における場合と同様であるので、その説明は省略する。
【０１７８】
なお、上述のメトリック計算回路３９−１，３９−２の出力の対数に−１を乗じた値をビット逆拡散回路１０１−１乃至１０１−４に供給し、さらに、ビタビ復号器３７におけるブランチメトリックおよびパスメトリックの算出を加算にで行うようにしてもよい。
【０１７９】
次に、本発明のデータ受信装置の第２の実施例について説明する。
【０１８０】
第２の実施例においては、メトリックの計算に使用する式およびメトリック計算回路３９−１，３９−２の構成が、第１の実施例のものと異なるだけであるので、メトリックに使用する式およびメトリック計算回路３９−１，３９−２についてだけ説明を行い、その他の構成要素の説明を省略する。
【０１８１】
図６は、第２の実施例のメトリック計算回路３９−１の構成例を示している。このメトリック計算回路３９−１においては、確率計算回路１１１−１により計算された、集合ＳＩ００に対する事後確率と、確率計算回路１１１−２により計算された、集合ＳＩ０１に対する事後確率の和を、第１のビットに対するメトリックｕ’として出力し、確率計算回路１１１−１により計算された、集合ＳＩ００に対する事後確率と、確率計算回路１１１−３により計算された、集合ＳＩ１０に対する事後確率の和を、第３のビットに対するメトリックｘ’として出力する。
【０１８２】
また同様に、第２の実施例の図示せぬメトリック計算回路３９−２においては、図４の確率計算回路１２１−１により計算された、集合ＳＱ００に対する事後確率と、確率計算回路１２１−２により計算された、集合ＳＱ０１に対する事後確率の和を、第２のビットに対するメトリックｖ’として出力し、確率計算回路１２１−１により計算された、集合ＳＱ００に対する事後確率と集合ＳＱ１０に対する事後確率の和を、確率計算回路１２１−３により計算された、第４のビットに対するメトリックｙ’として出力する。
【０１８３】
即ち、式（６）の分母ΣＰ（ＳＩ_ｋ∩ＲＩ）は、どのメトリックを算出する場合においても同一であり、最尤パスの選択に影響を与えないので、第２の実施例においては、式（６）の分子を、第１または第３のビットに対するメトリックとして利用している。
【０１８４】
同様に、式（７）の分母ΣＰ（ＳＱ_ｋ∩ＲＱ）は、どのメトリックを算出する場合においても同一であり、最尤パスの選択に影響を与えないので、第２の実施例においては、式（７）の分子を、第２または第４のビットに対するメトリックとして利用している。
【０１８５】
このように、式（６）および式（７）の分子をメトリックとして利用することにより、メトリックを算出する式が簡単になり、回路規模を小さくすることができる。
【０１８６】
なお、第１の実施例および第２の実施例におけるメトリック計算回路３９−１，３９−２は、図７に示すように、ＲＯＭ４２−１，４２−２を利用して実現することもできる。
【０１８７】
図７に示すメトリック計算回路３９−１においては、Ａ／Ｄ変換器４１は、シンボル逆変換回路３３より供給されたＩ成分Ｉ’の信号をデジタル値に変換し、そのデジタル値をＲＯＭ４２−１，４２−２に出力する。
【０１８８】
そして、ＲＯＭ４２−１は、供給されたデジタル値が指すアドレスに予め記憶されている値（即ち、Ｉ成分Ｉ’の値に対応する、第１のビットに対するメトリックｕ’）を出力し、ＲＯＭ４２−２は、供給されたデジタル値が指すアドレスに予め記憶されている値（即ち、Ｉ成分Ｉ’の値に対応する、第３のビットに対するメトリックｘ’）を出力する。
【０１８９】
なお、図７のメトリック計算回路３９−１と同様に、メトリック計算回路３９−２を、ＲＯＭとＡ／Ｄ変換器で構成してもよい。
【０１９０】
また、これらのＲＯＭには、第１の実施例におけるメトリックを、対応するアドレスに予め記憶させておく。あるいは、第２の実施例におけるメトリックを、予めＲＯＭに記憶させておいてもよい。
【０１９１】
図８は、本発明のデータ受信装置の第３の実施例の構成を示している。第３の実施例においては、第１の実施例または第２の実施例における２つのメトリック計算回路３９−１，３９−２の代わりに、並直列変換器５１、メトリック計算回路３９、および、直並列変換器５２が使用されている。
【０１９２】
並直列変換器５１は、シンボル逆拡散回路３３より２系列で供給されたＩ成分の信号Ｉ’およびＱ成分の信号Ｑ’を、１系列でメトリック計算回路３９に出力する。
【０１９３】
メトリック計算回路３９は、上述のメトリック計算回路３９−１，３９−２と同様に構成されており、Ｉ成分の信号Ｉ’が供給されると、シンボルの第１のビットに対するメトリックｕ’と第３のビットに対するメトリックｘ’を計算し、その計算結果を直並列変換器５２に出力し、Ｑ成分の信号Ｑ’が供給されると、シンボルの第２のビットに対するメトリックｖ’と第４のビットに対するメトリックｙ’を計算し、その計算結果を直並列変換器５２に出力する。
【０１９４】
そして、直並列変換器５２は、メトリック計算回路３９より供給されたメトリックｕ’，ｘ’またはｖ’，ｙ’を、第１のビットおよび第３のビットに対するメトリック、または、第２のビットおよび第４のビットに対するメトリックとしてビット逆拡散回路１０１−１，１０１−３または１０１−２，１０１−４にそれぞれ出力する。
【０１９５】
このようにして、第３の実施例においては、メトリック計算回路３９を１個だけ使用して、第１のビット乃至第４のビットに対するメトリックを計算するので、回路規模を小さくすることができる。
【０１９６】
上記実施例においては、１６ＱＡＭ方式でデータを変調し、復調するようにしたが、このほか、６４ＱＡＭ、２５６ＱＡＭなどの、Ｉ成分とＱ成分が、それぞれ２以上のビットに対応する多値多位相変調方式を採用する場合においても、本発明を適用することが可能である。
【０１９７】
【発明の効果】
以上のごとく、請求項１に記載のデータ受信装置および請求項４に記載のデータ受信方法によれば、Ｉ成分およびＱ成分のうちの少なくとも一方に対して、その成分の値が同一であるシンボルの集合毎に、シンボルが伝送され、かつ、そのシンボルが受信された事後確率を計算し、その成分を表すビットのうちの１つが所定の値であるシンボルの集合に対する事後確率の総和を、すべてのシンボルの集合に対する事後確率の総和で除した値を、その１つのビットに対するメトリックとして計算するようにしたので、簡単な回路でメトリックを計算し、Ｉ成分とＱ成分がそれぞれ２ビット以上に対応する多値多位相変調方式で伝送されてきたデータを正確に復号化することができる。
【０１９８】
請求項５に記載のデータ受信装置および請求項８に記載のデータ受信方法によれば、Ｉ成分およびＱ成分のうち少なくとも一方に対して、その成分の値が同一であるシンボルの集合毎に、シンボルが伝送され、かつ、そのシンボルが受信された事後確率を計算し、その成分を表すビットのうちの１つが所定の値であるシンボルの集合に対する事後確率の総和を、その１つのビットに対するメトリックとして計算するようにしたので、さらに簡単な回路でメトリックを計算し、Ｉ成分とＱ成分がそれぞれ２ビット以上に対応する多値多位相変調方式で伝送されてきたデータを正確に復号化することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施例の構成例を示すブロック図である。
【図２】１６ＱＡＭの信号点についてＩ成分またはＱ成分の値が同一であるシンボルの集合を示す図である。
【図３】図１のメトリック計算回路３９−１の構成例を示すブロック図である。
【図４】図１のメトリック計算回路３９−２の構成例を示すブロック図である。
【図５】図１のビタビ復号器の構成例を示すブロック図である。
【図６】本発明の第２の実施例のメトリック計算回路の構成例を示すブロック図である。
【図７】メトリック計算回路の他の構成例を示すブロック図である。
【図８】本発明の第３の実施例の構成を示すブロック図である。
【図９】従来のデータ送信装置の構成例を示すブロック図である。
【図１０】図９の畳み込み符号化器の構成例を示すブロック図である。
【図１１】図１０の畳み込み符号化器の状態遷移を説明する図である。
【図１２】ＱＰＳＫの信号点配置を説明する図である。
【図１３】従来のデータ受信装置の構成例を示すブロック図である。
【図１４】図１３のビタビ復号器の構成例を示すブロック図である。
【図１５】図１４のブランチメトリック演算回路の構成例を示すブロック図である。
【図１６】図１４のパスメモリの構成例を示すブロック図である。
【図１７】１６ＱＡＭを用いた場合のデータ送信装置の構成例を示すブロック図である。
【図１８】１６ＱＡＭの信号点配置を説明する図である。
【図１９】図１７の装置で送信したデータを受信するデータ受信装置の構成例を示す図である。
【図２０】図１９の実施例の動作を説明する図である。
【符号の説明】
３２ 復調器， ３３ シンボル逆拡散回路， ３５ 並直列変換器， ３６ビット挿入回路， ３７ ビタビ復号器， ３８ 再生情報， ３９，３９−１，３９−２ メトリック計算回路， ４１ Ａ／Ｄ変換器， ４２−１，４２−２ ＲＯＭ， １０１−１乃至１０１−４ ビット逆拡散回路， １１１−１乃至１１１−４ 確率計算回路， １１２−１，１１２−２ 加算回路， １１３ 加算回路， １１４−１，１１４−２ 割算回路， １２１−１乃至１２１−４ 確率計算回路， １２２−１，１２２−２ 加算回路， １２３ 加算回路， １２４−１，１２４−２ 割算回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data receiving apparatus and method, and in particular, calculates a posterior probability that a symbol is transmitted and the symbol is received for each set of symbols having the same value of the I component or the Q component, and The present invention relates to a data receiving apparatus and method for calculating a sum of posterior probabilities for a set of symbols in which one of bits representing a component has a predetermined value as a metric for the one bit.
[0002]
[Prior art]
In the United States, digital broadcasting has already started. Even in Europe, in order to introduce digital TV broadcasting, a standardized organization Digital Video Broadcasting (DVB) has been formed and its standard system is being compiled. This digital broadcasting is introduced, for example, on pages 139 to 151 of Nikkei Electronics 1996.1.15 (no. 653) as “Digital broadcasting, Europe will be put to practical use after the US”.
[0003]
When performing digital broadcasting, it is desirable to reduce the power consumption as much as possible. In such a communication channel with severe power limitation, generally, an encoding gain is obtained using an error correction code to reduce power. In such a system, error correction coding is generally performed on the transmission side, and error correction decoding is performed on the reception side. In particular, a convolutional code is advantageous in a communication channel with a small signal power to noise power ratio (C / N ratio), and this code can easily perform soft decision decoding by using the Viterbi decoding method. Gain can be obtained.
[0004]
Further, there is known a punctured code that can easily realize a plurality of coding rates using the same decoder by thinning out a code output sequence of a convolutional encoder according to a certain rule. Further, by spreading the code output sequence of the punctured encoder for each bit according to a certain rule, it is possible to improve resistance to noise superimposed on the transmission path.
[0005]
FIG. 9 shows a configuration example of a transmission apparatus proposed in the standard DVB-T for DVB terrestrial television broadcasting. In this apparatus, a punctured convolutional code, bit spreading, and a QPSK modulation method are used.
[0006]
In other words, in the example of FIG. 9, the 1-bit serial data output from the information source 1 is input to the convolutional encoder 2 to generate punctured code mother code sequences X and Y. In this example, the coding rate is ½. X and Y each represent a 1-bit code sequence.
[0007]
The code sequences X and Y are input to the bit erasure circuit 3 and are subjected to bit erasure processing according to a predetermined rule. The serialized punctured code sequence output from the bit erasure circuit 3 is input to the serial-parallel converter 4 so as to be converted from one series of data to two series of data.
[0008]
The two series of data x and y output from the serial / parallel converter 4 are input to the bit spreading circuits 5-1 and 5-2, respectively, so that bit spreading processing is performed in which the order of bits is spread (interlaced). Has been made. Bit spread data x ′ and y ′ output from the bit spread circuits 5-1 and 5-2 are input to the signal point assignment circuit 6 and assigned to symbols on the transmission path. The signal point assignment circuit 6 outputs coordinate data I ′ and Q ′ of signal points represented by an in-phase component (I component) and a quadrature component (Q component) that are orthogonal to each other.
[0009]
The symbol spreading circuit 7 executes symbol spreading processing for spreading the order of symbols defined by the coordinate data I ′ and Q ′ output from the signal point assigning circuit 6, and calculates the I and Q components of the spread symbols. Output. The modulator 8 is configured to digitally modulate an I component and a Q component, for example, by an OFDM (Orthogonal Frequency Division Multiplex) method, and output the result via an antenna 9 as a radio wave.
[0010]
FIG. 10 shows a configuration example of the convolutional encoder 2. However, this configuration example is not defined by DVB-T, and shows a principle configuration for explaining the convolution process. In this example, 1-bit serial data output from the information source 1 is input from the terminal 21, and sequentially delayed by one clock by the delay circuits 22 and 23, and then output to the adder circuits 24 and 25. ing. The adder circuit 24 is also supplied with the output of the terminal 21 and the output of the delay circuit 22. The adder circuit 24 adds these data (exclusive OR operation) and then outputs the data X from the terminal 26. It is designed to output. The adder circuit 25 adds the output of the terminal 21 and the output of the delay circuit 23 (exclusive OR operation) and outputs the result as data Y from the terminal 27.
[0011]
That is, in this embodiment, for a 1-bit input, a 2-bit mother code determined from the internal state of the delay circuits 22 and 23 is output. In this example, the constraint length is 3, the internal delay element is 2, the number of states is 4, and the coding rate is 1/2.
[0012]
FIG. 11 shows a state transition diagram of the convolutional encoder 2. The state transition of the convolutional encoder 2 is as follows.
[0013]
That is, for example, when 0 is input from the terminal 21 in the state 00 (the output of the delay element 22 and the output of the delay element 23 are both 0), (XY) = (00) is output from the terminals 26 and 27. Is output and transitions to state 00. When 1 is input from state 00, (XY) = (11) is output and the state transitions to 10. When 0 is input from state 01, (XY) = (11) is output and the state transitions to state 00. When 1 is input from the state 01, (XY) = (00) is output, and the state transitions to the state 10.
[0014]
Also in other states, as shown in FIG. 11, the illustrated output is output in response to the input of 0 or 1, and the state transits to the illustrated state.
[0015]
The bit erasing circuit 3 can change the coding rate as a result by erasing data at an appropriate position from the mother code sequence (XY) according to a certain rule. Below, for example,
X: 10
Y: 11
A case where bits are erased according to the erase map as described above will be described.
[0016]
The bit corresponding to 1 in the erasure map is transmitted, and the bit corresponding to 0 is not transmitted (erased). According to the erasure map, the outputs X (= X1) and Y (= Y1) of the convolutional encoder 2 at a certain time are transmitted in the order of X1Y1, and at the next time, the output X of the convolutional encoder 2 is transmitted. (= X2) is erased and not transmitted, and only Y (= Y2) is transmitted. That is, the bits transmitted at these two times are X1Y1Y2. With this operation, the number of bits input to the convolutional encoder 2 is 2 bits, and the number of bits output from the bit erasure circuit 3 is 3 bits, so that the coding rate R is 2/3. This operation is repeated every two unit times.
[0017]
In the serial-parallel converter 4, the input one series of data X1, Y1, Y2,... Is converted into two series of data (x, y).
[0018]
The bit spreading circuits 5-1 and 5-2 spread the bits by changing the order of the input data series x and y according to a predetermined rule. At this time, generally, the spreading methods of the bit spreading circuits 5-1 and 5-2 are different.
[0019]
An example of bit diffusion is shown below. An M-bit input data is defined as one block, and an appropriate numerical value s is determined. Bit spread is a vector consisting of an M-bit input sequence
From (B0, B1, ..., Bk, ..., BM-1),
Vector consisting of M-bit output sequence after spreading
Meaning substitution to (B′0, B′1,..., B′n,..., B′M−1). At this time, B′n = Bk (n = k + s mod M).
[0020]
By using different s in the bit spreading circuits 5-1 and 5-2, different bit spreading circuits can be configured with the same algorithm.
[0021]
The signal point assignment circuit 6 assigns the input data (x ′, y ′) to the symbols on the transmission path. The assignment is performed according to the QPSK method, for example, as shown in FIG. That is,
When (x ′, y ′) = (0, 0), (I ′, Q ′) = (1 / √2, 1 / √2),
When (x ′, y ′) = (0, 1), (I ′, Q ′) = (1 / √2, −1 / √2),
When (x ′, y ′) = (1, 0), (I ′, Q ′) = (− 1 / √2, 1 / √2),
When (x ′, y ′) = (1, 1), (I ′, Q ′) = (− 1 / √2, −1 / √2)
Is assigned as
[0022]
The symbol spreading circuit 7 performs symbol spreading by replacing the order of the symbols S ′ represented by (I ′, Q ′) according to a predetermined rule to obtain the symbols S (I, Q). Thereby, burst errors received on the transmission path can be diffused.
[0023]
To give a specific example, when N-1 symbols are used as a unit block for spreading and a number G that is less than N and relatively prime to N is determined, spreading is a vector whose elements are symbols before spreading.
From (S′1, S′2,..., S′k,..., S′N−1)
A vector whose elements are the symbols after spreading
It is executed as a replacement to (S1, S2,..., Sn,..., SN-1). At this time, Sn = S′k (n = G ^ k mod N).
[0024]
In the modulator 8, the carrier wave is modulated according to the I component and Q component of the input symbol S and transmitted via the antenna 9.
[0025]
FIG. 13 illustrates a configuration example of a receiving device that receives data transmitted from the transmitting device in FIG. 9. The demodulator 32 demodulates the radio wave received via the antenna 31 and outputs an I component signal and a Q component signal. The symbol despreading circuit 33 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 9, that is, a process for returning the order of the symbols replaced in the symbol spreading circuit 7 to the original order, and the I signal component I ′ And Q signal component Q ′.
[0026]
The bit despreading circuits 34-1 and 34-2 are the bits changed in the bit spreading circuits 5-1 and 5-2 of FIG. 9 with respect to the I ′ signal and the Q ′ signal output from the symbol despreading circuit 33. The process of returning the order to the original order is executed.
[0027]
The data x corresponding to the I ′ signal component output from the bit despreading circuits 34-1 and 34-2 and the data y corresponding to the Q ′ signal component are input to the parallel-serial converter 35, and two series of data (X, y) is converted into one series of data and supplied to the bit insertion circuit 36.
[0028]
In the bit insertion circuit 36, a bit insertion process is performed opposite to the bit erase process in the bit erase circuit 3 of FIG. The bit insertion circuit 36 inputs the I-signal component data x and the Q-signal component data y into which the bits are inserted, and the Viterbi decoder 37 performs Viterbi decoding and outputs the reproduced information 38. .
[0029]
Next, the operation will be described.
[0030]
The received signal received by the antenna 31 is demodulated by the demodulator 32 to obtain I component and Q component data of each symbol. The data of the I component and the Q component is input to the symbol despreading circuit 33, where an operation reverse to that in the symbol spreading circuit 7 is performed to obtain despread data I ′ and Q ′.
[0031]
That is, when this despreading operation is expressed using the same values N and G as those used in the symbol spreading circuit 7, it is a vector whose elements are symbols before despreading.
(S1, S2,..., Sn,..., SN-1)
A vector whose elements are symbols after despreading
This is a process of replacing (S′1, S′2,..., S′k,..., S′N−1). At this time, Sn = S′k (n = G ^ k mod N).
[0032]
The I component data I ′ and Q component data Q ′ supplied from the symbol despreading circuit 33 are supplied to the bit despreading circuits 34-1 and 34-2, respectively.
[0033]
The bit despreading circuits 34-1 and 34-2 correspond to the bit spreading circuits 5-1 and 5-2, respectively, and perform operations reverse to those of the bit spreading circuits 5-1 and 5-2, respectively.
[0034]
That is, M input data is set as one block, an appropriate numerical value s is determined, and a vector composed of M input sequences
From (B′0, B′1,..., B′n,..., B′M−1),
Vector consisting of M output sequences after despreading
(B0, B1,..., Bk,..., BM-1) are obtained. At this time, B′n = Bk (n = k + s mod M).
[0035]
Here, the numerical value s used in the bit despreading of the bit despreading circuits 34-1 and 34-2 is the same value as the numerical value s used in the bit spreading circuits 5-1 and 5-2, respectively.
[0036]
The data sequence (x, y) that has been bit-despread in this way is supplied to the parallel-to-serial converter 35 of the next stage, where the reverse operation of the serial-to-parallel converter 4 is performed, and two series of data (x, y). To one series of data.
[0037]
In the bit insertion circuit 36, an operation reverse to that of the bit erasure circuit 3 is performed. That is, the erase map in the previous example
X: 10
Y: 11
In response to the processing of the bit erasing circuit 3 using
X1, Y1, Y2 (in this case, x1, y1, y2)
For the data input in this order, arbitrary dummy data (here, 0) is inserted at a position corresponding to the erased data X2 (x2),
As X data, X1 (x1), 0 is
As Y data, Y1 (y1), Y2 (y2) are
Output in this order. Further, an insertion flag indicating the position where the dummy data is inserted is supplied to the Viterbi decoder 37.
[0038]
The Viterbi decoder 37 performs Viterbi decoding according to the state transition of the convolutional encoder 2 (FIG. 11). FIG. 14 shows an example of the Viterbi decoder 37. Data X and Y output from the bit insertion circuit 36 are input to the input terminals 62-1 and 62-2, respectively. These data X and Y are input to the branch metric calculation circuits 63-1 to 63-4. In the branch metric calculation circuit 63-1, the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) shown in FIG. 12 is calculated as a branch metric. Similarly, in the branch metric calculation circuits 63-2 to 63-4, the input data (X, Y) and the coordinate points (1 / √2, −1 / √2), (−1 / √2, 1 / √). 2) or (−1 / √2, −1 / √2) is calculated.
[0039]
The outputs (branch metrics) BM00 and BM11 of the branch metric calculation circuits 63-1 and 63-4 are input to ACS (Add Compare Select) circuits 64-1 and 64-3. Similarly, the output (branch metric) BM01 of the branch metric calculation circuit 63-2 and the output (branch metric) BM10 of the branch metric calculation circuit 63-3 are input to the ACS circuits 64-2 and 64-4.
[0040]
The ACS circuits 64-1 and 64-3 also receive the output (state metric) SM00 of the state metric storage device 66-1 and the output (state metric) SM01 of the state metric storage device 66-2. 64-2 and 64-4 are supplied with the output (state metric) SM10 of the state metric storage device 66-3 and the output (state metric) SM11 of the state metric storage device 66-4.
[0041]
The ACS circuits 64-1 to 64-4 add one input branch metric BM and the corresponding state metric SM, and add the other branch metric BM and the corresponding state metric SM. Then, the ACS circuits 64-1 to 64-4 compare the two addition results, and in response to the comparison result, the smaller addition value is newly stored in the state metric storage devices 66-1 to 66-4. While outputting as the state metric SM, signals SEL00 to SEL11 representing the selection results are output to the path memory 65. Further, state metrics SM00 to SM11 are input to the path memory 65 from the state metric storage devices 66-1 to 66-4.
[0042]
The state metric storage devices 66-1 to 66-4 are reset by a signal input from the terminal 61. The path memory 65 is configured to output a decoding result from a terminal 67.
[0043]
Next, the operation will be described.
[0044]
In the branch metric calculation circuit 63-1, the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) is calculated as the branch metric BM00. Similarly, in the branch metric calculation circuit 63-2, the distance between the input data (X, Y) and the coordinate point (1 / √2, −1 / √2), and in the branch metric calculation circuit 63-3, the input data (X, Y). ) And the coordinate point (−1 / √2, 1 / √2), the branch metric calculation circuit 63-4 uses the input data (X, Y) and the coordinate point (−1 / √2, −1 / √2). ) Are calculated as branch metrics BM01, BM10, and BM11, respectively. Here, the distance calculation for the inserted dummy data is omitted according to the insertion flag supplied from the bit insertion circuit 36 at the preceding stage. That is, the distance between the inserted bit and the coordinate to be compared is all the same (for example, 0).
[0045]
The ACS circuit 64-1 calculates the following two expressions according to the state transition of the convolutional encoder 2, and selects the one with the highest likelihood, that is, the one with the smaller calculation result, and the selection information SEL is the path memory in the subsequent stage. In 65, the calculation result SM is supplied to the state metric storage device 66-1.
[0046]
SM00 + BM00 (1)
SM01 + BM11 (2)
[0047]
Here, SM00 is a value of the state metric storage device 66-1 one unit time ago, SM01 is a value of the state metric storage device 66-2 one unit time ago, and BM00 is a value of the branch metric calculation circuit 63-1. The calculation result, BM11, represents the calculation result of the branch metric calculation circuit 63-4.
[0048]
If the calculation result of Expression (1) is smaller, SEL00 = 0 is supplied to the subsequent path memory 65, and if the calculation result of Expression (2) is smaller, SEL00 = 1 is supplied. In the former case, SM00 + BM00 is stored, and in the latter case, SM01 + BM11 is stored as a new state metric SM00 in the state metric storage device 66-1.
[0049]
This calculation will be described with reference to the state transition diagram of FIG. There are two paths that reach state 00. The first is a path that receives 0 in state 00 and outputs 00, and the calculation expression to be compared is as shown in equation (1), and the second is in state 01. In a path in which 0 is input and 11 is output, a calculation expression to be compared is as shown in Expression (2). The smaller of the calculation results is supplied as new state metric SM00 to state metric storage device 66-1.
[0050]
Similar operations are performed in the ACS circuits 64-2 to 64-4. Note that the state metric storage devices 66-1 to 66-4 are reset to 0 at the initial stage when the system operates. This control is performed via a terminal 61 from a control device (not shown).
[0051]
The path memory 65 selects, stores, and propagates input data, that is, decoded data, using selection information SEL00 to SEL11 from the ACS circuits 64-1 to 64-4 according to the state transition diagram of FIG.
[0052]
FIG. 15 illustrates a configuration example of the branch metric calculation circuit 63-1. The data X input from the terminal 62-1 is input to the subtraction circuit 51 and is subtracted by 1 / √2 from the generation circuit 52. The output of the subtracting circuit 51 is branched and input to the multiplying circuit 53 and multiplied (ie, squared). The selector 203 receives the output of the multiplication circuit 53 and the output of the generation circuit 202. When the insertion flag for X is input from the bit insertion circuit 36 via the terminal 201, the selector 203 generates 0 generated by the generation circuit 202. In other cases, the output of the multiplication circuit 53 is selected and output to the addition circuit 54.
[0053]
Similarly, the data Y input from the terminal 62-2 is input to the subtraction circuit 55 and is subtracted by 1 / √2 from the generation circuit 56. The output of the subtracting circuit 55 is branched and input to the multiplying circuit 57, and is multiplied (squared). The selector 206 receives the output of the multiplication circuit 57 and the output of the generation circuit 205, and selects 0 generated by the generation circuit 205 when the insertion flag for Y is input from the bit insertion circuit 36 via the terminal 204. At other times, the output of the multiplication circuit 57 is selected and output to the addition circuit 54. The adder circuit 54 adds the output of the selector 203 and the output of the selector 206 and outputs the result as a branch metric BM00.
[0054]
That is, in this example, when the insertion flag is not input, the subtracting circuit 51 outputs X−1 / √2, which is squared by the multiplying circuit 53 and is output from the multiplying circuit 53 (X−1 / √2). ) ² Is output. Similarly, the subtracting circuit 55 outputs Y−1 / √2, and this value is squared by the multiplying circuit 57, and the multiplying circuit 57 is (Y−1 / √2). ² Is output. The adder circuit 54 is an addition value (X−1 / √2) of the output of the multiplier circuit 53 and the output of the multiplier circuit 57. ² + (Y-1 / √2) ² Is output as the branch metric BM00.
[0055]
On the other hand, when the insertion flag for X is input, the selector 203 outputs 0, so the output of the adder circuit 54 is (Y−1 / √2). ² When the insertion flag for Y is input, the selector 206 outputs 0, so that the output of the adder circuit 54 is (X−1 / √2) ² It becomes.
[0056]
In the branch metric calculation circuits 63-2 to 63-4, the same calculation is performed by a circuit having the same configuration as that shown in FIG. However, in the branch metric calculation circuit 63-2, the output of the generation circuit 52 is 1 / √2, and the output of the generation circuit 56 is −1 / √2. In the branch metric calculation circuit 63-3, the outputs of the generation circuits 52 and 56 are -1 / √2 and 1 / √2, respectively. In the branch metric calculation circuit 63-4, -1 / √√ respectively. 2 and -1 / √2.
[0057]
FIG. 16 shows a block diagram of the path memory 65. The selection information SEL00 to SEL11 output from the ACS circuits 64-1 to 64-4 is input to the terminals 71-1 to 71-4. These selection information SEL00 to SEL11 are input as control signals to the two-input one-output selectors 73-1 to 73-4, respectively. The selector 73-1 receives fixed data 0 from the terminal 72-1 as two inputs. Similarly, fixed data 0, 1 or 1 is input to the selectors 73-2 to 73-4 as two inputs from the terminals 72-2 to 72-4, respectively.
[0058]
The selectors 73-1 to 73-4 select one of the two inputs corresponding to the selection information SEL00 to SEL11 and output the selected input to the subsequent registers 81-1 to 81-4. However, since the same data is input to the first column selectors 73-1 to 73-4 as two inputs from the terminals 72-1 to 72-4 as described above, the register 81-1 Through 81-4, 0, 0, 1 or 1 is stored, respectively.
[0059]
Hereinafter, similarly, a configuration including selectors and registers of n columns (four columns in the case of FIG. 16) is provided. That is, in the second column, selectors 74-1 to 74-4 and registers 82-1 to 82-4 are provided. The selectors 74-1 and 74-3 are supplied with the output of the register 81-1 in the previous column and the output of the register 81-2. The outputs of the register 81-3 and the register 81-4 are input to the selectors 74-2 and 74-4. Then, the selectors 74-1 to 74-4 select one of the two inputs corresponding to the values of the selection information SEL00 to SEL11, and perform processing to output to the subsequent registers 82-1 to 82-4. . For example, the register 74-1 selects the output of the register 81-1 when the selection information SEL00 is 0, and selects and outputs the output of the register 81-2 when the selection information SEL00 is 1. Has been made.
[0060]
The outputs of the registers 84-1 to 84-4 in the final column are input to the selector 85 having four inputs and one output.
[0061]
State metrics SM00 to SM11 output from the state metric storage devices 66-1 to 66-4 in FIG. 14 are input to the minimum value comparison circuit 88 from terminals 87-1 to 87-4. The minimum value comparison circuit 88 compares the sizes of the four state metrics and selects the smallest one. When the state metric SM00 is minimum, the data 00 is output. When the state metric SM01 is minimum, the data 01 is output. When the state metric SM10 is minimum, the data 10 is output. When the state metric SM11 is minimum, data 11 is output. The selector 85 selects the output of the register 84-1 when the input from the minimum value comparison circuit 88 is 00, selects the output of the register 84-2 when it is 01, and selects the register 84 when it is 10. -3 is selected. When the output is 11, the output of the register 84-4 is selected and output from the terminal 86 as a decoding result. The fixed values of the terminals 72-1 to 72-4 mean the decoding information corresponding to each pixel.
[0062]
Such connection of the path memory 65 is based on the state transition diagram of FIG. In the configuration of the path memory 65, the top row corresponds to the state 00, the second row corresponds to the state 01, the third row corresponds to the state 10, and the bottom row corresponds to the state 11. In the first column, decoding information is fetched. According to FIG. 11, there are two paths from state 00 and state 01 to reach state 00. The input bit corresponding to each path, that is, the decoding information is 0 in all cases. Therefore, in the first column in the state 00 (top row), the input terminal of the selector 73-1 is wired so that the corresponding decoding information 0 is selected by the selection information SEL00.
[0063]
In the first column, connection is made in the same manner for the state 01, the state 10 and the state 11.
[0064]
In the second and subsequent columns, selection, propagation, and storage of decoded sequences are performed. According to FIG. 11, there are two paths from state 00 and state 01 to reach state 00. Therefore, in the second column in the state 00, the input terminal of the selector 74-1 is wired so that the data from the corresponding state is selected by the selection information SEL00.
[0065]
In the second and subsequent rows, the wiring is similarly performed. Further, in the state 01, the state 10, and the state 11 in the second to third rows, the wiring is similarly performed.
[0066]
In the last column of the path memory 65, data corresponding to the path with the highest likelihood is output as final decoded data from the four stored decoded data. The “maximum likelihood path” is a path corresponding to the one having the minimum value among the four state metrics SM00 to SM11. The selector 85 uses the path corresponding to the minimum value of the state metric at that time. That is, the path with the highest likelihood is selected.
[0067]
[Problems to be solved by the invention]
By the way, in recent years, while high-speed (high bit rate) transmission is screamed, it is conceivable to expand the modulation method of the digital data transmission system from QPSK to 16QAM, 64QAM, 256QAM, and the like. In this way, the number of bits that can be transmitted is 4 bits, 6 bits, or 8 bits for 2 bits of QPSK, respectively, and increases 2 times, 3 times, and 6 times that of QPSK.
[0068]
FIG. 17 shows a block diagram of a 16QAM data transmission apparatus. In FIG. 17, portions corresponding to those in FIG. 9 are denoted by the same reference numerals. That is, in this example, the serial / parallel converter 4 converts the serial data output from the bit erasure circuit 3 into data u, v, x, y in units of 4 bits. Then, bit diffusion processing is performed for each data in the bit diffusion circuits 91-1 to 91-4, and the data is supplied to the signal point assignment circuit 6 as data u ′, v ′, x ′, y ′. Has been made. Other configurations are the same as those in FIG.
[0069]
In other words, in this example, the series-parallel converter 4 converts one series of data into four series of data (u, v, x, y) corresponding to 16QAM, which are bit spreading circuits 91-1 through 91, respectively. In -4, bit diffusion processing is performed by changing the order of bits according to a predetermined rule. The processing is the same as the processing in the bit spreading circuits 5-1 and 5-2 in FIG. 9, and different bit spreading processing is executed using different numerical values s.
[0070]
The signal point assignment circuit 6 assigns the input 4-bit data (u ′, v ′, x ′, y ′) to the symbols on the transmission path. The assignment is performed, for example, according to FIG. That is, for example,
When (u ′, v ′, x ′, y ′) = (0, 0, 0, 0),
(I ′, Q ′) = (3 / √10, 3 / √10),
When (u ′, v ′, x ′, y ′) = (0, 0, 0, 1),
(I ′, Q ′) = (3 / √10, 1 / √10)
Is assigned as
[0071]
Similar assignments are made for other inputs.
[0072]
Thereafter, the same processing as in FIG. 9 is performed, and data is transmitted.
[0073]
When the transmitting apparatus shown in FIG. 17 performs signal point allocation by the 16QAM system as shown in FIG. 18 and receives the transmitted data, the receiving apparatus is configured as shown in FIG. 19 corresponding to FIG. It is possible. However, actually, the receiving apparatus cannot be configured as shown in FIG.
[0074]
That is, as described above, the components I and Q of the data (I and Q) input from the demodulator 32 to the symbol despreading circuit 33 each represent 1 bit in the QPSK system. In the case of the 16QAM system, each represents 2 bits. For example, in the case of the signal point arrangement shown in FIG. 18, I represents the data of the first bit and the third bit, and Q represents the data of the second bit and the fourth bit. However, for example, I is a single value such as 1 / √10 or 3 / √10, and Q is also a single value. Therefore, as shown in FIG. 19, it cannot be divided into u ′ and v ′ or into x ′ and y ′. As a result, the data receiving apparatus in the case of the 16QAM system is also configured as shown in FIG.
[0075]
As a result, the processing performed in the bit insertion circuit 36 of FIG. 13 is considered as follows.
[0076]
For example, as shown in FIG. 20A, if data is input to the bit insertion circuit 36 as x1, y1, x2, y2, x3, y3,... As described above, x1 and y1 are output as data X1 and Y1, then dummy data d is output as data X2, and data x2 is output as data Y2. Similarly, after data y2 and x3 are output as data X3 and Y3, dummy data d is output as data X4, and then data y3 is output as data Y4.
[0077]
However, this process does not execute the reverse process of the process in the bit erasing circuit 3 of FIG. That is, the bit erasure (bit operation) processing performed in the bit erasure circuit 3 is performed in units of 1 bit. On the other hand, the data x1, y2, etc. shown in FIG. 20B each correspond to 2-bit data, after which 1-bit dummy data d is inserted, and then When 2-bit data x2 is output, a data array that is completely different from the original data array is output.
[0078]
As a result, when the Viterbi decoder 37 viterbi-decodes the output of the bit insertion circuit 36, the decoding results are not such that the components are slightly degraded, and are completely different, so that decoding is impossible.
[0079]
On the other hand, if a hard decision is made in the symbol despreading circuit 33 of the data receiving apparatus shown in FIG. 19, for example, from (I, Q), u ′, v ′, It is considered that x ′ and y ′ can be generated. That is, in this case, the distance between the coordinates of (I, Q) and each signal point shown in FIG. 18 is calculated, and (I, Q) corresponds to the signal point with the shortest distance. It is possible to generate u ′, v ′, x ′, and y ′. However, if such a hard decision is made, accurate data decoding becomes difficult.
[0080]
The present invention has been made in view of such a situation, and makes it possible to accurately decode data transmitted by a multi-level multi-phase modulation system such as 16QAM, 64QAM, and 256QAM. is there.
[0081]
[Means for Solving the Problems]
The data receiving apparatus according to claim 1, wherein a demodulator that demodulates an I component and a Q component from a received signal and a symbol having the same value of at least one of the I component and the Q component For each set of symbols, calculate the posterior probability that the symbol was transmitted and the symbol was received, and sum all the posterior probabilities for the set of symbols for which one of the bits representing the component is a predetermined value. Metric calculation means for calculating a value obtained by dividing the sum of the posterior probabilities for the set of symbols as a metric for the one bit, and decoding means for decoding data using the metric.
[0082]
According to a fourth aspect of the present invention, there is provided a data reception method comprising: demodulating an I component and a Q component from a received signal; and a symbol having the same value for at least one of the I component and the Q component. For each set, calculate the posterior probability that the symbol was transmitted and that symbol was received, and the sum of the posterior probabilities for the set of symbols for which one of the bits representing the component is a predetermined value is The method includes a step of calculating a value obtained by dividing a sum of posterior probabilities for a set of symbols as a metric for the one bit, and a step of decoding data using the metric.
[0083]
6. A data receiving apparatus according to claim 5, wherein a demodulating means for demodulating an I component and a Q component from a received signal and a symbol having the same value of at least one of the I component and the Q component. For each set, the posterior probability that a symbol is transmitted and that symbol is received is calculated, and the sum of the posterior probabilities for the set of symbols in which one of the bits representing the component is a predetermined value is It is characterized by comprising metric calculation means for calculating as a metric for one bit and decoding means for decoding data using the metric.
[0084]
9. The data receiving method according to claim 8, wherein the I component and the Q component are demodulated from the received signal, and at least one of the I component and the Q component is a set of symbols having the same component value. Each time, a posterior probability that a symbol was transmitted and that symbol was received is calculated, and the sum of the posterior probabilities for a set of symbols in which one of the bits representing the component is a predetermined value is The method includes a step of calculating as a metric for bits, and a step of decoding data using the metric.
[0085]
In the data receiving apparatus according to claim 1, the demodulating unit demodulates the I component and the Q component from the received signal, and the metric calculating unit is configured to detect at least one of the I component and the Q component. For each set of symbols with the same value of, the posterior probability that the symbol is transmitted and that symbol is received is calculated, and one of the bits representing the component is a predetermined value for the set of symbols A value obtained by dividing the sum of the posterior probabilities by the sum of the posterior probabilities for the set of all symbols is calculated as a metric for the one bit, and the decoding means decodes the data using the metric.
[0086]
5. The data receiving method according to claim 4, wherein the I component and the Q component are demodulated from the received signal, and a set of symbols having the same component value for at least one of the I component and the Q component. For each symbol, the posterior probability that the symbol was transmitted and that symbol was received is calculated, and the sum of the posterior probabilities for a set of symbols in which one of the bits representing the component is a predetermined value is calculated for all symbols. A value obtained by dividing the sum of the posterior probabilities for the set is calculated as a metric for the one bit, and data is decoded using the metric.
[0087]
6. The data receiving apparatus according to claim 5, wherein the demodulating means demodulates the I component and the Q component from the received signal, and the metric calculating means applies the component to at least one of the I component and the Q component. For each set of symbols with the same value of, the posterior probability that the symbol is transmitted and that symbol is received is calculated, and one of the bits representing the component is a predetermined value for the set of symbols The sum of the posterior probabilities is calculated as a metric for the one bit, and the decoding means decodes the data using the metric.
[0088]
9. The data receiving method according to claim 8, wherein the I component and the Q component are demodulated from the received signal, and for each set of symbols having the same component value for at least one of the I component and the Q component. The posterior probability that a symbol is transmitted and the symbol is received is calculated, and the sum of the posterior probabilities for a set of symbols in which one of the bits representing the component is a predetermined value is calculated as one bit. Is calculated as a metric for, and data is decoded using the metric.
[0089]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a first embodiment of the data receiving apparatus of the present invention for receiving data transmitted by the data transmitting apparatus of FIG. In FIG. 1, parts corresponding to those in the conventional case shown in FIG. In the embodiment of FIG. 1, the symbol despreading circuit 33 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 17, that is, a process for returning the order of the symbols replaced in the symbol spreading circuit 7 to the original order. The I signal component I ′ and the Q signal component Q ′ are output to the metric calculation circuits 39-1 and 39-2 (metric calculation means), respectively.
[0090]
The metric calculation circuit 39-1 calculates a metric u ′ for the first bit of the symbol defined by the I component I ′ of the received signal and a metric x ′ for the third bit, and a metric u ′ for the first bit. Is output to the bit despreading circuit 101-1, and the metric x 'for the third bit is output to the bit despreading circuit 101-3.
[0091]
The metric calculation circuit 39-2 calculates a metric v 'for the second bit of the symbol defined by the Q component Q' of the received signal and a metric y 'for the fourth bit, and a metric v' for the second bit. Is output to the bit despreading circuit 101-2, and the metric y ′ for the fourth bit is output to the bit despreading circuit 101-4.
[0092]
In the metric calculation circuits 39-1 and 39-2 of the present embodiment, for each set of symbols having the same value of the I component I ′ or the Q component Q ′ of the received signal, the received data belongs to the set of symbols. Calculate posterior probabilities for each.
[0093]
In the present embodiment, as shown in FIG. 18, a signal subjected to signal point assignment processing by 16QAM is received. Among these, symbols corresponding to 16QAM signal points 0000, 0001, 0101, and 0100 shown in FIG. 18 and having an I component value of 3 / √10 constitute a symbol set SI00 shown in FIG. Symbols corresponding to 16QAM signal points 0010, 0011, 0111, and 0110 having a component value of 1 / √10 constitute a symbol set SI01 shown in FIG.
[0094]
Furthermore, symbols corresponding to 16QAM signal points 1010, 1011, 1111, and 1110 shown in FIG. 18 and having an I component value of −1 / √10 constitute a symbol set SI11 shown in FIG. Symbols corresponding to 16QAM signal points 1000, 1001, 1101, and 1100 having component values of −3 / √10 constitute a symbol set SI10 shown in FIG.
[0095]
Similarly, symbols corresponding to 16QAM signal points 0000, 0010, 1010, and 1000 having a Q component value of 3 / √10 shown in FIG. 18 constitute symbol set SQ00 shown in FIG. The symbols corresponding to the 16QAM signal points 0001, 0011, 1011 and 1001 having a Q component value of 1 / √10 constitute the symbol set SQ01 shown in FIG.
[0096]
Furthermore, symbols corresponding to 16QAM signal points 0101, 0111, 1111 and 1101 shown in FIG. 18 and having a Q component value of −1 / √10 constitute the symbol set SQ11 shown in FIG. Symbols corresponding to 16QAM signal points 0100, 0110, 1110, and 1100 having a component value of −3 / √10 constitute the symbol set SQ10 shown in FIG.
[0097]
The metric calculation circuit 39-1 is configured as shown in FIG. As shown in FIG. 3, the I component I ′ of the received signal supplied from the symbol despreading circuit 33 is an n number of probability calculation circuits 111-1 to 111 -n for calculating a posteriori probability for each set of symbols described above. Is input. In this case, as shown in FIG. 18, since signal point assignment processing is performed with 16QAM, this n is 4 (= 16 ^1/2 ).
[0098]
The probability calculation circuit 111-1 calculates a probability P (SI00∩R) that a symbol belonging to the set SI00 is transmitted and the received signal R is received. Similarly, the probability calculation circuit 111-2 calculates the probability P (SI01ＳＩR) that the symbol belonging to the set SI01 is transmitted and the received signal R is received, and the probability calculation circuit 111-3 sets the set SI10. The probability P (SI10∩R) that the symbol belonging to is transmitted and the received signal R is received is calculated. Then, the probability calculation circuit 111-4 calculates a probability P (SI11∩R) that the symbol belonging to the set SI11 is transmitted and the received signal R is received.
[0099]
The adder circuit 112-1 includes the posterior probability P (SI00∩R) for the symbol set SI00 calculated by the probability calculation circuit 111-1 and the posterior probability P for the symbol set SI01 calculated by the probability calculation circuit 111-2. The sum of (SI01∩R) (P (SI00∩R) + P (SI01∩R)) is calculated, and the calculation result is output to the division circuit 114-1.
[0100]
The adder circuit 112-2 includes the posterior probability P (SI00∩R) for the symbol set SI00 calculated by the probability calculation circuit 111-1 and the posterior probability P for the symbol set SI10 calculated by the probability calculation circuit 111-3. The sum of (SI10∩R) (P (SI00∩R) + P (SI01∩R)) is calculated and output to the division circuit 114-2.
[0101]
The adding circuit 113 calculates the sum of the posterior probabilities (P (SI00∩R) + P (SI01∩R) + P (SI11∩R) + P (SI10∩R)) supplied from the probability calculation circuits 111-1 to 111-4. The calculation is performed and the calculation result is output to the division circuits 114-1 and 114-2.
[0102]
The dividing circuit 114-1 uses the value (P (SI00∩R) + P (SI01∩R)) supplied from the adding circuit 112-1 as the value (P (SI00∩R) + P supplied from the adding circuit 113). (SI01∩R) + P (SI11∩R) + P (SI10∩R)), and the calculation result is output to the bit despreading circuit 101-1 as the metric u ′ for the first bit of the symbol. Has been made.
[0103]
The dividing circuit 114-2 uses the value (P (SI00∩R) + P (SI10∩R)) supplied from the adding circuit 112-2 as the value (P (SI00∩R) + P supplied from the adding circuit 113). (SI01∩R) + P (SI11∩R) + P (SI10∩R)), and the calculation result is output to the bit despreading circuit 101-3 as the metric x ′ for the third bit of the symbol. Has been made.
[0104]
FIG. 4 shows a configuration example of the metric calculation circuit 39-2. As shown in FIG. 4, the Q component Q ′ of the received signal supplied from the symbol despreading circuit 33 is the n probability calculation circuits 121-1 to 121-n for calculating the posterior probabilities for the above-described symbol sets. Is input.
[0105]
The probability calculation circuit 121-1 calculates a probability P (SQ00∩R) that a symbol belonging to the set SQ00 is transmitted and a reception signal R is received. Similarly, the probability calculation circuit 121-2 calculates a probability P (SQ01ＱR) that a symbol belonging to the set SQ01 is transmitted and the received signal R is received, and the probability calculation circuit 121-3 sets the set SQ10. The probability P (SQ10∩R) that the symbol belonging to is transmitted and the received signal R is received is calculated. Then, the probability calculation circuit 121-4 calculates a probability P (SQ11∩R) that the symbol belonging to the set SQ11 is transmitted and the reception signal R is received.
[0106]
The adder circuit 122-1 includes the posterior probability P (SQ00∩R) for the symbol set SQ00 calculated by the probability calculation circuit 121-1, and the posterior probability P for the symbol set SQ01 calculated by the probability calculation circuit 121-2. The sum of (SQ01∩R) (P (SQ00∩R) + P (SQ01∩R)) is calculated, and the calculation result is output to the division circuit 124-1.
[0107]
The adder circuit 122-2 includes the posterior probability P (SQ00∩R) for the symbol set SQ00 calculated by the probability calculation circuit 121-1, and the posterior probability P for the symbol set SQ10 calculated by the probability calculation circuit 121-3. The sum of (SQ10∩R) (P (SQ00∩R) + P (SQ10∩R)) is calculated and output to the division circuit 124-2.
[0108]
The adder circuit 123 calculates the sum of the posterior probabilities (P (SQ00∩R) + P (SQ01∩R) + P (SQ11∩R) + P (SQ10∩R)) supplied from the probability calculation circuits 121-1 to 121-4. The calculation result is output to the division circuits 124-1 and 124-2.
[0109]
The division circuit 124-1 uses the value (P (SQ00∩R) + P (SQ01∩R)) supplied from the addition circuit 122-1 as the value (P (SQ00∩R) + P supplied from the addition circuit 123. (SQ01∩R) + P (SQ11∩R) + P (SQ10∩R)), and the calculation result is output to the bit despreading circuit 101-2 as the metric v ′ for the second bit of the symbol. Has been made.
[0110]
The division circuit 124-2 uses the value (P (SQ00∩R) + P (SQ10∩R)) supplied from the addition circuit 122-2 as the value (P (SQ00∩R) + P supplied from the addition circuit 123. (SQ01ＳR) + P (SQ11∩R) + P (SQ10∩R)), and the calculation result is output to the bit despreading circuit 101-4 as the metric y ′ for the fourth bit of the symbol. Has been made.
[0111]
The bit despreading circuit 101-i (i = 1,..., 4) in FIG. 1 performs the metric for the i-th bit supplied from the metric calculation circuits 39-1 and 39-2 in FIG. Each metric is output to the parallel-serial converter 35 after executing the process of returning the changed bit order to the original order in the bit spreading circuit 91-i.
[0112]
The parallel-serial converter 35 is configured to convert four series of data into one series of data.
[0113]
FIG. 5 shows a configuration example of the Viterbi decoder 37 of FIG. In this embodiment, the output X of the bit insertion circuit 36 (a value corresponding to the metric u for the first bit or the metric x for the third bit) is input to the input terminal 62-1 and is input to the input terminal 62-2. The output Y of the bit insertion circuit 36 (a value corresponding to the metric v for the second bit or the metric y for the fourth bit) is input.
[0114]
Then, the value X input from the input terminal 62-1 is input to the selector 134-1, and also input to the inverting circuit 131-1. After all the bits are inverted, the value X is input to the selector 134-3. It is made so that. Also, the value Y input from the input terminal 62-2 is input to the selector 134-2 and also input to the inverting circuit 131-2. After all the bits are inverted, the value Y is input to the selector 134-4. It is made to be done.
[0115]
The selector 134-1 receives the value 1 output from the constant generation circuit 135-1 and the value X via the input terminal 62-1, and receives an insertion flag for X from the bit insertion circuit 36. The value 1 generated by the constant generation circuit 135-1 is selected. At other times, the value X is selected, and the selected value is output to the multiplication circuits 132-1 and 132-2.
[0116]
The selector 134-2 receives the value 1 output from the constant generation circuit 135-2 and the value Y via the input terminal 62-2, and when the insertion flag for Y is input from the bit insertion circuit 36. The value 1 generated by the constant generation circuit 135-2 is selected. At other times, the value Y is selected, and the selected value is output to the multiplication circuits 132-1 and 132-3.
[0117]
The selector 134-3 receives the value 1 which is the output of the constant generation circuit 135-3 and the value obtained by inverting the value X which is the output of the inversion circuit 131-1, and is inserted into the X from the bit insertion circuit 36. When the flag is input, the value 1 generated by the constant generation circuit 135-3 is selected. In other cases, a value obtained by inverting the value X is selected, and the selected value is supplied to the multiplication circuits 132-3 and 132-4. It is designed to output.
[0118]
The selector 134-4 receives the value 1 which is the output of the constant generation circuit 135-4 and the value obtained by inverting the value Y which is the output of the inverting circuit 131-2, and is inserted from the bit insertion circuit 36 into Y. When the flag is input, the value 1 generated by the constant generation circuit 135-4 is selected. In other cases, a value obtained by inverting the value Y is selected, and the selected value is supplied to the multiplication circuits 132-2 and 132-4. It is designed to output.
[0119]
The multiplication circuit 132-1 multiplies the value supplied from the selector 134-1 by the value supplied from the selector 134-2, and outputs the multiplication result as a branch metric BM00. The multiplication circuit 132-2 multiplies the value supplied from the selector 134-1 by the value supplied from the selector 134-4, and outputs the multiplication result as a branch metric BM01. Similarly, the multiplication circuit 132-3 multiplies the value supplied from the selector 134-2 by the value supplied from the selector 134-3, and outputs the multiplication result as the branch metric BM10. The multiplication circuit 132-4 The value supplied from the selector 134-3 is multiplied by the value supplied from the selector 134-4, and the multiplication result is output as the branch metric BM11.
[0120]
The output BM00 of the multiplication circuit 132-1 and the output BM11 of the multiplication circuit 132-4 are input to the ACS circuits 133-1 and 133-3. Similarly, the output BM01 of the multiplication circuit 132-2 and the output BM10 of the multiplication circuit 132-3 are input to the ACS circuits 133-2 and 133-4.
[0121]
The ACS circuits 133-1 and 133-3 also receive the output SM00 of the state metric storage device 66-1 and the output SM01 of the state metric storage device 66-2, and are input to the ACS circuits 133-2 and 133-4. The output SM10 of the state metric storage device 66-3 and the output SM11 of the state metric storage device 66-4 are input.
[0122]
The ACS circuits 133-1 to 133-4 calculate new state metrics from the input branch metrics and state metrics, and output the calculation results to the state metrics storage devices 66-1 to 66-4 and select them. Information SEL00 to SEL11 corresponding to the passed path is output to the path memory 65.
[0123]
The other configuration of the Viterbi decoder 37 of this embodiment is the same as that in FIG.
[0124]
1 is the same as that in FIG. 13 and the description thereof is omitted.
[0125]
Next, the operation of the data receiving apparatus in FIG. 1 will be described.
[0126]
The demodulator 32 (demodulation means) demodulates the received signal received by the antenna 31 and outputs the I component and Q component data of the symbol to the symbol despreading circuit 33. The symbol despreading circuit 33 performs symbol despreading processing on the I component and Q component data, and then outputs the I component I ′ to the metric calculation circuit 39-1 and the Q component Q ′ as the metric. It outputs to the calculation circuit 39-2.
[0127]
The metric calculation circuit 39-1 calculates the metric u ′ for the first bit and the metric x ′ for the third bit constituting the 16QAM symbol from the supplied I component I ′ (details of the calculation method are as follows). The metric u ′ for the first bit is output to the bit despreading circuit 101-1, and the metric x ′ for the third bit is output to the bit despreading circuit 101-3.
[0128]
Similarly, the metric calculation circuit 39-2 calculates a metric v ′ for the second bit and a metric y ′ for the fourth bit constituting the 16QAM symbol from the supplied Q component Q ′, The metric v ′ for the bit is output to the bit despreading circuit 101-2, and the metric y ′ for the fourth bit is output to the bit despreading circuit 101-4.
[0129]
Next, metric calculation in the metric calculation circuits 39-1 and 39-2 will be described. The metric here means, for example, a conditional posterior probability with respect to bits constituting the received signal when a predetermined received signal is received, which is defined by the following equation.
P (bi = 0 | R) = P (bi = 0∩R) / P (R) (3)
[0130]
Here, P (bi = 0 | R) is the conditional posterior probability that the i-th bit of the transmission symbol is 0 when the received signal R (I, Q) is received, and P (R) is the received The probability that the signal R (I, Q) is received, and P (bi = 0∩R) is the probability that the symbol whose i-th bit is 0 is transmitted and the received signal R (I, Q) is received. , Respectively.
[0131]
Similarly, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained when the reception signal R (I, Q) is received by the following equation (4).
P (bi = 1 | R) = P (bi = 1∩R) / P (R) (4)
[0132]
Here, P (bi = 1 | R) is a conditional posterior probability that the i-th bit of the transmission symbol is 1 when the received signal R (I, Q) is received, and P (bi = 1∩R). ) Represents the probability that a symbol having an i-th bit of 1 is transmitted and a received signal R (I, Q) is received.
[0133]
Also according to the following equation (5), when the received signal R (I, Q) is received, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained.
P (bi = 1 | R) = 1-P (bi = 0 | R) (5)
[0134]
In the present embodiment, the metric calculation circuit 39-1 calculates a metric for the first bit and the metric for the third bit of the symbol from the I component I ′ of the received signal. From the Q component Q ′, a metric for the second bit and a metric for the fourth bit of the symbol are calculated.
[0135]
The metric calculation circuit 39-1 uses a bit string (for example, 00 in the set SI00) representing the I component RI of the received signal R as the metric u ′ (= P (b1 = 0 | R)) for the first bit of the symbol. Output the posterior probability P (b′1 = 0 | RI) that the first bit b′1 is 0, and the metric x ′ (= P (b3 = 0 | R)) for the third bit of the symbol, A posterior probability P (b′2 = 0 | RI) that the second bit b′2 of the bit string representing the I component RI of the received signal R is 0 is output.
[0136]
That is, the metric for the first bit of the 16QAM symbol is the condition for the symbol S0abc (a, b, c is 0 or 1) corresponding to the signal points 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111. In this embodiment, the 16 posterior probabilities P (S0abc | R) are summed up in accordance with the value of the I component.
SI00 = {S0000, S0001, S0101, S0100},
SI01 = {S0010, S0011, S0111, S0110},
SI11 = {S1010, S1011, S1111, S1110},
SI10 = {S1000, S1001, S1101, S1100}
Next, of these, posterior probabilities P (SI00） RI) and P (SI01∩RI) for a set of symbols SI00, SI01 (b′1 = 0) in which the first bit of the symbol is 0 The sum is calculated as a metric for the first bit.
[0137]
That is, in the metric calculation circuit 39-1, the metric for the first bit and the metric for the third bit are calculated according to the following equations.
[0138]

[0139]
Where P (SI _j ∩RI) is a symbol set SI in which the i-th bit b′i of the bit string representing the set is 0. _j Represents the probability that a symbol belonging to and a received signal R has been received, and ΣP (SI _j ∩RI) is the set SI of all symbols _j Probability P (SI for _j ∩RI).
[0140]
When b′1 = 0 (ie, when calculating the metric for the first bit), ΣP (SI _j ∩RI) is P (SI00∩RI) + P (SI01∩RI), and when b′2 = 0 (that is, when calculating the metric for the third bit), ΣP (SI _j ∩RI) is P (SI00∩RI) + P (SI10∩RI).
[0141]
Also, ΣP (SI _k ∩RI) is the probability P (SI) for the symbol _k ∩RI). In this case, ΣP (SI _k ∩RI) is P (SI00∩RI) + P (SI01∩RI) + P (SI11∩RI) + P (SI10∩RI).
[0142]
Therefore, the probability calculation circuit 111-1 in FIG. 3 transmits P (SI00∩RI), that is, a symbol belonging to the set SI00 (a symbol corresponding to any one of 0000, 0001, 0101, and 0100 of 16QAM). The probability calculation circuit 111-2 calculates P (SI01∩RI), that is, one of symbols belonging to the set SI01 (any one of 0010, 0011, 0111, and 0110 of 16QAM). The posterior probability of receiving the received signal R is calculated.
[0143]
The probability calculation circuit 111-3 transmits P (SI11ＳＩRI), that is, a symbol belonging to the set SI11 (a symbol corresponding to any of 10QAM 1010, 1011, 1111, and 1110) and receives a received signal. The posterior probability of receiving R is calculated, and the probability calculation circuit 111-4 corresponds to P (SI10∩RI), that is, one of the symbols belonging to the set SI10 (16QAM 1000, 1001, 1101, and 1100). Symbol) is transmitted and the posterior probability of receiving the received signal R is calculated.
[0144]
Then, the adder circuit 112-1 corresponds to the numerator of the equation (6), and the posterior probabilities of the above-described posterior probabilities for the symbols having the first bit b′1 of 0 in the sets SI00 to SI11, that is, SI00 and SI01. The summation circuit 112-2 calculates the sum corresponding to the numerator of equation (6), and the second bit b′2 of the sets SI00 to SI11 is the above-described symbol for SI00 and SI10. Calculate the sum of posterior probabilities.
[0145]
The adder circuit 113 calculates the sum of the above-described posterior probabilities for the sets SI00 to SI11 corresponding to the denominator of the equation (6).
[0146]
The division circuit 114-1 divides the output of the addition circuit 112-1 by the output of the addition circuit 113 according to the equation (6), calculates the metric u ′ for the first bit of the symbol, and the division circuit 114. −2 divides the output of the adder circuit 112-2 by the output of the adder circuit 113 according to the equation (6), and calculates the metric x ′ for the third bit of the symbol.
[0147]
The metric calculation circuit 39-2 uses a bit string (for example, 00 in the set SQ00) representing the Q component RQ of the received signal R as the metric v ′ (= P (b2 = 0 | R)) for the second bit of the symbol. The probability P (b′1 = 0 | RQ) when the first bit b′1 is 0 is output, and the metric y ′ (= P (b4 = 0 | R)) for the fourth bit of the symbol is output. The probability P (b′2 = 0 | RQ) when the second bit b′2 of the bit string representing the Q component RQ of the received signal R is 0 is output.
[0148]
That is, the metric for the second bit of the 16QAM symbol is the condition for the symbol Sa0bc (a, b, c is 0 or 1) corresponding to the signal points 0000, 0001, 0010, 0011, 1000, 1001, 1010, 1011. In this embodiment, 16 symbols are initially set as four sets according to the value of the Q component. The total of the posterior probabilities P (Sa0bc | R) is used.
SQ00 = {S0000, S0010, S1010, S1000},
SQ01 = {S0001, S0011, S1011, S1001},
SQ11 = {S0101, S0111, S1111, S1101},
SQ10 = {S0100, S0110, S1110, S1100}
Next, of these, the posterior probabilities P (SQ00∩RI) and P (SQ01∩R) for the set of symbols SQ00, SQ01 (b′1 = 0) in which the first bit of the symbol is 0 The sum is calculated as a metric for the second bit.
[0149]
That is, the metric for the second bit and the metric for the fourth bit are calculated according to the following equations.
[0150]

[0151]
Where P (SQ _j ∩RQ) is a set of symbols SQ in which the i-th bit b′i of the bit string representing the set is 0. _j Represents the probability that a symbol belonging to the symbol is transmitted and the received signal R is received, and ΣP (SQ _j ∩RQ) is the set SQ of all symbols _j Probability P (SQ for _j (RQ) represents the total sum.
[0152]
When b′1 = 0 (ie, when calculating the metric for the second bit), ΣP (SQ _j ∩RQ) is P (SQ00∩RQ) + P (SQ01∩RQ), and when b′2 = 0 (that is, when calculating the metric for the fourth bit), ΣP (SQ _j ∩RQ) is P (SQ00∩RQ) + P (SQ10∩RQ).
[0153]
Also, ΣP (SQ _k ∩RQ) is the probability P (SQ for the symbol _k (RQ) represents the total sum. In this case, ΣP (SQ _k ∩RQ) is P (SQ00∩RQ) + P (SQ01∩RQ) + P (SQ11∩RQ) + P (SQ10∩RQ).
[0154]
The metric calculation circuit 39-2 operates in the same manner as the metric calculation circuit 39-1, and calculates the metric v ′ for the second bit and the metric y ′ for the fourth bit according to the equation (7). That is, the metric v ′ for the second bit is the sum of the posterior probability for SQ00 calculated by the probability calculation circuit 121-1 and the posterior probability for SQ01 calculated by the probability calculation circuit 121-2. It is calculated by dividing by the sum of the posterior probabilities for SQ00 to SQ11 calculated by -1 to 121-4.
[0155]
On the other hand, the metric y ′ for the fourth bit is the sum of the posterior probability for SQ00 calculated by the probability calculation circuit 121-1 and the posterior probability for SQ10 calculated by the probability calculation circuit 121-3. It is calculated by dividing by the sum of the posterior probabilities for SQ00 to SQ11 calculated by -1 to 121-4.
[0156]
Note that various methods can be considered as calculation methods in the probability calculation circuits 111-1 to 111-4 in FIG. 3 and the probability calculation circuits 121-1 to 121-4 in FIG. Is assumed, for example, the probability calculation circuit 111-1 can calculate the probability as follows.

[0157]
Here, σ represents the square root of ½ of the noise power of the transmission line. That is, 2σ ² Represents the noise power of the transmission line. ‖SI00-RI‖ is the Euclidean distance between the value of the I component of the symbol set SI00 and the value of the I component RI of the received signal. In this case, since the value of the I component of SI00 and RI are scalars, ‖SI00-RI 同一 is the same as | SI00-RI | (absolute value).
[0158]
Note that the coefficient on the right side of equation (8) (1 / (2π)) ^1/2 σ) may be omitted because it does not affect the selection of the maximum likelihood path by the Viterbi decoder 37 (decoding means). In that case, the probability P (SI00∩RI) is calculated as follows.

[0159]
The probability calculation circuits 111-2 to 111-4 can similarly calculate the above-described posterior probabilities.
[0160]
The metrics u ′, v ′, x ′, and y ′ calculated by the metric calculation circuits 39-1 and 39-2 as described above are processed by the bit despreading circuits 101-1 to 101-4. Then, the subsequent parallel-serial converter 35 performs an operation reverse to that of the serial-parallel converter 4 in FIG. 17 to convert the four systems of data into one series of data.
[0161]
In the bit insertion circuit 36, the reverse operation of the bit erasing circuit 3 of FIG. That is, the erase map in the previous example
X: 10
Y: 11
Using,
u1, v1, x1, y1, u2, v2, x2, y2...
Arbitrary dummy data (0 in this case) is inserted immediately before the last 3 bits with a period of 3 bits for the data input in this order,
As data X, u1, 0, y1, 0, x2, ...
As data Y, v1, x1, u2, v2, y2, ...
Are supplied in this order, and an insertion flag indicating the position where the dummy data is inserted is supplied to the Viterbi decoder 37.
[0162]
The Viterbi decoder 37 performs Viterbi decoding according to the state transition of the convolutional encoder 2 to obtain reproduction information 38. Next, the operation of the Viterbi decoder 37 will be described in detail.
[0163]
When the dummy data is inserted as X in the bit insertion circuit 36 and the insertion flag for X is input, the selector 134-1 and the selector 134-3 set the value 1 to invalidate the metric probability calculation for the dummy data. Output.
[0164]
Similarly, the selector 134-2 and the selector 134-4 invalidate the metric probability calculation for the dummy data when dummy data is inserted as Y in the bit insertion circuit 36 and the insertion flag for Y is input. The value 1 is output.
[0165]
That is, the calculation of the branch metric by the multiplication circuits 132-1 to 132-4 and the calculation of the state metric by the ACS circuits 133-1 to 133-4 are all performed by multiplication (described later). By outputting the value 1, the metric calculation result is not affected.
[0166]
When no dummy data is inserted as X, the value X supplied from the bit insertion circuit 36 is supplied to the multiplier circuits 132-1 and 132-2 via the selector 134-1, and the value X is inverted. The value is supplied to multiplication circuits 132-3 and 132-4.
[0167]
Similarly, when dummy data is not inserted as Y, the value Y supplied from the bit insertion circuit 36 is supplied to the multiplication circuits 132-1 and 132-3 via the selector 134-2, and the value Y A value obtained by inverting is supplied to the multiplication circuits 132-2 and 132-4.
[0168]
In the multiplication circuit 132-1, the probability that the value of the first bit of the symbol is 0 or the probability that the value of the third bit is 0 and the value of the second bit is 0 Or the product of data Y corresponding to the probability that the value of the fourth bit is 0 (that is, the probability that the value of the first bit is 0 and the value of the second bit is 0, or The probability that the value of the bit 3 is 0 and the value of the fourth bit is 0) is calculated and output as the branch metric BM00. The branch metric BM00 corresponds to the code output 00 of the convolutional encoder 2.
[0169]
Similarly, the multiplication circuit 132-2 has the value X corresponding to the probability that the value of the first bit of the symbol is 0 or the value of the third bit is 0, and the value of the second bit is 1. Or the value corresponding to the probability that the value of the fourth bit is 1 (the value obtained by inverting the value Y) (that is, the value of the first bit is 0 and the second bit The probability that the value is 1 or the probability that the value of the third bit is 0 and the value of the fourth bit is 1) is calculated and output as the branch metric BM01. This branch metric BM01 corresponds to the code output 01 of the convolutional encoder 2.
[0170]
The multiplication circuit 132-3 includes a value corresponding to the probability that the value of the first bit of the symbol is 1 or the value of the third bit is 1 (a value obtained by inverting the value X), and the second bit. The product of the value Y corresponding to the probability that the value of 0 or the value of the fourth bit is 0 (that is, the value of the first bit is 1 and the value of the second bit is 0 Or the probability that the value of the third bit is 1 and the value of the fourth bit is 0) is output as the branch metric BM10. This branch metric BM 10 corresponds to the code output 10 of the convolutional encoder 2.
[0171]
The multiplication circuit 132-4 has a value corresponding to the probability that the value of the first bit of the symbol is 1 or the value of the third bit is 1 (a value obtained by inverting the value X), and the second bit. Of the value corresponding to the probability that the value of 1 or the value of the fourth bit is 1 (the value obtained by inverting the value Y) (that is, the value of the first bit is 1 and The probability that the value of the bit of 2 is 1 or the probability that the value of the third bit is 1 and the value of the fourth bit is 1) is calculated and output as the branch metric BM11. The branch metric BM11 corresponds to the code output 11 of the convolutional encoder 2.
[0172]
When dummy data is inserted as X or Y, the selectors 134-1 to 134-4 select 1 instead of the dummy data, so that the multiplication circuits 132-1 to 132-4 are dummy. An input value not corresponding to data is output as it is (multiplied by 1) as a branch metric.
[0173]
The ACS circuit 133-1 calculates the following two expressions according to the state transition of the convolutional encoder 2 (FIG. 9).
SM00 × BM00 (9)
SM01 × BM11 (10)
[0174]
Here, SM00 is the value of the state metric storage device 66-1 one unit time ago, SM01 is the value of the state metric storage device 66-2 one unit time ago, and BM00 is the calculation result of the multiplication circuit 132-1. BM11 represents the calculation result of the multiplication circuit 132-4.
[0175]
Then, the ACS circuit 133-1 selects the one with the highest likelihood, that is, the one with the larger calculation result among the equations (9) and (10), and outputs the selection information SEL 00 to the path memory 65 in the subsequent stage. At the same time, the larger one of the results obtained by calculating the equations (9) and (10) is supplied to the subsequent state metric storage device 66-1 and stored therein. That is, if the calculation result of Expression (9) is larger, SEL00 = 0 is set, and if the calculation result of Expression (10) is larger, SEL00 = 1 is set. In the former case, SM00 × BM00 is stored as new state metric SM00 in the state metric storage device 66-1, respectively.
[0176]
The ACS circuits 133-2 to 133-4 operate in the same manner, and calculate new state metrics SM01 to SM11.
[0177]
The other operations in the Viterbi decoder 37 are the same as those in FIG.
[0178]
A value obtained by multiplying the logarithm of the output of the metric calculation circuits 39-1 and 39-2 by -1 is supplied to the bit despreading circuits 101-1 to 101-4, and the branch metric in the Viterbi decoder 37 is also supplied. The path metric may be calculated by addition.
[0179]
Next, a second embodiment of the data receiving apparatus of the present invention will be described.
[0180]
In the second embodiment, the formulas used for metric calculation and the configurations of the metric calculation circuits 39-1 and 39-2 are different from those of the first embodiment. Only the metric calculation circuits 39-1 and 39-2 will be described, and description of other components will be omitted.
[0181]
FIG. 6 shows a configuration example of the metric calculation circuit 39-1 of the second embodiment. In this metric calculation circuit 39-1, the sum of the posterior probability for the set SI00 calculated by the probability calculation circuit 111-1 and the posterior probability for the set SI01 calculated by the probability calculation circuit 111-2 is the first. The sum of the posterior probability for the set SI00 calculated by the probability calculation circuit 111-1 and the posterior probability for the set SI10 calculated by the probability calculation circuit 111-3 Is output as a metric x 'for the bits of.
[0182]
Similarly, in the metric calculation circuit 39-2 (not shown) of the second embodiment, the posterior probability for the set SQ00 calculated by the probability calculation circuit 121-1 in FIG. The calculated sum of the posterior probabilities for the set SQ01 is output as the metric v ′ for the second bit, and the sum of the posterior probabilities for the set SQ00 and the posterior probabilities for the set SQ10 calculated by the probability calculation circuit 121-1. The metric y ′ for the fourth bit calculated by the probability calculation circuit 121-3 is output.
[0183]
That is, the denominator ΣP (SI) of Equation (6) _k ∩RI) is the same in calculating any metric, and does not affect the selection of the maximum likelihood path. Therefore, in the second embodiment, the numerator of Equation (6) is changed to the first or third. It is used as a metric for the bits.
[0184]
Similarly, the denominator ΣP (SQ of equation (7) _k ∩RQ) is the same in calculating any metric and does not affect the selection of the maximum likelihood path. Therefore, in the second embodiment, the numerator of Equation (7) is changed to the second or fourth. It is used as a metric for the bits.
[0185]
As described above, by using the numerators of the equations (6) and (7) as a metric, the equation for calculating the metric is simplified, and the circuit scale can be reduced.
[0186]
The metric calculation circuits 39-1 and 39-2 in the first and second embodiments can also be realized by using ROMs 42-1 and 42-2 as shown in FIG.
[0187]
In the metric calculation circuit 39-1 shown in FIG. 7, the A / D converter 41 converts the signal of the I component I ′ supplied from the symbol inverse conversion circuit 33 into a digital value, and converts the digital value into the ROM 42-1. , 42-2.
[0188]
Then, the ROM 42-1 outputs a value stored in advance at the address indicated by the supplied digital value (that is, the metric u ′ corresponding to the first bit corresponding to the value of the I component I ′). 2 outputs a value stored in advance at the address indicated by the supplied digital value (that is, the metric x ′ for the third bit corresponding to the value of the I component I ′).
[0189]
Note that, similarly to the metric calculation circuit 39-1 in FIG. 7, the metric calculation circuit 39-2 may be configured by a ROM and an A / D converter.
[0190]
In these ROMs, the metrics in the first embodiment are stored in advance at corresponding addresses. Alternatively, the metric in the second embodiment may be stored in the ROM in advance.
[0191]
FIG. 8 shows the configuration of the third embodiment of the data receiving apparatus of the present invention. In the third embodiment, instead of the two metric calculation circuits 39-1 and 39-2 in the first embodiment or the second embodiment, the parallel-serial converter 51, the metric calculation circuit 39, and the A parallel converter 52 is used.
[0192]
The parallel / serial converter 51 outputs the I component signal I ′ and the Q component signal Q ′ supplied from the symbol despreading circuit 33 in two series to the metric calculation circuit 39 in one series.
[0193]
The metric calculation circuit 39 is configured in the same manner as the above-described metric calculation circuits 39-1 and 39-2. When the I component signal I ′ is supplied, the metric u ′ and the metric u ′ for the first bit of the symbol are the same. The metric x ′ for the 3 bits is calculated, and the calculation result is output to the serial-parallel converter 52. When the signal Q ′ of the Q component is supplied, the metric v ′ for the second bit of the symbol and the fourth The metric y ′ for the bit is calculated, and the calculation result is output to the serial-parallel converter 52.
[0194]
The serial-to-parallel converter 52 converts the metrics u ′, x ′ or v ′, y ′ supplied from the metric calculation circuit 39 into metrics for the first bit and the third bit, or the second bit and The metric for the fourth bit is output to the bit despreading circuits 101-1, 101-3 or 101-2, 101-4, respectively.
[0195]
In this way, in the third embodiment, the metric for the first to fourth bits is calculated using only one metric calculation circuit 39, so the circuit scale can be reduced.
[0196]
In the above embodiment, the data is modulated and demodulated by the 16QAM system. In addition to this, multilevel multiphase modulation in which the I component and the Q component each correspond to two or more bits such as 64QAM and 256QAM. Even when the method is adopted, the present invention can be applied.
[0197]
【The invention's effect】
As described above, according to the data receiving device according to claim 1 and the data receiving method according to claim 4, symbols having the same component value for at least one of the I component and the Q component. For each set of symbols, calculate the posterior probability that the symbol was transmitted and the symbol was received, and sum all the posterior probabilities for the set of symbols in which one of the bits representing the component is a predetermined value, Since the value divided by the sum of the posterior probabilities for the set of symbols is calculated as the metric for that one bit, the metric is calculated with a simple circuit, and the I component and Q component each correspond to 2 bits or more Thus, it is possible to accurately decode the data transmitted by the multi-level multi-phase modulation method.
[0198]
According to the data receiving device according to claim 5 and the data receiving method according to claim 8, for each set of symbols having the same component value for at least one of the I component and the Q component, A posterior probability that a symbol is transmitted and that symbol is received is calculated, and the sum of the posterior probabilities for a set of symbols in which one of the bits representing the component is a predetermined value is a metric for that one bit. As a result, the metric is calculated with a simpler circuit, and the data transmitted by the multi-level multi-phase modulation method in which each of the I component and the Q component corresponds to 2 bits or more is accurately decoded. Can do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a first embodiment of the present invention.
FIG. 2 is a diagram showing a set of symbols having the same I or Q component value for 16QAM signal points.
3 is a block diagram showing a configuration example of a metric calculation circuit 39-1 in FIG. 1. FIG.
4 is a block diagram illustrating a configuration example of a metric calculation circuit 39-2 in FIG. 1;
FIG. 5 is a block diagram illustrating a configuration example of the Viterbi decoder of FIG. 1;
FIG. 6 is a block diagram showing a configuration example of a metric calculation circuit according to a second embodiment of the present invention.
FIG. 7 is a block diagram illustrating another configuration example of the metric calculation circuit.
FIG. 8 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.
FIG. 9 is a block diagram illustrating a configuration example of a conventional data transmission apparatus.
10 is a block diagram illustrating a configuration example of a convolutional encoder in FIG. 9;
11 is a diagram for explaining state transitions of the convolutional encoder in FIG. 10; FIG.
FIG. 12 is a diagram for explaining signal point arrangement of QPSK;
FIG. 13 is a block diagram illustrating a configuration example of a conventional data receiving apparatus.
14 is a block diagram illustrating a configuration example of the Viterbi decoder of FIG. 13;
15 is a block diagram illustrating a configuration example of a branch metric calculation circuit in FIG. 14;
16 is a block diagram illustrating a configuration example of the path memory in FIG. 14;
FIG. 17 is a block diagram illustrating a configuration example of a data transmission apparatus when 16QAM is used.
FIG. 18 is a diagram for explaining 16QAM signal point arrangement;
FIG. 19 is a diagram illustrating a configuration example of a data receiving device that receives data transmitted by the device of FIG. 17;
20 is a diagram for explaining the operation of the embodiment of FIG. 19;
[Explanation of symbols]
32 demodulator, 33 symbol despreading circuit, 35 parallel-serial converter, 36-bit insertion circuit, 37 Viterbi decoder, 38 reproduction information, 39, 39-1, 39-2 metric calculation circuit, 41 A / D converter, 42-1, 42-2 ROM, 101-1 to 101-4 bit despreading circuit, 111-1 to 111-4 probability calculation circuit, 112-1, 112-2 addition circuit, 113 addition circuit, 114-1, 114-2 division circuit, 121-1 to 121-4 probability calculation circuit, 122-1, 122-2 addition circuit, 123 addition circuit, 124-1, 124-2 division circuit

Claims (8)

In a data receiving apparatus for receiving data that is digitally modulated and transmitted in a multi-value multi-phase system,
Demodulation means for demodulating the I component and the Q component from the received signal;
For at least one of the I component and the Q component, for each set of symbols having the same value of the component, calculate the posterior probability that the symbol is transmitted and the symbol is received; A value obtained by dividing the sum of the posterior probabilities for the set of symbols in which one of the bits representing the component is a predetermined value by the sum of the posterior probabilities for all the sets of symbols. Metric calculation means for calculating as a metric for
A data receiving apparatus comprising: decoding means for decoding the data using the metric. The metric calculation unit converts the received data into a digital value, and outputs the metric stored in advance in a predetermined storage unit corresponding to the digital value. Data receiving device. 2. The data receiving apparatus according to claim 1, wherein the metric calculation unit inputs the I component and the Q component one by one, and calculates the metric for the input component. In a data receiving method for receiving data that has been digitally modulated and transmitted in a multi-value multi-phase system,
Demodulating the I and Q components from the received signal;
For at least one of the I component and the Q component, for each set of symbols having the same value of the component, calculate the posterior probability that the symbol is transmitted and the symbol is received; A value obtained by dividing the sum of the posterior probabilities for the set of symbols in which one of the bits representing the component is a predetermined value by the sum of the posterior probabilities for all the sets of symbols. Calculating as a metric for
And a step of decoding the data using the metric. In a data receiving apparatus for receiving data that is digitally modulated and transmitted in a multi-value multi-phase system,
Demodulation means for demodulating the I component and the Q component from the received signal;
For at least one of the I component and the Q component, for each set of symbols having the same value of the component, calculate the posterior probability that the symbol is transmitted and the symbol is received; Metric calculation means for calculating a sum of the posterior probabilities for the set of symbols in which one of the bits representing a component is a predetermined value, as a metric for the one bit;
A data receiving apparatus comprising: decoding means for decoding the data using the metric. The said metric calculation means converts the received data into a digital value, and outputs the said metric previously stored in a predetermined storage unit corresponding to the digital value. Data receiving device. 6. The data receiving apparatus according to claim 5, wherein the metric calculation unit inputs the I component and the Q component one by one, and calculates the metric for the input component. In a data receiving method for receiving data that has been digitally modulated and transmitted in a multi-value multi-phase system,
Demodulating the I and Q components from the received signal;
For at least one of the I component and Q component, for each set of symbols having the same value of the component, calculate the posterior probability that the symbol is transmitted and the symbol is received; Calculating the sum of the posterior probabilities for the set of symbols in which one of the bits representing is a predetermined value as a metric for the one bit;
And a step of decoding the data using the metric.

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