JP3606413B2 - Data receiving apparatus and method - Google Patents

Description

【０１３２】
ここで、σは伝送路の雑音電力の１／２の平方根を表す。即ち、２σ^２が伝送路の雑音電力を表す。‖Ｓ００００−Ｒ‖は、シンボルＳ００００と受信信号Ｒとの、Ｉ−Ｑ平面におけるユークリッド距離である。
【０１３３】
なお、式（７）の右辺の係数（１／（２π）^１／２σ）は、ビタビ復号器３７による最尤パスの選択に影響を与えないので、省略してもよい。その場合、Ｐ（Ｓ００００）∩Ｒ）は、次のように計算される。

【０１３４】
確率計算回路１１１−２乃至１１１−１６においても、同様にして、確率を計算することができる。
【０１３５】
次に、ビット逆拡散回路１０１−１乃至１０１−４は、メトリック計算回路３９より供給されたメトリックｕ’，ｖ’，ｘ’，ｙ’に対して、ビット逆拡散の処理を行った後、並直列変換器３５に出力する。
【０１３６】
そして、並直列変換器３５は、図１６の直並列変換器４と逆の操作を行い、供給された４系統のデータを１系列のデータに変換した後、ビット挿入回路３６に出力する。
【０１３７】
ビット挿入回路３６では、図１６のビット消去回路３と逆の操作が行われる。即ち、前述の例の消去マップ
Ｘ：１０
Ｙ：１１
を用いて、
ｕ１，ｖ１，ｘ１，ｙ１，ｕ２，ｖ２，ｘ２，ｙ２・・・
の順で入力されるデータに対して、３ビットを周期として、最後の３ビット目の直前に、任意のダミーデータ（ここでは０）を挿入して、
データＸとして、ｕ１，０，ｙ１，０，ｘ２，・・・
データＹとして、ｖ１，ｘ１，ｕ２，ｖ２，ｙ２，・・・
を、この順で出力するとともに、ダミーデータを挿入した位置を示す挿入フラグをビタビ復号器３７に供給する。
【０１３８】
ビタビ復号器３７では、畳み込み符号化器２の状態遷移に従ってビタビ復号を行い、再生情報３８を得る。次に、ビタビ復号器３７の動作について詳細に説明する。
【０１３９】
セレクタ１３２−１およびセレクタ１３２−３は、ビット挿入回路３６においてＸとしてダミーデータが挿入され、Ｘに対する挿入フラグが入力された場合、ダミーデータに対するメトリックの確率計算を無効にするため、値１を出力する。
【０１４０】
同様に、セレクタ１３２−２およびセレクタ１３２−４は、ビット挿入回路３６においてＹとしてダミーデータが挿入され、Ｙに対する挿入フラグが入力された場合、ダミーデータに対するメトリックの確率計算を無効にするため、値１を出力する。
【０１４１】
即ち、乗算回路１２１−１乃至１２１−４によるブランチメトリックの算出およびＡＣＳ回路１２２−１乃至１２２−４によりステートメトリックの算出は、すべて乗算によって行われているので（後述）、ダミーデータに対応して値１を出力することにより、メトリックの計算結果に影響を与えないようにしている。
【０１４２】
Ｘとしてダミーデータが挿入されていない場合においては、ビット挿入回路３６より供給された値Ｘが、セレクタ１３２−１を介して乗算回路１２１−１，１２１−２に供給され、値Ｘを反転した値が、乗算回路１２１−３，１２１−４に供給される。
【０１４３】
同様に、Ｙとしてダミーデータが挿入されていない場合においては、ビット挿入回路３６より供給された値Ｙが、セレクタ１３２−２を介して乗算回路１２１−１，１２１−３に供給され、値Ｙを反転した値が、乗算回路１２１−２，１２１−４に供給される。
【０１４４】
そして、乗算回路１２１−１では、ビット挿入回路３６の出力の第１のビットの値が０である確率または第３のビットの値が０である確率に対応するデータＸと、第２のビットの値が０である確率または第４のビットの値が０である確率に対応するデータＹの積（即ち、第１のビットの値が０であり、かつ、第２のビットの値が０である確率、あるいは、第３のビットの値が０であり、かつ、第４のビットの値が０である確率）を計算し、ブランチメトリックＢＭ００として出力する。このブランチメトリックＢＭ００は、畳み込み符号化器２の符号出力００に対応している。
【０１４５】
同様にして、乗算回路１２１−２は、ビット挿入回路３６の出力の第１ビットの値が０である確率または第３のビットの値が０である確率に対応する値Ｘと、第２のビットの値が１である確率または第４のビットの値が１である確率に対応する値（値Ｙを反転した値）の積（即ち、第１のビットの値が０であり、かつ、第２のビットの値が１である確率、あるいは、第３のビットの値が０であり、かつ、第４のビットの値が１である確率）を計算し、ブランチメトリックＢＭ０１として出力する。このブランチメトリックＢＭ０１は、畳み込み符号化器２の符号出力０１に対応している。
【０１４６】
乗算回路１２１−３は、ビット挿入回路３６の出力の第１のビットの値が１である確率または第３のビットの値が１である確率に対応する値（値Ｘを反転した値）と、第２のビットの値が０である確率または第４のビットの値が０である確率に対応する値Ｙの積（即ち、第１のビットの値が１であり、かつ、第２のビットの値が０である確率、あるいは、第３のビットの値が１であり、かつ、第４のビットの値が０である確率）を計算し、ブランチメトリックＢＭ１０として出力する。このブランチメトリックＢＭ１０は、畳み込み符号化器２の符号出力１０に対応している。
【０１４７】
乗算回路１２１−４は、ビット挿入回路３６の出力の第１のビットの値が１である確率または第３のビットの値が１である確率に対応する値（値Ｘを反転した値）と、第２のビットの値が１である確率または第４のビットの値が１である確率に対応する値（値Ｙを反転した値）の積（即ち、第１のビットの値が１であり、かつ、第２のビットの値が１である確率、あるいは、第３のビットの値が１であり、かつ、第４のビットの値が１である確率）を計算し、ブランチメトリックＢＭ１１として出力する。このブランチメトリックＢＭ１１は、畳み込み符号化器２の符号出力１１に対応している。
【０１４８】
なお、ＸまたはＹとしてダミーデータが挿入されている場合、セレクタ１３２−１乃至１３２−４は、そのダミーデータの代わりに、１を選択するので、乗算回路１２１−１乃至１２１−４は、ダミーデータに対応しない入力の値を、そのまま（１を乗じて）、ブランチメトリックとして出力する。
【０１４９】
ＡＣＳ回路１２２−１は、畳み込み符号化器２の状態遷移（図１０）に従って、次の２つの式の計算を行う。
ＳＭ００×ＢＭ００ （８）
ＳＭ０１×ＢＭ１１ （９）
【０１５０】
ここでＳＭ００は、１単位時間前のステートメトリック記憶装置６６−１の値、ＳＭ０１は、１単位時間前のステートメトリック記憶装置６６−２の値、ＢＭ００は、乗算回路１２１−１の演算結果、ＢＭ１１は、乗算回路１２１−４の演算結果をそれぞれ表している。
【０１５１】
そして、ＡＣＳ回路１２２−１は、尤度の大きい方、すなわち、式（８）と式（９）のうち、計算結果の大きい方を選択し、その選択情報ＳＥＬ００を後段のパスメモリ６５に出力するとともに、式（８）と式（９）を計算して得られた結果のうち大きい方を、後段のステートメトリック記憶装置６６−１に供給し、記憶させる。すなわち式（８）の計算結果の方が大きければ、ＳＥＬ００＝０とし、式（９）の計算結果の方が大きければ、ＳＥＬ００＝１とする。また、前者の場合、ＳＭ００×ＢＭ００が、後者の場合、ＳＭ０１×ＢＭ１１が、それぞれステートメトリック記憶装置６６−１に、新たなステートメトリックＳＭ００として記憶される。
【０１５２】
なお、ＡＣＳ回路１２２−２乃至１２２−４も同様に動作し、新たなステートメトリックＳＭ０１乃至ＳＭ１１を計算する。
【０１５３】
ビタビ復号器３７におけるその他の動作は、図１３における場合と同様であるので、その説明を省略する。
【０１５４】
図４は、メトリック計算回路３９の他の構成例を示している。
【０１５５】
Ａ／Ｄ変換器１４１−１は、シンボル逆拡散回路３３より供給されたＩ成分の信号Ｉ’をデジタル値に変換し、その値をＲＯＭ１４２−１乃至１４２−４に、アドレスデータとして出力するようになされている。
【０１５６】
Ａ／Ｄ変換器１４１−２は、シンボル逆拡散回路３３より供給されたＱ成分の信号Ｑ’をデジタル値に変換し、その値をＲＯＭ１４２−１乃至１４２−４に、アドレスデータとして出力するようになされている。
【０１５７】
ＲＯＭ１４２−ｉ（ｉ＝１，・・・，４）は、Ａ／Ｄ変換器１４１−１，１４１−２より供給されたアドレスデータに対応するアドレスに記憶されている値を第ｉのビットに対するメトリックとしてビット逆変換回路１０１−ｉに出力するようになされている。
【０１５８】
即ち、ＲＯＭ１４２−ｉ（ｉ＝１，・・・，４）には、受信信号ＲのＩ成分Ｉ’およびＱ成分Ｑ’の各値に対応した上述の事後確率の総和の値が、第ｉのビットに対するメトリックとして、予め記憶されている。
【０１５９】
図５は、本発明の第２の実施例の構成を示している。第２の実施例は、第１の実施例のメトリック計算回路３９とビット逆変換回路１０１−１乃至１０１−４の間に第２メトリック計算回路４０を挿入したものであるので、第２メトリック計算回路４０の説明だけを行い、他の構成要素の説明を省略する。
【０１６０】
図６は、第２メトリック計算回路４０の構成例を示している。
【０１６１】
この第２メトリック計算回路４０においては、対数演算器１５１−１は、メトリック計算回路３９より供給された値ｕ’の自然対数（ｌｏｇ（ｕ’））を計算し、その値を反転回路１５２−１に出力するようになされている。
【０１６２】
対数演算器１５１−２は、メトリック計算回路３９より供給された値ｖ’の自然対数（ｌｏｇ（ｖ’））を計算し、その値を反転回路１５２−２に出力するようになされている。
【０１６３】
同様に、対数演算器１５１−３は、メトリック計算回路３９より供給された値ｘ’の自然対数（ｌｏｇ（ｘ’））を計算し、その値を反転回路１５２−３に出力し、対数演算器１５１−４は、メトリック計算回路３９より供給された値ｙ’の自然対数（ｌｏｇ（ｙ’））を計算し、その値を反転回路１５２−４に出力するようになされている。
【０１６４】
反転回路１５２−１は、対数演算器１５１−１より供給された値（ｌｏｇ（ｕ’））に−１を乗じた値（−ｌｏｇ（ｕ’））を、第１のビットに対するメトリックｕ_１’としてビット逆変換回路１０１−１に出力するようになされている。
【０１６５】
反転回路１５２−２は、対数演算器１５１−２より供給された値（ｌｏｇ（ｖ’））に−１を乗じた値（−ｌｏｇ（ｖ’））を、第２のビットに対するメトリックｖ_１’としてビット逆変換回路１０１−２に出力するようになされている。
【０１６６】
同様に、反転回路１５２−３は、対数演算器１５１−３より供給された値（ｌｏｇ（ｘ’））に−１を乗じた値（−ｌｏｇ（ｘ’））を、第３のビットに対するメトリックｘ_１’としてビット逆変換回路１０１−３に出力し、反転回路１５２−４は、対数演算器１５１−４より供給された値（ｌｏｇ（ｙ’））に−１を乗じた値（−ｌｏｇ（ｙ’））を、第３のビットに対するメトリックｙ_１’としてビット逆変換回路１０１−４に出力するようになされている。
【０１６７】
次に、第２の実施例において利用されているメトリックについて説明する。
【０１６８】
受信装置が受信する信号Ｒが時間的に独立である場合、ビタビ復号器３７は、上述の条件付き事後確率Ｐ（ｂｉ＝０｜Ｒ）の積

が最大である系列（即ち、最尤パス）を選択し、復号を行う。
【０１６９】
ここで、Ｒ（ｔ）は、時刻ｔにおける受信信号を表し、｛Ｒ（ｔ）｝は、受信信号系列を表し、Ｐ（｛Ｒ（ｔ）｝）は、受信信号系列が｛Ｒ（ｔ）｝となる確率を表している。ｂｉ（ｔ）は、時刻ｔにおける伝送シンボルを構成する第ｉのビットの値（０または１）であり、｛ｂｉ（ｔ）｝は、伝送するビットデータ系列を表している。｛ｂｉ（ｔ）｝は、ｔ，ｉの値に対応して０または１の２通りの値をとるので、系列長が２である場合においては、｛００｝、｛０１｝、｛１０｝、および、｛１１｝の４通りの系列となり、系列長が３である場合においては８通りの系列、系列長が４である場合においては１６通りの系列となる。
【０１７０】
ビタビ復号器３７は、これらの複数の系列のうち、受信信号系列｛Ｒ（ｔ）｝を受信したとき、最も確からしい送信系列（最尤パス）を選択する。即ち、ビタビ復号器３７は、上述の条件付き事後確率Ｐ（ｂｉ＝０｜Ｒ）の積が最大であるパスを選択する。なお、式（１０）の分母ΠＰ（Ｒ（ｔ））は、パスの種類に依存しないので、ビタビ復号器３７は、式（１０）の分子ΠＰ（ｂｉ（ｔ）＝０∩Ｒ（ｔ））が最大であるパスを選択すればよい。
【０１７１】
さらに、第２の実施例においては、第１の実施例におけるメトリックである確率Ｐ（ｂｉ（ｔ）＝０∩Ｒ（ｔ））（時刻ｔにおけるＰ（ｂｉ＝０∩Ｒ））の関数形を、次式に示すように指数関数に仮定している。
Ｐ（ｂｉ（ｔ）＝０∩Ｒ（ｔ））＝ｅｘｐ（−Ａ_ｉ（ｔ）） （１１）
【０１７２】
このとき、式（１０）の分子ΠＰ（ｂｉ（ｔ）＝０∩Ｒ（ｔ））は、

となり、ビタビ復号器３７は、式
ΣＡ_ｉ（ｔ）＝Σ（−ｌｏｇ（Ｐ（ｂｉ（ｔ）＝０∩Ｒ（ｔ））））（１３）
の値が最小となるパスを、最尤パスとして選択すればよい。
【０１７３】
従って、各時刻ｔにおける各ビットｉに対するメトリックは、式
−ｌｏｇ（Ｐ（ｂｉ（ｔ）＝０∩Ｒ（ｔ））） （１４）
で得られる値となる。即ち、第１の実施例においては、メトリック計算回路３９は、式
Ｐ（ｂｉ（ｔ）＝０∩Ｒ（ｔ）） （１５）
に従ってメトリックを算出しているが、第２の実施例のおいては、第２メトリック計算回路４０が、メトリック計算回路３９により算出された値（式（１５）で得られる値）の自然対数に−１を乗じた値を算出して、式（１４）に従ったメトリックを算出している。
【０１７４】
なお、対数演算器１５１−１乃至１５１−４は、自然対数の代わりに常用対数を計算するようにしてもよい。
【０１７５】
また、メトリック計算回路３９および第２メトリック計算回路４０の代わりに、図４に示すメトリック計算回路３９を利用し、ＲＯＭ１４２−ｉ（ｉ＝１，・・・，４）に、受信信号ＲのＩ成分Ｉ’およびＱ成分Ｑ’の各値に対応した上述の事後確率の総和の値の対数を、第ｉのビットに対するメトリックとして予め記憶しておくようにしてもよい。
【０１７６】
図７は、第２の実施例のビタビ復号器３７の構成例を示している。図７のビタビ復号器３７においては、上述のように、入力端子６２−１と６２−２から、シンボルの第１のビットの値が０である確率または第３のビットの値が０である確率を指数関数と仮定したときのその指数部に対応するデータＸと、シンボルの第２のビットの値が０である確率または第４のビットの値が０である確率を指数関数と仮定したときのその指数部に対応するデータＹが入力される。
【０１７７】
そして、入力端子６２−１より入力された値Ｘは、セレクタ１６４−１に入力されるとともに、減算回路１６１−１に入力される。減算回路１６１−１は、指数部の最大値からＸを減算した後、その値をセレクタ１６４−３に出力するようになされている。また、入力端子６２−２より入力された値Ｙは、セレクタ１６４−２に入力されるとともに、減算回路１６１−２に入力される。減算回路１６１−２は、指数部の最大値からＹを減算した後、その値をセレクタ１６４−４に出力するようになされている。
【０１７８】
セレクタ１６４−１は、定数発生回路１６５−１の出力である値０と、入力端子６２−１を介して値Ｘの供給を受け、ビット挿入回路３６より、Ｘに対する挿入フラグが入力されたとき、定数発生回路１６５−１が発生した値０を選択し、その他のとき、値Ｘを選択し、選択した値を加算回路１６２−１，１６２−２に出力するようになされている。
【０１７９】
セレクタ１６４−２は、定数発生回路１６５−２の出力である値０と、入力端子６２−２を介して値Ｙの供給を受け、ビット挿入回路３６より、Ｙに対する挿入フラグが入力されたとき、定数発生回路１６５−２が発生した値０を選択し、その他のとき、値Ｙを選択し、選択した値を加算回路１６２−１，１６２−３に出力するようになされている。
【０１８０】
セレクタ１６４−３は、定数発生回路１６５−３の出力である値０と、減算回路１６１−１の出力である、指数部の最大値から値Ｘを減算した値の供給を受け、ビット挿入回路３６より、Ｘに対する挿入フラグが入力されたとき、定数発生回路１６５−３が発生した値０を選択し、その他のとき、指数部の最大値から値Ｘを減算した値を選択し、選択した値を加算回路１６２−３，１６２−４に出力するようになされている。
【０１８１】
セレクタ１６４−４は、定数発生回路１６５−４の出力である値０と、減算回路１６１−２の出力である、指数部の最大値から値Ｙを減算した値の供給を受け、ビット挿入回路３６より、Ｙに対する挿入フラグが入力されたとき、定数発生回路１６５−４が発生した値０を選択し、その他のとき、指数部の最大値から値Ｙを減算した値を選択し、選択した値を加算回路１６２−２，１６２−４に出力するようになされている。
【０１８２】
加算回路１６２−１は、セレクタ１６４−１より供給された値と、セレクタ１６４−２より供給された値を加算し、その結果をブランチメトリックＢＭ００として出力するようになされている。加算回路１６２−２は、セレクタ１６４−１より供給された値と、セレクタ１６４−４より供給された値を加算し、その結果をブランチメトリックＢＭ０１として出力している。同様に、加算回路１６２−３は、セレクタ１６４−２より供給された値と、セレクタ１６４−３より供給された値を加算し、その結果をブランチメトリックＢＭ１０として出力し、加算回路１６２−４は、セレクタ１６４−３より供給された値と、セレクタ１６４−４より供給された値を加算し、その結果をブランチメトリックＢＭ１１として出力するようになされている。
【０１８３】
加算回路１６２−１の出力ＢＭ００と、加算回路１６２−４の出力ＢＭ１１は、ＡＣＳ回路１６３−１，１６３−３に入力されている。同様に、加算回路１６２−２の出力ＢＭ０１と、加算回路１６２−３の出力ＢＭ１０が、ＡＣＳ回路１６３−２，１６３−４に入力されている。
【０１８４】
ＡＣＳ回路１６３−１，１６３−３にはまた、ステートメトリック記憶装置６６−１の出力ＳＭ００とステートメトリック記憶装置６６−２の出力ＳＭ０１が入力されており、ＡＣＳ回路１６３−２，１６３−４には、ステートメトリック記憶装置６６−３の出力ＳＭ１０とステートメトリック記憶装置６６−４の出力ＳＭ１１が入力されている。
【０１８５】
ＡＣＳ回路１６３−１乃至１６３−４は、入力されたブランチメトリックとステートメトリックを加算して、新たなステートメトリックを計算し、その計算結果をステートメトリック記憶装置６６−１乃至６６−４に出力するとともに、選択されたパスに対応する情報ＳＥＬ００乃至ＳＥＬ１１をパスメモリ６５に出力するようになされている。
【０１８６】
図７のビタビ復号器３７のＡＣＳ回路１６３−１乃至１６３−４は、ステートメトリックにブランチメトリックを加算して、パスメトリックを更新するので、セレクタ１６４−１，１６４−３は、Ｘに対する挿入フラグが入力されたとき、定数発生回路１３３−１，１３３−３が発生した値０を加算回路１６２−１，１６２−３にそれぞれ出力し、セレクタ１６４−２，１６４−４は、Ｙに対する挿入フラグが入力されたとき、定数発生回路１３３−２，１３３−４が発生した値０を加算回路１６２−２，１６２−４にそれぞれ出力するようにして、ダミーデータがメトリックの計算結果に影響を与えないようにしている。
【０１８７】
以上のようにして、上記実施例においては、受信信号Ｒを受信したとき、送信シンボルが所定のシンボルＳ_ｊである条件付き事後確率Ｐ（Ｓ_ｊ｜Ｒ）の代わりに、所定のシンボルＳ_ｊが送信され、受信信号Ｒが受信された事後確率Ｐ（Ｓ_ｊ∩Ｒ）を計算し、その事後確率Ｐ（Ｓ_ｊ∩Ｒ）から、シンボルの各ビットに対するメトリックを計算している。このようにすることにより、１６ＱＡＭ方式で送信されてきたデータに対するメトリックを算出し、受信したデータを正確に復号化することができる。
【０１８８】
上記実施例においては、１６ＱＡＭ方式でデータを変調し、復調するようにしたが、このほか、６４ＱＡＭ、２５６ＱＡＭなどの、Ｉ成分とＱ成分が、それぞれ２以上のビットに対応する多値多位相変調方式を採用する場合においても、本発明は適用することが可能である。
【０１８９】
【発明の効果】
以上のごとく、請求項１に記載のデータ受信装置および請求項４に記載のデータ受信方法によれば、所定のデータのシンボルが伝送され、かつ、そのシンボルが受信された事後確率をシンボル毎に計算し、シンボルのビット毎に、そのビットが所定の値であるシンボルの事後確率の総和を、そのビットに対するメトリックとして計算するようにしたので、比較的簡単な回路でメトリックを計算することができ、Ｉ成分とＱ成分がそれぞれ２ビット以上に対応する多値多相変調方式で伝送されてくる信号を受信し、正確に復号することができる。
【０１９０】
請求項５に記載のデータ受信装置および請求項８に記載のデータ受信方法によれば、所定のデータのシンボルが伝送され、かつ、そのシンボルが受信された事後確率をシンボル毎に計算し、シンボルのビット毎に、そのビットが所定の値であるシンボルの事後確率の総和の対数に−１を乗じた値を、そのビットに対するメトリックとして計算するようにしたので、比較的簡単な回路でメトリックを計算することができ、Ｉ成分とＱ成分がそれぞれ２ビット以上に対応する多値多相変調方式で伝送されてくる信号を受信し、正確に復号することができる。
【図面の簡単な説明】
【図１】本発明のデータ受信装置の第１の実施例の構成を示すブロック図である。
【図２】図１のメトリック計算回路の構成例を示すブロック図である。
【図３】図１のビタビ復号器の構成例を示すブロック図である。
【図４】図１のメトリック計算回路の他の構成例を示すブロック図である。
【図５】本発明のデータ受信装置の第２の実施例の構成を示すブロック図である。
【図６】図５の第２メトリック計算回路の構成例を示すブロック図である。
【図７】図５のビタビ復号器の構成例を示すブロック図である。
【図８】従来のデータ送信装置の構成例を示すブロック図である。
【図９】図８の畳み込み符号化器の構成例を示すブロック図である。
【図１０】図９の畳み込み符号化器の状態遷移を説明する図である。
【図１１】ＱＰＳＫの信号点配置を説明する図である。
【図１２】従来のデータ受信装置の構成例を示すブロック図である。
【図１３】図１２のビタビ復号器の構成例を示すブロック図である。
【図１４】図１３のブランチメトリック演算回路の構成例を示すブロック図である。
【図１５】図１３のパスメモリの構成例を示すブロック図である。
【図１６】１６ＱＡＭを用いた場合のデータ送信装置の構成例を示すブロック図である。
【図１７】１６ＱＡＭの信号点配置を説明する図である。
【図１８】図１６の装置で送信したデータを受信するデータ受信装置の構成例を示す図である。
【図１９】図１８の実施例の動作を説明する図である。
【符号の説明】
３２ 復調器， ３３ シンボル逆拡散回路， ３５ 並直列変換器， ３６ビット挿入回路， ３７ ビタビ復号器， ３８ 再生情報， ３９ メトリック計算回路， ４０ 第２メトリック計算回路，１０１−１乃至１０１−４ ビット逆拡散回路， １１１−１乃至１１１−１６ 確率計算回路， １１２−１乃至１１２−４ 加算回路， １４１−１，１４１−２ Ａ／Ｄ変換器， １４２−１乃至１４２−４ ＲＯＭ， １５１−１乃至１５１−４ 対数演算器，１５２−１乃至１５２−４ 反転回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data receiving apparatus and method, and more particularly to a data receiving apparatus that calculates a posterior probability that a symbol of predetermined data is transmitted and that the symbol is received for each symbol, and calculates a metric from the posterior probability. And methods.
[0002]
[Prior art]
In the United States, digital broadcasting has already started. In Europe as well, in order to introduce digital television broadcasting, a standardized organization Digital Video Broadcasting (DVB) has been formed and its standard system is being compiled. This digital broadcasting is introduced, for example, on pages 139 to 151 of Nikkei Electronics 1996.1.15 (no. 653) as “Digital broadcasting, Europe will be put to practical use after the US”.
[0003]
When performing digital broadcasting, it is desirable to reduce the power consumption as much as possible. In such a communication channel with severe power limitation, generally, an encoding gain is obtained using an error correction code to reduce power. In such a system, error correction coding is generally performed on the transmission side, and error correction decoding is performed on the reception side. In particular, a convolutional code is advantageous in a communication channel with a small signal power to noise power ratio (C / N ratio), and this code can easily perform soft decision decoding by using the Viterbi decoding method. Gain can be obtained.
[0004]
Further, there is known a punctured code that can easily realize a plurality of coding rates using the same decoder by thinning out a code output sequence of a convolutional encoder according to a certain rule. Further, by spreading the code output sequence of the punctured encoder for each bit according to a certain rule, it is possible to improve resistance to noise superimposed on the transmission path.
[0005]
FIG. 8 shows a configuration example of a transmitting apparatus proposed in the standard DVB-T for DVB terrestrial television broadcasting. In this apparatus, a punctured convolutional code, bit spreading, and a QPSK modulation method are used.
[0006]
That is, in the example of FIG. 8, the 1-bit serial data output from the information source 1 is input to the convolutional encoder 2, and the punctured code mother code sequences X and Y are generated. In this example, the coding rate is ½. X and Y each represent a 1-bit code sequence.
[0007]
The code sequences X and Y are input to the bit erasure circuit 3 so that bit erasure processing is performed according to a predetermined rule. The serialized punctured code sequence output from the bit erasure circuit 3 is input to the serial / parallel converter 4 so as to be converted from one series of data to two series of data.
[0008]
The two series of data x and y output from the serial / parallel converter 4 are input to the bit spreading circuits 5-1 and 5-2, respectively, so that bit spreading processing is performed in which the order of bits is spread (interlaced). Has been made. Bit spread data x ′ and y ′ output from the bit spread circuits 5-1 and 5-2 are input to the signal point assignment circuit 6 and assigned to symbols on the transmission path. The signal point assignment circuit 6 outputs coordinate data I ′ and Q ′ of signal points represented by an in-phase component (I component) and a quadrature component (Q component) that are orthogonal to each other.
[0009]
The symbol spreading circuit 7 executes symbol spreading processing for spreading the order of symbols defined by the coordinate data I ′ and Q ′ output from the signal point assigning circuit 6, and calculates the I and Q components of the spread symbols. Output. The modulator 8 is configured to digitally modulate an I component and a Q component, for example, by an OFDM (Orthogonal Frequency Division Multiplex) method, and output the result via an antenna 9 as a radio wave.
[0010]
FIG. 9 illustrates a configuration example of the convolutional encoder 2. However, this configuration example is not defined by DVB-T, and shows a principle configuration for explaining the convolution process. In this example, 1-bit serial data output from the information source 1 is input from the terminal 21, and sequentially delayed by one clock by the delay circuits 22 and 23, and then output to the adder circuits 24 and 25. ing. The adder circuit 24 is also supplied with the output of the terminal 21 and the output of the delay circuit 22. The adder circuit 24 adds these data (exclusive OR operation) and then outputs the data X from the terminal 26. It is designed to output. The adder circuit 25 adds the output of the terminal 21 and the output of the delay circuit 23 (exclusive OR operation) and outputs the result as data Y from the terminal 27.
[0011]
That is, in this embodiment, for a 1-bit input, a 2-bit mother code determined from the internal state of the delay circuits 22 and 23 is output. In this example, the constraint length is 3, the internal delay element is 2, the number of states is 4, and the coding rate is 1/2.
[0012]
FIG. 10 shows a state transition diagram of the convolutional encoder 2. The state transition of the convolutional encoder 2 is as follows.
[0013]
That is, for example, when 0 is input from the terminal 21 in the state 00 (the output of the delay element 22 and the output of the delay element 23 are both 0), (XY) = (00) is output from the terminals 26 and 27. Is output and transitions to state 00. When 1 is input from state 00, (XY) = (11) is output and the state transitions to 10. When 0 is input from state 01, (XY) = (11) is output and the state transitions to state 00. When 1 is input from the state 01, (XY) = (00) is output, and the state transitions to the state 10.
[0014]
Also in other states, as shown in FIG. 10, the illustrated output is output with respect to the input of 0 or 1, and the state transits to the illustrated state.
[0015]
The bit erasing circuit 3 can change the coding rate as a result by erasing data at an appropriate position from the mother code sequence (XY) according to a certain rule. Below, for example,
X: 10
Y: 11
A case where bits are erased according to the erase map as described above will be described.
[0016]
The bit corresponding to 1 in the erasure map is transmitted, and the bit corresponding to 0 is not transmitted (erased). According to the erasure map, the outputs X (= X1) and Y (= Y1) of the convolutional encoder 2 at a certain time are transmitted in the order of X1Y1, and at the next time, the output X of the convolutional encoder 2 is transmitted. (= X2) is erased and not transmitted, and only Y (= Y2) is transmitted. That is, the bits transmitted at these two times are X1Y1Y2. With this operation, the number of bits input to the convolutional encoder 2 is 2 bits, and the number of bits output from the bit erasure circuit 3 is 3 bits, so that the coding rate R is 2/3. This operation is repeated every two unit times.
[0017]
In the serial-parallel converter 4, the input one series of data X1, Y1, Y2,... Is converted into two series of data (x, y).
[0018]
The bit spreading circuits 5-1 and 5-2 spread the bits by changing the order of the input data series x and y according to a predetermined rule. At this time, generally, the spreading methods of the bit spreading circuits 5-1 and 5-2 are different.
[0019]
An example of bit diffusion is shown below. An M-bit input data is defined as one block, and an appropriate numerical value s is determined. Bit spread is a vector consisting of an M-bit input sequence
From (B0, B1, ..., Bk, ..., BM-1),
Vector consisting of M-bit output sequence after spreading
Meaning substitution to (B′0, B′1,..., B′n,..., B′M−1). At this time, B′n = Bk (n = k + s mod M).
[0020]
By using different s in the bit spreading circuits 5-1 and 5-2, different bit spreading circuits can be configured with the same algorithm.
[0021]
The signal point assignment circuit 6 assigns the input data (x ′, y ′) to the symbols on the transmission path. The assignment is performed according to the QPSK method, for example, as shown in FIG. That is,
When (x ′, y ′) = (0, 0), (I ′, Q ′) = (1 / √2, 1 / √2),
When (x ′, y ′) = (0, 1), (I ′, Q ′) = (1 / √2, −1 / √2),
When (x ′, y ′) = (1, 0), (I ′, Q ′) = (− 1 / √2, 1 / √2),
When (x ′, y ′) = (1, 1), (I ′, Q ′) = (− 1 / √2, −1 / √2)
Is assigned as
[0022]
The symbol spreading circuit 7 performs symbol spreading by replacing the order of the symbols S ′ represented by (I ′, Q ′) according to a predetermined rule to obtain the symbols S (I, Q). As a result, burst errors received on the transmission line can be diffused.
[0023]
To give a specific example, when N-1 symbols are used as a unit block for spreading and a number G that is less than N and relatively prime to N is determined, spreading is a vector whose elements are symbols before spreading.
From (S′1, S′2,..., S′k,..., S′N−1)
A vector whose elements are the symbols after spreading
It is executed as a replacement to (S1, S2,..., Sn,..., SN-1). At this time, Sn = S′k (n = G ^ k mod N).
[0024]
In the modulator 8, the carrier wave is modulated according to the I component and Q component of the input symbol S and transmitted via the antenna 9.
[0025]
FIG. 12 illustrates a configuration example of a receiving apparatus that receives data transmitted from the transmitting apparatus in FIG. The demodulator 32 demodulates the radio wave received via the antenna 31 and outputs an I component signal and a Q component signal. The symbol despreading circuit 33 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 8, that is, a process of returning the order of the symbols replaced in the symbol spreading circuit 7 to the original order, and the I signal component I ′ And Q signal component Q ′.
[0026]
The bit despreading circuits 34-1 and 34-2 are the bits changed in the bit spreading circuits 5-1 and 5-2 of FIG. 8 with respect to the I ′ signal and the Q ′ signal output from the symbol despreading circuit 33. The process of returning the order to the original order is executed.
[0027]
The data x corresponding to the I ′ signal component output from the bit despreading circuits 34-1 and 34-2 and the data y corresponding to the Q ′ signal component are input to the parallel-serial converter 35, and two series of data (X, y) is converted into one series of data and supplied to the bit insertion circuit 36.
[0028]
In the bit insertion circuit 36, a bit insertion process is performed opposite to the bit erase process in the bit erase circuit 3 of FIG. The bit insertion circuit 36 inputs the bit I data component data x and the Q signal component data y to the Viterbi decoder 37, which is Viterbi decoded and output as reproduction information 38. .
[0029]
Next, the operation will be described.
[0030]
The received signal received by the antenna 31 is demodulated by the demodulator 32 to obtain I component and Q component data of each symbol. The data of the I component and the Q component is input to the symbol despreading circuit 33, where an operation reverse to that in the symbol spreading circuit 7 is performed to obtain despread data I ′ and Q ′.
[0031]
That is, when this despreading operation is expressed using the same values N and G as those used in the symbol spreading circuit 7, it is a vector whose elements are symbols before despreading.
(S1, S2,..., Sn,..., SN-1)
A vector whose elements are symbols after despreading
This is a process of replacing (S′1, S′2,..., S′k,..., S′N−1). At this time, Sn = S′k (n = G ^ k mod N).
[0032]
The I component data I ′ and Q component data Q ′ supplied from the symbol despreading circuit 33 are supplied to the bit despreading circuits 34-1 and 34-2, respectively.
[0033]
The bit despreading circuits 34-1 and 34-2 correspond to the bit spreading circuits 5-1 and 5-2, respectively, and perform operations reverse to those of the bit spreading circuits 5-1 and 5-2, respectively.
[0034]
That is, M input data is set as one block, an appropriate numerical value s is determined, and a vector composed of M input sequences
From (B′0, B′1,..., B′n,..., B′M−1),
Vector consisting of M output sequences after despreading
(B0, B1,..., Bk,..., BM-1) are obtained. At this time, B′n = Bk (n = k + s mod M).
[0035]
Here, the numerical value s used in the bit despreading of the bit despreading circuits 34-1 and 34-2 is the same value as the numerical value s used in the bit spreading circuits 5-1 and 5-2, respectively.
[0036]
The data sequence (x, y) that has been bit-despread in this way is supplied to the parallel-to-serial converter 35 of the next stage, where the reverse operation of the serial-to-parallel converter 4 is performed, and two series of data (x, y). To one series of data.
[0037]
In the bit insertion circuit 36, an operation reverse to that of the bit erasure circuit 3 is performed. That is, the erase map in the previous example
X: 10
Y: 11
In response to the processing of the bit erasing circuit 3 using
X1, Y1, Y2 (in this case, x1, y1, y2)
For the data input in this order, arbitrary dummy data (here, 0) is inserted at a position corresponding to the erased data X2 (x2),
As X data, X1 (x1), 0 is
As Y data, Y1 (y1), Y2 (y2) are
Output in this order. Further, an insertion flag indicating the position where the dummy data is inserted is supplied to the Viterbi decoder 37.
[0038]
The Viterbi decoder 37 performs Viterbi decoding according to the state transition of the convolutional encoder 2 (FIG. 10). FIG. 13 shows an example of the Viterbi decoder 37. Data X and Y output from the bit insertion circuit 36 are input to the input terminals 62-1 and 62-2, respectively. These data X and Y are input to the branch metric calculation circuits 63-1 to 63-4. In the branch metric calculation circuit 63-1, the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) shown in FIG. 11 is calculated as a branch metric. Similarly, in the branch metric calculation circuits 63-2 to 63-4, input data (X, Y) and coordinate points (1 / √2, −1 / √2), (−1 / √2, 1 / √). 2) or (−1 / √2, −1 / √2) is calculated.
[0039]
The outputs (branch metrics) BM00 and BM11 of the branch metric calculation circuits 63-1 and 63-4 are input to ACS (Add Compare Select) circuits 64-1 and 64-3. Similarly, the output (branch metric) BM01 of the branch metric calculation circuit 63-2 and the output (branch metric) BM10 of the branch metric calculation circuit 63-3 are input to the ACS circuits 64-2 and 64-4.
[0040]
The ACS circuits 64-1 and 64-3 also receive the output (state metric) SM00 of the state metric storage device 66-1 and the output (state metric) SM01 of the state metric storage device 66-2. 64-2 and 64-4 are supplied with the output (state metric) SM10 of the state metric storage device 66-3 and the output (state metric) SM11 of the state metric storage device 66-4.
[0041]
The ACS circuits 64-1 to 64-4 add one input branch metric BM and the corresponding state metric SM, and add the other branch metric BM and the corresponding state metric SM. Then, the ACS circuits 64-1 to 64-4 compare the two addition results, and in response to the comparison result, the smaller addition value is newly stored in the state metric storage devices 66-1 to 66-4. While outputting as the state metric SM, signals SEL00 to SEL11 representing the selection results are output to the path memory 65. Further, state metrics SM00 to SM11 are input to the path memory 65 from the state metric storage devices 66-1 to 66-4.
[0042]
The state metric storage devices 66-1 to 66-4 are reset by a signal input from the terminal 61. The path memory 65 is configured to output a decoding result from a terminal 67.
[0043]
Next, the operation will be described.
[0044]
In the branch metric calculation circuit 63-1, the distance between the input data (X, Y) and the coordinate point (1 / √2, 1 / √2) is calculated as the branch metric BM00. Similarly, in the branch metric calculation circuit 63-2, the distance between the input data (X, Y) and the coordinate point (1 / √2, −1 / √2), and in the branch metric calculation circuit 63-3, the input data (X, Y). ) And the coordinate point (−1 / √2, 1 / √2), the branch metric calculation circuit 63-4 uses the input data (X, Y) and the coordinate point (−1 / √2, −1 / √2). ) Are calculated as branch metrics BM01, BM10, and BM11, respectively. Here, the distance calculation for the inserted dummy data is omitted according to the insertion flag supplied from the bit insertion circuit 36 at the preceding stage. That is, the distance between the inserted bit and the coordinate to be compared is all the same (for example, 0).
[0045]
The ACS circuit 64-1 calculates the following two expressions according to the state transition of the convolutional encoder 2, and selects the one with the highest likelihood, that is, the one with the smaller calculation result, and the selection information SEL is the path memory in the subsequent stage. In 65, the calculation result SM is supplied to the state metric storage device 66-1.
[0046]
SM00 + BM00 (1)
SM01 + BM11 (2)
[0047]
Here, SM00 is a value of the state metric storage device 66-1 one unit time ago, SM01 is a value of the state metric storage device 66-2 one unit time ago, and BM00 is a value of the branch metric calculation circuit 63-1. The calculation result, BM11, represents the calculation result of the branch metric calculation circuit 63-4.
[0048]
If the calculation result of Expression (1) is smaller, SEL00 = 0 is supplied to the subsequent path memory 65, and if the calculation result of Expression (2) is smaller, SEL00 = 1 is supplied. In the former case, SM00 + BM00 is stored, and in the latter case, SM01 + BM11 is stored as a new state metric SM00 in the state metric storage device 66-1.
[0049]
This calculation will be described with reference to the state transition diagram of FIG. There are two paths that reach state 00. The first is a path that receives 0 in state 00 and outputs 00, and the calculation expression to be compared is as shown in equation (1), and the second is in state 01. In a path in which 0 is input and 11 is output, a calculation expression to be compared is as shown in Expression (2). The smaller of the calculation results is supplied as new state metric SM00 to state metric storage device 66-1.
[0050]
Similar operations are performed in the ACS circuits 64-2 to 64-4. Note that the state metric storage devices 66-1 to 66-4 are reset to 0 at the initial stage when the system operates. This control is performed via a terminal 61 from a control device (not shown).
[0051]
The path memory 65 selects, stores, and propagates input data, that is, decoded data, using the selection information SEL00 to SEL11 from the ACS circuits 64-1 to 64-4 according to the state transition diagram of FIG.
[0052]
FIG. 14 illustrates a configuration example of the branch metric calculation circuit 63-1. The data X input from the terminal 62-1 is input to the subtraction circuit 51 and is subtracted by 1 / √2 from the generation circuit 52. The output of the subtracting circuit 51 is branched and input to the multiplying circuit 53 and multiplied (ie, squared). The selector 203 receives the output of the multiplication circuit 53 and the output of the generation circuit 202. When the insertion flag for X is input from the bit insertion circuit 36 via the terminal 201, the selector 203 generates 0 generated by the generation circuit 202. In other cases, the output of the multiplication circuit 53 is selected and output to the addition circuit 54.
[0053]
Similarly, the data Y input from the terminal 62-2 is input to the subtraction circuit 55 and is subtracted by 1 / √2 from the generation circuit 56. The output of the subtraction circuit 55 is branched and input to the multiplication circuit 57, and is multiplied (square). The selector 206 receives the output of the multiplication circuit 57 and the output of the generation circuit 205, and selects 0 generated by the generation circuit 205 when the insertion flag for Y is input from the bit insertion circuit 36 via the terminal 204. At other times, the output of the multiplication circuit 57 is selected and output to the addition circuit 54. The adder circuit 54 adds the output of the selector 203 and the output of the selector 206 and outputs the result as a branch metric BM00.
[0054]
That is, in this example, when the insertion flag is not input, the subtracting circuit 51 outputs X−1 / √2, which is squared by the multiplying circuit 53 and sent from the multiplying circuit 53 (X−1 / √2). ² Is output. Similarly, the subtraction circuit 55 outputs Y−1 / √2, and this value is squared by the multiplication circuit 57, and the multiplication circuit 57 is (Y−1 / √2). ² Is output. The adder circuit 54 is an addition value (X−1 / √2) of the output of the multiplier circuit 53 and the output of the multiplier circuit 57. ² + (Y-1 / √2) ² Is output as the branch metric BM00.
[0055]
On the other hand, when the insertion flag for X is input, the selector 203 outputs 0, so the output of the adder circuit 54 is (Y−1 / √2). ² When the insertion flag for Y is input, the selector 206 outputs 0, so that the output of the adder circuit 54 is (X−1 / √2) ² It becomes.
[0056]
In the branch metric calculation circuits 63-2 to 63-4, the same calculation is performed by a circuit having the same configuration as that shown in FIG. However, in the branch metric calculation circuit 63-2, the output of the generation circuit 52 is 1 / √2, and the output of the generation circuit 56 is −1 / √2. In the branch metric calculation circuit 63-3, the outputs of the generation circuits 52 and 56 are -1 / √2 and 1 / √2, respectively. In the branch metric calculation circuit 63-4, -1 / √√ respectively. 2 and -1 / √2.
[0057]
FIG. 15 shows a block diagram of the path memory 65. The selection information SEL00 to SEL11 output from the ACS circuits 64-1 to 64-4 is input to the terminals 71-1 to 71-4. These selection information SEL00 to SEL11 are input as control signals to the two-input one-output selectors 73-1 to 73-4, respectively. The selector 73-1 receives fixed data 0 from the terminal 72-1 as two inputs. Similarly, fixed data 0, 1 or 1 is input to the selectors 73-2 to 73-4 as two inputs from the terminals 72-2 to 72-4, respectively.
[0058]
The selectors 73-1 to 73-4 select one of the two inputs corresponding to the selection information SEL00 to SEL11 and output the selected input to the subsequent registers 81-1 to 81-4. However, since the same data is input to the first column selectors 73-1 to 73-4 as two inputs from the terminals 72-1 to 72-4 as described above, the register 81-1 Through 81-4, 0, 0, 1 or 1 is stored, respectively.
[0059]
Hereinafter, similarly, a configuration including selectors and registers of n columns (four columns in the case of FIG. 15) is provided. That is, in the second column, selectors 74-1 to 74-4 and registers 82-1 to 82-4 are provided. The selectors 74-1 and 74-3 are supplied with the output of the register 81-1 in the previous column and the output of the register 81-2. The outputs of the register 81-3 and the register 81-4 are input to the selectors 74-2 and 74-4. Then, the selectors 74-1 to 74-4 select one of the two inputs corresponding to the values of the selection information SEL00 to SEL11, and perform processing to output to the subsequent registers 82-1 to 82-4. . For example, the register 74-1 selects the output of the register 81-1 when the selection information SEL00 is 0, and selects and outputs the output of the register 81-2 when the selection information SEL00 is 1. Has been made.
[0060]
The outputs of the registers 84-1 to 84-4 in the final column are input to the selector 85 having four inputs and one output.
[0061]
State metrics SM00 to SM11 output from the state metric storage devices 66-1 to 66-4 in FIG. 13 are input to the minimum value comparison circuit 88 from terminals 87-1 to 87-4. The minimum value comparison circuit 88 compares the magnitudes of the four state metrics and selects the smallest one. When the state metric SM00 is minimum, the data 00 is output. When the state metric SM01 is minimum, the data 01 is output. When the state metric SM10 is minimum, the data 10 is output. When the state metric SM11 is minimum, the data 11 is output. The selector 85 selects the output of the register 84-1 when the input from the minimum value comparison circuit 88 is 00, selects the output of the register 84-2 when it is 01, and selects the register 84 when it is 10. -3 is selected. When the output is 11, the output of the register 84-4 is selected and output from the terminal 86 as a decoding result. The fixed values of the terminals 72-1 to 72-4 mean the decoding information corresponding to each state.
[0062]
Such connection of the path memory 65 is based on the state transition diagram of FIG. In the configuration of the path memory 65, the top row corresponds to the state 00, the second row corresponds to the state 01, the third row corresponds to the state 10, and the bottom row corresponds to the state 11. In the first column, decoding information is fetched. According to FIG. 10, there are two paths from state 00 and state 01 to reach state 00. The input bit corresponding to each path, that is, the decoding information is 0 in all cases. Therefore, in the first column in the state 00 (top row), the input terminal of the selector 73-1 is wired so that the corresponding decoding information 0 is selected by the selection information SEL00.
[0063]
In the first column, connection is made in the same manner for the state 01, the state 10 and the state 11.
[0064]
In the second and subsequent columns, selection, propagation, and storage of decoded sequences are performed. According to FIG. 10, there are two paths from state 00 and state 01 to reach state 00. Therefore, in the second column in the state 00, the input terminal of the selector 74-1 is wired so that the data from the corresponding state is selected by the selection information SEL00.
[0065]
In the second and subsequent rows, the wiring is similarly performed. Further, in the state 01, the state 10, and the state 11 in the second to third rows, the wiring is similarly performed.
[0066]
In the last column of the path memory 65, data corresponding to the path with the highest likelihood is output as final decoded data from the four stored decoded data. The “maximum likelihood path” is a path corresponding to the one having the minimum value among the four state metrics SM00 to SM11. The selector 85 uses the path corresponding to the minimum value of the state metric at that time. That is, the path with the highest likelihood is selected.
[0067]
[Problems to be solved by the invention]
By the way, in recent years, while high-speed (high bit rate) transmission is screamed, it is conceivable to expand the modulation method of the above-described digital data transmission system from QPSK to 16QAM, 64QAM, 256QAM, or the like. Thus, the number of bits that can be transmitted is 4 bits, 6 bits, or 8 bits for 2 bits of QPSK, respectively, and increases 2 times, 3 times, and 6 times that of QPSK.
[0068]
FIG. 16 shows a block diagram of a 16QAM data transmission apparatus. In FIG. 16, portions corresponding to those in FIG. 8 are denoted by the same reference numerals. That is, in this example, the serial / parallel converter 4 converts the serial data output from the bit erasure circuit 3 into data u, v, x, y in units of 4 bits. Then, bit diffusion processing is performed for each data in the bit diffusion circuits 91-1 to 91-4, and the data is supplied to the signal point assignment circuit 6 as data u ′, v ′, x ′, y ′. Has been made. Other configurations are the same as those in FIG.
[0069]
In other words, in this example, the series-parallel converter 4 converts one series of data into four series of data (u, v, x, y) corresponding to 16QAM, which are bit spreading circuits 91-1 through 91, respectively. In -4, bit diffusion processing is performed by changing the order of bits according to a predetermined rule. The processing is the same as the processing in the bit spreading circuits 5-1 and 5-2 in FIG. 8, and different bit spreading processing is executed using different numerical values s.
[0070]
The signal point assignment circuit 6 assigns the input 4-bit data (u ′, v ′, x ′, y ′) to the symbols on the transmission path. The assignment is performed, for example, according to FIG. That is, for example,
When (u ′, v ′, x ′, y ′) = (0, 0, 0, 0),
(I ′, Q ′) = (3 / √10, 3 / √10),
When (u ′, v ′, x ′, y ′) = (0, 0, 0, 1),
(I ′, Q ′) = (3 / √10, 1 / √10)
Allocation is done as
[0071]
Similar assignments are made for other inputs.
[0072]
Thereafter, the same processing as in FIG. 8 is performed, and data is transmitted.
[0073]
When the transmitting apparatus shown in FIG. 16 performs signal point allocation by the 16QAM system as shown in FIG. 17 and receives the transmitted data, the receiving apparatus is configured as shown in FIG. 18 corresponding to FIG. It is possible. However, in practice, the receiving apparatus cannot be configured as shown in FIG.
[0074]
That is, as described above, the components I and Q of the data (I and Q) input from the demodulator 32 to the symbol despreading circuit 33 each represent 1 bit in the QPSK system. In the case of the 16QAM system, each represents 2 bits. For example, in the case of the signal point arrangement shown in FIG. 17, I includes information of the first bit and the third bit, and Q includes information of the second bit and the fourth bit. However, for example, I is a single value such as 1 / √10 or 3 / √10, and Q is also a single value. Therefore, as shown in FIG. 18, it cannot be divided into u ′ and v ′ or divided into x ′ and y ′. As a result, the data receiving apparatus in the case of the 16QAM system is also configured as shown in FIG.
[0075]
As a result, the processing performed in the bit insertion circuit 36 in FIG. 12 is considered as follows.
[0076]
For example, as shown in FIG. 19A, when data is input to the bit insertion circuit 36 as x1, y1, x2, y2, x3, y3,... As described above, x1 and y1 are output as data X1 and Y1, then dummy data d is output as data X2, and data x2 is output as data Y2. Similarly, after data y2 and x3 are output as data X3 and Y3, dummy data d is output as data X4, and then data y3 is output as data Y4.
[0077]
However, this process does not execute a process opposite to the process in the bit erasing circuit 3 of FIG. That is, the bit erasure (bit operation) processing performed in the bit erasure circuit 3 is performed in units of 1 bit. On the other hand, the data x1, y2, etc. shown in FIG. 19B each correspond to 2-bit data, after which 1-bit dummy data d is inserted, and then When 2-bit data x2 is output, a data array that is completely different from the original data array is output.
[0078]
As a result, when the Viterbi decoder 37 viterbi-decodes the output of the bit insertion circuit 36, the decoding results are not such that the components are slightly degraded, and are completely different, so that decoding is impossible.
[0079]
On the other hand, if a hard decision is made in the symbol despreading circuit 33 of the data receiving apparatus shown in FIG. 18, for example, from (I, Q), u ′, v ′, It is considered that x ′ and y ′ can be generated. That is, in this case, the distance between the coordinates of (I, Q) and each signal point shown in FIG. 17 is calculated, and (I, Q) corresponds to the signal point with the shortest distance. It is possible to generate u ′, v ′, x ′, and y ′. However, if such a hard decision is made, accurate data decoding becomes difficult.
[0080]
The present invention has been made in view of such a situation, and makes it possible to accurately decode data transmitted by a multi-level multi-phase modulation system such as 16QAM, 64QAM, and 256QAM. is there.
[0081]
[Means for Solving the Problems]
The data receiving apparatus according to claim 1, wherein a symbol of data is transmitted and a posterior probability that the symbol is received is calculated for each symbol, and a sum of the posterior probabilities of the symbols whose predetermined bits are a predetermined value. Metric calculating means for calculating the bit as a metric for the bit, and decoding means for decoding data using the metric.
[0082]
The data reception method according to claim 4, wherein a symbol of data is transmitted and a posterior probability that the symbol is received is calculated for each symbol, and a sum of posterior probabilities of symbols having a predetermined bit of a predetermined value. Is calculated as a metric for the bit, and data is decoded using the metric.
[0083]
6. The data receiving apparatus according to claim 5, wherein a symbol of data is transmitted and a posterior probability that the symbol is received is calculated for each symbol, and a sum of posterior probabilities of the symbols whose predetermined bits are a predetermined value. Metric calculation means for calculating a value obtained by multiplying the logarithm of -1 as a metric for the bit, and decoding means for decoding data using the metric.
[0084]
9. The data reception method according to claim 8, wherein a symbol of data is transmitted and a posterior probability that the symbol is received is calculated for each symbol, and a sum of the posterior probabilities of the symbols whose predetermined bits are a predetermined value. A value obtained by multiplying the logarithm of −1 by −1 as a metric for the bit, and a step of decoding data using the metric.
[0085]
In the data receiving apparatus according to claim 1, the metric calculating means calculates a posterior probability that a symbol of data is transmitted and the symbol is received for each symbol, and a predetermined bit has a predetermined value. The sum of the posterior probabilities of the symbols is calculated as a metric for the bit, and the decoding means decodes the data using the metric.
[0086]
In the data reception method according to claim 4, a posterior probability that a symbol of data is transmitted and the symbol is received is calculated for each symbol, and a posterior probability of a symbol whose predetermined bit is a predetermined value is calculated. The sum is calculated as a metric for the bit, and data is decoded using the metric.
[0087]
6. The data receiving apparatus according to claim 5, wherein the metric calculating means calculates a posterior probability that the symbol of the data is transmitted and the symbol is received for each symbol, and the predetermined bit is a predetermined value. A value obtained by multiplying the logarithm of the sum of the posterior probabilities of symbols by −1 is calculated as a metric for the bit, and the decoding means decodes the data using the metric.
[0088]
In the data receiving method according to claim 8, a posterior probability that a symbol of data is transmitted and the symbol is received is calculated for each symbol, and a posterior probability of a symbol whose predetermined bit is a predetermined value is calculated. A value obtained by multiplying the logarithm of the sum by -1 is calculated as a metric for the bit, and data is decoded using the metric.
[0089]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a first embodiment of the data receiving apparatus of the present invention for receiving data transmitted by the data transmitting apparatus of FIG. In FIG. 1, parts corresponding to those shown in FIG. In the embodiment of FIG. 1, the symbol despreading circuit 33 performs a process reverse to the symbol spreading process in the symbol spreading circuit 7 of FIG. 16, that is, a process for returning the order of the symbols replaced in the symbol spreading circuit 7 to the original order. The I signal component I ′ and the Q signal component Q ′ are output to the metric calculation circuit 39 (metric calculation means).
[0090]
The metric calculation circuit 39 calculates metrics for the first to fourth bits from the supplied I signal component I ′ and Q signal component Q ′, and calculates the calculated metrics u ′, v ′, x ′, y ′, The signals are output to the bit despreading circuits 101-1 to 101-4, respectively.
[0091]
The metric calculation circuit 39 is configured as shown in FIG. As shown in FIG. 2, the I ′ and Q ′ signals supplied from the symbol despreading circuit 33 are input to n probability calculation circuits 111-1 to 111-n. In this case, as shown in FIG. 17, since signal point assignment processing is performed with 16QAM, n is set to 16.
[0092]
The probability calculation circuit 111-1 calculates the posterior probability P (S0000∩R) that the symbol S0000 corresponding to 0000 of 16QAM shown in FIG. 17 is transmitted and the received signal R is received, and the probability calculation circuit 111-2 , A posterior probability P (S0001∩R) that a symbol S0001 corresponding to 0001 of 16QAM is transmitted and the received signal R is received is calculated.
[0093]
Hereinafter, similarly, the probability calculation circuit 111-3 calculates the posterior probability P (S0010） R) that the symbol S0010 corresponding to 0010 of 16QAM is transmitted and the reception signal R is received, and the probability calculation circuit 111-4 Through 111-15 calculate the posterior probabilities corresponding to the symbols S0011 through S1110. The probability calculation circuit 111-16 calculates a posterior probability P (S1111１R) that the symbol S1111 corresponding to 1111 of 16QAM is transmitted and the received signal R is received.
[0094]
In this embodiment, the posterior probability when any one of the first to fourth bits of the symbol is 0 is calculated as a metric corresponding to the bit, so the posterior probability P (S1111∩R ) Is not particularly necessary and may be removed.
[0095]
The adder circuit 112-1 is a probability calculation circuit 111-1 to 111-8 that calculates posterior probabilities for symbols whose first bits are 0, that is, S0000, S0001, S0010, S0011, S0100, S0101, S0110, and S0111. , The sum of those values is calculated, and is output to the bit despreading circuit 101-1 as a metric for the first bit.
[0096]
The adder circuit 112-2 is a probability calculation circuit 111-1 to 111-4 that calculates posterior probabilities for symbols whose second bits are 0, that is, S0000, S0001, S0010, S0011, S1000, S1001, S1010, and S1011. , 111-9 to 111-12 are received, the sum of these values is calculated, and is output to the bit despreading circuit 101-2 as a metric for the second bit.
[0097]
The adder circuit 112-3 calculates a posterior probability for a symbol whose third bit is 0, that is, S0000, S0001, S0100, S0101, S1000, S1001, S1100, S1101, and a probability calculation circuit 111-i (i = 1). , 2, 5, 6, 9, 10, 13, 14), calculates the sum of these values, and outputs the result to the bit despreading circuit 101-3 as a metric for the third bit. ing.
[0098]
The adder circuit 112-4 calculates a posterior probability for a symbol whose fourth bit is 0, that is, S0000, S0010, S0100, S0110, S1000, S1010, S1100, S1110, and a probability calculation circuit 111-i (i = 1). , 3, 5, 7, 9, 11, 13, 15), calculates the sum of these values, and outputs the result to the bit despreading circuit 101-4 as a metric for the fourth bit. ing.
[0099]
The bit despreading circuit 101-i (i = 1,..., 4) changes the metric for the i-th bit supplied from the metric calculation circuit 39 in the bit spreading circuit 91-i of FIG. A process for returning the bit order to the original order is executed. Metrics for the first to fourth bits subjected to the bit despreading process are input to the parallel-serial converter 35 and converted from four series of data to one series of data.
[0100]
FIG. 3 shows a configuration example of the Viterbi decoder 37 (decoding means) in FIG. In this embodiment, the output X of the bit insertion circuit 36 (a value corresponding to the metric u for the first bit or the metric x for the third bit) is input to the input terminal 62-1 and is input to the input terminal 62-2. The output Y of the bit insertion circuit 36 (a value corresponding to the metric v for the second bit or the metric y for the fourth bit) is input.
[0101]
The value X input from the input terminal 62-1 is input to the selector 132-1, and also input to the inverting circuit 131-1, and all the bits are inverted and then input to the selector 132-3. It has been made so that. The value Y input from the input terminal 62-2 is input to the selector 132-2 and input to the inversion circuit 131-2. After all the bits are inverted, the value Y is input to the selector 132-4. It is made to be done.
[0102]
The selector 132-1 receives the value 1 output from the constant generation circuit 133-1 and the value X via the input terminal 62-1, and the insertion flag for X is input from the bit insertion circuit 36. The value 1 generated by the constant generation circuit 133-1 is selected. At other times, the value X is selected, and the selected value is output to the multiplication circuits 121-1, 121-2.
[0103]
The selector 132-2 receives the value 1 output from the constant generation circuit 133-2 and the value Y via the input terminal 62-2, and when the insertion flag for Y is input from the bit insertion circuit 36. The value 1 generated by the constant generation circuit 133-2 is selected. At other times, the value Y is selected, and the selected value is output to the multiplication circuits 121-1, 121-3.
[0104]
The selector 132-3 receives supply of the value 1 which is the output of the constant generation circuit 133-3 and the value obtained by inverting the value X which is the output of the inversion circuit 131-1, and is inserted into the X from the bit insertion circuit 36. When the flag is input, the value 1 generated by the constant generation circuit 133-3 is selected. In other cases, a value obtained by inverting the value X is selected, and the selected value is supplied to the multiplication circuits 121-3 and 121-4. It is designed to output.
[0105]
The selector 132-4 receives supply of the value 1 which is the output of the constant generation circuit 133-4 and the value Y which is the output of the inversion circuit 131-2 and the insertion to Y from the bit insertion circuit 36. When the flag is input, the value 1 generated by the constant generation circuit 133-4 is selected. In other cases, the value obtained by inverting the value Y is selected, and the selected value is supplied to the multiplication circuits 121-2 and 121-4. It is designed to output.
[0106]
The multiplication circuit 121-1 multiplies the value supplied from the selector 132-1 by the value supplied from the selector 132-2, and outputs the multiplication result as a branch metric BM00. The multiplication circuit 121-2 multiplies the value supplied from the selector 132-1 by the value supplied from the selector 132-4, and outputs the multiplication result as a branch metric BM01. Similarly, the multiplication circuit 121-3 multiplies the value supplied from the selector 132-2 by the value supplied from the selector 132-3, and outputs the multiplication result as the branch metric BM10. The multiplication circuit 121-4 The value supplied from the selector 132-3 is multiplied by the value supplied from the selector 132-4, and the multiplication result is output as the branch metric BM11.
[0107]
The output BM00 of the multiplication circuit 121-1 and the output BM11 of the multiplication circuit 121-4 are input to the ACS circuits 122-1, 122-3. Similarly, the output BM01 of the multiplication circuit 121-2 and the output BM10 of the multiplication circuit 121-3 are input to the ACS circuits 122-2 and 122-4.
[0108]
The ACS circuits 122-1 and 122-3 also receive the output SM00 of the state metric storage device 66-1 and the output SM01 of the state metric storage device 66-2. The output SM10 of the state metric storage device 66-3 and the output SM11 of the state metric storage device 66-4 are input.
[0109]
The ACS circuits 122-1 to 122-4 calculate a new state metric from the input branch metrics and state metrics, and output the calculation results to the state metric storage devices 66-1 to 66-4 and select them. Information SEL00 to SEL11 corresponding to the passed path is output to the path memory 65.
[0110]
The other configuration of the Viterbi decoder 37 of this embodiment is the same as that in FIG.
[0111]
The other configuration of the data receiving apparatus in FIG. 1 is the same as that in FIG.
[0112]
Next, the operation of the data receiving apparatus in FIG. 1 will be described.
[0113]
The received signal received by the antenna 31 is demodulated by the demodulator 32 to obtain I component and Q component data of the symbol. The symbol I component and Q component data are processed by the symbol despreading circuit 33 and then supplied to the metric calculation circuit 39.
[0114]
Next, metric calculation in the metric calculation circuit 39 will be described. The metric here means, for example, a conditional posterior probability for the bits constituting the received signal when a predetermined received signal is received, which is defined by the following equation.
P (bi = 0 | R) = P (bi = 0∩R) / P (R) (3)
[0115]
Here, P (bi = 0 | R) is the conditional posterior probability that the i-th bit bi of the transmission symbol is 0 when the received signal R (I, Q) is received, and P (R) is The probability of receiving the received signal R (I, Q) is P (bi = 0∩R), a symbol with the i-th bit bi being 0 is transmitted, and the received signal R (I, Q) is received. Each posterior probability is expressed.
[0116]
Similarly, the conditional posterior probability that the i-th bit of the transmission symbol is 1 can be obtained when the reception signal R (I, Q) is received by the following equation (4).
P (bi = 1 | R) = P (bi = 1∩R) / P (R) (4)
[0117]
Here, P (bi = 1 | R) is the conditional posterior probability that the i-th bit bi of the transmission symbol is 1 when the received signal R (I, Q) is received, and P (R) is The probability of receiving the received signal R (I, Q) is P (bi = 1∩R), the symbol whose i-th bit bi is 1 is transmitted, and the received signal R (I, Q) is received. Each posterior probability is expressed.
[0118]
Also, according to the following equation (5), when the received signal R (I, Q) is received, the conditional posterior probability that the i-th bit bi of the transmission symbol is 1 can be obtained. P (bi = 1 | R) = 1-P (bi = 0 | R) (5)
[0119]
Since the probability P (R) of receiving the received signal R does not depend on the type of symbol, the metric calculation circuit 39 replaces the conditional posterior probability P (bi = 0 | R) described above with the posterior probability P (bi = 0). (R) is calculated as a metric. Thus, the circuit configuration can be simplified by omitting the calculation of the probability P (R).
[0120]
That is, the metric calculation circuit 39 calculates the metrics for the first to fourth bits constituting the 16QAM symbol,
Metric P (b1 = 0∩R) for the first bit u ′,
Metric P (b2 = 0 ＝ R) for the second bit v ′,
Metric P (b3 = 0 ＝ R) for the third bit is x ′,
The metric P (b4 = 0∩R) for the fourth bit is y ′
As output.
[0121]
Calculation of each metric is performed according to the following equation.
P (bi = 0∩R) = (1/16) ΣP (S _j ∩R) (6)
[0122]
Where P (S _j ∩R) is a symbol S whose i-th bit is 0. _j Represents the posterior probability that the received signal R is received and ΣP (S _j ∩R) is the posterior probability P (S for all symbols Sj whose i-th bit is 0 _j Represents the sum of (R).
[0123]
In the metric calculation circuit 39 of FIG. 2, the probability calculation circuit 111-1 calculates the probability that P (S0000０R), that is, the symbol S0000 corresponding to 0000 of 16QAM is transmitted and the reception signal R is received.
[0124]
The probability calculation circuit 111-2 calculates the probability that the symbol S0001 corresponding to P (S0001∩R), that is, 0001 of 16QAM is transmitted and the received signal R is received.
[0125]
The probability calculation circuit 111-3 calculates the probability that the symbol S0010 corresponding to P (S0010∩R), that is, 0010 of 16QAM is transmitted and the reception signal R is received.
[0126]
Similarly, the probability calculation circuits 111-4 to 111-16 calculate the posterior probabilities for the remaining 16QAM symbols, respectively, and obtain a total of 16 posterior probability calculation results.
[0127]
The adder circuit 112-1 has a symbol whose first bit is 0, that is,
S0000, S0001, S0010, S0011,
S0100, S0101, S0110, S0111
Compute the sum of the above posterior probabilities for. Originally, the sum divided by 16 is P (b1 = 0∩R). However, there is no particular problem even if all the metrics are multiplied by 16, so the metric calculation circuit 39 calculates the posterior probability. The sum is output as the metric u ′ for the first bit.
[0128]
The adder circuit 112-2 has a symbol whose second bit is 0, that is,
S0000, S0001, S0010, S0011,
S1000, S1001, S1010, S1011
Compute the sum of the above posterior probabilities for. Originally, the sum divided by 16 is P (b2 = 0∩R). However, there is no particular problem even if all the metrics are multiplied by 16, so the metric calculation circuit 39 determines the posterior probability. The sum is output as a metric v ′ for the second bit.
[0129]
The adder circuit 112-3 has a symbol whose third bit is 0, that is,
S0000, S0001, S0100, S0101,
S1000, S1001, S1100, S1101
Compute the sum of the above posterior probabilities for. Originally, the sum divided by 16 becomes P (b3 = 0∩R). However, there is no particular problem even if all the metrics are multiplied by 16, so the metric calculation circuit 39 determines the posterior probability. The sum is output as metric x ′ for the third bit.
[0130]
The adder circuit 112-4 has a symbol whose fourth bit is 0, that is,
S0000, S0010, S0100, S0110,
S1000, S1010, S1100, S1110
Compute the sum of the above posterior probabilities for. Originally, the sum divided by 16 is P (b4 = 0∩R), but there is no particular problem even if all the metrics are multiplied by 16, so the metric calculation circuit 39 determines the posterior probability. The sum is output as a metric y ′ for the fourth bit.
[0131]
Note that various calculation methods are conceivable depending on the transmission path as the calculation method in the probability calculation circuits 111-1 to 111-16 in FIG. 2. The posterior probability can be calculated as follows.

[0132]
Here, σ represents the square root of ½ of the noise power of the transmission line. That is, 2σ ² Represents the noise power of the transmission line. ‖S0000-R‖ is the Euclidean distance in the IQ plane between the symbol S0000 and the received signal R.
[0133]
The coefficient (1 / (2π) on the right side of equation (7) ^1/2 Since σ) does not affect selection of the maximum likelihood path by the Viterbi decoder 37, it may be omitted. In that case, P (S0000) ∩R) is calculated as follows.

[0134]
The probability calculation circuits 111-2 to 111-16 can similarly calculate the probability.
[0135]
Next, the bit despreading circuits 101-1 to 101-4 perform bit despreading processing on the metrics u ′, v ′, x ′, y ′ supplied from the metric calculation circuit 39, It outputs to the parallel-serial converter 35.
[0136]
Then, the parallel / serial converter 35 performs the reverse operation of the serial / parallel converter 4 in FIG. 16, converts the supplied four systems of data into one series of data, and then outputs the data to the bit insertion circuit 36.
[0137]
In the bit insertion circuit 36, an operation reverse to that of the bit erasing circuit 3 in FIG. 16 is performed. That is, the erase map in the previous example
X: 10
Y: 11
Using,
u1, v1, x1, y1, u2, v2, x2, y2...
Arbitrary dummy data (0 in this case) is inserted immediately before the last 3 bits with a period of 3 bits for the data input in this order,
As data X, u1, 0, y1, 0, x2, ...
As data Y, v1, x1, u2, v2, y2, ...
Are supplied in this order, and an insertion flag indicating the position where the dummy data is inserted is supplied to the Viterbi decoder 37.
[0138]
The Viterbi decoder 37 performs Viterbi decoding according to the state transition of the convolutional encoder 2 to obtain reproduction information 38. Next, the operation of the Viterbi decoder 37 will be described in detail.
[0139]
When the dummy data is inserted as X in the bit insertion circuit 36 and the insertion flag for X is input, the selector 132-1 and the selector 132-3 set the value 1 to invalidate the metric probability calculation for the dummy data. Output.
[0140]
Similarly, the selector 132-2 and the selector 132-4 invalidate the metric probability calculation for the dummy data when dummy data is inserted as Y in the bit insertion circuit 36 and the insertion flag for Y is input. The value 1 is output.
[0141]
That is, the calculation of branch metrics by the multiplication circuits 121-1 to 121-4 and the calculation of state metrics by the ACS circuits 122-1 to 122-4 are all performed by multiplication (described later), and therefore correspond to dummy data. By outputting the value 1, the metric calculation result is not affected.
[0142]
When dummy data is not inserted as X, the value X supplied from the bit insertion circuit 36 is supplied to the multiplication circuits 121-1 and 121-2 via the selector 132-1, and the value X is inverted. The value is supplied to multiplication circuits 121-3 and 121-4.
[0143]
Similarly, when dummy data is not inserted as Y, the value Y supplied from the bit insertion circuit 36 is supplied to the multiplication circuits 121-1 and 121-3 via the selector 132-2, and the value Y A value obtained by inverting is supplied to the multiplication circuits 121-2 and 121-4.
[0144]
In the multiplication circuit 121-1, the data X corresponding to the probability that the value of the first bit of the output of the bit insertion circuit 36 is 0 or the value of the third bit is 0, and the second bit The product of the data Y corresponding to the probability that the value of 0 or the value of the fourth bit is 0 (that is, the value of the first bit is 0 and the value of the second bit is 0 Or the probability that the value of the third bit is 0 and the value of the fourth bit is 0) is output as branch metric BM00. The branch metric BM00 corresponds to the code output 00 of the convolutional encoder 2.
[0145]
Similarly, the multiplication circuit 121-2 includes a value X corresponding to the probability that the value of the first bit of the output of the bit insertion circuit 36 is 0 or the value of the third bit is 0, and the second value The product of values corresponding to the probability that the value of the bit is 1 or the value of the fourth bit is 1 (the value obtained by inverting the value Y) (that is, the value of the first bit is 0, and The probability that the value of the second bit is 1 or the probability that the value of the third bit is 0 and the value of the fourth bit is 1) is calculated and output as the branch metric BM01. This branch metric BM01 corresponds to the code output 01 of the convolutional encoder 2.
[0146]
The multiplication circuit 121-3 has a value (a value obtained by inverting the value X) corresponding to the probability that the value of the first bit of the output of the bit insertion circuit 36 is 1 or the value of the third bit is 1. , The product of the values Y corresponding to the probability that the value of the second bit is 0 or the value of the value of the fourth bit is 0 (ie, the value of the first bit is 1 and the second value The probability that the value of the bit is 0 or the probability that the value of the third bit is 1 and the value of the fourth bit is 0) is calculated and output as the branch metric BM10. This branch metric BM 10 corresponds to the code output 10 of the convolutional encoder 2.
[0147]
The multiplication circuit 121-4 has a value (a value obtained by inverting the value X) corresponding to the probability that the value of the first bit of the output of the bit insertion circuit 36 is 1 or the value of the third bit is 1. , The product of the values corresponding to the probability that the value of the second bit is 1 or the probability that the value of the fourth bit is 1 (the value obtained by inverting the value Y) (that is, the value of the first bit is 1) The probability that the value of the second bit is 1 or the probability that the value of the third bit is 1 and the value of the fourth bit is 1), and the branch metric BM11 Output as. The branch metric BM11 corresponds to the code output 11 of the convolutional encoder 2.
[0148]
When dummy data is inserted as X or Y, the selectors 132-1 to 132-4 select 1 instead of the dummy data, so that the multiplication circuits 121-1 to 121-4 An input value not corresponding to data is output as it is (multiplied by 1) as a branch metric.
[0149]
The ACS circuit 122-1 calculates the following two equations according to the state transition of the convolutional encoder 2 (FIG. 10).
SM00 × BM00 (8)
SM01 × BM11 (9)
[0150]
Here, SM00 is the value of the state metric storage device 66-1 one unit time ago, SM01 is the value of the state metric storage device 66-2 one unit time ago, and BM00 is the calculation result of the multiplication circuit 121-1. BM11 represents the calculation result of the multiplication circuit 121-4.
[0151]
Then, the ACS circuit 122-1 selects the one with the highest likelihood, that is, the one with the larger calculation result among the equations (8) and (9), and outputs the selection information SEL00 to the path memory 65 at the subsequent stage. At the same time, the larger one of the results obtained by calculating the equations (8) and (9) is supplied to and stored in the subsequent state metric storage device 66-1. That is, if the calculation result of Expression (8) is larger, SEL00 = 0, and if the calculation result of Expression (9) is larger, SEL00 = 1. In the former case, SM00 × BM00 is stored, and in the latter case, SM01 × BM11 is stored as a new state metric SM00 in the state metric storage device 66-1.
[0152]
The ACS circuits 122-2 to 122-4 operate in the same manner, and calculate new state metrics SM01 to SM11.
[0153]
The other operations in the Viterbi decoder 37 are the same as those in FIG.
[0154]
FIG. 4 shows another configuration example of the metric calculation circuit 39.
[0155]
The A / D converter 141-1 converts the I component signal I ′ supplied from the symbol despreading circuit 33 into a digital value, and outputs the value to the ROMs 142-1 to 142-4 as address data. Has been made.
[0156]
The A / D converter 141-2 converts the Q component signal Q ′ supplied from the symbol despreading circuit 33 into a digital value and outputs the value to the ROMs 142-1 to 142-4 as address data. Has been made.
[0157]
The ROM 142-i (i = 1,..., 4) stores the value stored in the address corresponding to the address data supplied from the A / D converters 141-1 and 141-2 with respect to the i-th bit. A metric is output to the bit reverse conversion circuit 101-i.
[0158]
That is, in the ROM 142-i (i = 1,..., 4), the total value of the above-described posterior probabilities corresponding to the respective values of the I component I ′ and the Q component Q ′ of the received signal R is i-th. Is stored in advance as a metric for each bit.
[0159]
FIG. 5 shows the configuration of the second embodiment of the present invention. In the second embodiment, the second metric calculation circuit 40 is inserted between the metric calculation circuit 39 and the bit inverse conversion circuits 101-1 to 101-4 of the first embodiment. Only the circuit 40 will be described, and description of other components will be omitted.
[0160]
FIG. 6 shows a configuration example of the second metric calculation circuit 40.
[0161]
In the second metric calculation circuit 40, the logarithm calculator 151-1 calculates the natural logarithm (log (u ′)) of the value u ′ supplied from the metric calculation circuit 39, and the value is inverted by the inversion circuit 152-. 1 is output.
[0162]
The logarithm calculator 151-2 calculates the natural logarithm (log (v ′)) of the value v ′ supplied from the metric calculation circuit 39, and outputs the value to the inverting circuit 152-2.
[0163]
Similarly, the logarithm calculator 151-3 calculates the natural logarithm (log (x ′)) of the value x ′ supplied from the metric calculation circuit 39, outputs the value to the inversion circuit 152-3, and performs the logarithmic operation. The calculator 151-4 calculates the natural logarithm (log (y ′)) of the value y ′ supplied from the metric calculation circuit 39 and outputs the value to the inverting circuit 152-4.
[0164]
The inverting circuit 152-1 obtains a value (−log (u ′)) obtained by multiplying the value (log (u ′)) supplied from the logarithmic calculator 151-1 by −1 and the metric u for the first bit. ₁ 'Is output to the bit reverse conversion circuit 101-1.
[0165]
The inverting circuit 152-2 uses a value (-log (v ')) obtained by multiplying the value (log (v')) supplied from the logarithmic calculator 151-2 by -1 as the metric v for the second bit. ₁ 'Is output to the bit reverse conversion circuit 101-2.
[0166]
Similarly, the inverting circuit 152-3 sets a value (-log (x ')) obtained by multiplying the value (log (x')) supplied from the logarithm calculator 151-3 by -1 to the third bit. Metric x ₁ 'Is output to the bit inverse conversion circuit 101-3, and the inverting circuit 152-4 multiplies the value (log (y')) supplied from the logarithmic calculator 151-4 by -1 (-log (y ')) For the metric y for the third bit ₁ 'Is output to the bit reverse conversion circuit 101-4.
[0167]
Next, the metric used in the second embodiment will be described.
[0168]
When the signal R received by the receiving apparatus is temporally independent, the Viterbi decoder 37 calculates the product of the conditional posterior probabilities P (bi = 0 | R) described above.

The sequence with the largest value (ie, the maximum likelihood path) is selected and decoded.
[0169]
Here, R (t) represents a received signal at time t, {R (t)} represents a received signal sequence, and P ({R (t)}) represents a received signal sequence {R (t )}. bi (t) is the value (0 or 1) of the i-th bit constituting the transmission symbol at time t, and {bi (t)} represents the bit data sequence to be transmitted. {Bi (t)} takes two values of 0 or 1 corresponding to the values of t and i. Therefore, when the sequence length is 2, {00}, {01}, {10} , And {11}, and when the sequence length is 3, there are 8 sequences, and when the sequence length is 4, there are 16 sequences.
[0170]
The Viterbi decoder 37 selects the most likely transmission sequence (maximum likelihood path) when receiving the received signal sequence {R (t)} among the plurality of sequences. That is, the Viterbi decoder 37 selects a path having the maximum product of the conditional posterior probabilities P (bi = 0 | R). Since the denominator ΠP (R (t)) in equation (10) does not depend on the type of path, the Viterbi decoder 37 uses the numerator （P (bi (t) = 0∩R (t) in equation (10). ) Should be selected.
[0171]
Further, in the second embodiment, the functional form of the probability P (bi (t) = 0∩R (t)) (P (bi = 0∩R) at time t), which is the metric in the first embodiment. Is assumed to be an exponential function as shown in the following equation.
P (bi (t) = 0∩R (t)) = exp (−A _i (T)) (11)
[0172]
At this time, the molecule ΠP (bi (t) = 0∩R (t)) of the formula (10) is

And the Viterbi decoder 37 is
ΣA _i (T) = Σ (−log (P (bi (t) = 0∩R (t)))) (13)
The path with the smallest value of may be selected as the maximum likelihood path.
[0173]
Therefore, the metric for each bit i at each time t is
-Log (P (bi (t) = 0∩R (t))) (14)
It becomes the value obtained by. That is, in the first embodiment, the metric calculation circuit 39 has the formula
P (bi (t) = 0∩R (t)) (15)
In the second embodiment, the second metric calculation circuit 40 uses the natural logarithm of the value calculated by the metric calculation circuit 39 (the value obtained by Expression (15)). A metric according to the equation (14) is calculated by calculating a value multiplied by -1.
[0174]
The logarithmic calculators 151-1 to 151-4 may calculate a common logarithm instead of the natural logarithm.
[0175]
Further, instead of the metric calculation circuit 39 and the second metric calculation circuit 40, the metric calculation circuit 39 shown in FIG. 4 is used to store the I of the received signal R in the ROM 142-i (i = 1,..., 4). The logarithm of the total value of the posterior probabilities corresponding to the values of the component I ′ and the Q component Q ′ may be stored in advance as a metric for the i-th bit.
[0176]
FIG. 7 shows a configuration example of the Viterbi decoder 37 of the second embodiment. In the Viterbi decoder 37 of FIG. 7, as described above, the probability that the value of the first bit of the symbol is 0 or the value of the third bit is 0 from the input terminals 62-1 and 62-2. When the probability is assumed to be an exponential function, the data X corresponding to the exponent part and the probability that the value of the second bit of the symbol is 0 or the probability that the value of the fourth bit is 0 are assumed to be an exponential function. Data Y corresponding to the exponent part of the hour is input.
[0177]
The value X input from the input terminal 62-1 is input to the selector 164-1 and also input to the subtraction circuit 161-1. The subtraction circuit 161-1 subtracts X from the maximum value of the exponent part, and then outputs the value to the selector 164-3. The value Y input from the input terminal 62-2 is input to the selector 164-2 and also input to the subtraction circuit 161-2. The subtracting circuit 161-2 subtracts Y from the maximum value of the exponent part, and then outputs the value to the selector 164-4.
[0178]
The selector 164-1 receives the value 0 which is the output of the constant generation circuit 165-1 and the value X via the input terminal 62-1, and when the insertion flag for X is input from the bit insertion circuit 36. The value 0 generated by the constant generation circuit 165-1 is selected. At other times, the value X is selected, and the selected value is output to the addition circuits 162-1 and 162-2.
[0179]
The selector 164-2 receives the value 0 output from the constant generation circuit 165-2 and the value Y via the input terminal 62-2, and when the insertion flag for Y is input from the bit insertion circuit 36. The value 0 generated by the constant generation circuit 165-2 is selected. At other times, the value Y is selected, and the selected value is output to the addition circuits 162-1 and 162-3.
[0180]
The selector 164-3 is supplied with a value 0 which is the output of the constant generation circuit 165-3 and a value obtained by subtracting the value X from the maximum value of the exponent part which is the output of the subtraction circuit 161-1. From 36, when the insertion flag for X is input, the value 0 generated by the constant generation circuit 165-3 is selected. In other cases, the value obtained by subtracting the value X from the maximum value of the exponent is selected and selected. The value is output to the adder circuits 162-3 and 162-4.
[0181]
The selector 164-4 is supplied with a value 0 which is the output of the constant generation circuit 165-4 and a value obtained by subtracting the value Y from the maximum value of the exponent part which is the output of the subtraction circuit 161-2. From 36, when the insertion flag for Y is input, the value 0 generated by the constant generation circuit 165-4 is selected, and at other times, the value obtained by subtracting the value Y from the maximum value of the exponent part is selected and selected. The value is output to the adder circuits 162-2 and 162-4.
[0182]
The adder circuit 162-1 adds the value supplied from the selector 164-1 and the value supplied from the selector 164-2, and outputs the result as a branch metric BM00. The adder circuit 162-2 adds the value supplied from the selector 164-1 and the value supplied from the selector 164-4, and outputs the result as a branch metric BM01. Similarly, the adder circuit 162-3 adds the value supplied from the selector 164-2 and the value supplied from the selector 164-3, and outputs the result as a branch metric BM10. The adder circuit 162-4 The value supplied from the selector 164-3 and the value supplied from the selector 164-4 are added, and the result is output as the branch metric BM11.
[0183]
The output BM00 of the adder circuit 162-1 and the output BM11 of the adder circuit 162-4 are input to the ACS circuits 163-1 and 163-3. Similarly, the output BM01 of the adder circuit 162-2 and the output BM10 of the adder circuit 162-3 are input to the ACS circuits 163-2 and 163-4.
[0184]
The ACS circuits 163-1 and 163-3 are also supplied with the output SM00 of the state metric storage device 66-1 and the output SM01 of the state metric storage device 66-2, and are input to the ACS circuits 163-2 and 163-4. Are inputted with the output SM10 of the state metric storage device 66-3 and the output SM11 of the state metric storage device 66-4.
[0185]
The ACS circuits 163-1 to 163-4 add the inputted branch metrics and state metrics, calculate new state metrics, and output the calculation results to the state metric storage devices 66-1 to 66-4. At the same time, information SEL00 to SEL11 corresponding to the selected path is output to the path memory 65.
[0186]
Since the ACS circuits 163-1 to 163-4 of the Viterbi decoder 37 of FIG. 7 add the branch metric to the state metric and update the path metric, the selectors 164-1 and 164-3 have an insertion flag for X. Is input, the value 0 generated by the constant generation circuits 133-1 and 133-3 is output to the addition circuits 162-1 and 162-3, respectively, and the selectors 164-2 and 164-4 are inserted flags for Y Is input, the value 0 generated by the constant generation circuits 133-2 and 133-4 is output to the addition circuits 162-2 and 162-4, respectively, so that the dummy data affects the metric calculation result. I am trying not to.
[0187]
As described above, in the above embodiment, when the reception signal R is received, the transmission symbol is the predetermined symbol S. _j Conditional posterior probability P (S _j | R) instead of the predetermined symbol S _j Is transmitted, and the posterior probability P (S _j ∩R) and calculate the posterior probability P (S _j From (R), a metric for each bit of the symbol is calculated. By doing so, it is possible to calculate a metric for data transmitted by the 16QAM system and to accurately decode the received data.
[0188]
In the above embodiment, the data is modulated and demodulated by the 16QAM system. In addition to this, multilevel multiphase modulation in which the I component and the Q component each correspond to two or more bits such as 64QAM and 256QAM. Even when the method is adopted, the present invention can be applied.
[0189]
【The invention's effect】
As described above, according to the data receiving device according to claim 1 and the data receiving method according to claim 4, a symbol of predetermined data is transmitted and the posterior probability that the symbol is received is determined for each symbol. For each bit of a symbol, the sum of the posterior probabilities of a symbol whose bit is a predetermined value is calculated as a metric for that bit, so the metric can be calculated with a relatively simple circuit. It is possible to receive and accurately decode a signal transmitted by a multi-level polyphase modulation system in which each of the I component and the Q component corresponds to 2 bits or more.
[0190]
According to the data receiving device according to claim 5 and the data receiving method according to claim 8, a posterior probability that a symbol of predetermined data is transmitted and the symbol is received is calculated for each symbol, For each bit, a value obtained by multiplying the logarithm of the sum of the posterior probabilities of symbols having a predetermined value by −1 is calculated as a metric for that bit, so the metric can be calculated with a relatively simple circuit. It is possible to calculate and receive a signal transmitted by the multi-level polyphase modulation method in which each of the I component and the Q component corresponds to 2 bits or more, and can be accurately decoded.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a data receiving apparatus of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a metric calculation circuit in FIG. 1;
FIG. 3 is a block diagram illustrating a configuration example of the Viterbi decoder of FIG. 1;
4 is a block diagram showing another configuration example of the metric calculation circuit of FIG. 1. FIG.
FIG. 5 is a block diagram showing a configuration of a second embodiment of the data receiving apparatus of the present invention;
6 is a block diagram illustrating a configuration example of a second metric calculation circuit in FIG. 5. FIG.
7 is a block diagram illustrating a configuration example of the Viterbi decoder of FIG. 5;
FIG. 8 is a block diagram illustrating a configuration example of a conventional data transmission apparatus.
9 is a block diagram illustrating a configuration example of a convolutional encoder in FIG. 8. FIG.
10 is a diagram for explaining state transition of the convolutional encoder in FIG. 9; FIG.
FIG. 11 is a diagram for explaining signal point arrangement of QPSK;
FIG. 12 is a block diagram illustrating a configuration example of a conventional data receiving apparatus.
13 is a block diagram illustrating a configuration example of the Viterbi decoder of FIG.
14 is a block diagram illustrating a configuration example of a branch metric calculation circuit in FIG. 13;
15 is a block diagram illustrating a configuration example of the path memory in FIG. 13;
FIG. 16 is a block diagram illustrating a configuration example of a data transmission apparatus when 16QAM is used.
FIG. 17 is a diagram for explaining 16QAM signal point arrangement;
18 is a diagram illustrating a configuration example of a data receiving device that receives data transmitted by the device in FIG. 16;
FIG. 19 is a diagram for explaining the operation of the embodiment of FIG. 18;
[Explanation of symbols]
32 demodulator, 33 symbol despreading circuit, 35 parallel-serial converter, 36-bit insertion circuit, 37 Viterbi decoder, 38 reproduction information, 39 metric calculation circuit, 40 second metric calculation circuit, 101-1 to 101-4 bits Despreading circuit, 111-1 to 111-16 probability calculation circuit, 112-1 to 112-4 adder circuit, 141-1, 141-2 A / D converter, 142-1 to 142-4 ROM, 151-1 To 151-4 logarithmic arithmetic unit, 152-1 to 152-4 inversion circuit

Claims (8)

In a data receiving apparatus for receiving data that is digitally modulated and transmitted in a multi-value multi-phase system,
The posterior probability that the symbol of the data is transmitted and received is calculated for each symbol, and the sum of the posterior probabilities of the symbols whose predetermined bits are a predetermined value is calculated as a metric for the bits. Metric calculation means to
A data receiving apparatus comprising: decoding means for decoding the data using the metric. 2. The data receiving apparatus according to claim 1, wherein the metric calculating unit calculates the posterior probability from an I component and a Q component of the received data. The metric calculation unit converts received data into a digital value, and outputs the metric stored in advance in a predetermined storage unit corresponding to the digital value. Data receiving device. In a data receiving method for receiving data that has been digitally modulated and transmitted in a multi-value multi-phase system,
The posterior probability that the symbol of the data is transmitted and received is calculated for each symbol, and the sum of the posterior probabilities of the symbols whose predetermined bits are a predetermined value is calculated as a metric for the bits. And steps to
And a step of decoding the data using the metric. In a data receiving apparatus for receiving data that is digitally modulated and transmitted in a multi-value multi-phase system,
The posterior probability that the symbol of the data is transmitted and the symbol is received is calculated for each symbol, and the logarithm of the sum of the posterior probabilities of the symbols whose predetermined bits are a predetermined value is multiplied by -1. A metric calculator that calculates the value as a metric for that bit;
A data receiving apparatus comprising: decoding means for decoding the data using the metric. 6. The data receiving apparatus according to claim 5, wherein the metric calculating unit calculates the posterior probability from an I component and a Q component of received data. The said metric calculation means converts the received data into a digital value, and outputs the said metric previously stored in a predetermined storage unit corresponding to the digital value. Data receiving device. In a data receiving method for receiving data that has been digitally modulated and transmitted in a multi-value multi-phase system,
The posterior probability that the symbol of the data is transmitted and the symbol is received is calculated for each symbol, and the logarithm of the sum of the posterior probabilities of the symbols whose predetermined bits are a predetermined value is multiplied by -1. Calculating a value as a metric for that bit;
And a step of decoding the data using the metric.

Images