JPH10107340A - Method for manufacturing fine tunnel junction part and method for manufacturing fine tunnel junction element - Google Patents

Method for manufacturing fine tunnel junction part and method for manufacturing fine tunnel junction element

Info

Publication number
JPH10107340A
JPH10107340A JP8256177A JP25617796A JPH10107340A JP H10107340 A JPH10107340 A JP H10107340A JP 8256177 A JP8256177 A JP 8256177A JP 25617796 A JP25617796 A JP 25617796A JP H10107340 A JPH10107340 A JP H10107340A
Authority
JP
Japan
Prior art keywords
deposition
film
tunnel junction
mask
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8256177A
Other languages
Japanese (ja)
Other versions
JP2917933B2 (en
Inventor
Chiyoushin Sai
兆申 蔡
Yasunobu Nakamura
泰信 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8256177A priority Critical patent/JP2917933B2/en
Publication of JPH10107340A publication Critical patent/JPH10107340A/en
Application granted granted Critical
Publication of JP2917933B2 publication Critical patent/JP2917933B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the size of an island to approximately the limiting resolution of lithography and to increase the operating temperature by passing through the hole of a mask being suspended in the air, changing a deposition angle at least for a specific number of times, and forming a metal deposition film on a substrate successively. SOLUTION: A first deposition 5 is performed through a suspension mask 3, and a first deposition film 7 is formed. Then, after the surface the first deposition metal film 7 is has been oxidized, deposition 6 is performed from a direction that is different from that of the first deposition through the same mask 3, and a second deposition film 8 is formed so that one portion contacts via first deposition film 7 and an oxide film. Then, a third deposition 10 is performed from a direction that is different from that of the depositions 5 and 6 through the same mask 3, and a third deposition film 9 is formed, so that it contacts via the first deposition film and oxide film at a part that is different from the overlapped part of the first and second deposition films, thus forming an island with a size (d) and two-tunnel junctions.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は単一電子トンネル素
子の製造方法に関する。
The present invention relates to a method for manufacturing a single electron tunnel device.

【0002】[0002]

【従来の技術】単一電子トンネル素子の構成要素である
微小なトンネル接合を作成するにはリソグラフィ技術が
不可欠である。金属系の微小トンネル接合形成のリソグ
ラフィを最も簡易化したものに図9、図10、図11に
示す中空に懸架されたマスク3を使った2重蒸着法があ
る。
2. Description of the Related Art A lithography technique is indispensable for forming a minute tunnel junction which is a component of a single electron tunnel element. The most simplified lithography for forming a metal-based small tunnel junction is a double vapor deposition method using a mask 3 suspended in the air as shown in FIGS. 9, 10 and 11.

【0003】この従来の方法では、まず図9に示すよう
に、スペーサー2により基板1より持ち上げられ、部分
的に中空に浮いた懸架マスク3を準備する。次に、図9
に示したように、この懸架マスク3を通してある角度
の方向より第一の金属膜の蒸着5を行った後、第一の
金属膜表面を酸化して第一の金属膜上に酸化膜バリアを
形成する。次に同じ懸架マスク3を通して第一の蒸着
5とは異なる角度の方向より蒸着6を行う。この第
2の蒸着は、酸化膜バリアを介して第一の金属膜と2ヵ
所において部分的に重複するように行う。
In this conventional method, first, as shown in FIG. 9, a suspension mask 3 which is lifted above a substrate 1 by a spacer 2 and partially floats in a hollow state is prepared. Next, FIG.
As shown in (1), after the deposition 5 of the first metal film is performed from the direction of a certain angle through the suspension mask 3, the surface of the first metal film is oxidized to form an oxide film barrier on the first metal film. Form. Next, vapor deposition 6 is performed through the same suspension mask 3 from a direction at an angle different from that of the first vapor deposition 5. The second vapor deposition is performed so as to partially overlap the first metal film at two places via the oxide film barrier.

【0004】このように、との異なる方向から同じ
マスクを用いて金属膜の蒸着5と蒸着6を順次行
い、2回の蒸着工程の間に金属膜の酸化を行い第一の金
属膜上に酸化膜バリアを形成することにより、第1、第
2の蒸着膜が重複する2ヵ所に微小トンネル接合4が形
成される。
As described above, the deposition 5 and the deposition 6 of the metal film are sequentially performed using the same mask from different directions from the above, and the metal film is oxidized between the two deposition steps to form a film on the first metal film. By forming the oxide film barrier, the minute tunnel junction 4 is formed at two places where the first and second deposited films overlap.

【0005】最も単純な単一電子素子である2接合より
成る単一電子トランジスタを例にとり、そのマスクパタ
ン及び各工程を、図10、図11を用いて説明する。
[0005] The mask pattern and each step will be described with reference to FIGS. 10 and 11 taking a single electron transistor consisting of two junctions, which is the simplest single electron element, as an example.

【0006】図10(a)はマスクパタンである。明る
い部分がマスクに空いた孔である。このようなマスクを
通して図10(b)の様な第一の金属膜7を成膜する。
FIG. 10A shows a mask pattern. The bright areas are the holes in the mask. A first metal film 7 as shown in FIG. 10B is formed through such a mask.

【0007】その後、第一の金属膜7表面を酸化して第
一の金属膜上に酸化膜バリアを形成する。次に同じ懸架
マスク3を通して、成膜角度を「縦方向」にずらして、
第一の金属膜と酸化膜を介して2ヵ所で部分的に重複す
るように第二の金属膜8を成膜すると、図10(c)の
様な二つの接合(酸化膜を介して第一、第二の金属膜が
重複する領域)とd′という大きさを持つ島より成る単
一電子トランジスタができる(ゲート電極は省略してあ
る)。
After that, the surface of the first metal film 7 is oxidized to form an oxide film barrier on the first metal film. Next, the film forming angle is shifted in the “vertical direction” through the same suspension mask 3,
When the second metal film 8 is formed so as to partially overlap at two places with the first metal film and the oxide film interposed therebetween, two junctions as shown in FIG. A single-electron transistor composed of an island having a size of d 'and a region where the first and second metal films overlap (gate electrode is omitted) is obtained.

【0008】また図11(a)のようなマスクを通し
て、図11(b)の様な第一の金属膜7を成膜し、その
後、第一の金属膜7表面を酸化して第一の金属膜上に酸
化バリアを形成する。次に同じ懸架マスク3を通して、
成膜角度を「横方向」にずらして、第一の金属膜と酸化
膜を介して2ヵ所で部分的に重複するように第二の金属
膜8を成膜すると、図11(c)の様な二つの接合(第
一、第二の金属膜が接する領域)とdという大きさを持
つ島7より成る単一電子トランジスタができる(ゲート
電極は省略してある)。
Further, a first metal film 7 as shown in FIG. 11B is formed through a mask as shown in FIG. 11A, and then the surface of the first metal film 7 is oxidized to An oxidation barrier is formed on the metal film. Next, through the same suspension mask 3,
When the film forming angle is shifted in the "lateral direction" and the second metal film 8 is formed so as to partially overlap at two places via the first metal film and the oxide film, the film shown in FIG. Thus, a single-electron transistor comprising two junctions (regions where the first and second metal films are in contact) and an island 7 having a size of d can be obtained (the gate electrode is omitted).

【0009】本明細書では、島とは、トンネル接合によ
り外部電極(リード電極12)に接続している孤立した
電極領域を指すこととする。
In this specification, an island refers to an isolated electrode region connected to an external electrode (lead electrode 12) by a tunnel junction.

【0010】[0010]

【発明が解決しようとする課題】単一電子素子の動作温
度は、その静電エネルギーの大きさの依存する。静電エ
ネルギーの大きさは、素子の総静電容量に反比例する。
素子の総静電容量は、究極的には島の自己静電容量によ
り制限される。
The operating temperature of a single electronic device depends on the magnitude of its electrostatic energy. The magnitude of the electrostatic energy is inversely proportional to the total capacitance of the device.
The total capacitance of the device is ultimately limited by the island's self capacitance.

【0011】島の自己静電容量は、島の大きさ(この場
合の島の大きさとは、島の厚さ、長さ、幅のうち一番大
きい寸法)に比例する。従って、動作温度の高い単一電
子素子を得るには、できるだけ小さな島を作らなくては
ならない。
The self-capacitance of the island is proportional to the size of the island (the size of the island in this case is the largest dimension among the thickness, length and width of the island). Therefore, in order to obtain a single electronic device having a high operating temperature, as small an island as possible must be formed.

【0012】従来の2重蒸着法では、島の大きさはd′
であるが、図10の様な縦方向に蒸着角度を変化させた
製法では、島の中心にトンネル接合には不必要なj′と
いう長さの領域ができる。この領域の影響を輸送特性に
反映させないようにするには、接合部の長さをjとする
と、j′>>jという条件が必要である。
In the conventional double vapor deposition method, the size of the island is d '.
However, in the manufacturing method in which the deposition angle is changed in the vertical direction as shown in FIG. 10, a region having a length of j 'which is unnecessary for the tunnel junction is formed at the center of the island. In order to prevent the influence of this region from being reflected on the transport characteristics, a condition of j ′ >> j is required, where j is the length of the joint.

【0013】jは蒸着角度で決まるが、制御性に影響さ
れ、通常j≒wである。d′>d>j′であり、リソグ
ラフィの分解能がδであれば、その限界ではδ≒w≒j
となる。したがってd′>>dとなり、島の大きさはリ
ソグラフィ分解能よりずいぶん大きなものになってしま
う。
Although j is determined by the deposition angle, it is affected by controllability, and usually j ≒ w. If d ′>d> j ′ and the resolution of lithography is δ, then at its limit, δ ≒ w ≒ j
Becomes Therefore, d '>> d, and the size of the island is much larger than the lithography resolution.

【0014】また、図11の様に横方向に蒸着角度を変
化させた製法では、島11の大きさdは電極間の距離D
によってほぼ決定される(d=D+2j)。しかし、図
11(a)の様なDという幅の狭い橋状のマスクを電子
ビームリソグラフィで作ると、露光時の近接効果による
過剰露光の影響のため、どうしてもd>D>δ≒wとな
ってしまう。
In the manufacturing method in which the deposition angle is changed in the horizontal direction as shown in FIG. 11, the size d of the island 11 is equal to the distance D between the electrodes.
(D = D + 2j). However, when a narrow bridge-shaped mask called D as shown in FIG. 11A is formed by electron beam lithography, d>D> δ ≒ w due to the influence of excessive exposure due to the proximity effect at the time of exposure. Would.

【0015】従って、従来の方法ではどのようにしても
島の大きさをリソグラフィの限界分解能δまで小さくす
ることが出来ず、動作温度を高くすることが出来なかっ
た。
Accordingly, in the conventional method, the size of the island cannot be reduced to the limit resolution δ of lithography in any way, and the operating temperature cannot be increased.

【0016】本発明の目的は、上記問題点を解決し、島
の大きさをリソグラフィの限界分解能δ程度に小さくし
て、動作温度の高い単一電子素子の製造方法を提供する
ことにある。
An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a single electronic device having a high operating temperature by reducing the size of an island to about the limit resolution δ of lithography.

【0017】[0017]

【課題を解決するための手段】本発明の微小トンネル接
合部の製造方法は、中空に懸架したマスクの孔を通し、
3回以上蒸着角度を変化させて、基板上に金属蒸着膜を
順次成膜して複数の前記蒸着膜が部分的に重複する重複
部を形成し、前記複数回の蒸着成膜工程間に同一蒸着装
置内で前記蒸着膜の前記重複部が形成される領域にトン
ネルバリアを成長させることにより、前記重複部にトン
ネル接合を形成することを特徴とする。
According to the present invention, there is provided a method for manufacturing a micro-tunnel junction, comprising the steps of:
By changing the deposition angle three times or more, a metal deposition film is sequentially formed on the substrate to form an overlapping portion in which the plurality of deposition films partially overlap, and the same portion is formed between the plurality of deposition film formation steps. A tunnel junction is formed in the overlapping portion by growing a tunnel barrier in a region where the overlapping portion of the deposited film is formed in the deposition apparatus.

【0018】また本発明は、中空に懸架した同一のマス
クの孔を通し基板上に少なくとも3回以上の金属蒸着を
順次行う工程を有する微小トンネル接合部の製造方法で
あって、前記マスクの孔を通して基板上に第1の金属蒸
着膜を成膜する工程と、前記第1の金属蒸着膜表面の少
なくともトンネル接合部が形成される領域を同一蒸着装
置内で酸化してトンネルバリアを形成する工程と、前記
マスクを通して第1の蒸着方向とは異なる方向から第2
の金属膜蒸着を、第1の蒸着膜と前記酸化膜を介して一
部接するように行う第2の蒸着工程と、第1及び第2の
蒸着方向とは異なる方向から前記マスクを通して第3の
金属膜蒸着を、前記第1と第2の蒸着膜が接する重複部
とは異なる領域で、前記第1の蒸着膜と前記酸化膜を介
して一部接するように行う第3の蒸着工程と、第3回以
降の金属蒸着を、前回迄の蒸着方向とは異なる方向から
前記マスクを通して順次金属蒸着を行い、前回までの重
複部とは異なる領域で前記第1の蒸着膜と前記酸化膜を
介して一部接するように行う第3回以降の蒸着工程を有
し、前記重複部にトンネル接合が形成されることを特徴
とする微小トンネル接合部の製造方法である。
The present invention also relates to a method of manufacturing a micro tunnel junction comprising a step of sequentially performing metal deposition at least three times on a substrate through holes of the same mask suspended in the air, wherein the holes of the mask are provided. Forming a first metal deposition film on a substrate through a process and forming a tunnel barrier by oxidizing at least a region of the surface of the first metal deposition film where a tunnel junction is to be formed in the same deposition apparatus And the second through the mask from a direction different from the first deposition direction.
A second deposition step of partially depositing a metal film through the oxide film and the first deposition film, and a third deposition process through the mask from a direction different from the first and second deposition directions. A third vapor deposition step of performing metal film vapor deposition in a region different from the overlapping portion where the first and second vapor deposited films are in contact with each other via the first vapor deposited film and the oxide film; The third and subsequent metal depositions are performed sequentially through the mask from a direction different from the previous deposition direction, through the mask, and in a region different from the previous overlapping portion through the first deposited film and the oxide film. And a third or later deposition step in which a tunnel junction is formed at the overlapping portion.

【0019】懸架マスクは、マスク上に設けられた孔と
孔の間の距離が、孔自身の寸法より大きいものを使用す
ることが好ましい。
It is preferable to use a suspension mask in which the distance between the holes provided on the mask is larger than the size of the holes themselves.

【0020】また、本発明の微小トンネル接合素子の製
造方法は、上記に記載のいずれかの微小トンネル接合部
を形成し、前記複数回の蒸着工程により形成された前記
複数の重複部間の微小な島状領域上に電極(以下、この
電極を島電極と称す)を形成し、島電極とトンネル接合
部を介して接続する複数のリード電極を形成することを
特徴とする。
According to a method of manufacturing a micro tunnel junction device of the present invention, the micro tunnel junction described above is formed, and the micro tunnel junction is formed between the plurality of overlapping portions formed by the plurality of vapor deposition steps. An electrode (hereinafter, this electrode is referred to as an island electrode) is formed on an island-like region, and a plurality of lead electrodes connected to the island electrode via a tunnel junction are formed.

【0021】さらに、前記複数回の蒸着成膜の工程間
に、同一蒸着装置中で前記島電極上にゲート絶縁膜を成
長し、ゲート絶縁膜上にゲート電極を形成することを特
徴とする微小トンネル接合素子の製造方法である。
Further, a gate insulating film is grown on the island electrode and the gate electrode is formed on the gate insulating film in the same vapor deposition device during the plurality of vapor deposition processes. This is a method for manufacturing a tunnel junction element.

【0022】[0022]

【発明の実施の形態】本発明による製造方法の一実施の
形態を図8を用いて説明する。図8は、本発明による製
造されるトンネル接合部の断面図である。
One embodiment of the manufacturing method according to the present invention will be described with reference to FIG. FIG. 8 is a sectional view of a tunnel junction manufactured according to the present invention.

【0023】まず、懸架マスク3を通してある角度より
第一の蒸着5を行い、第一の蒸着膜7を成膜する。次
に、第一の蒸着金属膜7の表面を酸化した後、同じマス
ク3を通して第一の蒸着とは異なる方向から蒸着6を
行い、第一の蒸着膜7と酸化膜を介して一ヵ所で一部が
接するように第二の蒸着膜8を成膜する。
First, the first vapor deposition 5 is performed from a certain angle through the suspension mask 3 to form a first vapor deposition film 7. Next, after oxidizing the surface of the first vapor-deposited metal film 7, vapor deposition 6 is performed through the same mask 3 from a direction different from that of the first vapor deposition, and at one place via the first vapor-deposited film 7 and the oxide film. The second deposited film 8 is formed so as to be partially in contact.

【0024】続いて、同じマスク3を通して蒸着5、
蒸着6とは異なる方向から第三の蒸着10を行い、
先の第一、第二の蒸着膜の重複部とは異なる箇所に、第
一の蒸着膜と酸化膜を介して接するように第3の蒸着膜
9を成膜する。
Subsequently, vapor deposition 5 is performed through the same mask 3,
The third vapor deposition 10 is performed from a direction different from the vapor deposition 6,
A third deposited film 9 is formed at a location different from the overlapping portion of the first and second deposited films so as to be in contact with the first deposited film via an oxide film.

【0025】このようにして、dの大きさを持った島と
二つのトンネル接合部(第一と第二の蒸着膜が接する部
分と、第一と第三の蒸着膜が接する部分)が形成され
る。
In this manner, an island having a size of d and two tunnel junctions (a portion where the first and second deposited films are in contact and a portion where the first and third deposited films are in contact) are formed. Is done.

【0026】本発明により作製された島の大きさdは、
マスクにあいた孔のwと同じ程度であり、これにより島
の大きさをリソグラフィの限界δまで小さくすることが
出来る。
The size d of the island produced according to the present invention is
It is about the same as w of the hole formed in the mask, so that the size of the island can be reduced to the limit δ of lithography.

【0027】[0027]

【実施例】【Example】

(実施例1)図1は本発明の第1の実施例を示すもので
ある。図1(a)はこの実施例に使う懸架マスク3であ
る(上面図)。明るい部分がマスクに空いた孔である。
このマスクを通して図1(b)の様な第一の金属膜7を
成膜する。図1(b′)は図1(b)の断面図である。
(Embodiment 1) FIG. 1 shows a first embodiment of the present invention. FIG. 1A shows a suspension mask 3 used in this embodiment (top view). The bright areas are the holes in the mask.
A first metal film 7 as shown in FIG. 1B is formed through this mask. FIG. 1 (b ′) is a cross-sectional view of FIG. 1 (b).

【0028】成膜の方法は、成膜時の原子の方向成分が
比較的そろう熱蒸着法が適している。蒸着する金属膜の
材料に特に制限はないが、表面に安定な自然酸化膜がで
きる材料が望ましい。例えば、アルミなどは良く適した
金属素材である。
As a film forming method, a thermal evaporation method in which the direction components of atoms during film formation are relatively aligned is suitable. The material of the metal film to be deposited is not particularly limited, but a material capable of forming a stable native oxide film on the surface is desirable. For example, aluminum is a suitable metal material.

【0029】第1の金属成膜後、同一真空装置中に酸素
を導入し、膜表面を酸化させトンネルバリア(酸化膜1
4)を作製する。
After the first metal film is formed, oxygen is introduced into the same vacuum apparatus to oxidize the film surface and to form a tunnel barrier (oxide film 1).
4) is prepared.

【0030】次に成膜角度を「縦方向」に変化して第2
の金属膜8を成膜すると、図1(c)の様な重複した構
造が得られる。図1(c′)は図1(c)の断面図であ
る。その後、成膜角度を再度「縦方向」に変化して第3
の金属膜9を成膜すると、図1(d)の様な二つの接合
4と島11より成る単一電子トランジスタができる。図
1(d′)は図1(d)の断面図である。ゲート電極1
3も図1(d)、(d′)に示されるようにトンネル接
合部と同時に作製できる。
Next, the film forming angle is changed to the "vertical direction" and the second
When the metal film 8 is formed, an overlapping structure as shown in FIG. 1C is obtained. FIG. 1 (c ') is a cross-sectional view of FIG. 1 (c). Thereafter, the film forming angle is changed to the “vertical direction” again, and the third
When the metal film 9 is formed, a single electron transistor including two junctions 4 and islands 11 as shown in FIG. FIG. 1D is a cross-sectional view of FIG. Gate electrode 1
3 can be manufactured simultaneously with the tunnel junction as shown in FIGS. 1 (d) and (d ').

【0031】マスクの寸法でD>dとすれば、図10
(c)にあるような従来問題であったj′の大きさを持
った余分な接合が島に出来ることを防げる。本実施例に
よれば、島の大きさはマスクに空いた孔の大きさdとw
に等しく、これはリソグラフィの分解能と同等の大きさ
まで小さく出来る。
If D> d in the size of the mask, FIG.
It is possible to prevent an extra junction having the size of j ', which is a conventional problem as shown in FIG. According to the present embodiment, the size of the island is the size d and w of the hole formed in the mask.
, Which can be reduced to a size comparable to the resolution of lithography.

【0032】PMMA電子ビームレジストを使った場
合、リソグラフィの分解能は約20nmである。本実施
例により、Dを50nm、dとwをそれぞれ20nmと
して作製すると、20nmの島を持つ単一電子素子が得
られ、その動作温度は100K以上であった。従来の方
法では、動作温度を4K以上にすることが難しく、本発
明によれば動作温度の高い単一電子素子を作製すること
ができる。
When a PMMA electron beam resist is used, the resolution of lithography is about 20 nm. According to this example, when D was set to 50 nm and d and w were each set to 20 nm, a single electronic device having an island of 20 nm was obtained, and the operating temperature was 100K or more. In the conventional method, it is difficult to increase the operating temperature to 4K or more, and according to the present invention, a single electronic device having a high operating temperature can be manufactured.

【0033】(実施例2)図2は本発明の第2の実施例
を示すものである。図2(a)はこの実施例に使う懸架
マスクである(上面図)。明るい部分がマスクに空いた
孔である。このマスクを通して図2(b)の様な第一の
金属膜7を成膜する。図2(b′)は図2(b)の点A
と点AA間の点線に沿った断面図である。
(Embodiment 2) FIG. 2 shows a second embodiment of the present invention. FIG. 2A shows a suspension mask used in this embodiment (top view). The bright areas are the holes in the mask. Through this mask, a first metal film 7 as shown in FIG. 2B is formed. FIG. 2 (b ′) is a point A in FIG. 2 (b).
FIG. 4 is a cross-sectional view taken along a dotted line between a point AA and a point AA.

【0034】成膜後、同一真空装置中に酸素を導入し、
第1の蒸着膜表面を酸化させトンネルバリア(酸化膜1
4)を作製する。
After the film formation, oxygen is introduced into the same vacuum device,
The surface of the first deposited film is oxidized to form a tunnel barrier (oxide film 1).
4) is prepared.

【0035】次に、成膜角度を「横方向」に変化して第
2の金属膜8を成膜すると、図2(c)の様な重複した
構造が得られる。図2(c′)は図2(c)の点Aと点
AA間の点線に沿った断面図である。
Next, when the second metal film 8 is formed by changing the film forming angle to the “lateral direction”, an overlapping structure as shown in FIG. 2C is obtained. FIG. 2C is a cross-sectional view taken along a dotted line between points A and AA in FIG.

【0036】その後、成膜角度を再度「横方向」に変化
して第3の金属膜8を成膜すると、図2(d)の様な二
つの接合4と島11より成る単一電子トランジスタがで
きる(ゲート電極は省略してある)。図2(d′)は図
2(d)の点Aと点AA間の点線に沿った断面図であ
る。
After that, the third metal film 8 is formed by changing the film forming angle to the “lateral direction” again, and a single electron transistor comprising two junctions 4 and islands 11 as shown in FIG. (The gate electrode is omitted). FIG. 2D is a cross-sectional view taken along a dotted line between points A and AA in FIG.

【0037】マスクの寸法でDは島の大きさに関係なく
比較的大きく取れるので、従来問題であった露光時の近
接効果による過剰露光は避けられる。したがって島の大
きさはマスクに空いた孔の大きさdとwに等しく、これ
はリソグラフィの分解能と同等の大きさまで小さく出来
る。
Since the size D of the mask can be relatively large irrespective of the size of the island, overexposure due to the proximity effect at the time of exposure, which has been a conventional problem, can be avoided. Therefore, the size of the island is equal to the sizes d and w of the holes formed in the mask, which can be reduced to a size equivalent to the resolution of lithography.

【0038】マスクの寸法でD>wとすれば、いかよう
な重複部の寸法を選んでも、図10(c)にあるような
従来問題であったj′の大きさを持った余分な接合が島
に出来ることを防げる。
If D> w in the dimensions of the mask, no matter what the size of the overlapping portion is selected, an extra junction having the size of j ', which is a conventional problem as shown in FIG. Can be done on the island.

【0039】(実施例3)図3、図4は本発明の第3の
実施例を示すものである。図3と図4は一連の工程(a
〜e)を示す図であり、図面作成上、分図されている。
(Embodiment 3) FIGS. 3 and 4 show a third embodiment of the present invention. 3 and 4 show a series of steps (a
FIGS. 7A to 7E are diagrams which are divided for the purpose of drawing.

【0040】実施例1と実施例2では、2接合と島より
なる単一電子トランジスタを例にとり実施例を述べた
が、更に複雑な回路もこの多重角度蒸着法で作製出来
る。本実施例では、一つの島に3つの接合がついた回路
も、適当なマスクパターンを準備して4回角度を変えて
蒸着成膜する事により実現出来、その島の大きさもリソ
グラフィの分解能相当の大きさを保つことが出来る。
In the first and second embodiments, a single-electron transistor composed of two junctions and an island has been described as an example. However, a more complicated circuit can be manufactured by this multi-angle evaporation method. In this embodiment, a circuit having three junctions on one island can be realized by preparing an appropriate mask pattern and depositing the film four times at different angles, and the size of the island is equivalent to the resolution of lithography. Size can be maintained.

【0041】図3(a)はこの実施例に使う懸架マスク
3である(上面図)。明るい部分がマスクに空いた孔で
ある。このマスクを通して図3(b)の様な第一の金属
膜7を成膜する。成膜後同一真空装置中に酸素を導入し
膜表面を酸化させトンネルバリアを作製する。
FIG. 3A shows a suspension mask 3 used in this embodiment (top view). The bright areas are the holes in the mask. A first metal film 7 as shown in FIG. 3B is formed through this mask. After the film is formed, oxygen is introduced into the same vacuum apparatus to oxidize the film surface to form a tunnel barrier.

【0042】次に成膜角度を「横方向」に変化して第2
の金属膜8を成膜すると、図4(c)の様な重複した構
造が得られる。その後成膜角度を再度「横方向」に変化
して第3の金属膜9を成膜すると、図4(d)の様な二
つの接合ができる。その後成膜角度を再度「横方向」に
変化して第4の金属膜16を成膜すると一つの島に3つ
の接合がついた回路が実現できる。
Next, the film forming angle is changed to the “lateral direction” and the second
When the metal film 8 is formed, an overlapping structure as shown in FIG. 4C is obtained. Thereafter, when the third metal film 9 is formed by changing the film formation angle to the “lateral direction” again, two junctions as shown in FIG. 4D can be formed. Thereafter, when the film forming angle is changed to the “lateral direction” again and the fourth metal film 16 is formed, a circuit having three junctions on one island can be realized.

【0043】実施例1及び2と同様に、従来問題であっ
た露光時の近接効果による過剰露光は避けられる。した
がって島の大きさはマスクに空いた孔の大きさに等し
く、これはリソグラフィの分解能と同等の大きさまで小
さく出来る。
As in the first and second embodiments, overexposure due to the proximity effect at the time of exposure, which is a conventional problem, can be avoided. Thus, the size of the island is equal to the size of the hole in the mask, which can be reduced to a size equivalent to the resolution of lithography.

【0044】(実施例4)図5〜図7は本発明の第4の
実施例を示すものである。図5、図6、図7は一連の工
程(a〜f)を示す図であり、図面作成上、分図して記
載されている。
(Embodiment 4) FIGS. 5 to 7 show a fourth embodiment of the present invention. FIG. 5, FIG. 6, and FIG. 7 are views showing a series of steps (a to f).

【0045】実施例1と実施例2の単一トランジスタで
はゲート電極は素子の横に配置してある。電圧ゲインを
大きくするためにはゲートの静電容量を大きくとらなく
てはならない。本実施例では、2接合単一電子トランジ
スタの島に絶縁膜15を介して縦形のゲート電極を配置
することが出来、その時の島の大きさもリソグラフィの
分解能相当の大きさを保つことが出来る。
In the single transistors of the first and second embodiments, the gate electrode is arranged beside the element. In order to increase the voltage gain, the capacitance of the gate must be increased. In this embodiment, a vertical gate electrode can be arranged on the island of the two-junction single-electron transistor via the insulating film 15, and the size of the island at that time can be maintained at a size corresponding to the resolution of lithography.

【0046】図4(a)はこの実施例に使う懸架マスク
である(上面図)。明るい部分がマスクに空いた孔であ
る。このマスクを通して図5(b)の様な第一の金属膜
7を成膜する。成膜後同一真空装置中に酸素を導入し膜
表面を酸化させトンネルバリアを作製する。
FIG. 4A shows a suspension mask used in this embodiment (top view). The bright areas are the holes in the mask. A first metal film 7 as shown in FIG. 5B is formed through this mask. After the film is formed, oxygen is introduced into the same vacuum apparatus to oxidize the film surface to form a tunnel barrier.

【0047】次に成膜角度を「横方向」に変化して第2
の金属膜8を成膜すると、図6(c)の様な重複した構
造が得られる。その後成膜角度を再度「横方向」に変化
して第3の金属膜9を成膜すると、図6(d)の様な二
つの接合ができる。その後成膜角度を再度「横方向」に
変化して図6(e)のように、島の上部にかかるように
絶縁膜15を成膜する。最後に図7(f)のように更に
蒸着角度を変え、ゲート電極13を成膜する。
Next, the film forming angle is changed to the “horizontal direction” and the second
When the metal film 8 is formed, an overlapping structure as shown in FIG. 6C is obtained. Then, when the third metal film 9 is formed by changing the film forming angle to the “lateral direction” again, two junctions as shown in FIG. 6D can be formed. Thereafter, the film forming angle is changed to the “lateral direction” again, and the insulating film 15 is formed so as to cover the upper part of the island as shown in FIG. Finally, as shown in FIG. 7F, the deposition angle is further changed, and the gate electrode 13 is formed.

【0048】このように、本実施例によれば縦形のゲー
ト電極を有する単一電子トランジスタが実現出来る。そ
して同時に実施例1及び2と同様に、従来問題であった
露光時の近接効果による過剰露光が避けられる。したが
って島の大きさはマスクに空いた孔の大きさに等しく、
これはリソグラフィの分解能と同等の大きさまで小さく
出来る。
As described above, according to this embodiment, a single-electron transistor having a vertical gate electrode can be realized. At the same time, similarly to the first and second embodiments, the overexposure due to the proximity effect at the time of exposure, which is a conventional problem, can be avoided. Therefore, the size of the island is equal to the size of the hole in the mask,
This can be reduced to a size equivalent to the resolution of lithography.

【0049】[0049]

【発明の効果】以上説明したように本発明によれば、電
子ビームリソグラフィの分解能と同等の大きさを持つ島
を有する高温動作に適した単一電子素子を実現出来る。
また同時に従来問題であった余分な接合が島に出来るこ
とを防げる。
As described above, according to the present invention, it is possible to realize a single electronic device suitable for high-temperature operation having islands having a size equal to the resolution of electron beam lithography.
At the same time, it is possible to prevent an extra junction from being formed on the island, which is a problem in the past.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例による微小トンネル接合
素子の製造工程図。
FIG. 1 is a manufacturing process diagram of a small tunnel junction device according to a first embodiment of the present invention.

【図2】本発明の第2の実施例による微小トンネル接合
素子の製造工程図。
FIG. 2 is a manufacturing process diagram of a small tunnel junction device according to a second embodiment of the present invention.

【図3】図3(a)は、本発明の第3の実施例で用いる
懸架マスクのパターンを示す上面図。図3(b)は、本
発明の第3の実施例による微小トンネル接合素子の製造
工程図(一部)。
FIG. 3A is a top view showing a pattern of a suspension mask used in a third embodiment of the present invention. FIG. 3 (b) is a view (partly) of a process for manufacturing a small tunnel junction device according to the third embodiment of the present invention.

【図4】本発明の第3の実施例による図3(b)に続く
微小トンネル接合素子の製造工程図。
FIG. 4 is a manufacturing process diagram of the small tunnel junction device following FIG. 3B according to the third embodiment of the present invention.

【図5】図5(a)は、本発明の第4の実施例で用いる
懸架マスクのパターンを示す上面図。図5(b)は、本
発明の第4の実施例による微小トンネル接合素子の製造
工程図(一部)。
FIG. 5A is a top view showing a pattern of a suspension mask used in a fourth embodiment of the present invention. FIG. 5 (b) is a view (partly) of a process for manufacturing a small tunnel junction device according to a fourth embodiment of the present invention.

【図6】本発明の第4の実施例による図5(b)に続く
微小トンネル接合素子の製造工程図。
FIG. 6 is a view showing a manufacturing process of the minute tunnel junction device following FIG. 5B according to the fourth embodiment of the present invention.

【図7】本発明の第4の実施例による図6(e)に続く
微小トンネル接合素子の製造工程図。
FIG. 7 is a manufacturing process diagram of the minute tunnel junction device following FIG. 6E according to the fourth embodiment of the present invention.

【図8】本発明による微小トンネル接合素子の構成図。FIG. 8 is a configuration diagram of a small tunnel junction device according to the present invention.

【図9】従来の製造方法による微小トンネル接合素子の
構成図。
FIG. 9 is a configuration diagram of a minute tunnel junction device according to a conventional manufacturing method.

【図10】従来の微小トンネル接合素子の製造工程図。FIG. 10 is a manufacturing process diagram of a conventional minute tunnel junction device.

【図11】従来の微小トンネル接合素子の製造工程図。FIG. 11 is a manufacturing process diagram of a conventional minute tunnel junction device.

【符号の説明】[Explanation of symbols]

1 基板 2 スペーサー 3 懸架マスク 4 接合 5 蒸着 6 蒸着 7 第1の蒸着膜 8 第2の蒸着膜 9 第3の蒸着膜 10 蒸着 11 島 12 リード電極 13 ゲート電極 14 酸化膜 15 絶縁膜 16 第4の蒸着膜 17 第5の蒸着膜 DESCRIPTION OF SYMBOLS 1 Substrate 2 Spacer 3 Suspension mask 4 Joining 5 Deposition 6 Deposition 7 First deposition film 8 Second deposition film 9 Third deposition film 10 Deposition 11 Island 12 Lead electrode 13 Gate electrode 14 Oxide film 15 Insulating film 16 Fourth Evaporated film 17 Fifth evaporated film

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】中空に懸架したマスクの孔を通し、3回以
上蒸着角度を変化させて基板上に金属蒸着膜を順次成膜
して複数の前記蒸着膜が部分的に重複する重複部を形成
し、前記複数回の蒸着成膜工程間に同一蒸着装置内で前
記蒸着膜の前記重複部が形成される領域にトンネルバリ
アを成長させることにより、前記重複部にトンネル接合
を形成することを特徴とする微小トンネル接合部の製造
方法。
1. A metal deposition film is sequentially formed on a substrate by changing the deposition angle three times or more through a hole of a mask suspended in a hollow, and an overlapping portion where a plurality of the deposition films partially overlap is formed. Forming and forming a tunnel junction in the overlapping portion by growing a tunnel barrier in a region where the overlapping portion of the deposited film is formed in the same deposition apparatus during the plurality of deposition film forming steps. Characteristic method for manufacturing a small tunnel junction.
【請求項2】中空に懸架した同一のマスクの孔を通し基
板上に少なくとも3回以上の金属蒸着を順次行う工程を
有する微小トンネル接合部の製造方法であって、 前記マスクの孔を通して基板上に第1の金属蒸着膜を成
膜する工程と、 前記第1の金属蒸着膜表面の少なくともトンネル接合部
が形成される領域を同一蒸着装置内で酸化してトンネル
バリアを形成する工程と、 前記マスクを通して第1の蒸着方向とは異なる方向から
第2の金属膜蒸着を、第1の蒸着膜と前記酸化膜を介し
て一部接するように行う第2の蒸着工程と、 第1及び第2の蒸着方向とは異なる方向から前記マスク
を通して第3の金属膜蒸着を、前記第1と第2の蒸着膜
が接する重複部とは異なる領域で、前記第1の蒸着膜と
前記酸化膜を介して一部接するように行う第3の蒸着工
程と、 第3回以降の金属蒸着を、前回迄の蒸着方向とは異なる
方向から前記マスクを通して順次金属蒸着を行い、前回
までの重複部とは異なる領域で前記第1の蒸着膜と前記
酸化膜を介して一部接するように行う第3回以降の蒸着
工程を有し、 前記重複部にトンネル接合が形成されることを特徴とす
る微小トンネル接合部の製造方法。
2. A method for manufacturing a micro-tunnel junction comprising a step of sequentially performing at least three or more metal depositions on a substrate through holes of the same mask suspended in the air, the method comprising: Forming a first metal deposited film on the surface of the first metal deposited film, and oxidizing at least a region where a tunnel junction is formed on the surface of the first metal deposited film in the same vapor deposition apparatus to form a tunnel barrier; A second vapor deposition step of performing a second metal film vapor deposition through a mask from a direction different from the first vapor deposition direction so as to be partially in contact with the first vapor deposited film via the oxide film; A third metal film deposition through the mask from a direction different from a deposition direction of the first deposition film and the oxide film in a region different from an overlapping portion where the first and second deposition films are in contact with each other. The third part of contact And the third and subsequent metal depositions are sequentially performed through the mask from a direction different from the previous deposition direction, and the first deposition film is formed in a region different from the overlapping portion of the previous time. A method for manufacturing a micro-tunnel junction, comprising: a third or subsequent deposition step performed so as to be partially in contact with the oxide film, wherein a tunnel junction is formed in the overlapping portion.
【請求項3】前記懸架マスク上に設けられた孔と孔の間
の距離が、孔自身の寸法より大きいことを特徴とする請
求項1又は請求項2記載の微小トンネル接合部の製造方
法。
3. The method according to claim 1, wherein a distance between the holes provided on the suspension mask is larger than a size of the hole itself.
【請求項4】請求項1〜請求項3に記載のいずれかの微
小トンネル接合部を形成し、前記複数回の蒸着工程によ
り形成された前記複数の重複部間の微小な島状領域上に
電極(以下、この電極を島電極と称す)を形成し、前記
島電極と前記トンネル接合部を介して接続する複数のリ
ード電極を形成することを特徴とする微小トンネル接合
素子の製造方法。
4. A micro-tunnel junction according to claim 1, wherein said micro-tunnel junction is formed on a fine island region between said plurality of overlapping portions formed by said plurality of vapor deposition steps. An electrode (hereinafter, this electrode is referred to as an island electrode) is formed, and a plurality of lead electrodes connected to the island electrode via the tunnel junction are formed.
【請求項5】前記複数回の蒸着成膜の工程間に、同一蒸
着装置中で前記島電極上にゲート絶縁膜を成長し、前記
ゲート絶縁膜上にゲート電極を形成することを特徴とす
る請求項4記載の微小トンネル接合素子の製造方法。
5. The method according to claim 5, wherein a gate insulating film is grown on the island electrode in the same vapor deposition apparatus and a gate electrode is formed on the gate insulating film during the plurality of vapor deposition processes. A method for manufacturing a small tunnel junction device according to claim 4.
JP8256177A 1996-09-27 1996-09-27 Method for manufacturing minute tunnel junction and method for manufacturing minute tunnel junction element Expired - Fee Related JP2917933B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8256177A JP2917933B2 (en) 1996-09-27 1996-09-27 Method for manufacturing minute tunnel junction and method for manufacturing minute tunnel junction element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8256177A JP2917933B2 (en) 1996-09-27 1996-09-27 Method for manufacturing minute tunnel junction and method for manufacturing minute tunnel junction element

Publications (2)

Publication Number Publication Date
JPH10107340A true JPH10107340A (en) 1998-04-24
JP2917933B2 JP2917933B2 (en) 1999-07-12

Family

ID=17288986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8256177A Expired - Fee Related JP2917933B2 (en) 1996-09-27 1996-09-27 Method for manufacturing minute tunnel junction and method for manufacturing minute tunnel junction element

Country Status (1)

Country Link
JP (1) JP2917933B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005057068A (en) * 2003-08-05 2005-03-03 Nec Corp Coupled superconductive charge quantum bit element and control ignore gate using same
CN111994867A (en) * 2020-08-02 2020-11-27 南京大学 Method for preparing large-area controllable nano channel based on suspended mask and growing film method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005057068A (en) * 2003-08-05 2005-03-03 Nec Corp Coupled superconductive charge quantum bit element and control ignore gate using same
JP4535701B2 (en) * 2003-08-05 2010-09-01 日本電気株式会社 Coupled superconducting charge qubit device and control negation gate using it
CN111994867A (en) * 2020-08-02 2020-11-27 南京大学 Method for preparing large-area controllable nano channel based on suspended mask and growing film method

Also Published As

Publication number Publication date
JP2917933B2 (en) 1999-07-12

Similar Documents

Publication Publication Date Title
JPH036675B2 (en)
JP2917933B2 (en) Method for manufacturing minute tunnel junction and method for manufacturing minute tunnel junction element
JP3164208B2 (en) Method of manufacturing single electronic device
JPH1131812A (en) Charge-transfer device and manufacture of the same
JPH05145062A (en) Manufacture of single electron transistor
JP2007227407A (en) Tunnel junction element, and manufacturing method thereof
JP3166704B2 (en) Single electronic device and method of manufacturing the same
JPH04206777A (en) Semiconductor memory device
JP2920216B1 (en) Semiconductor device and wiring method inside the device
JPS61144892A (en) Production of josephson integrated circuit
JPS61263179A (en) Manufacture of josephson junction element
JPS63296277A (en) Semiconductor integrated circuit device
JPS59119881A (en) Josephson integrated circuit
JP2656853B2 (en) Superconducting element and fabrication method
JP2641970B2 (en) Superconducting element and fabrication method
JP2641966B2 (en) Superconducting element and fabrication method
JPH05160465A (en) Manufacture of monoelectron transistor
JPH05243626A (en) Josephson device and manufacture thereof
JPS6329593A (en) Superconducting transistor and manufacture thereof
JPH05206531A (en) Manufacture of superconducting device
JPH01223751A (en) Manufacture of semiconductor device
JPH1056185A (en) Manufacture of single electronic transistor
JPH07192983A (en) Manufacture of microdevice
JPH05243627A (en) Josephson device and manufacture thereof
JPS6396973A (en) Manufacture of josephson junction element

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990323

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080423

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090423

Year of fee payment: 10

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313114

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090423

Year of fee payment: 10

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100423

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110423

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120423

Year of fee payment: 13

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120423

Year of fee payment: 13

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120423

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130423

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130423

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140423

Year of fee payment: 15

LAPS Cancellation because of no payment of annual fees