JPH05160465A - Manufacture of monoelectron transistor - Google Patents

Abstract

PURPOSE:To facilitate manufacture of a monoelectron transistor and to increase the packaging density of monoelectron transistors. CONSTITUTION:A counter lower layer electrode 1 is isolated via an insulating film 2 from an upper layer electrode or a wiring conductive material layer 3, thereby forming a junction 4 of a monoelectron transistor via a part where the insulating film 2 is thinned down.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a single electron transistor with high integration and high reproducibility.

[0002]

2. Description of the Related Art Conventionally, a single-electron transistor is shown in FIG.
As shown in (a) and (b), a minute bridge 8 separated from the substrate 5 is formed on the substrate 5 to form a minute bond, and a metal material 6 is vapor-deposited in an oblique direction so as to straddle the bridge. After the metal surface was oxidized to form the insulating film, the metal 7 was similarly vapor-deposited from the diagonally opposite direction.

[0003]

However, when the above method is used, it is difficult to manufacture a transistor,
There is a problem that the reproducibility of the bridge is poor.

An object of the present invention is to improve the low reproducibility in the fabrication of a bridge, to easily realize an electric circuit using a single electron transistor, and to achieve high integration.

[0005]

In order to achieve the above object, in the method of manufacturing a single electron transistor according to the present invention, insulation between electrodes of the single electron transistor and dielectric for forming a junction of the single electron transistor are provided. It is used in common with the body membrane.

[0006]

[Function] Since the electrode and the wiring are separated by the insulating film and are connected by the thin film portion of the insulating film, the fabrication of the single electron transistor is facilitated and the single electron transistor is highly integrated. can do.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention.

First, the lower electrode 1 and the wiring are formed on a semiconductor or insulator substrate 5. The electrode 1 and the wiring pattern are produced by, for example, a lift-off method of the electrode 1 and the wiring material, a method of forming the electrode and the wiring material on the entire surface, and then performing resist exposure by light, electrons, an ion beam or the like, and an etching treatment, or A maskless direct etching method using a focused ion beam or the like can be used.

After that, the insulating film 2 is formed on the entire surface of the substrate 5. After forming the insulating film 2, the insulating film 2 at the place where the junction 4 of the single-electron transistor is to be formed is thinned by etching so as to have a capacitance suitable for the junction. Various methods can be used for this process. For example,
There is a method of forming a thin film by dry or wet etching after patterning using a resist process by light, electron, or ion beam exposure.

There is also a method of directly etching by a maskless process using an electron beam or a focused ion beam.

After that, the conductive material layer 3 to be the upper electrode is formed. The upper electrode is also processed by the same patterning process. After that, the electrodes are taken out to form a single electron transistor alone or an integrated circuit.

The method of the present invention can further fabricate single electron transistors in multiple layers. At this time, it is also possible to form a single electron transistor between the lowermost layer and the conductive material of the third layer. This is shown in FIG. The manufacturing procedure is the same as the method described above, the insulating film 2 is provided in two or more layers, and the bonding portions 4 between the wirings between the insulating films 2 and between the wirings and the upper and lower electrodes are thinned. Is.

The above process is a planar process and is compatible with the conventional IC process. In addition, active and passive devices required for circuit configuration can be manufactured on the same substrate.

Further, even after the wiring pattern of the lower layer is formed, the position of the connection can be changed in design during manufacture depending on the position of the thinned hole formed between the wiring of the upper layer.

[0015]

According to the present invention, as compared with the conventional method, it is not necessary to separately form an insulating material between the counter electrode and the wiring and an insulator for joining to form a transistor, and the process is stable. It is possible to fabricate an integrated circuit that is excellent in performance, can be highly integrated, and has low power consumption and fineness of a single electron transistor.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an example of a manufacturing process of the present invention.

FIG. 2 is an explanatory view showing an example in which a single electron transistor is manufactured in multiple layers by the method of the present invention.

3A and 3B are explanatory views showing a conventional manufacturing process not using the present invention, in which FIG. 3A is a perspective view and FIG. 3B is a sectional view.

[Explanation of symbols]

 1 Lower Electrode of Single Electron Transistor 2 Insulation Film 3 Conductive Material Layer to Be Upper Layer Electrode and Wiring 4 Joint with Thinned Insulation Film 5 Substrate

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[Procedure amendment]

[Submission date] December 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 3

[Correction method] Delete ────────────────────────────────────────────── ────────

[Procedure amendment]

[Submission date] December 10, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 3

[Correction method] Added

[Correction content]

3A and 3B are explanatory views showing a conventional manufacturing process not using the present invention, in which FIG. 3A is a perspective view and FIG. 3B is a sectional view.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Added

[Correction content]

[Figure 3]

Claims (1)

[Claims] 1. A method of manufacturing a single-electron transistor, which comprises commonly using insulation between electrodes of the single-electron transistor and a dielectric film forming a junction of the single-electron transistor.