JPH10107270A - High breakdown voltage semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of an element without sacrificing the excellent characteristics of the element by deciding the distance from first and second main electrode lead-out sections so specific relations can be established respectively between the distances and the widths of first and second main electrodes at certain different two points. SOLUTION: A drain electrode lead-out section 8a and a source electrode lead-out section 9a are formed on both sides of an element area. When the widths of a drain electrode 8 and a p-type drain layer 3 on the section 8a side and opposite side are respectively represented as WDAI1 and WD1 and WDAI2 and WD2 and the widths between both sides of an n-type source layers 5 formed in a source electrode 9 and a p-type base electrode 4 on the section 9a side and opposite side are respectively represented as WSAI1 and WS1 and WSAI2 and WS2 , relations WDAI1 >WDAI2 , WD1 >WD2 , WSAI1 >WSAI2 , and WS1 >WS2 hold.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a high breakdown voltage semiconductor device used for an output element such as an inverter device.

[0002]

2. Description of the Related Art There is an insulated gate bipolar transistor (IGBT) as an element used for an output element such as an inverter device. FIG. 6 is a plan view of a conventional horizontal IGBT using a dielectric isolation substrate (SOI substrate), and FIG.
AA 'cross-sectional view of FIG.

In FIG. 1, reference numeral 101 denotes a p-type or n-type Si substrate, and a high-resistance n-type layer 102 is formed on the substrate 101 via an insulating film 101a. An n-type buffer layer 102 having a higher concentration than the n-type layer 102 is selectively formed on the n-type layer 102.
b is formed, and a high-concentration p-type drain layer 103 is formed on the surface of the n-type buffer layer 102b. The p-type base layers 104a, 104a and 1a are spaced from the p-type drain layer 103 by a certain distance so as to surround the p-type drain layer 103.
04b is formed. Further, a high-concentration n-type source layer 105 is selectively formed on the surface of the p-type base layer 104, and is formed on the surface of the p-type base layer 104 sandwiched between the n-type source layer 105 and the n-type layer 102. Is the gate insulating film 106
The gate electrode 107 is formed via the gate electrode 107. And p
Electrode 108, ohmic contact with n-type drain layer 103, n-type source layer 105 and p-type base layer 10
4 are provided with source electrodes that make ohmic contact with each other.

In FIG. 6, reference numeral 108a denotes a drain electrode take-out portion, and 109a denotes a source electrode take-out portion. The contact portion 108b of the drain electrode 108 with the p-type drain layer 103 is surrounded by the portion 102a of the n-type layer 102 exposed on the wafer surface and the gate electrode 107 as shown in FIG. Is configured.

[0005]

The hole current of the conventional horizontal IGBT constructed as shown in FIGS. 6 and 7 is reduced from the drain electrode extraction portion 108a to each IG as shown by the arrow in FIG.
Each source electrode 1 passes through the drain electrode 108 of the BT cell.
09 and flows out to the source electrode take-out part 109a.

Here, the length L in the longitudinal direction of each IGBT cell
Is 1 mm, for example, a horizontal IGB with a withstand voltage of 600 V
At T, a current of 200 mA flows through one IGBT cell. When using Al having a thickness of 2μm to the drain electrode 108 and source electrode 109, the width W _SAl width W _DAl and the source electrode of the drain electrode 108 shown in FIG. 7 must be at least 70μm in consideration of reliability However, the area of the element becomes large depending on these electrode widths.

To reduce the element area, the electrode width may be reduced. However, if the electrode width is reduced, the current density increases and the reliability of the Al electrode deteriorates. If the thickness of the Al electrode is increased, reliability is ensured, but in this case, miniaturization becomes difficult, and a new problem such as disconnection of the passivation film on the element surface occurs. In any case, it has been difficult to reduce the area of the device while maintaining good device characteristics.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a high breakdown voltage semiconductor device capable of reducing the area of an element while maintaining good element characteristics.

[0009]

In order to solve the above-mentioned problems, the present invention is directed to a first aspect of the present invention, in which a substrate, an element region formed on the substrate, and a space substantially parallel to the element region are provided. A first and a second main electrode formed so as to form a first and a second main electrode with a lead-out portion sandwiching the element region;
Certain distances from the first main electrode take-out portion are different
The width of the first main electrode at a point is W _DAl1 , W
_DAl2 , the width of the second main electrode at two points at different distances from the second main electrode take-out portion is W
_SAL1, W and _SAL2, W _DAL1 is close to the main electrode extraction portion of the first than W _DAl2, W _SAl1 said second than W _SAL2
W _DAl1 > W _DAl2 , W
A high withstand voltage semiconductor device characterized by satisfying the relationship of _SAl1 > _WSAl2 .

According to a second aspect of the present invention, there is provided a substrate, an element region formed on the substrate, and first and second main electrodes formed on the element region so as to be substantially parallel to each other. In the semiconductor device, the lead-out portions of the first and second main electrodes are formed so as to sandwich the element region, and the widths of the first and second main electrodes are respectively equal to those of the first and second main electrodes. A high breakdown voltage semiconductor device characterized in that the voltage decreases substantially continuously as the distance from the portion increases.

According to a third aspect of the present invention, there is provided a substrate, an element region formed on the substrate, and first and second main electrodes formed on the element region so as to be substantially parallel to each other. In the semiconductor device, a lead-out portion of the first and second main electrodes is formed so as to sandwich the element region, and the first and second main electrodes are wedge-shaped at a predetermined distance on a plurality of element regions. Provided is a high-breakdown-voltage semiconductor device characterized by having a complementary combination of shapes.

According to a fourth aspect of the present invention, there is provided a high breakdown voltage semiconductor device according to any one of the first to third aspects, wherein the element formed in the element region is an element which performs a bipolar operation.

According to a fifth aspect of the present invention, there is provided a high withstand voltage semiconductor device according to the fourth aspect, wherein the element performing the bipolar operation is an IGBT. According to the present invention, in the case of the first and second main electrodes, for example, IGBTs, the shape of the drain and source electrodes as viewed from the upper surface of the device is not a constant width in the device region as in the related art, but is the drain electrode. The width is narrower on the side farther from the drain electrode extraction part than on the side closer to it, and the source electrode is narrower on the side farther from the source electrode extraction side than on the closer side, and the width between the drain electrode and the source electrode is the same as before. Similarly, since they are substantially parallel, the area of the element can be reduced without impairing the element characteristics.

In order to reduce the width, the current concentration can be prevented by reducing the electrode width substantially continuously.
Thereby, for example, in the case of an IGBT, latch-up due to current concentration can be prevented.

With such a shape, the first and second main electrodes are combined in a wedge shape and complementarily at a predetermined distance from each other over a plurality of element regions from the viewpoint of easiness of manufacture and prevention of current concentration most easily. A contoured shape is most desirable.

In addition, the device formed in the device region is IGB
In the case of an element that performs a bipolar operation such as T, the volume of a high-resistance layer such as a high-resistance n-type layer below a p-type drain layer in an IGBT is reduced, so that holes and electrons in this region are reduced. The amount of accumulation is reduced, thereby shortening the turn-off time in the case of a switching element such as an IGBT or a bipolar transistor, and shortening the reverse recovery time in the case of a diode.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a lateral IGBT as a high breakdown voltage semiconductor device according to one embodiment of the present invention, and FIG.
(A) and (b) are sectional views taken along the lines AA 'and BB' of FIG. 1, respectively.

In FIG. 1, reference numeral 1 denotes a p-type or n-type Si substrate, which is formed on a substrate 1 through an insulating film 1a using an oxide film having a thickness of about 1 to 3 μm, and has a height of about 5 to 15 μm. An n-type layer 2 of resistance is formed. These substrate 1, insulating film 1a, and n-type layer 2 form an SOI substrate. The surface of the n-type layer 2 is selectively higher in concentration than the n-type layer 2 and has a thickness of about 5 to 15 μm.
An m-type n-type buffer layer 2b is formed, and a high-concentration p-type drain layer 3 having a thickness of about 0.2 to 2 μm is formed on the surface of the n-type buffer layer 2b. This p-type drain layer 3
A p-type base layer 4a having a thickness of about 2 to 4 μm and a thickness of about 10 to
A 15 μm p-type base layer 4b is formed. A portion sandwiched between the p-type drain layer 3 and the p-type base layer 4 is a portion 2a exposed on the wafer surface of the n-type layer. Further, the surface of the p-type base layer 4 has a thickness of about 0.1 to 0.3 μm selectively.
Is formed on the surface of the p-type base layer 4 sandwiched between the n-type source layer 5 and the n-type layer 2 with a thickness of about 0.02 to 0.06 μm. A gate electrode 7 is formed via a gate insulating film 6 using an oxide film. The thicker portion of the gate insulating film 6 functions as a field oxide film, and its thickness is about 0.5 to 1 μm.
Then, a drain electrode 8 using Al having a thickness of about 2 μm as a first main electrode that makes ohmic contact with the p-type drain layer 3 and a second ohmic contact with both the n-type source layer 5 and the p-type base layer 4 About 2 thickness as main electrode
Source electrodes 9 using μm of Al are provided.

In FIG. 1, reference numeral 8a denotes a drain electrode take-out portion, and 9a denotes a source electrode take-out portion. As shown in FIG. 1, the contact portion 8 b of the drain electrode 8 with the p-type drain layer 3 is formed between the exposed portion 2 a of the n-type layer 2 and the gate electrode 7.
, Thereby forming one IGBT cell surrounded by a solid line shown by C in FIG. D and E
A portion surrounded by a dotted line indicated by a symbol is a region where the gate electrode 7 is formed but does not operate as an element.

The feature of this embodiment is that the width of the drain electrode 8 decreases substantially continuously from the drain electrode take-out portion 8a to the source electrode take-out portion 9a to form a wedge shape. The point is that it decreases substantially continuously from 9a toward the drain electrode take-out portion 8a to form a wedge. Moreover, in the element region, the distance between the drain electrode 8 and the source electrode 9 is parallel, in other words, the width of the exposed portion 2a of the n-type layer 2 is constant. It can be said that they form a shape in which they are complementarily combined with each other. This corresponds to the shapes of the p-type drain layer 3 and the p-type base layer 4 on which the n-type source layer 5 is formed.

[0021] Here, as shown in FIGS. 2 and 3, the drain electrode 8 near the drain electrode extraction portion 8a side, p-type drain layer 3 of the width of each W _DAL1, W _D1, the far side, respectively W _DAL2, W Let _D2 be the width of the source electrode 9 on the side closer to the source electrode extraction portion 9a and the width of the two n-type source layers 5 formed in the p-type base layer 4 from W _SAl1 and W _{S1 to} the far side. , W _SAl2 and W _S2 respectively, W _DAl1 > W _DAl2 (1), W _D1 > W _D2 (2), W
_{SAl1> W SAl2 ... (3)} , W S1> W S2 ... relationship is established (4).

Usually, the p-type drain layer 3 and the n-type source layer 5
Is determined, the width of the drain electrode 8 or the source electrode 9 is correspondingly determined to be wider than the width of the p-type drain layer 3 or the p-type base layer 4, Moreover, since the area of the element is limited by the width of the drain electrode 8 and the source electrode 9, the above equations (1) to (4) can be summarized by the equations (1) and (3).

Therefore, for example, for a linear portion of an electrode as shown by the length L in the longitudinal direction of the IGBT cell in FIG.
1 mm, W _DAl1 = 70 μm, W _DAl2 = 6 μm, W
_{If SAl1} = 70 μm and W _SAl2 = 6 μm, the area of the IGBT cell C is reduced by more than 30% as compared with the conventional horizontal IGBT as shown in FIGS.

The relationship between the degree of such element area reduction and the above equations (1) to (4) will be described with reference to FIGS. FIG. 3 shows the horizontal IGBT of FIGS.
_{When D1} = 70 μm and the width L _D of the exposed portion 2a are fixed at 60 μm, the change amount of _WD1 / _WD2 and one IGBT
FIG. 7 is a diagram showing a relationship between an area S [mm ² ] of a cell C and an amount of change. In the figure, the horizontal axis is W _D1 / W _D2 , and the vertical axis is S [m
m ² ]. S is S = (W _D1 + W _D2 +0.12)
It is calculated by × L. As can be seen from the figure, W _D1 /
When W _D2 = 7, S becomes substantially constant.

FIG. 4 shows the vertical axis as an area reduction rate [%] instead of S for more clarity. From the figure, if W _D1 / W _D2 = 7, the area reduction ratio exceeds 30% and a sufficient area reduction effect can be obtained. Therefore, W _D1 / W _D2 ≧ 7 is preferable.

As described above, according to the electrode shape of this embodiment, the effect of reducing the area can be obtained, but the effect of this electrode shape is not limited to this. The other effects are listed below.

First, like the conventional IGBT, the hole current passes through the drain electrode take-out portion 8a, passes through the drain electrode 8 of each IGBT cell C, passes through each source electrode 9, and flows out to the source electrode take-out portion 9a. At this time, since the hole current decreases as the distance from the drain electrode extraction portion 8a increases, the current density does not increase even if the width of the drain electrode 108 is reduced, and the reliability of the Al electrode is not reduced. Absent.

On the other hand, the electron current is applied to the source electrode extraction side 9
a, but the width of the source electrode 9 is formed to be wider as it is closer to the source electrode extraction portion 9a, so that the current density does not increase as in the case of the hole current. The reliability of the electrodes does not decrease.

Even if the thickness of the Al electrode is the same as the conventional one, the reliability does not decrease and the element area can be reduced.
According to this embodiment, an effect is obtained that the area of the element can be reduced while maintaining good element characteristics.

Further, the width of the drain electrode 8, in other words, p
Since the volume of the n-type layer 2 under the p-type drain layer 3 is small in a region where the n-type drain layer 3 is narrow, holes injected from the p-type drain layer 103 in this region and n-type The amount of electrons injected from the source layer 105 is reduced. As a result, the turn-off time is reduced.

Under the same condition of L = 1 mm, the channel width is wider than that of the conventional horizontal IGBT as shown in FIGS. 6 and 7, so that the channel resistance is reduced, thereby reducing the on-resistance.

By the way, in the present invention, it is possible to take an electrode shape other than that shown in FIG. One example is shown in FIG. FIG. 5 shows only the drain electrode 8 and the source electrode 9 for simplification of the description.

In the figure, the drain electrode 8 and the source electrode 9 are formed in a substantially continuous and gentle step shape. When the electrode is formed in such a shape, and the p-type drain layer under the drain electrode 8 and the p-type base layer under the source electrode 9 have the same shape, holes flowing through the p-type base layer under the n-type source layer are used. In order to prevent latch-up due to the concentration of current, it is desirable not to form a channel at the corners of the p-type base layer having sharp corners.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment. For example, the n-type layer 2 may be a p-type layer, or a bulk substrate or an epitaxial substrate may be used instead of the SOI substrate. Further, the conductivity types of the above-described embodiments can be all reversed. Further, the present invention can be applied to a MOSFET in which the p-type drain layer of the IGBT is replaced with an n-type drain layer, and can also be applied to a bipolar transistor and a diode. M
When used for an OSFET, the channel width is increased, so that the on-resistance is reduced as in the case of the IGBT. In addition, since bipolar transistors and diodes are elements that perform a bipolar operation, the turn-off time is shortened in the case of a bipolar transistor, and the reverse recovery time is shortened in the case of a diode.

[0035]

As described above, according to the present invention, it is possible to provide a high withstand voltage semiconductor device capable of reducing the area of an element while maintaining good element characteristics.

[Brief description of the drawings]

FIG. 1 is a plan view of a horizontal IGBT according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a horizontal IGBT according to one embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a cell area and an electrode width of the lateral IGBT according to one embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between a cell area reduction ratio and an electrode width of the horizontal IGBT according to one embodiment of the present invention.

FIG. 5 is a diagram showing an electrode shape of a horizontal IGBT according to another embodiment of the present invention.

FIG. 6 is a plan view of a conventional horizontal IGBT.

FIG. 7 is a cross-sectional view of a conventional horizontal IGBT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... High resistance n-type layer, 3 ... P-type drain layer, 4
... p-type base layer, 5 ... n-type source layer, 6 ... gate insulating film, 7 ... gate electrode, 8 ... drain electrode, 9 ... source electrode

Claims (5)

[Claims] 1. A semiconductor device comprising: a substrate; an element region formed on the substrate; and first and second main electrodes formed on the element region so as to be substantially parallel to each other. The extraction portions of the first and second main electrodes are formed so as to sandwich the element region, and the width of the first main electrode at two points at different distances from the first main electrode extraction portion is respectively set. W _DAL1, W _DAL2, said second width of said second main electrode in two points at different distances is from the main electrode extraction portion and W _SAL1, W _SAL2 respectively, W _DAL1 is W
_Closer to the first main electrode take-out part than _{DAl2,
Satisfies} the relations of W _DAl1 > W _DAl2 and W _SAl1 > W _SAl2 when is closer to the second main electrode take-out part than W _SAl2 . 2. A semiconductor device comprising: a substrate; an element region formed on the substrate; and first and second main electrodes formed on the element region so as to be substantially parallel to each other. The lead-out portions of the first and second main electrodes are formed so as to sandwich the element region, and the widths of the first and second main electrodes become substantially smaller as the widths of the first and second main electrodes become farther from the lead portions of the first and second main electrodes, respectively. A high breakdown voltage semiconductor device characterized by a continuous decrease. 3. A semiconductor device comprising: a substrate; an element region formed on the substrate; and first and second main electrodes formed on the element region so as to be substantially parallel to each other. A lead-out portion of the first and second main electrodes is formed so as to sandwich the element region, and the first and second main electrodes are combined in a wedge shape and complementarily at a predetermined distance on a plurality of element regions. A high breakdown voltage semiconductor device characterized by having a shape. 4. The device according to claim 1, wherein the device formed in the device region performs a bipolar operation.
4. The high breakdown voltage semiconductor device according to 3. 5. The device according to claim 1, wherein the element performing the bipolar operation is an IGB.
5. The high breakdown voltage semiconductor device according to claim 4, wherein T is T.