JPH1010185A - Go/no go decision method for package arranged with electrode on one side and lead pin/pattern on opposite side using in-circuit tester, and resistor rod - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the test time by facilitating the positioning of a measuring pin probe such that it can deal with fine patterning thereby checking conduction between a lead pin and a corresponding pattern easily. SOLUTION: A resistor rod 20 is applied to touch each pattern 16 constituting an array 14 of patterns and then a DC current is fed through the resistor rod 20. Subsequently, the potential of each lead pin 12 is measured by touching a measuring pin probe to each lead pin 12 in order to check conduction between each lead pin 12 and a corresponding pattern 16. Thereafter, current supply to the resistor rod 20 is interrupted and conduction is checked between each lead pin 12 and a corresponding pattern 16 before measuring capacitance between an electrode and each lead pin 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for judging pass / fail of a single-sided electrode such as a PGA type semiconductor package, a liquid crystal package and the like, and a lead pin / pattern arrangement type package, and a resistance bar using an in-circuit tester.

[0002]

2. Description of the Related Art Conventionally, a mounting board, that is, a printed circuit board on which a large number of electronic components are mounted and soldered, uses an in-circuit tester to appropriately contact the tip of a probe to a required measurement point on the board. The presence or absence of each component is electrically detected, or the characteristic value or the like of each component is electrically measured to determine the quality of the board. This type of in-circuit tester includes a pin board type in which a fixture (pin board) as an inspection jig is installed on a measuring table on which a substrate to be inspected is mounted, and an XY on a measuring table on which the substrate to be inspected is mounted. There is an XY type in which units and the like are installed.

In the pin board method, a number of pin probes equal to the number of measurement points on the board to be inspected are provided on the board in correspondence with the positions of the measurement points, and a fixture is mounted on the board to be inspected. Each pin probe is brought into contact with each measurement point. On the other hand, in the XY method, a Z-axis unit movable in the Y-axis direction is provided on an arm movable in the X-axis direction, and one pin probe is movably supported in the Z-axis direction by the Z-axis unit. By controlling the XY unit, the pin probe is moved from above the substrate to the X-axis and Y-axis.
It moves appropriately in the directions of the axis and the Z-axis, and sequentially comes into contact with preset measurement points. Therefore, the pin-board type is suitable for measuring a large number of the same substrates to be inspected, while the X-
The Y type is suitable for measuring a large number of products and a small number of substrates to be inspected.

Using an in-circuit tester according to these methods, a ground or power supply electrode 10 is provided on the upper surface as shown in FIGS.
2 are arranged in a distributed manner, and two sets of the pattern rows 14 are further arranged in the center in a rectangular shape.
In the case of determining the quality of a package in which the second and each pattern 16 are connected substantially one-to-one, for example, a PGA type semiconductor package 18, the capacitance between the ground electrode 10 and each pattern 16 is measured for each pattern 16. Then, the quality of the PGA type semiconductor package 18 is determined by comparing the result with the corresponding capacitance of a non-defective product. Incidentally, most of each pattern 16 is buried in a material such as a ceramic, and the shape,
The thickness, the distance from the ground electrode 10, and the like are unknown.

[0005]

However, in such a PGA type semiconductor package 18, each pattern row 1
Since the patterns 16 constituting the pattern 4 are arranged at a fine pitch, there is a problem in that when the measuring pin probe is brought into contact with each pattern 16, high-precision positioning is required. Moreover, when the connection between the lead pin 12 and the corresponding pattern 16 is disconnected, it is difficult to check the connection. This is because if the connection between the lead pin 12 and the pattern 16 is cut near the lead pin 12, if there is no other problem, there is not much change even if the measured capacitance is compared with a good one. is there. When the measurement is performed by the XY system in-circuit tester, the measurement pin probes are sequentially moved while being in contact with the respective patterns 16, and the respective capacitances are measured, so that the inspection time naturally increases.

The present invention has been made in view of such conventional problems. First, it is easy to cope with the fine pitch of the pattern, the positioning of the measuring pin probe is easy, and the pattern corresponding to the lead pin is used. It is an object of the present invention to provide a pass / fail judgment method using an in-circuit tester for a one-sided electrode and a lead-pin / pattern-arranged-type package on the opposite side, which can easily check the continuity with the one-side electrode and the opposite-side lead pin / pattern arrangement type package. Another object of the present invention is to provide a resistance bar suitable for use in a pass / fail judgment method using an in-circuit tester for a package having a one-sided electrode and a lead pin / pattern arrangement on the opposite side.

[0007]

In order to achieve the above-mentioned object, an electrode is provided on one surface of a single-sided electrode according to the first object of the present invention, and a pass / fail judgment method using an in-circuit tester of a package having a lead pin / pattern arrangement type on the opposite side. A large number of lead pins and a pattern row are arranged on the opposite surface, and each lead pin and each pattern are connected almost one-to-one. The capacitance of the package is measured by an in-circuit tester, and the measurement result is obtained. The non-defective product of the package is determined from.

At this time, a resistance bar is pressed so as to come into contact with each pattern constituting the pattern row, a DC current is applied to the resistance bar, and a measuring pin probe is brought into contact with each lead pin to set the potential of each lead pin. Measured, the conduction state between each lead pin and the corresponding pattern was checked, the current flowing through the resistance bar was stopped, and all the conduction of each lead pin and the corresponding pattern were confirmed by each conduction check. Thereafter, the capacitance between the electrode and each lead pin is measured for each lead pin.

The resistance bar for the second purpose is made of a conductive material having elasticity and high resistivity.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view showing an arrangement state of each resistance bar with respect to each pattern row in which a lower surface side is upward at the time of judging pass / fail of a PGA type semiconductor package by a pin board type in-circuit tester to which the present invention is applied. In the figure, reference numeral 20 denotes a resistance rod, and reference numeral 22 denotes a power supply for applying a DC voltage to both ends. The resistance bar 20 is made of a conductive material having elasticity and a high resistivity, such as conductive rubber. Therefore, even if the voltage value applied to the resistance bar 20 is increased so as to be convenient for measuring the potential of each lead pin 12 described later, the calorific value can be kept small, and the PGA type semiconductor package 18 to be inspected is damaged. Never do.

Such a PGA type semiconductor package 18
At the time of pass / fail judgment by the pin board type in-circuit tester, first, the package 18 is placed on a measuring table and the lower surface thereof is fixed upward. Then, the resistance bar 20 corresponding to each pattern row 14 is lowered, and is pressed so as to make good contact with each of the patterns 16 constituting the pattern row 14. Thereafter, a direct current is passed through each resistance bar 20. Then, as shown in FIG. 2, the adjacent patterns 16 are all separated and have an interval L, so that a voltage drop occurs between the adjacent patterns 16 and a potential difference of V = Iρ · L / A. Can be. Here, ρ is the resistivity of the resistance bar 20, A is its cross-sectional area, and I is the current flowing therethrough.

In this way, different potentials are applied to all the patterns 16 in advance. Therefore, as shown in FIG. 3, the pin board is lowered from above to the package 18 in the direction of the arrow, and the tip portion 24 of each measuring pin probe is lowered.
To the corresponding lead pins 12. Then, although the interval between the adjacent patterns 16 is considerably narrow, the interval between the adjacent lead pins 12 is wide, so that the potential of each lead pin 12 can be measured without requiring high-precision positioning. When each of the resistance bars 20 is arranged and provided on a pin board as an inspection jig, and the inspection jig is attached to the tip of the piston rod of the air cylinder, etc., all the pin probes for measurement and the resistance rod 20 are connected. Can be simultaneously moved up and down, which is preferable.

At the time of measuring the potential of each lead pin 12, if the lead pin 12 and the corresponding pattern 16 are disconnected, the potential of the lead pin 12 naturally becomes zero.
The cutting of the lead pin 12 and the corresponding pattern 16 is likely to occur near the lead pin 12. Therefore, if the potential of each lead pin 12 is measured, the conduction state between each lead pin 12 and the corresponding pattern 16 can be checked. Thereafter, the current flowing through the resistance bar 20 is stopped. Incidentally, lead pins which are not normally used are also provided in the PGA type semiconductor package, and the pattern connected to the lead pins can be increased.

After confirming that all the lead pins 12 and the corresponding patterns 16 are all conducting by each conduction check, a measuring pin probe (not shown) is pressed against the ground electrode 10 of the package 18. Then, an AC voltage is applied, and the capacitance between the ground electrode 10 and each lead pin 12 is measured for each lead pin 12.
Note that the measuring pin probe is connected to all lead pins 1 at a time.
If the measurement of the potential of each lead pin 12 and the measurement of the capacitance are performed in the case of No. 2, the inspection can be performed instantaneously in each case, and the inspection time can be reduced.

After measuring the capacitance between the ground electrode 10 and each lead pin 12 in this manner, the measurement result is compared with the corresponding capacitance of a non-defective product, and the PGA to be inspected is measured. The quality of the type semiconductor package 18 is determined. If the conduction state is good and the capacitance is good, it is determined that the product is good.

In the above embodiment, the present invention is applied to a PGA.
Although the description has been given of the case where the present invention is applied to a type semiconductor package, the present invention can naturally be applied to another one-sided electrode, a BGA type semiconductor package which is a lead pin / pattern arrangement type package on the opposite side, a liquid crystal package and the like. Further, in the above embodiment, the case where the present invention is applied to the pin board type in-circuit tester has been described. However, the present invention can naturally be applied to the XY type in-circuit tester.

[0017]

According to the present invention described above, claim 1
In the described invention, the measuring pin probe is brought into contact with the lead pins having a large arrangement interval, and the resistance bar is brought into contact with each of the patterns having a small arrangement interval constituting the pattern row. Can handle pitching. Then, a direct current is passed through the resistance bar,
By measuring the potential of each lead pin, the conduction state between each lead pin and the corresponding pattern can be checked, and a defect due to the cutting of the package can be detected. Moreover, according to the pin board type in-circuit tester, the measurement pin probe can be applied to all the measurement pin probes at once, and the measurement of the potential of each lead pin and the measurement of the capacitance can be performed, thereby shortening the inspection time. it can.

According to the second aspect of the present invention, since a conductive material having elasticity and high resistivity is used as the resistance bar, the resistance bar can be brought into good contact with all the patterns constituting the pattern row. By increasing the voltage value applied to the resistance bar to increase the potential difference between adjacent patterns, the amount of generated heat can be reduced. Therefore, it is convenient for measuring the potential of each lead pin, and the package is not damaged.

[Brief description of the drawings]

FIG. 1 is a plan view showing an arrangement state of each resistance bar with respect to each pattern row with a lower surface side facing upward when a PGA type semiconductor package is judged to be good or bad by a pin board type in-circuit tester to which the present invention is applied.

FIG. 2 is an enlarged plan view showing an arrangement state of one resistance bar for one pattern row at the time of judging pass / fail of the PGA type semiconductor package.

FIG. 3 is a side view showing a correspondence relationship between each lead pin of the PGA type semiconductor package and a tip end of each measurement pin probe provided on a pin board at the time of judging pass / fail of the PGA type semiconductor package.

FIG. 4 is a plan view of a PGA type semiconductor package.

FIG. 5 is a bottom view of the PGA type semiconductor package.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Ground electrode 12 ... Lead pin 14 ... Pattern row 16 ... Pattern 18 ... PGA type semiconductor package 20 ... Resistance bar 22
... DC power supply 24 ... Measurement pin probe tip

Claims (2)

[Claims] An electrode is provided on one surface, a number of lead pins and a pattern array are provided on the opposite surface, and each of the lead pins and each pattern is connected almost one-to-one to reduce the capacitance of a package. One-sided electrodes are measured by an in-circuit tester, and the quality of the package is determined based on the measurement result. A DC current is applied to the resistance bar, and a measuring pin probe is brought into contact with each lead pin to measure the potential of each lead pin.The conduction state between each lead pin and the corresponding pattern is measured. Check each of them, stop the current flowing through the resistance bar, and check the continuity of each of After checking all continuity of the turn,
A pass / fail judgment method using an in-circuit tester for a one-sided electrode and an opposite-sided lead pin / pattern arrangement type package, wherein a capacitance between an electrode and each lead pin is measured for each lead pin. 2. A resistance bar comprising an electric conductor having elasticity and high resistivity.