JPH0999580A - Self-scanning type light-emitting device and its protective circuit for static breakage prevention - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protective circuit for static breakage prevention to be used in a self-scanning type light-emitting device. SOLUTION: A device is provided between an input terminal 60 and an input circuit and constituted of two PNPN structure thyristors 62 and 65 and two current limit resistors 66 and 68. An anode electrode 661 of the thyristor 62 is connected with one end of the resistor 66 on the input terminal side, while a gate electrode 622 is connected with a plus 5V power source voltage (VGK) of the thyistor itself through a protective resistor 624 of the thyristor. On the other hand, an anode electrode 641 of the thyristor 64 is grounded, while a gate electrode 642 is connected with one end of the resistor 66 on the input terminal side. Both of anode electrodes 625 and 644 of the thyristors 62 and 64 are grounded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic breakdown protection circuit, and more particularly to an electrostatic breakdown protection circuit used in a self-scanning light emitting device.

[0002]

2. Description of the Related Art The applicant of the present invention has found that a self-scanning light emitting device using an array of light emitting thyristor elements having a PNPN structure as a light emitting device of a light source for a printer, and a light emitting device having a PNPN structure for a shift register for driving the light emitting element array. Many applications have already been filed for self-scanning light-emitting devices using thyristor switch element arrays. For example, JP-A-2-26366
No. 8, "Light-Emitting Device", JP-A-2-212170, "Light-Emitting Element Array and Driving Method Therefor", JP-A No. 3-5
5885, "Light-Emitting / Light-Receiving Module," JP-A-3-
Japanese Patent Laid-Open No. 200364/2004, "Optical Signal Reading Method and Switch Element Array Used Therefor", Japanese Patent Laid-Open No. 4-23367
JP-A-4-296579, "Driving Method of Light-Emitting Element Array" and the like.

The structure of a typical self-scanning light emitting device is shown below.

FIG. 1 shows a light emitting thyristor element having a transfer function by connecting the gate electrodes of the respective light emitting thyristor elements with a resistor network.

FIG. 2 uses a diode as an electrical connection method between the gate electrodes of the light emitting thyristor element.

FIG. 3 shows a transfer function realized by a shift register. The shift register uses the structure of FIG. 2 as a switch element array, and its gate is connected to the gate of a corresponding light emitting thyristor element array. is there.

As an example, the operation of the self-scanning light emitting device of FIG. 3 will be described. First, it is assumed that the voltage of the transfer clock pulse φ ₁ is at high level and the switch element T (0) is in the ON state. At this time, the potential of the gate electrode G ₀ drops from the power source voltage V _GK of 5 V to almost zero V. The influence of this potential drop is transmitted to the gate electrode G ₁ by the diode D ₀ , and the potential thereof is set to about 1 V (the forward rising voltage of the diode D ₀ (equal to the diffusion potential)). However, since the diode D _-1 is in the reverse bias state, the gate electrode G
_No potential is connected to _-1, and the potential of the gate electrode G _-1 remains 5V. Since the ON potential of the thyristor is approximated by the gate electrode potential + diffusion potential of the PN junction (about 1V), the high level voltage of the next transfer clock pulse φ ₂ is about 2V (to turn on the switch element T (1). Required voltage) and about 4V (switch element T (3)
(Voltage necessary for turning on), only the switch element T (1) can be turned on and the other switch elements can be kept off. Therefore, the ON state is transferred by two transfer clock pulses.

The start pulse φ _S is a pulse for disclosing such a transfer operation.
At the same time when _{S is set} to low level (about 0V), the corresponding transfer clock pulse is set to high level (about 2 to about 4V),
The first-stage switching element T is turned on. Immediately thereafter, the start pulse φ _S is returned to the high level.

Now, assuming that the switch element T (0) is in the ON state, the potential of the gate electrode G ₀ is the power supply voltage V _GK.
It becomes lower and becomes almost zero volt. Therefore, if the voltage of the write signal S _in is equal to or higher than the diffusion potential of the PN junction (about 1 volt), the light emitting element L (0) can be brought into a light emitting state.

On the other hand, the gate electrode G _-1 is about 5 volts and the gate electrode G ₁ is about 1 volt. Therefore, the writing voltage of the light emitting element L (-1) is about 6 volts,
The writing voltage of the light emitting element L (1) is about 2 volts.
From this, the voltage of the write signal S _in which can be written only to the light emitting element L (0) is in the range of 1 to 2 volts. The light emitting element L (0) is turned on, that is, enters a light emitting state. The emission intensity is determined by the amount of current flowing _{in the} write signal S _in , and image writing can be performed at any intensity. Further, in order to transfer the light emitting state to the next light emitting element, it is necessary to once hold the voltage of the write signal S _in line to 0 V and once turn off the light emitting element which is emitting light.

As one of the improvements in the reliability of the self-scanning light emitting device using the thyristor element having the PNPN structure as described above, it is necessary to prevent electrostatic breakdown due to overvoltage generated by electrostatic discharge, for example. To prevent the circuit from electrostatic damage, insert a protection circuit between the input terminal and the input circuit,
It is common for the protection circuit to absorb the overvoltage.

As shown in FIG. 4, the protection circuit for preventing electrostatic breakdown includes two diodes (PN junction) as protection elements.
There are some which use 10 and 12. First diode 10
Acts as a protection element against a positive overvoltage, and the second diode 12 acts as a protection element against a negative overvoltage.

When a positive overvoltage arrives, the first diode 10 is turned on to release the positive overvoltage to the power source V _GK . On the contrary, when a negative overvoltage arrives, the second diode 12 is turned on and the negative overvoltage is reached. Overvoltage is released to the ground (GND).

[0014]

In the self-scanning light emitting device using the thyristor element having the PNPN structure, which the applicant of the present invention has already proposed, there is no pure PN junction. Therefore, in order to realize a protection circuit using a PN junction as a protection element as shown in FIG. 4, a part of the thyristor element's PN junction is used.

FIG. 5 is a sectional view of the device structure of the self-scanning light emitting device of FIG. Grounded N-type semiconductor substrate 1
The N-type semiconductor layer 24, the P-type semiconductor layer 23, the N-type semiconductor layer 22, and the P-type semiconductor layer 21 are formed on the respective layers, and the individual light emitting thyristors L (-1) to L (are formed by photolithography and etching. +1) (separation groove 50). The anode electrode 40 is in ohmic contact with the P-type semiconductor layer 21, and the gate electrode 41 is in ohmic contact with the N-type semiconductor layer 22.

As can be seen from the device structure of FIG. 5, the PN junction that can be used as a protective element is the anode electrode 40.
Is a PN junction composed of the P-type semiconductor layer 21 connected to and the N-type semiconductor layer 22 connected to the gate electrode 41.

When this PN junction is used as a protection element, there arises a problem that the NPN structure connected to this PN junction causes a failure in protection operation. Another problem is that once the thyristor turns on, it does not turn off unless the current is cut off, so the characteristics of this thyristor may affect the operation of the PN junction as a protection element.

An object of the present invention is to provide a protection circuit for preventing electrostatic breakdown which can be used in a self-scanning light emitting device in consideration of the above problems.

[0019]

According to the present invention, a plurality of light emitting thyristors having gate electrodes for controlling a threshold voltage or a threshold current for light emitting operation are arranged, and the gate electrodes of each light emitting thyristor are arranged in the vicinity thereof. Is connected to the gate electrode of at least one light emitting thyristor via a connection resistor or an electric element having electrical unidirectionality, and a power supply line is connected to each light emitting thyristor via a load resistor, and One end is connected to the input terminal in the electrostatic discharge protection circuit used in the self-scanning light-emitting device formed by connecting the clock pulse line to each light-emitting thyristor and the start pulse line to the first-stage light-emitting thyristor. A current limiting resistor and the other end of the current limiting resistor is connected to an anode electrode or a cathode electrode,
A first thyristor having a gate electrode connected to the power supply line and a cathode electrode or an anode electrode grounded;
A second thyristor having a gate electrode connected to the other end of the current limiting resistor and an anode electrode and a cathode electrode grounded.

Further, according to the present invention, a plurality of transfer thyristors having gate electrodes for controlling a threshold voltage or a threshold current for a transfer operation are arranged, and at least one gate thyristor of each thyristor is located in the vicinity thereof. Connect to the gate electrode of the transfer thyristor via a connecting resistor or an electronic element having electrical unidirectionality, connect the power supply line to each transfer thyristor via a load resistor, and clock pulses to each transfer thyristor. Connect the lines,
In addition, a transfer thyristor array formed by connecting a start pulse line to the first stage transfer thyristor, and a light emitting thyristor in which a plurality of light emitting thyristors having gate electrodes for controlling a threshold voltage or a threshold current for light emitting operation are arranged. Self-scanning light emission comprising an array, each gate electrode of the light emitting thyristor is electrically connected to a corresponding gate electrode of the transfer thyristor, and a line for applying a current for light emission to each light emitting thyristor is provided. A device, wherein a current limiting resistor having one end connected to an input terminal, an anode electrode or a cathode electrode connected to the other end of the current limiting resistor, a gate electrode connected to the power supply line, a cathode electrode or an anode electrode First grounded
And a second thyristor in which the gate electrode is connected to the other end of the current limiting resistor and the anode electrode and the cathode electrode are grounded.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 6 is a circuit diagram of an embodiment of a protection circuit for preventing electrostatic breakdown according to the present invention. It is provided between the input terminal 60 and an input circuit (not shown) and is composed of two thyristors 62 and 64 having a PNPN structure and current limiting resistors 66 and 68.

The anode electrode 621 of the thyristor 62 is
The gate electrode 6 is connected to one end of the resistor 66 on the input terminal side.
22 is connected to the positive power supply voltage ( _VGK ) via the protective resistance 624 of the thyristor itself. On the other hand, the thyristor 64
The anode electrode 641 is grounded, and the gate electrode 642 is connected to one end of the resistor 66 on the input terminal side. The cathode electrodes 625 and 644 of the thyristors 62 and 64 are both grounded.

Basically, the protection circuit having the above configuration is shown in FIG.
The protection circuit is the same as the protection circuit shown in FIG. 1, and has a PN junction in which the anode electrode and the gate electrode are connected (in FIG.
PN junction 623, thyristor 64 PN junction 643)
Is used as a protection element. In this case, as described above, the NPN between the gate electrode and the cathode electrode
There is a problem that the structure does not affect the PN junction as a protection element in operation. According to the consideration of the inventors of the present application, it is known that this problem does not affect operation. That is, the breakdown voltage is sufficient from the element characteristics of the NPN structure of the thyristor, the NPN structure is always in the off state, and there is no influence on the on / off operation of the protection element.

Further, as described above, since the current continues to flow in the thyristor once it is turned on, the problem that this may affect the operation of the protection element is dealt with as follows. There is.

First, in the thyristor 64, the P-type region to which the anode electrode 641 is connected and the cathode electrode 64.
The connected N-type region 4 is short-circuited via the ground. Even if the PN junction 643 is turned on due to the incoming overvoltage, it is reset immediately after the current is turned off and the current no longer flows, so there is no problem.

On the other hand, the thyristor 62 does not function as a protection circuit when it is turned on by the overvoltage that has arrived and the current continues to flow. So, in this invention,
We are making the following efforts. That is, the resistance from the anode electrode 621 to the power source V _GK via the gate electrode 622 is reduced. This resistance includes the resistance from the anode electrode 621 to the gate electrode 622 via the PN junction 623 and the resistance of the protective resistance 624 (about 1 kΩ). If the resistance from the anode electrode 621 to the power supply V _GK is set smaller than the driving capability of the thyristor, the thyristor turns off itself. Since the value of the protection resistor 624 cannot be reduced, the resistance between the anode electrode 621 and the gate electrode 622 is reduced. For this purpose, as shown in FIG. 7, the anode electrode and the gate electrode are formed around the anode electrode in a ring shape around the anode electrode. With such a structure, electric field concentration from the anode electrode to the gate electrode is avoided, and the resistance between the anode electrode and the gate electrode is lowered.

By using the electrode having such a ring structure, the resistance from the anode electrode 621 to the power source V _GK becomes small. When the NPN structure is turned on by the arrival of an overvoltage, the N-type region to which the gate electrode 622 is connected momentarily falls to 0 V, but the resistance to the power source V _GK is small, so the N-type region is V _GK . The immediate return results in the NPN structure returning to the off state.

Next, the operation of this embodiment will be described. When a positive overvoltage arrives at the input terminal 60, P of the thyristor 62
The N-junction turns on and the overvoltage escapes to the power supply V _GK . Also, when a negative overvoltage arrives, the PN junction of the thyristor 64 turns on, allowing the overvoltage to escape to the ground.

Since the protection circuit for preventing electrostatic breakdown using the pn junction of the thyristor as described above uses the thyristor element, the above-mentioned problem was feared. Can be prevented from electrostatic breakdown.

In the above embodiment, the case where the power supply voltage V _GK is positive has been described, but when the power supply voltage V _GK is negative,
It is clear that the thyristors can be connected with different polarities.

[0031]

[Embodiment 2] FIG. 8 is a diagram showing a protection element that works only against a positive overvoltage. (A) is sectional drawing, (b) is a top view. This protection element is a grounded N-type semiconductor substrate 1
Each layer of the N-type semiconductor layer 24, the P-type semiconductor layer 23, the N-type semiconductor layer 22, and the P-type semiconductor layer 21 is formed on it.

The uppermost layer 21 is, as shown in FIG.
A central semiconductor layer 21a having a narrow neck for resistance.
And side semiconductor layers 21b and 21c on both sides. The gate electrode 41 is provided on the side semiconductor layer 21b so that the anode electrode 40 extends over the side semiconductor layer 21c and the lower semiconductor layer 22. The gate electrode 41 is connected to the positive power source V _GK via the protective resistor 51.

When a positive overvoltage arrives at the anode electrode 40, a current I ₁ instantaneously flows from the anode electrode 40 to the gate electrode 41 through the central semiconductor layer 21a forming the internal resistance. As a result, a potential difference is generated due to the internal resistance, the PN junction below the anode electrode 40 is turned on, and the current I ₂ flows to absorb the positive overvoltage.

[0034]

[Embodiment 3] FIG. 9 shows a specific example in which the protection circuit for preventing electrostatic breakdown of Embodiment 1 is provided in a self-scanning light emitting device. In the self-scanning light emitting device of FIGS. 1, 2 and 3, many elements are connected to each of the clock pulse terminals φ ₁ , φ ₂ , φ ₃ , the power supply terminal V _GK , and the write signal S _in . Therefore, it is not necessary to provide a protection circuit for preventing electrostatic discharge,
Since the start pulse terminal φ _S is the weakest against electrostatic damage, it is necessary to provide a protection circuit inside the start pulse terminal φ _S.

FIG. 9 shows a protection circuit 70 for preventing electrostatic breakdown inside the start pulse terminal of the self-scanning light emitting device of FIG.
The example which provided is shown.

[0036]

[Embodiment 4] The self-scanning light emitting device of FIG.
FIG. 10 shows an example in which a protection circuit for preventing electrostatic breakdown is provided in the circuit where _E is provided. The reason for providing the end terminal φ _E is, for example, when a plurality of 128-bit 1-chip light emitting devices are arranged on a mounting board to form a light source for a printer, each chip after being mounted on the mounting board. This is to test the operation of.

Like the start pulse terminal φ _S , such an end terminal φ _E is vulnerable to electrostatic breakdown, so that
It is necessary to provide a protection circuit to prevent electrostatic breakdown inside the end terminal φ _E. In FIG. 10, a protection circuit 72 is provided inside the end terminal φ _E of the light emitting device (128 bits, 1 chip) of FIG.
An example in which is provided.

[0038]

[Embodiment 5] In the following embodiment, an example of a self-scanning light emitting device in which the protection circuit for preventing electrostatic breakdown of the present invention can be provided will be described.

The light emitting device of this embodiment utilizes an electric potential as a medium of interaction. FIG. 11 shows an equivalent circuit diagram of the light emitting device of this embodiment. The light emitting thyristors L (-2) to L (+2) according to the present invention are used as light emitting elements, and the light emitting thyristors L (-2) to L (+2) are respectively provided with gate electrodes G _{-2 to} G _+2. ing. The power supply voltage V _GK is applied to each gate electrode via the load resistance R _L.
Further, the respective gate electrodes G _{-2 to} G ₊₂ are electrically connected to each other through a resistor R _I to make an interaction. In addition, three transfer clock lines (φ ₁ , φ ₂ , φ ₃ ) are provided on the anode electrode of each single light-emitting thyristor, and each of them has three lines.
Every other element is connected (repeatedly).

The operation will be described. First, the transfer clock φ ₃
Is at a high level and the light emitting thyristor L (0) is on. At this time, from the characteristics of the three-terminal thyristor,
The gate electrode G ₀ is pulled down to near zero volts. Assuming that the power supply voltage V _GK is 5 V, the gate voltage of each light emitting thyristor is determined from the network of the load resistance R _L and the interaction resistance R _I. Then, the light emitting thyristor L (0)
The gate voltage of the element close to
The gate voltage increases as the distance from (0) increases. This can be expressed as:

V _G0 <V _G1 = V _G-1 <V _G2 = V _G-2 (1) The difference between these voltages is the load resistance R _L and the interaction resistance R _I.
It can be set by appropriately selecting the value of.

It is known that the turn-on voltage V _ON on the anode side of the three-terminal thyristor becomes higher than the gate voltage by the diffusion potential V _dif .

V _ON ≈V _G + V _dif (2) Therefore, if the voltage applied to the anode is set higher than the turn-on voltage V _ON , the light emitting thyristor turns on.

Now, with the light emitting thyristor L (0) turned on, the high level voltage V _H is applied to the next transfer clock pulse φ ₁ . This clock pulse φ ₁ is simultaneously applied to the light emitting thyristors L (+1) and L (−2),
By setting the value of the high level voltage V _{H in} the following range, only the light emitting thyristor L (+1) can be turned on.

V _G−2 + V _dif > V _H > V _{G + 1} + V _dif (3) Thus, the light emitting thyristors L (0) and L (+1) are simultaneously turned on. When the high level voltage of the clock pulse φ ₃ is cut off, the light emitting thyristor L (0) is turned off and the transfer in the on state is completed.

As described above, in this embodiment, by connecting the gate electrodes of the respective light emitting thyristors with the resistance network, it becomes possible to give the light emitting thyristors a transfer function.

From the principle described above, if the high-level voltages of the transfer clocks φ ₁ , φ ₂ , and φ ₃ are set so as to overlap each other little by little, the ON state of the light emitting thyristor is sequentially transferred. . That is, the light emitting points are sequentially transferred, and a self-scanning light emitting device can be realized.

Next, the structure of the self-scanning light emitting device of this embodiment which is integrated and manufactured will be described.

FIG. 12 is a schematic diagram showing the structure of the light emitting device of this embodiment.
Shown in The N-type semiconductor layer 24, the P-type semiconductor layer 23, the N-type semiconductor layer 22, and the P-type semiconductor layer 21 are formed on the grounded N-type GaAs substrate 1. Then, by photolithography, etching, etc., each single light emitting thyristor L
(-1) to L (+1) are separated. The separation groove is shown at 50. The anode electrode 40 has ohmic contact with the P-type semiconductor layer 21, and the gate electrode 41 has ohmic contact with the N-type semiconductor layer 22.

The insulating layer 30 prevents a short circuit between the element and wiring,
At the same time, it is also a protective film for preventing characteristic deterioration. N type Ga
The As substrate 1 is the cathode of this thyristor. Three transfer clock lines (φ ₁ , φ ₂ , φ ₃ ) are connected to the anode electrode 40 of each single light emitting thyristor every three elements. Further, the gate electrode 41 is connected to a resistance network including a load resistance R _L and an interaction resistance R _I.

[0051]

[Sixth Embodiment] In this embodiment, the inventors of the present invention disclosed in Japanese Patent Laid-Open No. 2-92.
The self-scanning light-emitting device disclosed in Japanese Patent No. 650 is one of the examples to which the present invention can be applied.

In this embodiment, an example of resistance connection will be further described. An equivalent circuit diagram of the light emitting device of this embodiment is shown in FIG.

This shows the case where a light emitting thyristor is used as the light emitting thyristor whose light emitting threshold voltage and current can be controlled from the outside. Light emitting thyristors L (-2) to L
(+2) is arranged in a line. Each light emitting thyristor is represented as a combination of transistors Tr ₁ and Tr ₂ . The transistor Tr ₁ is a PNP transistor, and the transistor Tr ₂ is an NPN transistor. The resistor R _I for interconnection between the light emitting thyristors is NPN.
It is connected between the bases of the transistors Tr ₂ . Three transfer clock lines (φ ₁ , φ ₂ , φ ₃ ) are sequentially and repeatedly connected to the anode electrode of each single light emitting thyristor one by one. The clock line is provided with a current limiting resistor R _e for the clock line.

The operation will be described. First, it is assumed that the transfer clock φ ₃ becomes high level and the light emitting thyristor L (0) is turned on. At this time, the NPN transistor Tr ₂ (0)
The base of is set to a potential at which the ON current of the light emitting thyristor L (0) can flow. Interconnect contact anti R _I is this potential
Through adjacent light emitting thyristors L (-1), L
(1) NPN transistor Tr ₂ (−1), Tr
₂ These (1) are transmitted to the base and these base currents flow. However, as long as the transfer clock lines φ ₁ and φ ₂ are at the low level, the light emitting thyristors L (-1) and L (1) remain off.

Now, if this interconnection resistance R _I is small, the NPN transistors Tr ₂ (-1) and Tr ₂ (1)
Has the ability to pass the same current as the ON current of the light emitting thyristor L (0). However, if the interconnection resistance R _I is large, the NPN transistors Tr ₂ (−1), Tr
The base current of ₂ (1) is limited by the interconnection resistance R _I , and the NPN transistors Tr ₂ (-1) and Tr ₂ (1)
The current drive capacity of is reduced. NPN transistor Tr ₂
(-1), Tr ₂ NP located farther than (1)
The base currents of the N-transistors Tr ₂ (−2) and Tr ₂ (2) are further reduced, and the current drive capability thereof is further reduced.

It is known that the turn-on voltage of the light emitting thyristor decreases when the base current amount of the NPN transistor Tr ₂ , that is, the current driving capability increases. This is shown in FIG. The horizontal axis is the anode voltage (P
(Emitter voltage of NP transistor Tr ₁ ), and the vertical axis represents the anode current. Here, the turn-on voltage V _S is a turn-on voltage when there is no external influence,
The turn-on voltage V _S (1) is the light emitting thyristor L (1).
Of the turn-on voltage V _S (-2) is the light emitting thyristor L
It represents the turn-on voltage of (-2). Minimum voltage required to maintain the ON state is called a hold voltage V _h. The light-emitting thyristors L (-1) and L (1) closest to the light-emitting thyristor L (0) being turned on have the turn-on voltage lowered and become the turn-on voltage V _S (1) for the reason described above. The next closest light emitting thyristors L (-2) and L (2) are less affected by the base current and have a turn-on voltage V _S (-2).
Becomes

Now, in FIG. 13, the clock pulse φ
The next clock pulse φ ₁ of ₃ light-emitting thyristor L
(1), L (-2) are applied. These turn-on voltages are respectively the turn-on voltage V _S for the reasons described above.
(1) and V _S (−2), the high-level voltage of the clock pulse is the turn-on voltage V _S (1),
If you set between V _S (-2) light-emitting thyristor L
Only (1) can be turned on. If the clock pulses φ ₁ , φ ₂ , φ ₃ are set so that their high levels overlap with each other, the ON-state light emitting thyristors will be sequentially transferred. From this, a self-scanning light emitting device can be realized.

From the above, it can be seen that the light emitting device can be constructed with a simple structure since only one resistor is required to connect the light emitting thyristors in this embodiment.

Next, the structure when the light emitting device of this embodiment is integrated and manufactured will be described. The essential point of this embodiment is a structure in which even a resistance element can be formed in the same step as the light emitting thyristor by providing an interconnecting resistor for making electrical coupling by utilizing a part of the light emitting thyristor. .

FIG. 15 is a conceptual diagram of a structural cross section of the light emitting device of this example. On the grounded N-type GsAs substrate 1, the N-type semiconductor layer 24, the P-type semiconductor layer 23, the N-type semiconductor layer 22, and P
Each layer of the shaped semiconductor layer 21 is formed. Then, the individual light-emitting thyristors L (-2) to L (2) are separated by photolithography and etching (separation groove 50).

The N-type GaAs substrate 1 serves as the cathode of this thyristor and is grounded. Transfer clock lines φ ₁ , φ ₂ , and φ ₃ are connected to every two elements to the P-type semiconductor layer 21 serving as the anode of each single light emitting thyristor. The feature of this structure is that the P-type semiconductor layer 23 forming the thyristor is connected through each element. The internal resistance of the P-type semiconductor layer 23 becomes the interconnection resistance R _I shown in FIG.

As described above, in the light emitting device of this embodiment, it is not necessary to provide a gate electrode, and only one resistor is used for interconnecting the light emitting thyristors, and further the interconnecting resistance R
_I can be formed of a semiconductor layer that constitutes a light emitting thyristor. A self-scanning light emitting device having a simpler structure can be realized.

[0063]

EXAMPLE 7 In this example, the inventors of the present invention described in JP-A-2-14.
The self-scanning light-emitting device disclosed in Japanese Patent No. 584 is one of the examples to which the present invention can be applied.

In this embodiment, an example using a diode will be described as an electrical connection method. FIG. 1 is an equivalent circuit diagram for explaining the principle of the self-scanning light emitting device of this embodiment.
6 is shown. This shows a case where a three-terminal light emitting thyristor is used as a light emitting thyristor whose light emission threshold voltage and current can be controlled from the outside. Light emitting thyristor L (-2)
-L (+2) are arranged in a line.
G _{-2 to} G ₊₂ are light emitting thyristors L (-2) to L (+2)
Of each gate electrode. R _L represents the load resistance of the gate electrode, and D _{−2 to} D ₊₂ represent diodes that make an electrical interaction. V _GK represents the power supply voltage. Two transfer clock lines (φ ₁ , φ ₂ ) are connected to the anode electrode of each single light emitting thyristor every other element.

The operation will be described. First, it is assumed that the transfer clock φ ₂ becomes high level and the light emitting thyristor L (0) is turned on. At this time, due to the characteristics of the three-terminal thyristor, the gate electrode G ₀ is pulled down to near zero volt. Assuming that the power supply voltage V _GK is 5 V, the gate voltage of each light emitting thyristor is determined by the network of the resistor _RL and the diodes D _{-2 to} D ₊₂ . Then, the gate voltage of the element close to the light emitting thyristor L (0) is the lowest, and thereafter, the gate voltage is increased with increasing distance from L (0).

However, due to the unidirectionality and asymmetry of the diode characteristics, the effect of lowering the voltage works only to the right of L (0). That is, the gate electrode G ₁ is set to a voltage higher than G ₀ by the diode forward-direction rising voltage V _dif , and the gate electrode G ₂ is set to a voltage higher than G ₁ by the diode forward-direction rising voltage V _dif. To be done. On the other hand, the gate electrode G on the left side of L (0)
_{In -1,} since the diode D _-1 is reverse biased, no current flows, and therefore the potential is the same as the power supply voltage V _GK .

The next transfer clock pulse φ ₁ is the closest light emitting thyristors L (1), L (-1), and L (3).
And L (−3), among these,
The element with the lowest turn-on voltage is L (1),
The turn-on voltage of L (1) is about the gate voltage of G ₁ + V
_dif , which is about twice V _dif . The element with the next lowest turn voltage is T (3), which is about four times V _dif . The turn-on voltage of L (-1) and L (-3) is about V _GK + V _dif .

[0068] From the above, by setting the high-level voltage of the transfer clock pulses between about 2 times the V _dif of approximately 4 times the V _dif, it is possible to turn on only the light-emitting thyristor L (1), Transfer operations can be performed.

Next, the structure in the case where the self-scanning light emitting device of this embodiment is integrated and manufactured will be described.

FIG. 17 shows a conceptual diagram of the structure of the light emitting element array of this example. On the grounded N-type GaAs substrate 1, N
Type semiconductor layer 24, P type semiconductor layer 23, N type semiconductor layer 2
2, each layer of the P-type semiconductor layer 21 is formed. Then, the individual light emitting thyristors L (−2) to L (+1) are separated by photolithography and etching. 5 separation grooves
It is indicated by 0. The anode electrode 40 is in ohmic contact with the P-type semiconductor layer 21, and the gate electrode 41 is the N-type semiconductor layer 2.
It is in ohmic contact with 2. The insulating layer 30 prevents a short circuit between the element and the wiring, and at the same time acts as a protective film for preventing characteristic deterioration. Here, the insulating layer 30 is made of a material that does not allow light of the emission wavelength of the light emitting thyristor to pass therethrough.

The N-type GaAs substrate 1 serves as a cathode. Two transfer clock lines (φ ₁ , φ ₂ ) are connected to the anode electrode 40 of each single light emitting thyristor every other element.

If the high-level voltages of the transfer clocks φ ₁ and φ ₂ are set so as to alternately overlap each other little by little, the ON states of the light emitting thyristors are sequentially transferred. That is, the light emitting points are sequentially transferred, and an integrated self-scanning light emitting element array using potential coupling by diodes can be realized.

[0073]

[Embodiment 8] In this embodiment, the inventors of the present invention disclosed in Japanese Patent Laid-Open No. 2-92.
The self-scanning light emitting device disclosed in Japanese Patent No. 651 is one of the examples to which the present invention can be applied.

FIG. 18 shows an equivalent circuit diagram for explaining the principle of the light emitting device of this embodiment. This is the emission threshold voltage,
A light emitting thyristor with three terminals is used as the light emitting thyristor whose current can be controlled from the outside. Each light emitting thyristor is represented as a combination of transistors Tr ₁ and Tr ₂ . The transistor Tr ₁ is a PNP transistor, and the transistor Tr ₂ is an NPN transistor. The transistor Tr ₃ is provided, the base of the transistor Tr ₃ is connected to the base of the NPN transistor Tr _2, constitute a current mirror circuit I is combined with NPN transistor Tr _2. The light emitting thyristors L (-1) to L (1) are arranged in a line, and the light emitting thyristors are connected by a current mirror circuit.

Light emitting thyristors L (-1) to L (+1)
Have respective gate electrodes G _{-1 to} G ₊₁ which have a load resistance R _L. For the gate electrode,
The power supply voltage V _GK is applied via the load resistance R _L. Anode electrode of each light emitting thyristor (emitter of Tr ₁ )
In addition, two transfer clock lines (φ ₁ , φ ₂ ) are connected every other element. The clock line is provided with a current limiting resistor R _e for the clock line.

The operation will be described. First, transfer clock φ ₂
Is at a high level and the light emitting thyristor L (0) is on. At this time, the gate electrode G ₀ is pulled down to near zero volt due to the characteristics of the three-terminal thyristor. When the power supply voltage V _GK is 5 V, a current limited by the load resistance R _L flows into the gate electrode G ₀ . A current limited by the resistance R _e flows into the emitter (anode).

Since the transistors Tr ₂ and Tr ₃ are current mirror circuits, the transistor Tr
₃ has a current drive capacity proportional to Tr ₂ .
From this current driving capability, a current is drawn through the load resistor R _L connected to the collector of the transistor Tr ₃ , and the potential of the gate electrode G ₁ of the adjacent light emitting thyristor L (1) is lowered. By properly adjusting the driving capability of the transistor Tr ₃ , the potential of the gate electrode G ₁ can be reduced to almost zero.

[0078] ON voltage of the light-emitting thyristor L (1), since a voltage higher diffusion potential V _dif than the potential of the gate electrode G _1, the voltage of the transfer clock pulses phi ₁ is equal to or diffusion potential V _dif more on Light up state Thyristor L (1)
Can be transmitted to.

Now, as described above, the light emitting thyristor L (1)
However, the turn-on voltage of the light emitting thyristor L (-1) located on the opposite side does not change. This is because the voltage of the gate electrode G _-1 which determines the on-voltage of the light emitting thyristor L (-1) is not affected even if the gate G _{0 drops} to almost zero. Therefore, if the high-level voltages of the transfer clocks φ ₁ and φ ₂ are set to alternately overlap each other little by little, the ON states of the light emitting thyristors are sequentially transferred. That is, it is possible to realize a self-scanning light emitting device in which light emitting points are sequentially transferred and integrated by optical coupling.

From the above, the light emitting element array using this current mirror circuit is operated by the transfer clock pulse voltage from V _dif to V _GK + V _dif, and is operated in a wide operating voltage range of V _GK. You can

Next, the structure in the case where the self-scanning light emitting device of this embodiment is integrated and manufactured will be described.

FIG. 19 is a structural conceptual diagram of the light emitting device of this embodiment.
Shown in The N-type semiconductor layer 24, the P-type semiconductor layer 23, the N-type semiconductor layer 22, and the P-type semiconductor layer 21 are formed on the grounded N-type GaAs substrate 1. Then, the individual light emitting thyristors L (-1) to L (+1) are separated by photolithography and etching. 50 separation grooves
Indicated by The anode electrode 40 is in ohmic contact with the P-type semiconductor layer 21, and the gate electrode 41 is in the N-type semiconductor layer 22.
Is in ohmic contact with. The insulating layer 30 prevents a short circuit between the element and the wiring, and at the same time acts as a protective film for preventing characteristic deterioration.

In the figure, the portion surrounded by the broken line is the transistor T.
r ₃ and is connected to the gate electrode 41. The transistor Tr ₃ includes a collector 22, a base 23, and an emitter 24.
Having. The transistor Tr ₁ has a collector 23, a base 22, and an emitter 21. Transistor Tr
₂ has a collector 22, a base 23, and an emitter 24.

The base of the transistor Tr ₂ is electrically connected to the base of the transistor Tr ₃ . Also, the collectors of these transistors are separated. The gate electrode 41 is connected to the power supply V _GK via the load resistance R _L , and the substrate 1 is grounded. The substrate 1 also serves as the emitters of the transistors Tr ₂ and Tr ₃ .

[0085]

[Embodiment 9] In this embodiment, the inventors of the present invention disclosed in JP-A-2-26.
The self-scanning light-emitting device disclosed in Japanese Patent No. 3668 is one of the examples to which the light-emitting thyristor of the present invention can be applied.

FIG. 20 shows an equivalent circuit diagram for explaining the principle of the light emitting device of this embodiment.

This light emitting device has a switch element T (-1).
To T (2), writing light emitting elements L (-1) to L (2)
Consists of The configuration of the switch element portion shows an example using diode connection. Gate electrode G of switch element
_{-1 to} G ₁ are also connected to the gate of the writing light emitting element. A write signal S _in is applied to the anode of the write light emitting element.

The operation of this self-scanning light emitting device will be described below. FIG. 21 shows a simplified sectional view of the configuration of the switch element circuit. Now, assuming that the switch element T (0) is in the ON state, the voltage of the gate electrode G ₀ becomes lower than V _GK (here, assumed to be 5 V) and becomes almost 0 V. Therefore, if the voltage of the write signal S _in is equal to or higher than the diffusion potential of the PN junction (about 1 volt), the light emitting element L
(0) can be in a light emitting state.

On the other hand, the gate electrode G _-1 is about 5 volts and the gate electrode G ₁ is about 1 volt. Therefore, the writing voltage of the light emitting element L (-1) is about 6 volts,
The writing voltage of the light emitting element L (1) is about 2 volts.
From this, the voltage of the write signal S _in which can be written only to the light emitting element L (0) is in the range of about 1 to 2 volts. When the light emitting element L (0) is turned on, that is, enters the light emitting state, the voltage of the write signal S _in line is fixed to about 1 volt, so that an error that another light emitting element is selected can be prevented. it can.

The light emission intensity is determined by the amount of current flowing _{in the} write signal S _in , and it becomes possible to write an image at any intensity. Further, in order to transfer the light emitting state to the next element, it is necessary to once hold the voltage of the write signal S _in line to 0 volt and once turn off the light emitting element.

[0091]

[Embodiment 10] This embodiment is a self-scanning light emitting device in which a plurality of light emitting elements can emit light at the same time. FIG. 22 shows an equivalent circuit diagram of this light emitting device.

The difference from the circuit shown in FIG.
The light emitting elements in one block are controlled by one switch element, and the write signal lines S _in 1 and S 1 are respectively provided to the light emitting elements in one block.
_The point is that the light emission of the light emitting element was controlled by connecting _in 2 and S _in 3. In the figure, light emitting elements L ₁ (-1), L ₂ (-1),
L ₃ (−1), light emitting elements L ₁ (0), L ₂ (0), L ₃
(0), light emitting elements L ₁ (−1), L ₂ (−1), L
₃ (-1) and the like indicate the light emitting element that is blocked.

The operation is the same as that of the circuit of FIG. 20, _in which the light emission is written by S _in one element at a time, a plurality of elements are simultaneously written and emit light, and the light is transferred for each block.

Now, considering the use of this light emitting device as a light source for a generally known optical printer such as an LED printer, a print corresponding to the short side (about 21 cm) of A4 with a resolution of 16 dots / mm. About 3 to print
A 400-bit light emitting element is required.

In the light emitting device described in Example 9,
There is always one point that emits light, and an image is written by changing the intensity of this light emission. When an optical printer is formed by using this, compared with a commonly used LED array for an optical printer (LEDs located at a point to write an image are controlled by a drive IC so that they simultaneously emit light) In some cases, a luminance of 3400 times is required, and if the luminous efficiency is the same, it is necessary to flow a current of 3400 times. However, the light emission time is, on the contrary, 1/3400 of that of a normal LED array.

However, the light-emitting element generally tends to have a shorter life as the current increases, and the life is shorter than that of the conventional LED printer, although the duty is 1/3400. Had a point.

However, according to the present embodiment, if the comparison is made under the condition that the total number of bits is the same, in this example, 3 in 1 block.
Since the element is included, the light emission time of one element is three times as long as that of the light emitting device of Example 17. Therefore, the current passed through the light emitting element in the ON state may be 1/3, and the life can be extended as compared with Example 17.

In this embodiment, the case where three elements are included in one block has been described as an example, but the larger the number of elements, the smaller the write current, and the longer the life can be achieved.

[0099]

[Embodiment 11] An example of a self-scanning light emitting device capable of further improving the duty will be described below with reference to FIGS.
4, using FIG. 25. FIG. 23 is a block diagram of the self-scanning light emitting device of this embodiment.

The light emitting device of this embodiment is composed of the shift register 2
00, write switch array 201, reset switch array 202, and light emitting element array 203. Each array is composed of N elements, and their numbers are (1) to (N).

The shift register 200 is driven by the power supply V ₁ , a plurality of transfer pulses φ, and a start pulse φ _S , and the ON state is transferred (self-scanning). Here, the transfer direction is from left to right, that is, (1) to (N).

The write switch array 201 is a switch for writing the image signal V _IN to the light emitting element array 203, and is synchronized with the shift register 200. That is, time t
It has a function of writing the image signal V _IN (t) into the bit of the light emitting element array 203 corresponding to the shift register 200 in the ON state.

In the present embodiment, the writing of the image signal V _IN is performed within the same number for each bit. The light emission information once written is stored in the light emitting element array 20.
3 is held.

On the other hand, the shift register 200 is configured to address the reset switch array 202 at the same time. However, the output of the shift register of number (1) is to the reset switch of number (2), the output of the shift register of number (2) is to the reset switch of number (3), etc.
It is connected to the element that has advanced in the 1-bit transfer direction.

When the reset switch is addressed, the light emitting element is reset. That is, when the shift register is turned on, the light emitting element that has advanced from the shift register in the 1-bit transfer direction is once returned to the non-light emitting state (off state) regardless of the light emitting state or the non-light emitting state.

With such a structure, the time change of the image signal is written as the position change of the light emitting element, the image information is written in the light emitting element, and the image pattern by light emission is formed. Then, when writing the next image signal, the image information written by the reset switch is erased, and immediately after that, new image information is written. Therefore, the light emitting element is almost in a state of being almost always turned on, and the duty is substantially 1.

Here, only one shift register 200 is provided and the output is used for both image signal writing and reset. However, two shift registers are provided and used for image signal writing and reset, respectively. Good.

FIG. 24 shows a diagram in which the circuit of FIG. 22 is rewritten with P and N images. The shift register 200 is composed of thyristors T _S (1) to T _S (4). Each thyristor is composed of transistors Tr ₁ and Tr ₂ , and its gate is connected to the adjacent thyristor and power supply V ₁ via a load resistance _RL and a coupling resistance R _I. The output of this shift register is taken out from the gate and output voltage V
It is displayed as _O (1) to V _O (3). (1) ~
(3) is the number of each bit. In the figure, the resistor that limits the current of the transfer clock line is represented by the resistor R _e .

[0109] As a write switch, using a PNP transistor _{Tr 3 (1) ~Tr 3 (} 3), as a reset switch, NPN transistor Tr ₄ (1) ~Tr ₄
(3) is used. The resistor R _e is a resistor that limits the current flowing through the light emitting element. As the light emitting element, a light emitting thyristor displayed by a combination of the transistors Tr ₅ and Tr ₆ is used. As the characteristics of this light emitting thyristor,
It has the feature that once it is turned on, it continues to be turned on until the power is turned off. This is used as a memory function for light emission.

The operation of this circuit will be described with reference to the pulse timing chart shown in FIG. In FIG. 24, T _{1 to} T
₅ represents the time. The transfer clock is φ ₁ to φ ₃ , and φ
₁ is between T _{1 and} T ₂ and T _{4 and} T ₅ , and φ ₂ is between T _{2 and} T
_During the period of ₃ , φ ₃ is at the high level between T _{3 and} T ₄ . The shift register outputs V _O (1) to V _O (3) are taken out in synchronization with φ _{1 to} φ ₃ , respectively, and the output is given as a low level. The image signal V _IN becomes high level from time T _{2 to} T ₃ , and is written in the light emitting element of bit number (2).

Now, consider the time between T _{1 and} T ₂ . At this time, the output V _O (1) is taken out as a low level as the output of the shift register. This output V _O (1) is connected to the base of the transistor Tr ₃ (1) which is a write switch, and makes the transistor Tr ₃ (1) writable. However, here, since the image signal V _IN is at a low level, writing to the light emitting element is not performed.

On the other hand, the output V _O (1) is simultaneously applied to the base of the transistor Tr ₄ (2) which is a reset switch. Since this output V _O (1) drops to about 0 volt, the emitter voltage of the transistor Tr ₄ (2) also becomes almost 0 volt, turning off the light emitting element.
Therefore, the light emitting element having the bit number (2) has been reset.

Next, consider the period between times T _{2 and} T ₃ . The shift register output is V _O (2), which is Tr ₃ (2)
Applied to the base. Here, since the image signal V _IN is at a high level, a current flows through the transistor Tr ₃ (2) and flows into the light emitting memory. This current is the transistor T
It becomes a base current of r ₆ (2), which turns on the light emitting element of bit number (2). This light emission is maintained until the next reset signal. At this time, the light emitting element having the bit number (3) is reset by V _O (2).

The current flowing through the light emitting element is limited by the resistance R _e , and the duty is large, so that a small current is sufficient and a highly reliable light emitting device can be obtained.

FIG. 26 shows a case where the light emitting device of this embodiment is integrated and manufactured. Each bit of the shift register is represented by a four-layer structure of PNPN, and the light emitting element is also PNP.
It is represented by N configuration. Each bit of PNPN of the shift register is represented by T _S (1) to T _S (4), and each bit of the light emitting element is represented by T _L (1) to T _L (4). This structure is manufactured on the semiconductor substrate 1.

In particular, FIG. 26 is a sectional view showing the bit number (2). On the semi-insulating GaAs substrate 1, the N-type GaAs layer 24, the P-type GaAs layer 23,
It has a structure in which an N-type GaAs layer 22 and a P-type GaAs layer 21 are sequentially stacked. Each semiconductor layer is separated by an insulating film 30, divided into elements having respective functions, and electrically connected by a metal electrode 43. Resistances R _L and R _I are N
It is a resistance element formed by the GaAs layer 22, and its end is connected to the power supply V ₁ .

The shift register T _S (2) includes the semiconductor layer 2
It is composed of four layers 1, 22, 23 and 24.

The write switch Tr ₃ (2) is composed of the semiconductor layers 21, 22 and 23, and the unnecessary semiconductor layer 24.
Are connected to the semiconductor layer 23 to kill the effect of the semiconductor layer 24.

The light emitting element T _L (2) is composed of the semiconductor layers 21 and 2.
The write switch Tr ₃ (2) has the semiconductor layers 23 and 24 connected to the semiconductor layer 23 of the shift register T _L (2). This serves as a writing electrode of the light emitting element. The resistor R _{e is} also formed of the N-type GaAs layer 22 like the resistors R _L and R _I.

The reset switch Tr ₄ (2) is composed of the semiconductor layers 22, 23 and 24 and does not include the unnecessary semiconductor layer 21.
Are connected to the semiconductor layer 22. The semiconductor layer 23 is connected to the base 21 of the write switch Tr ₃ (1).
By using the structure shown in FIG. 26, the above-mentioned function can be fully achieved.

This self-scanning light-emitting device can be applied to a writing head of an optical printer, a display, etc.,
It can make a significant contribution to lower prices and higher performance of these devices.

[0122]

[Embodiment 12] This embodiment is one example of the self-scanning light emitting device disclosed in Japanese Patent Laid-Open No. 4-23367, to which the light emitting thyristor of the present invention can be applied.

The light emitting device of the example is shown in FIG. FIG.
In FIG. 1, the switch element array and the light emitting element array are described separately in the upper and lower parts.

First, a switch element array having a shift register function will be described. T (-2) to T (2)
Is a switch element (thyristor with PNPN structure)
It is. φ ₁ and φ ₂ are transfer clocks for driving the switch element array. CL ₁ is the transfer clock φ
CL ₂ is a clock line supplied with ₁ and CL ₂ is a clock line supplied with a transfer clock φ ₂ .

The gate electrodes G _{-1 to} G ₂ of the switch elements T (-2) to T (2) are connected by coupling diodes D _{-2 to} D ₁ , respectively. Since such a diode coupling system is adopted, the switch element array can perform the information transfer operation with the two-phase transfer clocks φ ₁ and φ ₂ .

Further, R _A1 and R _A2 are anode load resistors respectively connecting the anodes of the switch elements T (−2) to T (2) and one of the clock lines CL ₁ and CL ₂ . This anode load resistance R _A1 , R _A2
Is for limiting the amount of current in the ON state of each of the switch elements T (−2) to T (2). Each switch element T (-
The cathodes 2) to T (2) are grounded.

Further, R _L1 and R _L2 are load resistances of the gates that connect the gates G _{-2 to} G _{2 of the} switch elements T (-2) to T (2) and the DC power source of the power source voltage V _GK , respectively. Is. The gate load resistors R _L1 and R _L2 limit the amount of current flowing from the DC power source of the power source voltage V _GK to the gates G _{-2 to} G ₂ . Then, each gate G _-2 , G ₀ , G
₂ are connected to the cathodes of the diodes D _-2 ', D ₀ ' and D ₂ ', respectively.

Next, the light emitting element array will be described.
φ _R is a light emitting element (light emitting thyristor) L (-2), L
It is a clock that controls permission / prohibition of writing information to (0) and L (2) and resets the written state. Further, CL _R is a current supply line for supplying the clock φ _R.

Further, R _A3 is each of the light emitting elements L (-2), L
It is an anode load resistance that connects the anodes of (0) and L (2) and the current supply line CL _R. The anode load resistance R _A3 is used for each light emitting element L (−2), L (0), L
This is to limit the amount of current in the ON state of (2). The cathodes of the light emitting elements L (-2), L (0), L (2) are grounded.

Further, R _L3 is each of the light emitting elements L (-2), L
_These are gate load resistors that connect the gates G _-2 ′, G ₀ ′ and G ₂ ′ of (0) and L (2) to the power supply voltage V _GK . The gate load resistor R _L3 limits the amount of current flowing from the DC power source of the power source voltage V _GK to each of the gates G _-2 ′, G ₀ ′ and G ₂ ′. Then, each gate G _-2 ', G ₀ ',
G ₂ ′ includes diodes D ₋₂ ′, D ₀ ′ and D ₂ ′, respectively.
Connected to the anode of.

That is, in FIG. 27, the gates of the switch elements T (−2), T (0), T (2) emit light via the diodes D ₋₂ ′, D ₀ ′, D ₂ ′, respectively. The gates G _-2 ', G of the elements L (-2), L (0), L (2)
₀ ', G _2' are individually connected to.

Next, the operation of the switch element array portion will be described. Now, assume that a high-level or low-level voltage is supplied to the anode (not shown) of the switch element T (-3) as the start pulse φ _S. In this case,
When the high level voltage is higher than the voltage obtained by adding the diffusion potential V _dif to the power supply voltage V _GK , the switch element T (−3) is turned on. Then, the low-level voltage of the start pulse φ _S supplied next is set to the switching element T (−3).
If it is lower than the on-state maintaining voltage of, T (-3) is in the off state.

In the ON state, the gate potential of the switch element T (-3) becomes approximately 0 volt, and in the OFF state, the gate voltage becomes the same voltage as the power supply voltage V _GK . Switch element T
When the gate potential of (-3) becomes 0 V, the switching diode T _-3 (not shown) causes the switching element T (-
The gate potential of 2) decreases. And the switch element T
The turn-on voltage of (-2) also decreases. Therefore, the switch element T (−2) can be turned on by the transfer clock φ ₂ .

This ON state is sequentially set by φ ₁ and φ ₂ ,
The data is transferred to the right in FIG. That is, the ON state is written in the switch element array by the high-level voltage of the start pulse φ _S , and the ON state is sequentially transferred to the right.

However, when all the bits are in the ON state, it is impossible to transfer the ON state from the operating principle of the switch element array, and the ON and OFF are repeated every other bit. Will be transferred. That is, the waveform of the start pulse φ _S is also the transfer pulse φ ₁ ,
It is necessary to send high level and low level alternately in synchronization with φ ₂ .

Now, assuming that there is valid information in the ON and OFF states of only even bits, assuming that the ON state is 1 and the OFF state is 0, 1 or 0 is written by the start pulse φ _S , and the transfer clock φ ₁ , ₁ , ₂ will transfer the 1, 0. In this way, the signal (information) of 1 or 0 is written in the switch element array.

Next, the light emitting elements L (-2) (L (0), L
The operation (2)) will be described. If L (−2) is 0, the light emitting element L (−2) is not turned on if the voltage of the clock φ _R is 0 volt. That is, the light emitting element L (-2) is set to the write-protected state. The voltage of the clock φ _R is the light emitting element L (-2)
If the voltage is set to a voltage between V _GK + V _dif from the ON state maintaining voltage of _{No. 1} , the light emitting element L (−2) is set to the write-enabled state. Then, by changing the potential of the gate G _-2 ', the light emitting element L (-2) can be set to the ON state.

Writing of information from the switch element array to the light emitting element array will be described. The 1 or 0 signal is written in the switch element array as described above. At the stage where the last bit is written, the transfer clocks φ ₁ and φ ₂ are maintained at low level and high level, respectively. As a result, the information transfer operation is completed, and the information written in the switch element array is held (especially, held in even bits).

In the even-numbered bits of the switch element array, the gate potential of the switch element T in the ON state is almost 0 volt, and the gate potential of the switch element T in the OFF state is about twice or more V _dif . The gate potential of the switch element T in the off state is approximately twice V _dif when the adjacent even bit located in the opposite direction to the transfer direction is in the on state, and otherwise V _dif . About 2
Double the voltage. Here, V _dif is PN
It is the diffusion potential of the junction.

Switch elements T (-2), T (0), T
The gate voltage of each of (2) is the diode D _-2 ',
D ₀ ′ and D ₂ ′ correspond to the corresponding light emitting elements L (−2),
L (0), the gate G _-2 of _{L (2) ', G 0} ', is transmitted to the G ₂ '. Therefore, the light emitting elements L (-2), L
The gate voltages of (0) and L (2) are V in the ON state.
_dif , which is three times V _dif or more in the off state. In the ON state, the turn-on voltage of the light emitting element is twice V _dif , and in the OFF state it is 4 times V _dif .

On the other hand, clock φ_ROnce about
Set it to zero volts to eliminate all light emission (ie
Set), then high level potential V_HRUp to
You. This voltage φ_HRAs 2V_dif<V_HR<4V_dif  When set to the range of
The light-emitting element L corresponding to is turned on and turned off.
The light emitting element L corresponding to the switch element T remains in the off state.
Become.

Therefore, the information of 1, 0 written in the switch element array is directly written in the light emitting element array.

After that, the voltage V _HR is reset to a value which is equal to or higher than the ON state maintaining voltage of the light emitting element and less than twice the voltage V _dif . As a result, the light emitting element L is not affected by the gate potential of the switch element T and continues to hold the written information. Then, while the light emitting element array is in the information holding state, the following information is written in the switch element array in the same manner as described above.

Eventually, the clock φ _R is set to the low level voltage and each light emitting element L is reset. After the reset, the information is written in the light emitting element array again. As described above, a series of operations is repeated.

Next, the self-scanning light emitting device shown in FIG.
The case of application to a writing light source for an optical printer will be described.

For example, if the light emitting device has a light emitting element L of 2048 bits, the switch element T needs 4096 bits, which is twice that. Since the current amount of the writing light source in the optical printer is about 5 mA, if the light emitting elements L of all the bits are in the light emitting state, a current of about 10 A flows.

On the other hand, it is experimentally known that the current for transferring information from the switch element T is 0.5 mA when the gate load resistance R _L3 = 30 kΩ. In the light emitting state, it is about 1A. Note that the amount of current for this information transfer is about 10% compared to 10 A required for optical printing, which is a value that poses no practical problem.

Further, when the information from the switch element T is moved to the light emitting element L, the voltages of the clocks φ ₁ and φ ₂ are once reduced to zero volt, and the entire switch element array is turned off and reset. Is done. When this method is used, the current value equivalently decreases when the time during which the switch element T is turned on is taken into consideration. That is, 0.5A is equivalent to 1A described above.
It has fallen to a degree.

For 2048 bits of the light emitting element L, if there is only one data input terminal (not shown) to which the start pulse φ _S is supplied, it is necessary that the transfer rate of information is considerably high. In this regard, the information transfer rate can be reduced by providing a plurality of data input terminals. For example, typically 64 bits or 128
A chip of the light emitting element L is formed with the bit as one unit,
Information may be input for each chip.

When data is input in parallel every 128 bits, 20 data input terminals are provided for 2048 bits. Therefore, the transfer rate of information is 1
/ 20 is good. Therefore, the light emitting device can perform a sufficient operation.

Note that the anode load resistance R _A3 can be finely adjusted by a laser or the like in order to prevent variations in the amount of light output from the light emitting element L. As a result, it is possible to obtain a light emitting device in which the output light does not vary.

Further, in FIG. 27, the switch element array is
Coupling diode connected to the right side of the even bit in
D_-2, D₀Characteristics and the connection connected to the right side of the odd bit.
Combined diode D_-1, D₁The characteristics are different. I
Therefore, the operating current etc. is divided by the even bit and the odd bit.
It is important to optimize. For this reason, R_L2 <
R_L1, R_A1<R_A2Should be set to
In addition, the light emitting device can operate more stably and at higher speed.

Further, in FIG. 27, a configuration called a diode coupling system is adopted, but the coupling system is not limited to this, and an optical coupling system utilizing the light emitting function and light receiving function of the switch element or a resistance coupling system is used. It may be.

FIG. 28 is a sectional view showing an example of a case where the equivalent circuit shown in FIG. 27 is manufactured on the same semiconductor substrate. In FIG. 28, 71 is an N-type semiconductor substrate, and 8
Reference numeral 1 is a P-type semiconductor layer, 82 is an N-type semiconductor layer, and 83 is a P-type semiconductor layer. The same elements as those in FIG. 27 are designated by the same reference numerals.

The important points in the embodiment shown in FIG. 28 are the switching element T and the coupling diode D _-2 shown in FIG.
D ₁ , D ₋₂ ′ to D ₂ ′, the light emitting element L and the like are semiconductor layers 81,
It can be formed by combining 82, 83 and the semiconductor substrate 71. Therefore, the circuit configuration of FIG. 27 is integrated and formed without complicating the manufacturing process.

For example, in the switch element T (-2),
The uppermost P-type semiconductor layer 81 serves as an anode, the N-type semiconductor layer 82 serves as a gate G _-2 , and the N-type semiconductor substrate 71 serves as a cathode. The two islands of the P-type semiconductor layer 81 formed on the N-type semiconductor layer 82 serve as coupling diodes D _-2 and D _-2 '. These diodes D ₋₂ and D ₋₂ ′ have the same structure as the switch element S (−2) and are formed by the same manufacturing process as S (−2).

Further, the light emitting element L (-2) also has exactly the same structure as the switch element T (-2) and is formed in the same step. In addition, the resistance portions R _{A1 to} R _A3 and R _L1
To R _L3 may be formed by a thin film resistor, or can be formed using a semiconductor layer 81, 82, 83.

In the above-described light emitting device, the self-scanning light emitting device is used as the transfer array, and the light emitting function is separated to another light emitting element array having almost the same structure. Therefore, the on-state transfer which causes the bias light is transferred. A light-shielding layer can be provided on the switch element for performing the operation, and the influence of bias light on the writing of image information can be removed. Therefore, when applying the light emitting device to an optical printer or the like,
The quality of an optical printer or the like can be improved.

The signal for writing the image information is
It can be directly input to the switch element as part of the start pulse. Therefore, the drive circuit can be simplified. Further, since the information written in the light emitting element is maintained until it is reset by the scanning signal, the duty cycle of light emission is set to approximately 1. Therefore, the current (peak value) flowing through the light emitting element can be reduced, and the life of the light emitting device can be extended.

[0160]

According to the present invention, since the protection circuit for preventing electrostatic breakdown can be manufactured by utilizing the PNPN structure of the thyristor array, the protection circuit can be manufactured easily. Further, the self-scanning light emitting device provided with the protection circuit for preventing electrostatic breakdown of the present invention has an effect of preventing electrostatic breakdown due to the arrival of overvoltage.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a conventional self-scanning light emitting device.

FIG. 2 is an equivalent circuit diagram of a conventional self-scanning light emitting device.

FIG. 3 is an equivalent circuit diagram of a conventional self-scanning light emitting device.

FIG. 4 is a circuit diagram showing an example of a protection circuit for preventing electrostatic breakdown.

5 is a cross-sectional view of a device structure of the light emitting device of FIG.

FIG. 6 is a circuit diagram of a protection circuit for preventing electrostatic breakdown according to a first embodiment of the present invention.

FIG. 7 is a diagram showing structures of an anode electrode and a gate electrode of Example 1.

8A and 8B are a sectional view and a plan view showing a structure of a protection circuit for preventing electrostatic breakdown according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram of a light emitting device according to a third embodiment of the invention.

FIG. 10 is a circuit diagram of a light emitting device according to a fourth embodiment of the invention.

FIG. 11 is a circuit diagram of a light emitting device according to a fifth embodiment of the invention.

FIG. 12 is a cross-sectional view of a light emitting device of Example 5.

FIG. 13 is a circuit diagram of a light emitting device of Example 6 of the present invention.

14 is a characteristic diagram of the light emitting thyristor of FIG.

15 is a structural cross-sectional conceptual diagram of the light emitting device of FIG.

FIG. 16 is a circuit diagram of a light emitting device of Example 7 of the present invention.

FIG. 17 is a sectional view of a light emitting device of Example 7.

FIG. 18 is a circuit diagram of a light emitting device of Example 8 of the present invention.

FIG. 19 is a cross-sectional view of a light emitting device of Example 8.

FIG. 20 is a circuit diagram of a light emitting device of Example 9 of the present invention.

21 is a cross-sectional view of a configuration of a switch element circuit of the light emitting device of FIG.

FIG. 22 is a circuit diagram of a light emitting device of Example 10 of the present invention.

FIG. 23 is a block diagram of a light emitting device of Example 11 of the present invention.

FIG. 24 is a PN image diagram of an equivalent circuit of the light emitting device of Example 11.

FIG. 25 is a pulse timing chart showing the driving method of the light emitting device of the eleventh embodiment.

FIG. 26 is a cross-sectional view of the light emitting device of Example 11.

FIG. 27 is a circuit diagram of a light emitting device of Example 12 of the invention.

28 is a cross-sectional view of the light emitting device of Example 12. FIG.

[Explanation of symbols]

T transfer thyristor L light emitting thyristor D coupling diode φ transfer clock pulse R _L gate load resistance R _e cathode load resistance R _I resistance for making interaction Tr transistor 1 first conductivity type substrate 22, 24 first conductivity type semiconductor Layers 21 and 23 Second conductivity type semiconductor layer 30 Insulating film 40 Anode electrode 41 Gate electrode 42 Cathode electrode 50 Separation groove 62, 64 Thyristor 66, 68 Current limiting resistor 621, 641 Anode electrode 622, 642 Gate electrode

Claims (6)

[Claims] 1. At least one light-emitting thyristor having a plurality of light-emitting thyristors having gate electrodes for controlling a threshold voltage or a threshold current for light-emitting operation, the gate electrodes of each light-emitting thyristor being located in the vicinity thereof. To the gate electrode of each of the light-emitting thyristors via a connection resistor or an electric element having electrical unidirectionality, a power supply line to each light-emitting thyristor via a load resistor, and a clock pulse line to each light-emitting thyristor In a protection circuit for preventing electrostatic breakdown used in a self-scanning light-emitting device formed by connecting a start pulse line to a first-stage light emitting thyristor, a current limiting resistor having one end connected to an input terminal, and the current An anode electrode or a cathode electrode is connected to the other end of the limiting resistor, a gate electrode is connected to the power source line, The is over cathode electrode or the anode electrode is grounded 1
And a second thyristor in which a gate electrode is connected to the other end of the current limiting resistor, and an anode electrode and a cathode electrode are grounded. 2. A plurality of transfer thyristors each having a gate electrode for controlling a threshold voltage or a threshold current for a transfer operation are arranged, and the gate electrode of each thyristor is located in the vicinity of at least one transfer thyristor. Connect to the gate electrode via a connection resistor or an electronic element that has electrical unidirectionality, connect the power supply line to each transfer thyristor via a load resistor, and connect the clock pulse line to each transfer thyristor. In addition, a transfer thyristor array formed by connecting a start pulse line to the first stage transfer thyristor and a plurality of light emitting thyristors having gate electrodes for controlling the threshold voltage or the threshold current for light emitting operation are arranged. A thyristor array, wherein each gate electrode of the light emitting thyristor corresponds to the corresponding transfer thyristor. It is a self-scanning light emitting device that is connected to the gate electrode of the star by electrical means and has a line for applying a current for light emission to each light emitting thyristor, and a current limiting resistor whose one end is connected to the input terminal. An anode electrode or a cathode electrode is connected to the other end of the current limiting resistor, a gate electrode is connected to the power supply line, and a cathode electrode or an anode electrode is grounded.
And a second thyristor in which a gate electrode is connected to the other end of the current limiting resistor, and an anode electrode and a cathode electrode are grounded. 3. The protection circuit for preventing electrostatic breakdown according to claim 1, wherein the anode electrode or the cathode electrode and the gate electrode of the first and second thyristors have a gate around the anode electrode or the cathode electrode. A protection circuit for preventing electrostatic breakdown, which has a concentric circular structure in which electrodes are surrounded by a ring. 4. A self-scanning light emitting device comprising the protection circuit for preventing electrostatic breakdown according to claim 1, wherein the input terminal is connected to the start pulse line. 5. A self-scanning light emitting device having a protection circuit for preventing electrostatic breakdown according to claim 1, wherein the input terminal is connected to an end terminal drawn out from the light emitting thyristor at the final stage. 6. The input terminal is connected to an end terminal drawn out from the transfer thyristor at the final stage.
Alternatively, a self-scanning light-emitting device including the protection circuit for preventing electrostatic breakdown according to 3.