JPH0997121A - System clock switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system clock switching circuit which starts its operation in a low speed operation mode that is set by a low speed clock signal in order to prevent the shift of the low speed operation mode to a high speed operation mode when the power voltage is lower than its guarantee level and therefore can prevent the easy occurrence of a system malfunction in a reset mode excluding moving into a power supply input mode. SOLUTION: When the power voltage monitor voltage 209 is latched by a D flip-flop 20 by a reset signal 102 with a reset signal 102 as the clock input, the signals at a low level are outputted after a reset mode set in a power input mode, and the signals of high levels are outputted after the reset mode set in a mode excluding the power supply input mode, thereby, a system clock is switched in a low speed operation mode between a dividing signal 106 of a high speed clock signal and a low speed clock signal 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system clock switching circuit.

[0002]

2. Description of the Related Art In recent years, a microcomputer system has been used in a VCR or the like, which keeps a timer running by a built-in battery and holds stored contents such as recording reservation settings even when external power is not supplied. Such a microcomputer system has a high frequency (about 14 to 1).
An oscillation circuit that supplies a high-speed clock signal of 6 MHz) and an oscillation circuit that supplies a low-speed clock signal of low frequency (about 30 KHz) are provided inside the system, and a system clock is switched according to the state of the power supply voltage (hereinafter , High-speed clock signal system clock mode is the high-speed operation mode, low-speed clock signal system clock mode is called the low-speed operation mode).

The high-speed operation mode has an advantage of high processing speed, but has disadvantages such as a high guaranteed power supply voltage (5V ± 10%) for guaranteeing the operation of the CPU and a large current consumption. In low-speed operation mode, the guaranteed power supply voltage is low (about 3
V), it has the advantage of low current consumption, but has the disadvantage of slow processing speed. Therefore, when the external power is supplied, it is possible to obtain a higher processing speed by operating in the high-speed operation mode, but when the external power is not supplied, the low-speed operation mode is used to minimize the consumption of the built-in battery. It is desirable to switch to.

Further, the oscillation stable period of the high-speed clock signal is about 30 milliseconds, which is much shorter than the oscillation stable period of the low-speed clock signal (about 1 second). for that reason,
When the system is initialized, it is faster to use the high-speed clock signal as the system clock.
FIG. 5 shows an example of a microcomputer system having a conventional system clock switching circuit. This microcomputer system includes an external reset switch 1, a power supply voltage 2, a pull-up resistor 3, a capacitor 4, a Schmitt type inverter 5, a transistor switch 6, a low speed operation mode system clock selection unit 8, a high speed clock signal output unit 9, and a low speed clock. Signal output unit 10, high-speed clock signal frequency divider 11, CPU 12,
A timer 13 is provided. Further, 101 is a reset request signal, 102 is a reset signal, 103 is a self-reset signal by a CPU, 105 is a high-speed clock signal, 106 is a divided signal of a high-speed clock signal, 107 is a low-speed clock signal, and 108 is a system for low-speed operation mode. Clock signal,
Reference numeral 504 is a system clock selection signal for the low speed operation mode.

The external reset switch 1 is an electrical switch that is turned on in response to a reset request from a reset button or a peripheral circuit other than the CPU 12, and outputs a negative logic reset request signal 101. The pull-up resistor 3 and the capacitor 4 blunt the rising waveform of the transient voltage of the power supply voltage 2 and output it as the reset request signal 101.

The Schmitt type inverter 5 receives the reset request signal 101 and is at a high level indicating a reset while the input is at a low level, and is at a low level indicating a reset release when the input exceeds a threshold voltage. The reset signal 102 is output. Transistor switch 6
Is turned on when the self-reset signal 103 is input by the CPU 12, and outputs the reset request signal 101.

The low-speed operation mode system clock selection section 8 uses the divided signal 106 of the high-speed clock signal as the low-speed operation mode system clock signal 108 when the low-speed operation mode system clock selection signal 504 from the CPU 12 is at a low level. When the low-speed operation mode system clock selection signal 504 is at the high level, the low-speed clock signal 107 is supplied to the CPU 12 as the low-speed operation mode system clock signal 108.

The high speed clock signal output section 9 outputs a high speed clock signal 105. Low-speed clock signal output unit 10
Outputs the low-speed clock signal 107. The high-speed clock signal divider 11 divides the high-speed clock signal 105 to a frequency that can be used as a low-speed operation mode system clock, and divides the high-speed clock signal to the low-speed operation mode system clock selection unit 8. The signal 106 is output.

The CPU 12 operates with the system clock signal 108 for the low speed operation mode or the high speed clock signal 105 as the system clock. System clock signal 108 for low speed operation mode and high speed clock signal 105
Software controls which of the two is used as the system clock. When the power is turned on, the system clock signal 108 for low speed operation mode is used as the system clock. Further, the self-reset signal 103 is output when an abnormality is recognized in the operation of the software.

The timer 13 operates using the low speed clock signal 107 as a clock signal. The operation of the system clock switching circuit configured as above will be described below. When power is turned on, pull-up resistor 3 and capacitance 4
Accordingly, a transient voltage (reset request signal 101) is generated. The reset signal 102 is supplied to the CPU 12 and other circuit groups (not shown) until the reset request signal 101 exceeds the input threshold voltage of the Schmitt inverter 5. When the reset request signal 101 exceeds the input threshold voltage of the Schmitt inverter 5, the reset is released and the reset signal 102 becomes low level. Then, after the oscillation stabilization period of the high-speed clock signal 105, C
PU12 starts operation. Since the low-speed operation mode system clock selection signal 504 is at a low level, the CPU 12 starts operation in the low-speed operation mode using the divided signal 106 of the high-speed clock signal as the system clock. The oscillation stabilization period of the high-speed clock signal 105 is completed in a much shorter time than the oscillation stabilization period of the low-speed clock signal 107, so that the system operation is slower than when the operation is started in the low-speed operation mode using the low-speed clock signal as the system clock. The initialization can be completed in a short time. After the system has been initialized, it is switched to the high-speed operation mode by the high-speed clock signal 105 under the control of software.

When the external power supply is stopped and only the internal battery is activated, the operating mode of the CPU 12 is switched to the low speed operating mode by the low speed clock signal 107 in order to reduce the current consumption of the system. Further, the high-speed clock signal 105 is stopped, and if necessary, C
The operation of the PU 12 is stopped. When the supply of external power is restarted, the restart of power supply is detected by an interrupt, etc.,
The low-speed operation mode is changed to the high-speed operation mode and the normal operation is resumed.

In this system clock switching circuit, even when operating in the low speed operation mode by the low speed clock signal 107, when the CPU 12 outputs the self reset signal 103, or the reset button or the peripheral circuit passes through the external reset switch 1. Immediately after resetting when a reset request that is input is generated, the low-speed operation mode is set by the divided signal 106 of the high-speed clock signal. In this case, the low-speed clock signal 1 is used to reduce current consumption.
When the shift to the low speed operation mode according to 07 is made, the divided signal 106 of the high speed clock signal and the low speed clock signal 10
Since 7 is asynchronous, it is necessary to shift to the high speed operation mode once and then to the low speed operation mode by the low speed clock signal 107.

[0013]

However, in the above-mentioned conventional system clock switching circuit, the voltage at the time of shifting to the high speed operation mode may be equal to or lower than the guaranteed power supply voltage (5 V ± 10%) in the high speed operation mode. There is a problem that the system may malfunction.

If the operation mode immediately after reset is fixed to the low speed operation mode by the low speed clock signal 107,
It is considered that the problem at the time of shifting from the low speed operation mode by the frequency-divided signal 106 of the high speed clock signal to the low speed operation mode by the low speed clock signal 107 is solved, but the oscillation stabilization period at power-on becomes long. In view of the above problems, the present invention provides a system clock switching circuit that can avoid the transition to the high-speed operation mode when the power supply voltage may not be guaranteed and reduce the possibility of system malfunction. To aim.

[0015]

In order to solve the above-mentioned problems, the invention of claim 1 is a reset at the time of turning on the power by detecting the power supply voltage when the reset occurs, or other than that. Identification means for identifying whether or not the reset is performed, and if the reset is determined when the power is turned on, the divided signal obtained by dividing the high-speed clock signal is selected, and the other reset is performed. And a selecting means for selecting the low speed clock signal and supplying the low speed clock signal to the CPU as the low speed clock signal.

In the invention of claim 2, as the identifying means, an RC circuit composed of a resistor and a capacitor connected in series from a power supply voltage, and a voltage level between the resistor and the capacitor are input, and at the time of reset release. And a flip-flop that outputs a logic level signal indicating a discrimination result by taking in the voltage level.

[0017]

According to the above means, in the system clock switching circuit according to the first aspect, the identifying means detects the power supply voltage when the reset occurs, and performs the reset when the power is turned on or the other reset. Identify. When the identifying means identifies the reset when the power is turned on, the selecting means supplies the frequency-divided signal of the high-speed clock signal to the CPU as the system clock for the low-speed operation mode, and resets when the power is not turned on. If so, the low-speed clock signal is supplied to the CPU as the system clock for the low-speed operation mode.

In the system clock switching circuit according to a second aspect of the present invention, the RC circuit provided as the identifying means smoothes the output waveform of the transient voltage between the resistance and the capacitance after the power is turned on. The flip-flop is identified as a reset after the power is turned on if the voltage level between the resistor and the capacitance at the time of reset release is lower than a certain voltage, and if the voltage level exceeds the certain voltage, it is a reset other than when the power is turned on. Then, a logic level signal representing the identification result is output.

[0019]

1 is a block diagram of a microcomputer system having a system clock switching circuit according to an embodiment of the present invention. As shown in the figure, this microcomputer system includes an external reset switch 1, a power supply voltage 2, a pull-up resistor 3, a capacitor 4, a Schmitt type inverter 5, a transistor switch 6, a power supply voltage detection unit 7, a system clock for low speed operation mode. A selection unit 8, a high-speed clock signal output unit 9, a low-speed clock signal output unit 10, a high-speed clock signal frequency divider 11, a CPU 12, and a timer 13 are provided. Further, 101 is a reset request signal, 102 is a reset signal, 103 is a self-reset signal by the CPU, 104 is a system clock selection signal for low speed operation mode, 105 is a high speed clock signal, 106 is a frequency division signal of a high speed clock signal, and 107 is The low-speed clock signal 108 is a system clock signal for the low-speed operation mode.

In the present microcomputer system, the parts other than the power supply voltage detection unit 7 are the same as those used in the microcomputer system described in the prior art, and therefore the description thereof will be omitted and the different points will be mainly described. To do. The power supply voltage detection unit 7 detects the power supply voltage and detects the power supply voltage when the reset is released, so that the power supply voltage detection unit 7 has a low level when the power is turned on and a high level when the reset is not performed. The mode system clock selection signal 104 is output to the low speed operation mode system clock selection unit 8.

The low-speed operation mode system clock selection unit 8 is different from FIG. 5 in that the low-speed operation mode system clock selection signal 104 is output from the power supply voltage detection unit 7. FIG. 2 shows a concrete configuration diagram of the present microcomputer system. As shown in the figure, the microcomputer system includes a D-flip-flop 20, a power supply voltage 21, a pull-up resistor 22, and a capacitor 23 as the power supply voltage detection unit 7. 209 is a power supply voltage monitor voltage.

The D-flip-flop 20 latches the power supply voltage monitor voltage 209 at the falling edge of the reset signal 102 when reset is released, and outputs it as the system clock selection signal 104 for low speed operation mode. The pull-up resistor 22 and the capacitor 23 blunt the rising waveform of the power supply voltage 21 and output it as the power supply voltage monitor voltage 209.

At this time, assuming that the input threshold voltage of the Schmitt inverter 5 and the input threshold voltage of the D input of the D-flip-flop 20 are the same, the pull-up resistor 3 and the capacitor 4 connected to the reset terminal are connected. It is necessary to set the time constant RC of the pull-up resistor 22 and the capacitor 23 to be larger than the time constant RC of. Regarding the system clock switching circuit of the present embodiment configured as described above,
The operation will be described below.

FIG. 3 shows an operation timing chart in the system clock switching circuit of this embodiment in the case of a reset at the time of power-on. In FIG. 3, (a) is a power supply voltage waveform,
(B) is the waveform of the reset request signal 101, (c) is the waveform of the reset signal 102, (d) is the waveform of the power supply voltage monitor voltage 209, and (e) is the waveform of the system clock selection signal 104 for low speed operation mode. .

When the power is turned on, the pull-up resistor 3 and the capacitor 4 generate a transient voltage (reset request signal 101) shown in FIG. 3B. Reset request signal 101
Of the reset signal 1 shown in FIG. 3 (c) until the voltage exceeds the input threshold voltage of the Schmitt type inverter 5.
02 is supplied to the CPU 12 and other circuit groups (not shown). When the reset request signal 101 exceeds the input threshold voltage of the Schmitt inverter 5, the reset is released and the reset signal 102 becomes low level. afterwards,
After the stable oscillation period of the high-speed clock signal 105, the CPU 1
2 starts operation. In the reset at power-on, the voltage value of the power supply voltage monitor voltage 209 latched by the falling edge of the reset signal 102 is less than the input threshold voltage of the D input of the D-flip-flop 20 (FIG. 3D). . As a result, the low-speed operation mode system clock selection signal 104 becomes low level as shown in (e) of FIG. 3, and the low-speed operation mode system clock selection unit 8 operates the divided signal 106 of the high-speed clock signal at low speed. It is output as the mode system clock signal 108.

Next, the operation in the case of a reset other than when the power is turned on will be described. FIG. 4 shows an operation timing chart in the system clock switching circuit of this embodiment in the case of a reset other than when the power is turned on. In FIG. 4, (a) is a power supply voltage waveform, and (b) is a reset request signal 1.
01 waveform, (c) waveform of reset signal 102,
(D) is a waveform of the power supply voltage monitor voltage 209, (e) is a waveform of the low-speed operation mode system clock selection signal 104, (f) is a self-reset signal 103 by the CPU 12.
Alternatively, it is an input waveform to the external reset switch 1 from a peripheral circuit other than the CPU 12. When (f) is at a high level, the external reset switch 1 or the transistor switch 6 is turned on.

The CPU 1 is in a state other than when the power is turned on.
2 or the input pulse to the external reset switch 1 from the peripheral circuit other than the CPU 12 is input in the waveform as shown in (f) of FIG. 4, the reset request signal 101 becomes The waveform is as shown in (b). The reset request signal 101 passes through the Schmitt type inverter 5 and has the waveform of the reset signal 102 shown in FIG. At this time, the reset signal 10
The power supply voltage monitor voltage 209 latched by the falling edge of 2 is already at the high level as shown in FIG. Therefore, the low-speed operation mode system clock selection signal 104 becomes high level as shown in FIG. 4E, and the low-speed clock signal 107 is output as the low-speed operation mode system clock signal 108.

As described above, it is possible to operate in the low-speed operation mode by the low-speed clock signal 107 which consumes less current, without shifting to the high-speed operation mode in which the power supply voltage may be lower than the guaranteed power supply voltage.

[0029]

According to the invention of claim 1, the low-speed clock signal 107 is selected as the system clock in the low-speed operation mode immediately after resetting at the time of resetting other than when the power is turned on. Since there is no transition to the operation mode, there is an effect that a malfunction does not easily occur.

According to the invention of claim 2, the effect of the invention of claim 1 can be realized with a simple structure.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a microcomputer system having a system clock switching circuit according to an embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a microcomputer system having a system clock switching circuit according to an embodiment of the present invention.

FIG. 3 is an operation timing chart at the time of power-on reset of the system clock switching circuit according to the embodiment of the present invention.

FIG. 4 is an operation timing chart of the system clock switching circuit according to the embodiment of the present invention at a reset other than when the power is turned on.

FIG. 5 is a configuration diagram of a microcomputer system having a conventional system clock switching circuit.

[Explanation of symbols]

1 External Reset Switch 2 Power Supply Voltage 3 Pull-up Resistor 4 Capacitance 5 Schmidt Inverter 6 Transistor Switch 7 Power Supply Voltage Detection Section 8 System Clock Selection Section for Low Speed Operation Mode 9 High Speed Clock Signal Output Section 10 Low Speed Clock Signal Output Section 11 High Speed Clock Signal Frequency divider 12 CPU 13 Timer 20 D-flip-flop 21 Power supply voltage 22 Pull-up resistance 23 Capacity 101 Reset request signal 102 Reset signal 103 Self-reset signal by CPU 12 104 System clock selection signal for low speed operation mode 105 High speed clock signal 106 High speed Frequency division signal of clock signal 107 Low speed clock signal 108 System clock signal for low speed operation mode 209 Power supply voltage monitor voltage 504 System clock selection signal for low speed operation mode

Claims (2)

[Claims] 1. A plurality of clock signals are switched to a CPU which has a low-speed operation mode operating with a low-speed clock signal and a high-speed operation mode operating with a high-speed clock signal, and starts operation in the low-speed operation mode immediately after resetting. It is a system clock switching circuit that is supplied as a power supply, and by detecting the power supply voltage when a reset occurs, it is possible to identify whether it is a reset at power-on or another reset, and power-on. If it is identified as a time reset, select the divided signal obtained by dividing the high-speed clock signal,
A system clock switching circuit comprising: selecting means for selecting a low-speed clock signal when it is identified as a reset other than that and supplying it to the CPU as a system clock signal for low-speed operation mode. 2. The identifying means is applied with a voltage at an RC circuit made up of a resistor and a capacitor connected in series with a power supply voltage, and a connection portion between the resistor and the capacitor, and takes in the voltage level at the time of reset release. 3. The system clock switching circuit according to claim 1, further comprising a flip-flop that outputs a logic level signal indicating the identification result.