KR100278279B1 - Clock generator having clock generating controller - Google Patents

Abstract

The present invention relates to a clock generator, and more particularly to a clock generator for controlling the start (UP-UP) of the clock generator.

In the present invention, the amplitude of the crystal oscillation is detected (detected) at two levels. That is, one is the amplitude at which it is determined that the crystal has reached a stable state, and the other is an amplitude sufficient for the crystal to drive a typical CMOS buffer. The present invention to implement such a clock generator, the oscillator; Clock generation means for receiving an output of the oscillator and generating a clock signal; And blocking the output of the oscillator from being input to the clock generating means in the power saving mode, and outputting the buffering means to the clock generating means after the output value of the oscillator is sufficiently stabilized in the operation mode. Clock generation control means.

Description

CLOCK GENERATOR HAVING CLOCK GENERATING CONTROLLER}

The present invention relates to a clock generator, and more particularly to a clock generator for controlling the start (UP-UP) of the clock generator.

As the technology of circuit integration advances, many devices are developed to be portable. In the design of portable devices, low power circuits are required for long battery life. In addition, existing devices also require low power to save energy.

Currently, a lot of efforts are being made to develop low power circuits, and one of the methods is to save power by switching to a power saving mode when the user does not use or the circuit does not operate.

In the power saving mode, the clock is stopped to freeze the operation of the circuit to maintain the standby state. There are a series of ways to exit this power saving mode. That is, when a signal is applied from the outside, it returns from the "power saving mode" to the "normal operation mode" in accordance with the signal. At this time, the stopped clock is operated again.

One of the problems in this process is the irregular operation of the clock. The clock mainly applies a voltage to the crystal and amplifies its fine oscillation to a CMOS level output.

Crystals show very unstable oscillation characteristics at the beginning of voltage application. Fig. 1 shows the operation of the crystal at the beginning of voltage application. As shown in the figure, the voltage is very unstable at the initial stage of voltage application and gradually stabilizes with time. At the beginning of voltage application, the amplitude is unstable, and thus the conventional method using only a general buffer results in a "missing" of the clock in the block A of the figure.

The circuit is in a constant state before entering the system's power saving mode. It stays in power saving mode, and when exiting power saving mode, returning to normal operation mode, and restarting, the system must start operation from the previous state. Since a system having a conventional clock generator does not maintain the full state in the "missing" part A, an operation that must operate from the state when entering the power saving mode even when the clock is supplied again causes a malfunction.

The following method is used to prevent the loss of state due to such "missing clock".

First, a method of converting a dynamic circuit into a static circuit in a system circuit. Since dynamic circuits are changed by the clock, they are changed to static circuits which are not affected by the clock. However, such a change causes a larger area of the static circuit than the dynamic circuit, resulting in an increase in the manufacturing cost by increasing the size of the overall chip. In addition, there is a problem that it is not easy to test whether all the dynamic circuits are changed to static.

Second, the system malfunction is delayed until the crystal is sufficiently stable. This method requires a control circuit for applying the system operation after the crystal operation is sufficiently stabilized even when returning from the power saving mode to the normal operation mode. In this case, there is a problem that a separate delay device must be added to the system to delay the operation of the system until the crystal settling time.

Disclosure of Invention The present invention devised to solve the above problems is to provide a clock generator capable of supplying a stable clock without missing or uninterrupted clock by controlling an unstable oscillation characteristic at the initial power-up of a crystal oscillator.

1A and 1B show an unstable output view of a crystal oscillator at the beginning of voltage application and an output waveform diagram of the buffer after the crystal output passes through a general CMOS buffer.

2 is a clock generation circuit diagram employing a clock generation controller according to the present invention.

3 is a block diagram of a clock generation controller according to an embodiment of the present invention.

4 is a block diagram of a clock generation controller according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: first level detector 12: second level detector

13, 42: counter 14, 43: AND gate

41: S-R flip-flop 50: Hysteresis buffer

Clock generator according to the present invention to achieve the above object, the oscillator; Clock generation means for receiving an output of the oscillator and generating a clock signal; And blocking the output of the oscillator from being input to the clock generating means in the power saving mode, and outputting the buffering means to the clock generating means after the output value of the oscillator is sufficiently stabilized in the operation mode. And a clock generation control means.

According to an aspect of the present invention, a clock generation control means includes: a first level detector for detecting whether an input from the oscillator reaches a level higher than a first level when converting from a power saving mode to a normal operation mode; If the first level detector detects that a level higher than the first level is input, the input is counted for a predetermined time, and if the first level detector detects an input lower than the first sensed level while the count is in progress. Counting means reset; A second level detector that detects whether the amplitude of the oscillation is of sufficient amplitude to drive a CMOS buffer and holds an output for a low input; And logic means for receiving the output of the counting means and the second level detector and providing the output buffered at the CMOS level to the clock generator.

In addition, the clock generation control means according to another aspect of the present invention comprises a circuit for detecting a level at which the input from the oscillator is stable and enabling the clock supply to the clock generator when the level is maintained for a certain period of time. It is characterized by.

In addition, the clock generation control means according to another aspect of the invention, the hysteresis buffer for outputting a buffered clock signal of the CMOS level for a predetermined voltage level or more in the operation mode; Counting means which starts counting by the clock signal of the hysteresis buffer and outputs high when the counting is performed by a predetermined number; And a flip-flop receiving a state mode signal, reset by an active signal of the counting means, and providing a control signal for operating the hysteresis buffer as a CMOS inverter.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

First, the characteristics of the crystal used as the oscillator, the crystal is stable oscillation only after sufficient time after applying the voltage. This means that the oscillation is stable only after the energy level inside the crystal reaches a constant state. Amplitudes are not constant until the energy levels are at a constant level, and even clocks can be interrupted. Once the crystal has been in constant oscillation for a certain time, it can be said that the crystal is in a stable state.

Therefore, the present invention implements the oscillation circuit so that the oscillation of the crystal is applied to the clock generator when the crystal enters a stable state, so that the clock generator can supply a stable clock without "missing clock" or disconnection of the clock to the system. do.

In other words, after a voltage is applied to the crystal, the amplitude of the crystal oscillation becomes a level sufficient to drive the CMOS buffer. However, the crystal oscillator at this time has not yet reached a stable level of state, and thus may exhibit unstable oscillation characteristics due to minute influences. Therefore, it is not appropriate to drive the clock generator at this time.

In the present invention, the amplitude of the crystal oscillation is detected (detected) at two levels. That is, one is the amplitude at which it is determined that the crystal has reached a stable state, and the other is an amplitude sufficient for the crystal to drive a typical CMOS buffer (the former is higher than the latter).

The counter starts counting when the amplitude of the crystal reaches the first sense level. If a voltage lower than the first sense level is detected during counting, the counter resets and waits for a voltage higher than the first sense level.

If the oscillation of the crystal is higher than the first level while the counter is counting a predetermined number of times, it can be considered that the crystal has entered a stable state.

2 shows a configuration of a clock generator according to the present invention.

As shown in the figure, the clock generator according to the present invention is provided between the buffer 2 and the clock generator 4 in addition to the conventional configuration consisting of the crystal oscillator 1, the buffer 2 and the clock generator 4. The clock generation controller 3 was added.

The oscillation of the crystal oscillator 1 is buffered in the crystal oscillator buffer 2 and the clock generation controller 3 is configured to provide a CMOS level clock to the clock generator 4 when a stable crystal oscillation enters the input.

The clock generator 4 receives a stable clock and generates a system clock required by the system. The signal coming out of the buffer 2 is a fine signal and the signal coming out of the clock generation controller 3 is at the CMOS level and the output from the clock generator 4 has sufficient drive capability to drive the system.

3 illustrates a detailed configuration of a clock generation controller according to an embodiment of the present invention, wherein the clock generation controller 3 includes a first level detector 11, a second level detector and a buffer 12, and a counter ( 13) and an AND gate 14.

The first level detector 11 checks the state of the current system from the power saving mode signal and detects whether the input of the crystal has reached a level higher than the first level when the current system switches from the power saving mode to the normal operation mode. Detection). If a high level is detected, a counter is allowed by the counter 13, and if an input lower than the detection level comes in while counting is in progress, the counter immediately resets and waits for an input higher than the detection level again.

The second level detector and buffer 12 converts the fine amplitude of the crystal oscillation into a CMOS level amplitude and senses a voltage lower than the second sense level. Inputs above the sense level are buffered and hold the output for low inputs.

At this time, the counter 13 starts counting by receiving the input of the first level detector 11 and is reset upon request of the first level detector 11. If a predetermined counting is made, a control signal is output to enable the supply of the output value of the second level detector and buffer 12 to the clock generator. That is, the AND gate 14 inputs the output of the counter 13 to provide the clock generator with the outbreak of the crystal buffered at the CMOS level.

That is, when the system exits from the power saving mode and converts to the normal operation mode, the first level detector 11 detects whether the input of the crystal oscillation reaches a predetermined level and counts when the predetermined level is reached. When the output of the crystal is maintained at a constant level for a predetermined time, the buffer 2 connected to the crystal oscillator 1 applies the output of the buffer, which is buffered in a stable state, to the clock generation controller 3. From then on, detection only detects signals below the second level.

4 illustrates a detailed configuration of a clock generation controller according to another embodiment of the present invention, wherein the clock generation controller includes a hysteresis buffer 50 including CMOS inverters P2, P3, N0, and N4; Control means 40 for enabling or disabling the hysteresis buffer 50, an SR flip-flop 41, a counter 42 and an AND gate 43 for selectively outputting the buffered clock. In the figure, P1 to P3 and P7 P10 represent PMOS transistors, and N0, N4, N5, N8 and N11 represent NMOS transistors, respectively.

When the power saving mode signal PWM is a logic "1", the buffered clock signal BUFFERED_CLOCK becomes a logic "0" by the NMOS transistor N5, and the clock enable signal CLOCK_ENABLE is also an SR flip-flop ( The logic " 0 "

When the PWDN signal becomes logic " 0 ", the PMOS transistor P1 is turned on so that the NMOS transistor N5 is turned off and enables the hysteresis buffer 50 to operate. For an input that is equal to or greater than the input potential of the hysteresis buffer 50, the hysteresis buffer 50 outputs a CMOS level output. This corresponds to the first level as described above in FIG.

The counter 42 starts counting by this output. When the counting is done by a predetermined number, the output of the counter is active high. The output of the active counter resets the SR flip-flop 41, and the clock enable signal is made high by the qn output terminal of the SR flip-flop 41 to clock the clock signal buffered through the AND gate 43. Output to the generator.

The NMOS transistor N11 and the PMOS transistor P10 are turned off by the q output terminal of the S-R flip-flop 41 to disable the feedback elements P7 and P8 of the hysteresis buffer 50. Since the feedback element is disabled, the hysteresis buffer 50 operates as a normal CMOS inverter. Because it operates as a CMOS inverter, the output of the inverter has the effect of sensing for crystal inputs below the CMOS input level. This corresponds to the second level as described above in FIG.

In another embodiment of the present invention, after the output of the counter is activated, it can be seen that the crystal input sensing level is changed from the first level to the second level.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention made as described above can ensure the smooth operation of the system to restart the operation from the previous state when returning to the normal operation mode after entering the power saving mode.

The circuit can be protected from unstable oscillation of the crystal at the beginning of power supply.

Claims (2)

oscillator; Clock generation means for receiving an output of the oscillator and generating a clock signal; And In the power saving mode, the output of the oscillator is blocked from being input to the clock generating means, and in the operation mode, the clock for outputting the buffering means to the clock generating means after the output value of the oscillator is sufficiently stabilized. It comprises a generation control means, The clock generation control means, A first level detector for detecting whether an input from the oscillator has reached a level higher than a first level when converting from a power saving mode to a normal operating mode; If the first level detector detects that a level higher than the first level is input, the input is counted for a predetermined time, and if the first level detector detects an input lower than the first sensed level while the count is in progress. Counting means reset; A second level detector that detects whether the amplitude of the oscillation is of sufficient amplitude to drive a CMOS buffer and holds an output for a low input; And Logic means for receiving the output of the counting means and the second level detector and providing an output buffered at CMOS level to the clock generator Clock generator comprising a. The method of claim 1, wherein the clock generation control means, A hysteresis buffer for outputting a CMOS level buffered clock signal for a predetermined or higher voltage level in an operating mode; Counting means which starts counting by the clock signal of the hysteresis buffer and outputs high when the counting is performed by a predetermined number; And A flip-flop that receives a status mode signal, is reset by an active signal of the counting means, and provides a control signal for operating the hysteresis buffer as a CMOS inverter Clock generator comprising a.

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