KR100554984B1 - Active voltage generator of semiconductor memory device - Google Patents

Abstract

The present invention provides a semiconductor memory device having an active voltage generator for preventing cell data loss in an active power-down mode and a driving method therefor. The present invention provides an active voltage generator for supplying a voltage in an active period. Way; And driving the active voltage generator during an active period in response to a low active signal and a precharge signal, and disabling the active voltage generator in an active power down mode in response to a clock enable signal to enter the active power down mode. However, the present invention provides an active voltage generator of a semiconductor memory device having drive control means for disabling the active voltage generation means after ensuring a minimum time for low activation.

Active operation, active power-down mode, current consumption, tRASmin, skew logic

Description

ACTIVE VOLTAGE GENERATOR OF SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram of an active voltage generator according to the prior art.

FIG. 2 is an internal circuit diagram of the driving control unit of FIG. 1. FIG.

3 is an operational waveform diagram of FIG. 1.

Figure 4 is a block diagram of an active voltage generator according to another prior art.

5 is an internal circuit diagram of the driving control unit of FIG. 4.

6 is an operational waveform diagram of FIG. 4.

7 is a block diagram of an active voltage generator according to the present invention.

8 is an operational waveform diagram of FIG. 7.

9 is an internal circuit diagram of the driving controller of FIG. 7;

10 is an internal circuit diagram of a delay unit of FIG. 9;

11 is an operational waveform diagram of FIG. 9.

* Description of the main parts of the drawing

100: drive control unit

200: active voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having an active voltage generator.

Generally, entering the power-down mode from the low active state is called the active power-down mode, and the current consumption is minimized at this time. In the specification, it is indicated as IDD3P. Entering the power-down mode is a state in which the clock enable signal (/ CKE) transitions from the logic value 'high' to 'low', and the clock enable signal (/ CKE) is again changed from the logic value 'low' to 'high'. The transition to 'is called a power-down exit.

1 is a block diagram of an active voltage generator according to the prior art.

Referring to FIG. 1, the active voltage generator generates an active voltage in an active period by inputting an active voltage generator 20 for supplying an active voltage, a low active signal row_actz and a precharge signal prcgz. The driving control unit 10 for driving the unit 20 includes an active period, that is, active voltage generation in the memory operation period until the low active signal row_actz is applied and the precharge signal prcgz is applied. It is configured to occur.

FIG. 2 is an internal circuit diagram of the driving control unit 10 of FIG. 1.

Referring to FIG. 2, the driving controller 10 includes an input unit 12 for inputting a precharge signal prcgz and a row active signal row_actz, and a latch 14 for latching an output signal of the input unit 12. And an inverter I2 for inverting the output signal of the latch 14 and outputting the output signal as the voltage generator driving signal Drv_Enz.

The input unit 12 inputs an inverter I1 for inverting the row active signal row_actz, a PMOS transistor PM1 having a precharge signal prcgz as a gate input, and an output signal of the inverter I1. An NMOS transistor NM1 is provided, and a PMOS transistor PM1 and an NMOS transistor NM1 are arranged in series between a power supply voltage and a ground voltage, and their connection nodes become output nodes.

On the other hand, referring to the operation waveform diagram of FIG. 3, it can be seen that the driving signal Drv_Enz is activated even in the active power-down mode (/ CKE is 'low' section). That is, even if the power-down mode is entered in the active state, the active voltage generator 20 operates unnecessarily.

As a result, since the active voltage generation value of FIG. 1 is not controlled by the clock enable signal / CKE and still consumes current in the active power-down mode, it has an adverse effect on the power-down mode to reduce current consumption.

Therefore, in the improved conventional technology, the clock enable signal / CKE is controlled so that the voltage generator driving signal Drv_Enz is inactivated in the active power-down mode period. A block diagram of a voltage generator.

Referring to FIG. 4, the active voltage generator includes an active voltage generator 20 for supplying an active voltage in an active period, a low active signal row_actz, a precharge signal prcgz, and a clock enable signal / CKE. A drive control unit 30 for driving control of the active voltage generator 20 in response to the ().

5 is an internal circuit diagram of the driving control unit 30 of FIG.

Referring to FIG. 5, the drive controller 30 includes a power down mode detector 34 further provided at an output side of the drive controller 10 of FIG. 2, and the power down mode detector 34 is a clock. In response to the enable signal / CKE, the voltage generator driving signal Drv_Enz is deactivated and output in the power-down mode.

The power down mode detector 34 inputs an inverter I3 for inverting the clock enable signal / CKE, an output signal of the inverter I3, and an output signal of the section detection unit 32 as inputs. Inverter I4 is used to invert the output signal of the gate NR1 and the NOR gate NR1 and output the inverted signal as the voltage generator driving signal Drv_Enz.

FIG. 6 is an operation waveform diagram of the block of FIG. 4, and with reference to this, the operation of the active voltage generator in the active power down mode will be described.

First, when the row active signal row_actz is activated, the driving controller 30 activates the voltage generator driving signal Drv_Enz in response to the active signal generator 20. Subsequently, when the clock enable signal / CKE is activated to enter the power down mode, the driving controller 30 deactivates the voltage generator driving signal Drv_Enz to turn off the active voltage generator 20. After the clock enable signal / CKE is deactivated, the driving controller 30 reactivates the voltage generator driving signal Drv_Enz so that the active voltage generator 20 is driven. Thereafter, when the precharge signal prcgz is activated, the voltage generator driving signal Drv_Enz is inactivated again.

As described above, the driving controller 30 senses the power down mode and directly applies the active voltage generator 20 to the active voltage generator 20 to reduce the current consumption by preventing the active voltage generator 20 from being driven.

However, in the case of using the improved conventional technology, even if the power-down mode (/ CKE is 'low') is not satisfied after the active (row_actz is 'low') tRASmin, the driving controller 30 immediately activates the active voltage generator. Since cell 20 is not driven, cell data is lost. That is, the minimum time for the cell data to be stably secured because the low active signal is applied and the process of sensing and amplifying the memory cell data of the selected word line is completed. In this situation, the clock enable signal is not satisfied. When (/ CKE) is applied, the memory cell data of the selected word line is lost because the active voltage generator 20 does not supply the active voltage.

The present invention has been proposed to solve the problems of the prior art as described above, and provides an active voltage generator of a semiconductor memory device for preventing cell data loss in the active power-down mode.

According to the present invention for achieving the above technical problem, the active voltage generator of the semiconductor memory device comprises an active voltage generating means for supplying a voltage in the active period; And driving the active voltage generator during an active period in response to a low active signal and a precharge signal, and disabling the active voltage generator in an active power down mode in response to a clock enable signal to enter the active power down mode. Even if it is provided with a drive control means for disabling the active voltage generating means after ensuring a minimum time for low active.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

7 is a block diagram of an active voltage generator according to the present invention.

Referring to FIG. 7, the active voltage generator generates an active voltage during an active period in response to an active voltage generator 200 for supplying a voltage in an active period, a low active signal row_actz and a precharge signal prcgz. Minimum time for driving the unit 200 and disabling the active voltage generator 200 in the active power down mode in response to the clock enable signal / CKE, even if the active power down mode is entered. After driving (tRASmin) is provided with a drive control unit 100 for disabling the active voltage generator 200.

FIG. 8 is an operation waveform diagram of the block of FIG. 7, and with reference to this, the operation of the active voltage generator in the active power down mode according to the present invention will be described.

First, when the row active signal row_actz is activated, the driving controller 100 activates the voltage generator driving signal Drv_Enz to drive the active voltage generator 200 in response thereto. Subsequently, even when the power-down mode is entered (/ CKE is 'low') without satisfying the tRASmin, the driving controller 100 satisfies tRASmin internally and then deactivates the voltage generator driving signal Drv_Enz, thereby causing the active voltage generator to operate. Do not allow 200 to be driven. Subsequently, when the power-down mode exits (/ CKE is 'high'), the driving controller 100 immediately activates the voltage generator driving signal Drv_Enz so that the active voltage generator 200 is driven.

As described above, the present invention guarantees tRASmin in the driving controller 100 even after entering the active power-down mode without satisfying tRASmin, thereby deactivating the voltage generator driving signal Drv_Enz, thereby ensuring that the low active operation is completed normally. do.

For reference, all the above signals are low active signals.

9 is a circuit diagram illustrating an example of the drive control unit 100 of FIG. 7.

Referring to FIG. 9, the driving controller 100 receives a low active signal row_actz and a precharge signal prcgz, detects an active period, and generates an active period signal act_node. In response to the active section signal act_node, the row active driving guarantee unit 140 generates a driving guarantee signal node having information related to the minimum time for activating the row, and the active section signal act_node and driving. In response to the guarantee signal (node) and the clock enable signal (/ CKE), the voltage generator is activated in the active section and deactivated in the power-down mode section, but is inactivated after ensuring the minimum time tRASmin for low active. An output unit 160 for generating a signal Drv_Enz is provided.

Specifically, the active section detecting unit 120 is disposed in series between the inverter I5 for inverting the row active signal row_actz, the power supply voltage and the ground voltage, and the precharge signal prcgz and the inverter I5. A signal generator 122 implemented with a PMOS transistor PM2 and an NMOS transistor NM2 having an output signal as its gate input, a latch 124 for latching an output signal of the signal generator 122; An inverter I6 for inverting the signal of the latch 124 and outputting it as an active period signal act_node is provided.

The low active driving guarantee unit 140 includes a delay unit 142 for delaying the active section signal act_node for tRASmin and outputting it as an active driving guarantee signal node. An internal circuit diagram of the guarantee unit 140 is shown.

Referring to FIG. 10, the low active driving guarantee unit 140 is a skew logic circuit implemented as a delay element of an inverter and a capacitor. When the active section signal act_node transitions from a logic high to a low The delay amount is longer than the delay amount when the transition from 'low' to 'high'.

Therefore, when the active section signal act_node transitions from the logic value 'high' to 'low', that is, when the active section signal enters the active section, the active section signal act_node is delayed by tRASmin to deactivate the active driving guarantee signal node. By outputting, even if the power-down mode is entered without satisfying tRASmin, the active voltage generator 200 is turned off after tRASmin. In addition, when the active section signal act_node transitions from the logic value 'low' to 'high', it is at the time of exiting the active section so that the input active section signal act_node has a minimum delay so that the active driving guarantee signal node Output as.

In addition, the output unit 160 inverts the output signal of the NAND gate ND1 and the NAND gate ND1 having the active section signal act_node and the active driving guarantee signal node as input signals to the driving signal en. Inverter I7 for output, NOR gate NR2 having a clock enable signal / CKE and an active drive guarantee signal node as inputs, an output signal and a drive signal en of NOR gate NR2. NOR gate NR3 having an input as an input, and an inverter I8 for inverting the output signal of the NOR gate NR3 to output the voltage generator drive signal Drv_Enz.

The NOR gate NR2 is a means for sensing the power down mode and controlling the voltage generator driving signal Drv_Enz. Unlike the conventional method, the NOR gate NR2 is a voltage generator driving signal during tRASmin even in a power down mode by an active driving guarantee signal node. Drv_Enz) is activated.

FIG. 11 is an operation waveform diagram of the circuit of FIG. 9 and looks at the operation of an active voltage generator in an active power-down mode with reference to this.

Referring to FIG. 11, the active section detection unit 120 is activated when the low active signal row_actz is applied and enters the active mode, and is activated when the precharge signal prcgz is activated and deactivated when the active mode ends. act_node). The low active driving guarantee unit 140 generates a driving guarantee signal node by delaying the active section signal act_node by tRASmin. The drive signal en is output by the NAND gate ND1 and the inverter I7 of the output unit 160, and the clock enable signal / CKE is 'low' by the NOR gate NR2, so that the power-down mode When entering, the voltage generator driving signal Drv_Enz is deactivated, but when the driving guarantee signal node is still high, the voltage generator driving signal Drv_Enz is activated even when the clock enable signal / CKE is at a low level. .

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

When the low active signal is applied, the above-described present invention generates an active driving guarantee signal which is delayed by tRASmin. Therefore, even when the clock enable signal is applied without entering tRASmin and enters the power-down mode, the active driving guarantee signal having the information of the tRASmin is used without applying it directly to the voltage generator driving signal. Operation by signal is guaranteed to prevent loss of cell data.

Claims (7)

delete Active voltage generating means for supplying a voltage in an active section; And In response to a low active signal and a precharge signal, the active voltage generating means is driven during an active period and the active voltage generating means is disabled in an active power down mode in response to a clock enable signal. And driving control means for disabling the active voltage generating means after ensuring a minimum time for low activation even when entering. The drive control means, An active section detection unit configured to generate an active section signal by sensing the active section by receiving the low active signal and the precharge signal; A row active driving guarantee unit configured to generate an active driving guarantee signal having information related to a minimum time for activating a row in response to the active section signal; And And an output unit for outputting a driving control signal for controlling driving of the active voltage generating means in response to the active section signal, the active driving guarantee signal, and the clock enable signal. Device. The method of claim 2, The active section detection unit, And generating the active period signal that is activated when the low active signal is activated and deactivated when the precharge signal is activated. The method of claim 2, The active section detection unit, A first inverter for inverting the low active signal; A PMOS transistor and an NMOS transistor connected in series between a power supply voltage and a ground voltage and having the precharge signal and the output signal of the first inverter as their respective gate inputs; A latch connected to a connection node of the PMOS transistor and an NMOS transistor to latch a signal of the connection node; And A second inverter inverting the output signal of the latch and outputting the signal as an active section signal; The active voltage generator of the semiconductor memory device, characterized in that implemented as. The method of claim 2, And the low active driving guarantee unit comprises delay means for delaying the active period signal by a minimum time for low active and outputting the active driving signal as the active driving guarantee signal. The method of claim 5, The delay means is a skew logic that delays the time when the active section signal transitions to activation by the minimum time and relatively less delays the time when the active section signal transitions by deactivation of the active section signal. Voltage generator. The method of claim 2, The output unit, A NAND gate having the active period signal and the active driving guarantee signal as an input, a first inverter for inverting and outputting an output signal of the NAND gate, the clock enable signal and the active driving guarantee signal as inputs A second NOR gate having a first NOR gate, an output signal of the first NOR gate and the first inverter as an input, and a second inverter that inverts an output signal of the second NOR gate and outputs a driving control signal. What is implemented An active voltage generator of a semiconductor memory device, characterized in that.

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