JPH0992763A - Punching process method for lead frame - Google Patents

Punching process method for lead frame

Info

Publication number
JPH0992763A
JPH0992763A JP24420995A JP24420995A JPH0992763A JP H0992763 A JPH0992763 A JP H0992763A JP 24420995 A JP24420995 A JP 24420995A JP 24420995 A JP24420995 A JP 24420995A JP H0992763 A JPH0992763 A JP H0992763A
Authority
JP
Japan
Prior art keywords
lead frame
punched
plating
burrs
punching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24420995A
Other languages
Japanese (ja)
Inventor
Motoya Ishida
基哉 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP24420995A priority Critical patent/JPH0992763A/en
Publication of JPH0992763A publication Critical patent/JPH0992763A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of a burrs at flattening process even when cracks and burrs of plating occur at a punched end surface part of a lead frame for a transistor. SOLUTION: A lead frame material with plating is punched into a specified form. When a part of a punched end surface part 4 of the punched lead frame is flattened, flattening process of chamfer is performed in advance for forming a chamfer 11. The flattening process for raising adhesion-property of the mold resin is performed on the punched end surface part 4 after the chamfer flattening process, for forming a flattening 5. By this, occurrence of burrs on the edge of the flatting 5 due to the teared plating 7 is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はリードフレームの打
抜き加工方法に係り、特に打抜き後に行われる端面部の
処理技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for punching a lead frame, and more particularly to a technique for processing an end face portion after punching.

【0002】[0002]

【従来の技術】リードフレーム、例えばパワトランジス
タ用リードフレーム(特にTO−220、TO−3Pタ
イプ)では、図2のように、抜き端面部4の一部、例え
ばトランジスタチップが搭載されるヘッダ部1のヘッダ
端面2や、トランジスタ取付用のビス孔部3に、モール
ド樹脂の食い付き性を高めるために、平つぶし加工を施
して平つぶし5を形成するものが多い。従来、この平つ
ぶし加工は、トランジスタ用リードフレームの打抜きを
行った後に直接行っていた。なお、リードフレームの母
材6の表面には通常めっき7が施されている。
2. Description of the Related Art In a lead frame, for example, a power transistor lead frame (particularly TO-220, TO-3P type), as shown in FIG. 2, a part of the extraction end surface portion 4, for example, a header portion on which a transistor chip is mounted is mounted. In many cases, the flat end 5 is formed on the header end face 2 of No. 1 and the screw hole 3 for mounting the transistor in order to improve the biting property of the mold resin. Conventionally, this flattening process has been performed directly after punching a lead frame for a transistor. The surface of the base material 6 of the lead frame is usually plated.

【0003】[0003]

【発明が解決しようとする課題】表面にめっきを施した
トランジスタ用リードフレーム材を打ち抜いてトランジ
スタ用リードフレームを製造するが、従来のように抜き
を行った後に直接平つぶし加工を行うと、次のような不
具合が発生しやすかった。
A lead frame material for a transistor having a plated surface is punched out to manufacture a lead frame for a transistor. When the flattening process is performed directly after punching as in the conventional case, It was easy for problems such as

【0004】図1(a)に示すように、打ち抜かれた後
の材料には、微小なバリ8が発生するが、バリ8の近傍
では材料の変形が大きいため、表面のめっき7にクラッ
ク9が入りやすい。このクラック9は、特にニッケル等
の硬いめっき材に顕著に見られる。バリ8の部分は強度
的に弱いため、その後、抜き端面部4に直接平つぶし加
工を施すと、図3に示すように、めっき7がちぎれてヒ
ゲバリ10が発生する。
As shown in FIG. 1 (a), minute burrs 8 are generated in the material after punching, but since the material is largely deformed in the vicinity of the burrs 8, cracks 9 are formed in the plating 7 on the surface. Is easy to enter. The crack 9 is particularly noticeable in a hard plated material such as nickel. Since the burr 8 portion is weak in strength, if the punched end face portion 4 is directly flattened thereafter, the plating 7 is torn and a whisker burr 10 is generated as shown in FIG.

【0005】ヒゲバリ10は、実装工程中等に脱落する
と、電気回路のショートにつながり、最終製品にて制御
系の誤動作の原因となるため、大変危険な不良である。
しかし、リードフレームの製造過程において、ヒゲバリ
発生の原因となるめっきのクラック9及びバリ8を皆無
にすることは非常に困難である。
The whisker 10 is a very dangerous defect because if it falls off during the mounting process or the like, it will lead to a short circuit in the electric circuit and cause a malfunction of the control system in the final product.
However, in the manufacturing process of the lead frame, it is very difficult to eliminate the plating cracks 9 and burrs 8 that may cause whiskers.

【0006】本発明の目的は、上述した従来技術の問題
点を解消して、めっきのクラック、バリが発生してもヒ
ゲバリの発生を抑えることが可能なリードフレームの打
抜き加工方法を提供することにある。
An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a lead frame punching method capable of suppressing the occurrence of whiskers even when cracks and burrs of plating occur. It is in.

【0007】[0007]

【課題を解決するための手段】本発明のリードフレーム
の打抜き加工方法は、めっき付きリードフレーム材を所
定形状に打抜き、打抜かれたリードフレームの端面部に
面取りのつぶし加工を施すものである。
According to the method of punching a lead frame of the present invention, a plated lead frame material is punched into a predetermined shape, and an end face portion of the punched lead frame is subjected to chamfering crushing.

【0008】また、本発明のリードフレームの打抜き加
工方法は、めっき付きリードフレーム材を所定形状に打
抜き、打抜かれたリードフレームの端面部の平つぶし加
工を行う部分に面取りのつぶし加工を施し、この面取り
つぶし加工を施した端面部に、モールド樹脂の食い付き
性を高めるための平つぶし加工を行うものである。
Further, the lead frame stamping method of the present invention is such that a plated lead frame material is stamped into a predetermined shape, and the end face portion of the stamped lead frame is flattened, and chamfering is performed. The flattening process for improving the biting property of the mold resin is performed on the end face portion subjected to the chamfering process.

【0009】これらの場合、面取りのつぶし加工の角度
を10°≦θ≦60゜とすることが、ヒゲバリを有効に
解消することができる。
In these cases, the beveling can be effectively eliminated by setting the angle for chamfering crushing to 10 ° ≦ θ ≦ 60 °.

【0010】[0010]

【発明の実施の形態】以下に本発明の実施の形態を図面
を用いて詳細に説明する。従来と同様に、TO−22
0、TO−3Pタイプなどのめっき付きパワトランジス
タ用リードフレーム材を所定形状に打抜いて、パワトラ
ンジスタ用リードフレームを製造する。すると、図1
(a)に示すように、打ち抜かれた後の材料には、微小
なバリ8が発生するが、バリ8の近傍では材料の変形が
大きいため、表面のめっき7にクラック9が入りやすい
ことは前述した通りである。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. As in the past, TO-22
The lead frame material for power transistors, such as 0 and TO-3P type, is punched into a predetermined shape to form a lead frame material for power transistors. Then, Figure 1
As shown in (a), minute burrs 8 are generated in the material after punching, but since the material is largely deformed in the vicinity of the burrs 8, cracks 9 are easily formed in the plating 7 on the surface. As described above.

【0011】平つぶし加工のとき発生するヒゲバリは、
強度的に弱いバリ8の部分にクラック9の入っためっき
7が載っていることが発生原因である。したがって、本
実施の形態では、抜きを行った後、平つぶし加工を施す
前に、図1(b)に示すように、バリ部に角面取りのつ
ぶし加工を施して、角面取り11を形成する。このよう
な角面取りつぶし加工によって、バリ8及びクラック9
のはいっためっき12を母材6の中に埋め込み、強度的
に弱い部分を排除し、その後の平つぶし加工によるめっ
きのちぎれを防止している。
The burrs that occur during flattening are
The cause is that the plating 7 having the cracks 9 is placed on the burr 8 where the strength is weak. Therefore, in the present embodiment, after punching and before flattening processing, as shown in FIG. 1B, the chamfering processing of square chamfering is performed on the burrs to form the square chamfering 11. . Burrs 8 and cracks 9 are formed by such a corner surface cutting process.
The plated plating 12 is embedded in the base material 6 to eliminate a portion having weak strength, and to prevent the plating from breaking due to the flattening process thereafter.

【0012】したがって、この角面取りつぶし加工を施
した抜き端面部に、平つぶし加工を施して平つぶし5を
形成しても、図1(c)に示すように、ヒゲバリの発生
のない製品が得られる。実際に、現在のところ、角面取
りつぶしによるヒゲバリ発生は見つかっていない。
Therefore, even if the flattened 5 is formed by flattening the end face portion that has been subjected to the flattening process of the corner surface, as shown in FIG. can get. In fact, at present, the occurrence of whiskers due to the scraping of the corner has not been found.

【0013】このように、めっき付きのトランジスタ用
リードフレームの抜き端面部に平つぶし加工を入れる
際、予め抜き端面部に角面取りつぶし加工を施すように
したので、ヒゲバリの発生を有効に防止できる。
As described above, when the flattening process is applied to the punched end face portion of the plated lead frame for a transistor, the punched end face portion is subjected to the square face squashing process in advance, so that the occurrence of whiskers can be effectively prevented. .

【0014】特に本発明は、図2に示すように、パワト
ランジスタ用リードフレームのヘッダ部1において、C
u合金の母材6にニッケルめっき7を施した材料に、ヘ
ッダ端面2、ビス孔部3に平つぶしを加工する場合に有
効である。
Particularly, according to the present invention, as shown in FIG. 2, in the header portion 1 of the lead frame for power transistor, C
This is effective when flattening the header end face 2 and the screw hole portion 3 in a material obtained by nickel-plating the base material 6 of the u alloy.

【0015】ところで、角面取りのつぶし加工の角度θ
は、バリ8及びクラック9のはいっためっきを母材6に
埋め込むという点から10゜を下限とし、また、角度が
きつ過ぎるとかえってバリ8を削り取ってしまうため6
0゜を上限とする。
By the way, the angle θ of the crushing process of the chamfer
Has a lower limit of 10 ° from the viewpoint of embedding the plating with burrs 8 and cracks 9 in the base material 6, and if the angle is too tight, the burrs 8 will be scraped off.
The upper limit is 0 °.

【0016】なお、抜きだけでもめっきヒゲバリが発生
する場合もあるので、平つぶし加工を施さない抜き端面
部でも角面取りつぶし加工は有効である。また、本発明
はトランジスタ用リードフレームに限定されず、めっき
が施されたリードフレームであればよく、例えばIC用
リードフレームにも適用できる。
[0016] In addition, since the plating mustaches may be generated only by the punching, the square face shaving process is effective even for the punched end face portion which is not flattened. Further, the present invention is not limited to the lead frame for transistors, and may be any lead frame that is plated, and may be applied to, for example, an IC lead frame.

【0017】[0017]

【発明の効果】請求項1に記載の発明によれば、打抜か
れた端面部に面取りのつぶし加工を施すので、抜きだけ
でめっきヒゲバリが発生するような場合でも、ヒゲバリ
を解消することができ、ヒゲバリによるショートを防止
できる。
According to the invention as set forth in claim 1, since the punched end face is subjected to a crushing process for chamfering, it is possible to eliminate the whisker even when the plating mustache is generated only by punching. It can prevent short circuit due to beard.

【0018】請求項2に記載の発明によれば、打抜き後
平つぶし加工の際に、抜き端面部にあらかじめ面取りつ
ぶし加工を行うようにしたので、抜き端面部にめっきの
クラックやバリが発生しても、めっきヒゲバリの発生を
有効に防止できる。
According to the second aspect of the present invention, when the flattening process is performed after the punching, the chamfering process is performed in advance on the punched end face portion, so that cracks and burrs of plating occur on the punched end face portion. However, it is possible to effectively prevent the occurrence of plating burrs.

【0019】請求項3に記載の発明によれば、面取りの
つぶし加工の角度を10°≦θ≦60゜としたので、バ
リを削り取ることなく母材に埋め込むことができる。
According to the invention described in claim 3, since the angle of the chamfering crushing process is 10 ° ≦ θ ≦ 60 °, the burr can be embedded in the base material without scraping.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のリードフレームの打抜き加工方法の実
施の形態を示す工程図であって、(a)は打抜き後のバ
リ付近を示す材料の断面図、(b)バリ部の面取りつぶ
し加工を施した材料の断面図、(c)は平つぶし加工を
行った材料の断面図である。
FIG. 1 is a process diagram showing an embodiment of a lead frame punching method of the present invention, in which (a) is a sectional view of a material showing the vicinity of a burr after punching, and (b) a chamfering process of a burr part. FIG. 3C is a cross-sectional view of the material subjected to the flattening process, and FIG.

【図2】本発明の実施の形態と従来例とに共通した代表
的なパワトランジスタ用リードフレームの斜視図であ
る。
FIG. 2 is a perspective view of a typical lead frame for power transistor, which is common to the embodiment of the present invention and the conventional example.

【図3】従来例の平つぶし加工を行った後のヒゲバリの
発生状態を示す材料の断面図である。
FIG. 3 is a cross-sectional view of a material showing a state of occurrence of whiskers after performing a flattening process of a conventional example.

【符号の説明】[Explanation of symbols]

4 端面部 5 平つぶし 6 母材 7 めっき 8 バリ 9 クラック 11 面取り 12 クラックの入っためっき 4 End face 5 Flattened 6 Base metal 7 Plating 8 Burr 9 Crack 11 Chamfering 12 Cracked plating

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】めっき付きリードフレーム材を所定形状に
打抜き、打抜かれたリードフレームの端面部に面取りの
つぶし加工を施したリードフレームの打抜き加工方法。
1. A method for punching a lead frame, wherein a lead frame material with plating is punched into a predetermined shape, and the end surface of the punched lead frame is chamfered.
【請求項2】めっき付きリードフレーム材を所定形状に
打抜き、打抜かれたリードフレームの端面部の平つぶし
加工を行う部分に面取りのつぶし加工を施し、この面取
りつぶし加工を施した端面部に、モールド樹脂の食い付
き性を高めるための平つぶし加工を行うリードフレーム
の打抜き加工方法。
2. A lead frame material with plating is punched into a predetermined shape, and the flattened portion of the punched lead frame is chamfered, and the chamfered end surface is subjected to chamfering. A lead frame punching method that performs flattening to improve the biteability of the mold resin.
【請求項3】面取りのつぶし加工の角度を10°≦θ≦
60゜とした請求項1または2に記載のリードフレーム
の打抜き加工方法。
3. The angle of chamfering crushing is 10 ° ≦ θ ≦
The lead frame punching method according to claim 1, wherein the lead frame is 60 °.
JP24420995A 1995-09-22 1995-09-22 Punching process method for lead frame Pending JPH0992763A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24420995A JPH0992763A (en) 1995-09-22 1995-09-22 Punching process method for lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24420995A JPH0992763A (en) 1995-09-22 1995-09-22 Punching process method for lead frame

Publications (1)

Publication Number Publication Date
JPH0992763A true JPH0992763A (en) 1997-04-04

Family

ID=17115390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24420995A Pending JPH0992763A (en) 1995-09-22 1995-09-22 Punching process method for lead frame

Country Status (1)

Country Link
JP (1) JPH0992763A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000082770A (en) * 1998-06-11 2000-03-21 Internatl Rectifier Corp Housing of large current capacity semiconductor device
KR100479911B1 (en) * 1997-08-05 2005-09-30 삼성테크윈 주식회사 Apparatus for rvemoving burr of lead frame
US7174626B2 (en) * 1999-06-30 2007-02-13 Intersil Americas, Inc. Method of manufacturing a plated electronic termination

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479911B1 (en) * 1997-08-05 2005-09-30 삼성테크윈 주식회사 Apparatus for rvemoving burr of lead frame
JP2000082770A (en) * 1998-06-11 2000-03-21 Internatl Rectifier Corp Housing of large current capacity semiconductor device
US7174626B2 (en) * 1999-06-30 2007-02-13 Intersil Americas, Inc. Method of manufacturing a plated electronic termination

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