JPH0992659A - Hetero junction bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable hetero junction bipolar transistor(HBT) with a III-V group compound semiconductor. SOLUTION: Un-doped polycrystal or polycrystal with impurity density of 1×10<16> /cm<3> or below is used for an emitter mesa side-wall film 7. The polycrystal includes a III-V group compound semiconductor of 90% or above, which is the same material as a highly doped p-type base layer 4. Then, a side wall of an emitter layer made up of an n-type wide gap semiconductor layer 5 and a highly doped n-type semiconductor layer 6 has the same coefficient of thermal expansion as a base layer 4, and at the same time the side wall is coated with side-wall film 7 having high resistivity of 1MΩcm or above. Since the stress remaining in the base layer 4 becomes substantially zero, a III-V group compound semiconductor HBT with a very small change in characteristics caused by electrical continuity can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor (HBT), and more particularly to an HBT made of a III-V group compound semiconductor with improved reliability.

[0002]

2. Description of the Related Art Conventionally, as this type of III-V compound semiconductor HBT, a transistor having a sectional structure shown in FIG. 2 is known. In FIG. 2, reference numeral 1 indicates a semiconductor substrate on which a highly doped n-type semiconductor layer 2, an n-type semiconductor layer 3 serving as a collector layer, a highly-doped p-type semiconductor layer 4 serving as a base layer, and an emitter are provided. The n-type wide-gap semiconductor layer 5 and the highly-doped n-type semiconductor layer 6 that are layers are stacked. A collector electrode 10 is provided on the highly-doped n-type semiconductor layer 2, and an emitter electrode 8 is provided on the highly-doped n-type semiconductor layer 6. Emitter layer 5,
6 is mesa-etched, and SiO 2 is formed on the side wall of the emitter mesa.
_An insulating film side wall 11 made of ₂ or the like is provided. Furthermore,
A base electrode 9 is provided on the highly-doped p-type semiconductor layer 4,
The base electrode 9 is different from the emitter layers 5 and 6 in the insulating film side wall 1.
1 are provided.

As described above, the isolation between the emitter mesa side wall and the base extraction electrode in the conventional HBT is as follows.
This has been done using the insulating film side wall 11 made of SiO ₂ or the like. Regarding the HBT having the above structure, for example, IEE Transactions on Electron Devices Vol. 35 (1988)
Pp. 1771-p. 1777 (IEEE Transactions on El
ectron Devices Vol.35 (1988) pp.1771-1777).

[0004]

However, according to the above-mentioned prior art HBT, the Si on the side wall of the emitter mesa is formed.
The thermal expansion coefficient of the insulating film side wall 11 made of O _{2 and the} like, III-V
Since the thermal expansion coefficient of the base layer semiconductor 4 made of a group compound semiconductor is different by nearly one digit, the base layer semiconductor 4 contains several tens of M
The stress of Pa remained, causing a problem in the reliability of HBT. Here, as an example, an AlGaAs / GaAs HBT using carbon as a p-type impurity of the base layer 4 is taken,
The problem of element reliability in the related art will be described.

FIG. 3 (a) shows current-voltage characteristics before and after an energization test for the carbon-doped AlGaAs / GaAs HBT according to the prior art shown in FIG. HBT used
Has an emitter area of 2 × 10 μm ² , and the conditions of the energization test are an emitter current of 24 mA, a substrate temperature of 180 ° C., and an energization time of 5 hours. As can be seen from FIG. 3 (a),
While the collector current did not change before and after energization, the base current increased significantly by energization. This means that the grounded-emitter current amplification factor, which is defined by the ratio of the collector current to the base current, is reduced by energization, which has been a great obstacle to the practical application of the HBT and a circuit using the HBT.

Therefore, an object of the present invention is to provide a heterojunction bipolar transistor made of a III-V group compound semiconductor, which is designed to improve reliability without reducing the grounded-emitter amplification factor even when conducting an energization test. It is in.

[0007]

In order to achieve the above object, a heterojunction bipolar transistor according to the present invention is provided with a base layer, an emitter layer provided on the base layer, and an emitter layer provided on the base layer. In a heterojunction bipolar transistor composed of a collector layer
The emitter layer is characterized in that the periphery of the side surface of the emitter layer is deposited by a polycrystal containing 90% or more of the same material as the base layer and having an impurity concentration of 1 × 10 ¹⁶ / cm ³ or less including undoped. To do. That is, as shown in FIG. 1, the above object is to obtain a high resistivity containing 90% or more of the same material as the highly doped p-type semiconductor layer 4 constituting the base layer as the sidewall film formed on the sidewalls of the emitter layers 5 and 6. It is achieved by using the polycrystalline semiconductor 7 of. The high-resistivity polycrystalline semiconductor 7 is an undoped polycrystalline semiconductor having an impurity concentration of 1 × 10 ¹⁶ / cm ³ or less. still,
In FIG. 1, the same components as those of the conventional example shown in FIG. 2 are designated by the same reference numerals.

In the HBT, the base layer, the emitter layer and the collector layer are single crystals made of III-V group compound semiconductors. Here, the single crystal made of a III-V group compound semiconductor includes a mixed crystal of a III-V group compound, for example, a single crystal made of Al _0.1 Ga _0.9 As. In this case, it is preferable that the base layer has p-type conductivity and carbon is included as an impurity, and the emitter layer is preferably AlGaAs having n-type conductivity.

The emitter layer has n-type conductivity and may be composed of three layers of AlGaAs, InGaAs and AlGaAs, or may be composed of one layer of InGaP.

Further, the heterojunction bipolar transistor according to the present invention is a heterojunction bipolar transistor composed of a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer. It is characterized in that the material that covers the side surface of the emitter layer and the material that constitutes the base layer have the same coefficient of thermal expansion.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The heterojunction bipolar transistor according to the present invention uses, as a sidewall film for isolation from the base electrode provided on the sidewall of the emitter mesa, 90% or more of a III-V group compound semiconductor made of the same material as the base layer. Containing undoped or impurity concentration of 1 × 10 ¹⁶ / cm ³
The following polycrystals are used. As a result, a sidewall film having a high resistivity can be obtained. This is because an undoped or polycrystalline III-V compound semiconductor with an impurity concentration of 1 × 10 ¹⁶ / cm ³ or less can easily obtain a high resistivity of 1 MΩcm or more. Moreover, since the side wall film using this polycrystalline III-V group compound semiconductor has almost the same thermal expansion coefficient as that of the base layer semiconductor, the residual stress in the base layer semiconductor becomes substantially zero, and high reliability is ensured. It is possible to realize the III-V group compound semiconductor HBT having. Even if the material of the side wall film of the emitter mesa is not the same as the material of the base layer semiconductor material, if the coefficient of thermal expansion of the side wall film and that of the base layer semiconductor material match within an error of 10%, the reliability of the HBT is substantially high. There is no problem.

[0012]

EXAMPLES Specific examples of the heterojunction bipolar transistor according to the present invention will be described below in detail with reference to the accompanying drawings.

<Embodiment 1> FIGS. 4 to 8 are longitudinal sectional structural views showing an embodiment of a heterojunction bipolar transistor according to the present invention, in which carbon-doped AlGaAs / GaA.
It is the figure which showed the manufacturing process of HBT using s in order.

First, referring to FIG. 4, undoped GaAs
A highly doped n-type GaAs layer 22 (impurity Si, electron concentration 5 × 10 ¹⁸ / cm ³ , film thickness 0.5 μm), n-type GaA is formed on a (100) substrate 21 by a molecular beam epitaxy method.
s layer 23 (impurity Si, electron concentration 5 × 10 ¹⁶ / cm ³ ,
Highly doped p-type GaAs layer 24 (impurity C, hole concentration 2 × 10 ¹⁹ / cm ³ , film thickness 0.07 μm)
m), n-type AlGaAs layer 25 (AlAs molar ratio of 0.
3, impurity Si, electron concentration 3 × 10 ¹⁷ / cm ³ , film thickness 0.1 μm, n-type InGaAs layer 26 (InAs molar ratio 0.2, impurity Si, electron concentration 1 × 10 ¹⁸ / cm ³ ,
N-type AlGaAs layer 27 (AlA
s molar ratio 0.3, impurity Si, electron concentration 3 × 10 ¹⁷ / c
m ³ , film thickness 0.1 μm), n-type GaAs layer 28 (impurity Si, electron concentration 5 × 10 ¹⁸ / cm ³ , film thickness 0.2 μm)
Were sequentially grown at a substrate temperature of 580 ° C. In addition to the molecular beam epitaxy method, metalorganic vapor phase epitaxy (MO
VPE) method and the like can also be used.

After that, AuGe (film thickness: 0.3 μm) is vapor-deposited by a vacuum vapor deposition method such as resistance heating or a sputtering method, and then an AuGe emitter electrode 29 is formed by a lift-off method, and Cl (chlorine) plasma is formed using this emitter electrode as a mask. N-type GaAs layer 2 by dry etching using
8 and n-type AlGaAs layer 27 were mesa-etched. At this time, etching was automatically stopped at the surface of the n-type InGaAs layer 26.

Next, as shown in FIG. 5, the undoped polycrystalline GaAs layer 32 is formed on the entire surface of the sample including the side surface of the sample by revolving the sample in an ultra-high vacuum vapor deposition apparatus of about 10 ⁻⁷ Pa or less. (Film thickness 0.9 μm) was deposited.

Subsequently, as shown in FIG. 6, the entire surface of the undoped polycrystalline GaAs layer 32 is etched by anisotropic dry etching using Cl plasma, and n-type AlGa is obtained.
A sidewall film 32 made of undoped polycrystalline GaAs was formed on the sidewall of the emitter mesa made of the As layer 27, the n-type GaAs layer 28, and the AuGe emitter electrode 29. At this time, etching was automatically stopped at the surface of the n-type InGaAs layer 26.

Thereafter, as shown in FIG. 7, AuZn is vapor-deposited (film thickness 0.2 μm) by a vacuum vapor deposition method or a sputtering method.
Then, the AuZn base electrode 30 is formed. And
A photoresist pattern is formed by using the photolithography technique, and the semiconductor layer 23 to
26 is wet-etched with a mixed solution of phosphoric acid, hydrogen peroxide and water to perform base / collector mesa processing. Although not shown, in the semiconductor layers 26 and 25 immediately below the base electrode 30, since Zn of the base electrode 30 diffuses into a high-concentration p-type layer, the base electrode 30 and the p-type base layer 24 are separated from each other. Ohmic contact can be made.

Finally, as shown in FIG. 8, AuGe (film thickness 0.2 μm) is vapor-deposited by the vacuum vapor deposition method or the sputtering method, and then the AuGe collector electrode 31 is formed by the lift-off method, and the photolithography technique is used. The highly doped n-type GaAs layer 22 is wet-etched with the above mixed solution to separate the elements, and C-doped A
A 1 GaAs / GaAs HBT was prepared. Although not shown, or provided with a side wall film of an insulating film such as SiO ₂ between the base / collector electrodes, it may be or a protective film such as SiO ₂ on the surface course.

FIG. 3B shows C-doped Al according to the present invention.
It is a current-voltage characteristic showing the result of a 5-hour current-carrying test of GaAs / GaAs HBT. Almost no change in collector current and base current due to energization was observed, and it can be seen that a highly reliable HBT of C-doped AlGaAs / GaAs can be realized.

According to the present embodiment, the sidewall of the emitter mesa has a high resistivity of 1 MΩcm or more and is highly doped p-type G.
Since the sidewall film 32 made of undoped polycrystalline GaAs having the same thermal expansion coefficient as that of the aAs base layer 24 is used, the residual stress in the base layer due to the sidewall of the insulating film such as SiO ₂ which has been a conventional problem is substantially reduced to zero. As a result, there is an effect that an extremely reliable CBT-doped AlGaAs / GaAs HBT can be realized. In this embodiment, the side wall film 32 of the emitter mesa is made of undoped polycrystal, but if the impurity concentration is 1 × 10 ¹⁶ / cm ³ or less, it has a high resistivity of 1 MΩcm or more, and the same effect is obtained. Also,
In this embodiment, the sidewall film 32 is a polycrystalline GaAs layer,
A mixed crystal of Al _0.1 Ga _0.9 As, In _0.1 Ga _0.9 As, or the like may be used, and if the mixed crystal is up to 10% with respect to Ga, other Group III elements may be used to give a resistivity and a thermal expansion coefficient. Since the influence is small, the same effect can be obtained. Further, although the n-type InGaAs layer 26 is used as the etching stop layer during the dry etching using Cl plasma, the dry etching may be performed by controlling the time without using this. Furthermore, in the present embodiment, an example of a GaAs-based HBT formed on a GaAs substrate is shown, but the same can be applied to an HBT using another III-V group compound semiconductor such as an InGaAs-based HBT on an InP substrate. Of course.

<Embodiment 2> FIGS. 9 to 12 are longitudinal sectional structural views showing another embodiment of the heterojunction bipolar transistor according to the present invention, which is C-doped InGaP / GaAs.
FIG. 6 is a diagram sequentially showing a manufacturing process of HBT using.

First, referring to FIG. 9, undoped GaAs
A highly doped n-type GaAs layer 22 (impurity Si, electron concentration 5 × 10 ¹⁸ / cm ³ , film thickness 0.5 μm), n-type G is formed on a (100) substrate 21 by using a metal organic vapor phase epitaxy method.
aAs layer 23 (impurity Si, electron concentration 5 × 10 ¹⁶ / cm
³ , film thickness 0.3 μm), highly doped p-type GaAs layer 24
(Impurity C, hole concentration 2 × 10 ¹⁹ / cm ³ , film thickness 0.0
7 μm), the n-type InGaP layer 33 (InP molar ratio of 0.
5. Impurity Si, electron concentration 3 × 10 ¹⁷ / cm ³ , film thickness 0.03 μm), n-type GaAs layer 28 (impurity Si, electron concentration 5 × 10 ¹⁸ / cm ³ , film thickness 0.2 μm) It was grown sequentially at a temperature of 500 ° C. In addition to the organometallic vapor phase epitaxy method, a molecular beam epitaxy method or the like can be used.

After that, AuGe (film thickness 0.3 μm) is deposited by a vacuum deposition method such as resistance heating or a sputtering method, and then an AuGe emitter electrode 29 is formed by a lift-off method, and Cl plasma is used with this emitter electrode as a mask. The n-type GaAs layer 28 was mesa-etched by dry etching. At this time, the etching is n-type InG
It was automatically stopped on the surface of the aP layer 33.

Next, as shown in FIG. 10, the undoped polycrystalline GaAs layer 32 is formed on the entire surface of the sample including the side surface of the sample by revolving the sample in an ultrahigh vacuum vapor deposition apparatus of about 10 ⁻⁷ Pa or less. (Film thickness 0.9 μm) was deposited.

Subsequently, as shown in FIG. 11, the entire surface of the undoped polycrystalline GaAs layer 32 is etched by anisotropic dry etching using Cl plasma, and n-type GaA is formed.
A sidewall film 32 made of undoped polycrystalline GaAs was formed on the sidewall of the emitter mesa made of the s layer 28 and the AuGe emitter electrode 29. At this time, the etching is n-type InGa
It stopped automatically at the surface of the P layer 33.

Thereafter, as shown in FIG. 12, AuZn is vapor-deposited (film thickness 0.2 by a vacuum vapor deposition method or a sputtering method).
μm) to form the AuZn base electrode 30. Although not shown, since the semiconductor layer 33 immediately below the base electrode 30 becomes a high-concentration p-type layer due to diffusion of Zn of the base electrode 30, ohmic contact between the base electrode 30 and the p-type base layer 24 occurs. Can be taken. Next, by using the photolithography technique, the semiconductor layers 33, 2 are masked with the resist pattern.
4 and 23 were wet-etched with a mixed solution of phosphoric acid, hydrogen peroxide and water to perform base / collector mesa processing. Finally, as in Example 1, AuGe having a film thickness of 0.2 μm was formed.
The collector electrode 31 is formed, and the highly-doped n-type GaAs layer 22 is wet-etched to isolate the elements from each other to form C.
A HBT of doped InGaP / GaAs was produced. Although not shown in this embodiment, the base / or provided sidewall film an insulating film such as SiO ₂ between the collector electrode, it may be or a protective film such as SiO ₂ is of course the surface .

C-doped InGaP / Ga according to this embodiment
The HBT current test of As is shown in FIG.
HB of C-doped AlGaAs / GaAs shown in (b)
Similar to the result of the energization test of T, almost no change in collector current and base current due to energization was observed, and a highly reliable C-doped InGaP / GaAs HBT could be obtained.

According to this embodiment, the side wall of the emitter mesa has a high resistivity of 1 MΩcm or more and is highly doped p-type G.
Since the sidewall film 32 made of undoped polycrystalline GaAs having the same thermal expansion coefficient as that of the aAs base layer 24 is used, the residual stress in the base layer due to the sidewall of the insulating film such as SiO ₂ which has been a conventional problem is substantially reduced to zero. As a result, there is an effect that an extremely reliable CBT-doped InGaP / GaAs HBT can be realized. In this embodiment, the side wall film 32 of the emitter mesa is made of undoped polycrystal, but if the impurity concentration is 1 × 10 ¹⁶ / cm ³ or less, it has a high resistivity of 1 MΩcm or more, and the same effect is obtained. In addition, although the sidewall film 32 is a polycrystalline GaAs layer in this embodiment,
A mixed crystal such as l _0.1 Ga _0.9 As or In _0.1 Ga _0.9 As may be used.
Even if a group III element is used, the same effect can be obtained because the effect on the resistivity and the coefficient of thermal expansion is small. Further, the n-type InGaP layer 33 was used as the etching stop layer during the dry etching using Cl plasma, but the dry etching may be performed by controlling the time without using this. Furthermore, in this embodiment, GaA formed on a GaAs substrate is used.
An example of s-based HBT is shown, but InG on InP substrate
It is needless to say that the same can be applied to HBTs using other III-V group compound semiconductors such as aAs-based HBTs.

<Embodiment 3> FIGS. 13 to 15 are vertical sectional structural views showing another embodiment of the heterojunction bipolar transistor according to the present invention, which is C-doped InGaP / G.
It is the figure which showed the manufacturing process of HBT using aAs in order.

First, referring to FIG. 13, undoped GaA
Highly doped n-type G on the s (100) substrate 21 by using a metalorganic vapor phase epitaxy method or a molecular beam epitaxy method.
aAs layer 22 (impurity Si, electron concentration 5 × 10 ¹⁸ / cm
³ , a film thickness of 1.0 μm) was grown, and 0.5 μm of the highly-doped n-type GaAs layer 22 other than the intrinsic region of the transistor was removed by using photolithography and dry etching. Then, the SiO ₂ film 41 as an insulating film is 0.8 μm thick.
After the deposition, a photoresist 42 was applied to flatten the sample surface.

Next, the SiO ₂ film 41 and the photoresist 42 are subjected to uniform dry etching to obtain a highly doped n-type Ga.
The surface of the As layer 22 was exposed. Subsequently, the sample was transferred to a gas source molecular beam epitaxy apparatus using a single metal as a group III raw material and arsine and phosphine as a group V raw material,
As shown in FIG. 14, the n-type GaAs layer 23 (impurity S
i, electron concentration 5 × 10 ¹⁶ / cm ³ , film thickness 0.3 μm),
Highly doped p-type GaAs layer 24 (impurity C, hole concentration 4 ×
10 ²⁰ / cm ³ , film thickness 0.07 μm), n-type InGaP
Layer 33 (InP molar ratio 0.5, impurity Si, electron concentration 3
× 10 ¹⁷ / cm ³ , film thickness 0.03 μm), n-type GaAs
A layer 28 (impurity Si, electron concentration 5 × 10 ¹⁸ / cm ³ , film thickness 0.3 μm) was sequentially grown on the substrate at 500 ° C.

At this time, on the SiO ₂ film 41, an n-type polycrystalline GaAs layer 43 (impurity Si, resistivity> 1 MΩcm, film thickness 0.3 μm) and a highly-doped p-type polycrystalline GaAs layer 44 are formed.
(Impurity C, resistivity = 0.04 Ωcm, film thickness 0.07 μ
m), the n-type polycrystalline InGaP layer 45 (InP molar ratio of 0.
5, impurity Si, resistivity> 1 MΩcm, film thickness 0.03μ
m), an n-type polycrystalline GaAs layer 46 (impurity Si, resistivity> 1 MΩcm, film thickness 0.3 μm) was formed.

Thereafter, as in the second embodiment, as shown in FIG. 15, an AuGe emitter electrode 29 having a thickness of 0.3 μm is formed, and the n-type GaAs layer 2 is formed using this emitter electrode as a mask.
8 and the n-type polycrystalline GaAs layer 46 are dry-etched. At this time, dry etching is performed on the n-type InGaP layer 33.
And the n-type polycrystalline InGaP layer 45 was automatically stopped at the surface. Next, by performing an orbital rotation in an ultra-high vacuum vapor deposition apparatus, an undoped polycrystalline GaAs layer 32 of 0.9 μm is vapor-deposited on the entire surface of the sample including the side surface of the emitter, and then anisotropic dry etching using Cl plasma is applied to the entire surface. Etching was performed to form a sidewall film 32 made of undoped polycrystalline GaAs on the sidewall of the emitter mesa. At this time, the dry etching was automatically stopped on the surfaces of the n-type InGaP layer 33 and the n-type polycrystalline InGaP layer 45. After that, an AuZn base electrode 30 having a film thickness of 0.2 μm is formed (not shown, but the semiconductor layers 33 and 45 immediately below the base electrode 30 become p-type high-concentration layers due to diffusion of Zn of the base electrode 30. So
An ohmic contact can be established between the base electrode 30 and the p-type base 24. ), Using a photoresist as a mask using the photolithography technique, wet etching is performed on the SiO ₂ film 41 and the polycrystalline semiconductor layers 43 to 45 with a mixed solution of phosphoric acid, hydrogen peroxide solution and water to form a base / collector film. Perform mesa processing. Finally, similarly to the first embodiment, the AuGe collector electrode 31 having a thickness of 0.2 μm is formed and the highly-doped n-type GaAs layer 22 is wet-etched to separate the elements, and as shown in FIG.
A GaP / GaAs HBT was manufactured. Although not shown in this embodiment, Si is provided between the base and collector electrodes.
A side wall film made of an insulating film such as O ₂ is provided, or Si
It goes without saying that a protective film such as O ₂ is provided.

C-doped InGaP / Ga according to this embodiment
In the HBT of As, a SiO ₂ film 41 having a relative permittivity as low as about ⅓ of GaAs is embedded in the collector region, and a conductive polycrystalline GaAs base layer 4 having a resistivity as low as 0.04 Ωcm 4 is formed.
Since 4 is used, the base / collector capacitance can be reduced to about 1/3 and the maximum oscillation frequency can be increased by about 70% in addition to the features described in the second embodiment.

Although the sidewall film 32 of the emitter mesa is made of undoped polycrystal in this embodiment, the impurity concentration is 1
It had a similar effect because it has a × 10 ¹⁶ / cm ³ higher resistivity than 1MΩcm not more than. In addition, although the sidewall film 32 is a polycrystalline GaAs layer in this embodiment, Al _0.1 G
a mixed crystal such as a _0.9 As or In _0.1 Ga _0.9 As may be used,
If a mixed crystal of up to 10% with respect to Ga is used, the same effect can be obtained even if another group III element is used, since the effect on the resistivity and the thermal expansion coefficient is small. Furthermore, in this embodiment, an example of a GaAs-based HBT formed on a GaAs substrate is shown, but an InGaAs-based HBT on an InP substrate is shown.
Needless to say, HBTs using other III-V group compound semiconductors can be similarly implemented.

Although the preferred embodiment of the heterojunction bipolar transistor according to the present invention has been described above, the present invention is not limited to this. For example, Si-G
It is of course applicable to the emitter side wall film of the e-type heterojunction bipolar transistor, and various design changes can be made without departing from the spirit of the present invention.

[0038]

According to the present invention, as the sidewall film of the emitter mesa, undoped semiconductor of the same semiconductor as the base layer or polycrystal having an impurity concentration of 1 × 10 ¹⁶ / cm ³ or less, or 90% of the same semiconductor material as the base layer is used. By using an undoped mixed crystal containing the above or a polycrystal having an impurity concentration of 1 × 10 ¹⁶ / cm ³ or less, the sidewall film has a high resistivity and has a thermal expansion coefficient almost the same as that of the base layer. The residual stress in the layer is substantially zero. For this reason,
It is possible to realize a highly reliable III-V group compound semiconductor HBT in which the grounded-emitter amplification factor does not decrease even when the energization test is performed.

[Brief description of drawings]

FIG. 1 is a vertical sectional structural view showing an embodiment of a heterojunction bipolar transistor according to the present invention.

FIG. 2 is a vertical sectional structural view showing a conventional heterojunction bipolar transistor.

3A and 3B are current-voltage characteristics showing a characteristic variation of a C-doped AlGaAs / GaAs heterojunction bipolar transistor before and after a current test, (a) is a characteristic diagram of a conventional structure, and (b) is a structure of the present invention. It is a characteristic diagram.

FIG. 4 is a vertical sectional structural view showing a first embodiment of a heterojunction bipolar transistor according to the present invention, which is a sectional structural view showing the middle of the manufacturing process.

5 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

6 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

7 is a cross-sectional structure diagram showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

8 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG. 7. FIG.

FIG. 9 is a vertical sectional structural view showing a second embodiment of the heterojunction bipolar transistor according to the present invention, which is a sectional structural view showing the middle of the manufacturing process.

10 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

11 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

12 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

FIG. 13 is a vertical sectional structural view showing a third embodiment of the heterojunction bipolar transistor according to the present invention, which is a sectional structural view showing the middle of the manufacturing process.

14 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

15 is a sectional structural view showing a next manufacturing step of the heterojunction bipolar transistor shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Highly doped n-type semiconductor layer, 3 ... N-type semiconductor layer, 4 ... Highly-doped p-type semiconductor layer, 5 ... N-type wide gap semiconductor layer, 6 ... Highly-doped n-type semiconductor layer, 7 ... Undoped polycrystalline semiconductor layer, 8 ... Emitter electrode, 9 ... Base electrode, 10 ... Collector electrode, 11 ... Insulating film, 21 ... Undoped GaAs substrate, 22 ... Highly doped n-type GaAs
Layer, 23 ... n-type GaAs layer, 24 ... highly-doped p-type GaA
s layer, 25 ... n-type AlGaAs layer, 26 ... n-type InGa
As layer, 27 ... N-type AlGaAs layer, 28 ... Highly doped n
-Type GaAs layer, 29 ... AuGe (emitter electrode), 30
... AuZn (base electrode), 31 ... AuGe (collector electrode), 32 ... Undoped polycrystalline GaAs (sidewall film),
33 ... N-type InGaP layer, 41 ... Insulating film (SiO ₂ ),
42 ... Photoresist, 43 ... N-type polycrystalline GaAs layer, 4
4 ... Highly doped p-type polycrystalline GaAs layer, 45 ... N-type polycrystalline InGaP layer, 46 ... Highly doped n-type polycrystalline GaAs layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Hirata 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd.

Claims (7)

[Claims] 1. In a heterojunction bipolar transistor including a base layer, an emitter layer provided on the base layer, and a collector layer provided on the bottom of the base layer, 90% of the same material as the base layer is used. It is a polycrystal containing the above and the impurity concentration includes undoped 1 × 10 ¹⁶ /
A heterojunction bipolar transistor, characterized in that the periphery of the side surface of the emitter layer is deposited by a polycrystal of cm ³ or less. 2. The heterojunction bipolar transistor according to claim 1, wherein the base layer, the emitter layer and the collector layer are single crystals made of a III-V group compound semiconductor. 3. The heterojunction bipolar transistor according to claim 2, wherein the base layer has p-type conductivity and contains carbon as an impurity. 4. The emitter layer is A having n-type conductivity.
The heterojunction bipolar transistor according to claim 3, which is 1GaAs. 5. The emitter layer is n-type conductive and is A
The heterojunction bipolar transistor according to claim 3, comprising three layers of 1 GaAs, InGaAs and AlGaAs. 6. The emitter layer is In having n-type conductivity.
The heterojunction bipolar transistor according to claim 3, which is GaP. 7. A heterojunction bipolar transistor including a base layer, an emitter layer provided above the base layer, and a collector layer provided below the base layer, wherein a side surface of the emitter layer is deposited. A heterojunction bipolar transistor, characterized in that the material and the material forming the base layer have the same coefficient of thermal expansion.