JPH0991965A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an RAM in which high speed memory cell is realized while reducing power consumption, increasing the capacity and shortening the design schedule. SOLUTION: The RAM comprises two port memory cells (C11-Cmn) 1 arranged in array, an RAM control circuit 2 for generating word line and digit line information from address signals AD1-ADp, a two port I/O circuit 4 and a circuit 3 for selecting I/O of two port. A plurality of I/O ports I1-In/O1-On are selected sequentially one by one and each digit line of the plurality of I/O ports is precharged sequentially at a different timing thus shortening the apparent operational cycle time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a random access memory (RAM) device for improving read / write cycle operation.

[0002]

2. Description of the Related Art Conventionally, in such a RAM device, various circuits have been proposed for accelerating read / write cycle operations.

FIG. 4 is a block diagram of a RAM device (hereinafter, simply referred to as RAM) showing an example of such a conventional technique. As shown in FIG. 4, the conventional RAM has a plurality of memory cells (C11 to Cmn) 1a arranged in a matrix and having one input / output port, and an address signal AD1 for writing to the memory cell 1a to be accessed. Permission signal W
E, a RAM control circuit 2 for creating word line and digit line information based on the clock signal CLK, a decoder 5 for designating the word lines WA1 to WAm by the information from this control circuit 2, and digit lines DA1 and DA1. Inversion,
..., DAn, DAn inversion and an input / output circuit 4a which is connected between the input / output data signal terminals I1 to In and O1 to On and sequentially switches digit lines designated by the control from the RAM control circuit 2. I have it.

Generally, the RAM includes a synchronous RAM and an asynchronous RAM. In the asynchronous RAM, the access time is important, and its cycle operation is determined by the access time. When an address transition detection circuit (ATD circuit) or the like is added to the synchronous RAM, the asynchronous RA
It can be used as M, but has little effect on cycle time. Therefore, the following description will be made on the assumption that the synchronous RAM is used.

FIG. 5 is a waveform diagram of various signals in FIG. As shown in FIG. 5, first, regarding the read operation, the RAM control circuit 2 takes in the address signals AD1 to ADp at the rising edge of the synchronous clock signal CLK and passes the address information to the decoder 5. By this address information, the decoder 5 sequentially activates the word lines WA1 to WAm of the selected address. Also, the digit line D
A1, DA1 inversion; ...; DAn, DAn inversion are sequentially precharged by the input / output circuit 4a before reading in order to increase the reading speed. Thereafter, the data of the selected memory cell (C11 to Cmn) 1a is read out to the input / output circuit 4a via the digit lines DA1, DA1 inversion; ...; DAn, DAn inversion. The read data is amplified by the input / output circuit 4a and output to the output data signal terminals O1 to On. Here, the address signal ADp, the digit lines DAn and DAn inverted, and the output data On are shown in a representative form.

Next, regarding the write operation, R
The AM control circuit 2 takes in the address signals AD1 to ADp at the rising edge of the synchronous clock signal CLK and passes the address information to the decoder 5. Based on this address information, the decoder 5 causes the word lines WA1 to WA1 of the selected address.
WAm is activated sequentially. Further, since the RAM control circuit 2 receives the write permission signal WE, it gives write permission to the input / output circuit 4a. As a result, the input / output circuit 4
a is the digit line DA1, DA1 inversion; ...; DAn,
DAn inversion is sequentially activated to write data signal terminal I
Send data from 1 to In. Therefore, this data corresponds to the word lines WA1 to WA activated by the decoder 5.
Data is sequentially written in the memory cells (C11 to Cmn) 1a connected to Am.

As described above, in the synchronous cycle read operation, the address signal AD is generated at the rising edge of the CLK signal at the point A.
The complementary data of the selected memory cell 1a is read out through the inversion of the precharged digit lines DAn and DAn, amplified by the input / output circuit 4a, and then output to the output data terminal On. Similarly, the reading of the next cycle starts from the point A '.

The read cycle time is usually C
The LK circuit operation, the decoder circuit operation, and the digit line charging / discharging time have a great influence, and particularly, the digit line data read time (digit line discharging time) and the precharge time (digit line charging time) occupy a large part. ing.

[0009]

In the conventional semiconductor memory device (RAM) described above, the shortest cycle time is the read time (time from decoding to amplification read).
And the digit line precharge time. Therefore, in order to shorten the cycle time, it is necessary to shorten both the read time and the precharge time for the digit line. That is, it is indispensable to accelerate the decode time, the amplification read time, the precharge time, and the charge / discharge time of the digit line by the memory cell.

As described above, in the conventional RAM, in order to realize high-speed decoding circuit, input / output circuit, and memory cell, the circuit scale and layout area must be increased and power consumption must be increased. However, there is a drawback that the design period is extended. Further, if the memory capacity of the RAM is large, it is not suitable for shortening the cycle, and there is also a problem that the memory capacity cannot be increased so much.

Further, the write cycle can be speeded up to a certain extent by writing with a large driver, and the speed can be increased faster than the read cycle. However, on the other hand, power consumption increases.

It is an object of the present invention to provide a semiconductor memory device which, in realizing such a high speed operation of a memory cell, has a low power consumption, a large capacity, and a short design period. It is in.

[0013]

In the semiconductor memory device of the present invention, a 2-port memory cell arranged in an array and an R for generating word line and digit line information by an address signal.
An AM control circuit, a decoder for creating word line information to be selected under the control of the RAM control circuit, and one 2-port word line output connected to the 2-port memory cell based on the decoder output. A decoder selection circuit for selecting, an input / output circuit connected to the 2-port memory cell, and an input / output selection circuit connected to a plurality of input / output ports and selecting 2-port input / output through the input / output circuit And each of the plurality of input / output ports is sequentially selected for input / output, and each digit line of the plurality of input / output ports is sequentially precharged at different timing. To be done.

Also, the semiconductor memory device of the present invention is a 2-port memory cell arranged in an array, a RAM control circuit for creating word line and digit line information by an address signal, and selected by control of the RAM control circuit. A decoder for creating word line information to be written, and a decoder selection circuit for selecting one of two port word line outputs connected to the two port memory cells based on the decoder output,
A plurality of input / output ports connected to the plurality of input / output ports, and an input / output selection circuit connected to the two-port memory cells and selecting input / output of the two ports. Of these, one port at a time is sequentially selected for input / output, while the digit lines of the plurality of input / output ports are sequentially precharged at different timings.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device according to the present embodiment exemplifies a synchronous RAM using 2-port memory cells. This RAM
Is a 2-port memory cell (C1n to Cmn) 1 and a RAM for taking in the address signals AD1 to ADp, the write enable signal WE, and the clock signal CLK and controlling each circuit unit.
A control circuit 2, a decoder 5 for creating information for designating a word line based on the information from the control circuit 2, and a 2-port word line WA1 to WA based on the output of the decoder 5.
a decoder selection circuit 6 for selecting m, WB1 to WBm,
Digit lines DA1, DA1 inversion, DB1, DB1 inversion,
..., DAn, DAn inversion, DBn, DBn inversion and output ports OA1, OB1; ...; OAn, OBn
An input / output circuit 4 connected between the input / output circuits 4 for writing / reading data to / from the memory cell 1 under the control of the RAM control circuit 2 and two-port input / output data signal terminals I1 to I
n, O1 to On, and an input / output selection circuit 3 for switching input / output under the control of the RAM control circuit 2. In particular, the memory cell 1 is connected to the digit lines DA1 to DAn, DA1 inversion to DAn inversion and DB1 to DBn, DB1 inversion to DBn inversion for each port and arranged in a matrix. Further, one port of these two-port memories is designated as A port, and the other port is designated as B port. The input / output circuit 4 and the input / output selection circuit 3
Although there is an input port between them, it is not shown here because it is similar to the output port.

For the circuit operation of this RAM, that is, the read operation and the write operation, refer to the signal waveform diagram of FIG.

FIG. 2 is a waveform diagram of various signals in FIG. As shown in FIG. 2, first, in the case of a read operation, RA
The M control circuit 2 uses the clock signal CL as a synchronization control signal.
Address signals AD1 to AD1 at the rising edge of K (point A)
ADp is taken in and the decoder 5 selects the word line of the selected address. Based on the output of the decoder 5, the decoder selection circuit 6 selects the word line of either of the two ports. In this case, only one of the word lines is sequentially selected, and the word line WAm of the A port is selected here.

The selected word line WAm of the A port outputs memory data to the digit lines DA1 to DAn, DA1 inversion to DA1 inversion of the A port of the memory cells Cm1 to Cmn. This data is amplified by the input / output circuit 4 and output to the A port outputs OA1 to OAn.
At this time, the input / output selection circuit 3 selects the output of the A port and outputs the output signals O1 to On. After the output from the input / output selection circuit 3, the digit lines DA1 to DAn, DA1
The inversion to DAn inversion are precharged by the input / output circuit 4. The synchronization control signal CLK has a cycle that is twice the conventional cycle time.

Next, at the rising edge (point B) of the synchronization control signal CLK, the next address signals AD1 to ADp are fetched and the decoder 5 selects the word line of the selected address again. Therefore, the decoder selection circuit 6 selects the B port word line WBm. The memory cells Cm1 to Cm selected by the word line WBm of the selected B port
The memory data is output to the digit lines DB1 to DBn, DB1 inversion to DBn inversion of the B port of mn, amplified by the input / output circuit 4, and then the B port outputs OB1 to OB.
It is output to n. Similarly, the input / output selection circuit 3 selects the output of the B port and outputs the output signals O1 to On.

The above-mentioned digit lines and word lines of the A port and the B port are independent of each other and can be operated at different timings. That is, during the read operation of the A port, the B port performs the precharge and read preparation operations, and after the read of the A port, the B port starts the read operation and the A port starts the precharge. In short, by starting the read cycle of the B port in the middle of the read cycle of the A port and selectively switching the output sequentially, it is possible to output in the cycle of about half the original cycle time.

Thus, when the A port is selected at the rising edge (point A) of the clock signal CLK and the A port is output, the B port is selected at the next edge (point B),
The B port is output. Similarly, the next edge (A '
When the port A is again selected and output at the point), the port B is again selected and output at the next edge (point B ').

On the other hand, also in the write operation, similar to the read operation, the A port and the B port are selected in a cycle of a double cycle, and writing is performed by sequentially switching. The input / output terminals at this time also have two ports, but since the memory cells 1 are the same, the data identity is maintained.

By the read operation and the write operation, the apparent operation cycle time is shortened. That is, current consumption during operation does not concentrate and is divided into two, so that power consumption is low and reliability is easily improved.
Further, since the cycle time for one port remains the same, the overhead of layout and circuit design can be reduced, and the design period can be shortened. Furthermore, since the power consumption is low and the cycle time for one port remains the same, there is an advantage that a large capacity of the memory can be easily realized.

FIG. 3 shows an RA showing another embodiment of the present invention.
It is a block diagram of M. As shown in FIG. 3, this embodiment is similar to FIG. 1 in that it has two-port memory cells (C11 to C11).
Cmn) 1, RAM control circuit 2, decoder 5 and decoder selection circuit 6 for selecting 2-port word line output
In addition to the above, two-port digit lines DA1 to DA
n, DA1 inversion to DAn inversion and DB1 to DBn, D
An input / output selection circuit 3 for selecting an output of B1 inversion to DBn inversion and an input / output circuit 4 connected to the input / output terminals I1 to In and O1 to On are provided. Also in this case, the memory cell 1 has digit lines DA1 to DAn, DA1 inversion to DAn inversion and DB1 to DBn, DB1 inversion to D for each port.
It is connected to Bn inversion and arranged in a matrix. In this case as well, one port of the 2-port memory is set as the A port, and the other port is set as the B port.
OAn is a bidirectional terminal.

In the present embodiment, the input / output selection circuit 3 first switches the 2-port digit lines, and thereafter, the input / output circuit 4 amplifies and outputs the digit line data and sets the input / output terminals for writing or reading. Only one system. According to this embodiment, since the input / output selection circuit 3 switches the digit line first,
There is an advantage that the circuit scale of the input / output circuit 4 can be made smaller than that of the circuit shown in FIG.

[0027]

As described above, in the semiconductor memory device of the present invention, memory cells having a plurality of input / output ports are arranged in a matrix, and one of the input / output ports is sequentially selected. Input and output, and by sequentially precharging the digit lines of the plurality of input and output ports at different timings, the read operation cycle and the write operation cycle as well as the apparent operation cycle time are shortened, and the power consumption is reduced. In addition to the measurement, there is an effect that the capacity of the memory can be increased and the design period can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a RAM showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of various signals in FIG.

FIG. 3 is a block diagram of a RAM showing another embodiment of the present invention.

FIG. 4 is a block diagram of a RAM showing a conventional example.

5 is a waveform diagram of various signals in FIG.

[Explanation of symbols]

 1 memory cell 2 RAM control circuit 3 input / output selection circuit 4 input / output circuit 5 decoder 6 decoder selection circuit I1-In input data terminals O1-On output data terminals

Claims (2)

[Claims] 1. A two-port memory cell arranged in an array, a RAM control circuit for creating word line and digit line information by an address signal, and word line information to be selected by control of the RAM control circuit. A decoder,
A decoder selection circuit for selecting one of the two-port word line outputs connected to the two-port memory cells based on the decoder output; an input / output circuit connected to the two-port memory cells; And an input / output selection circuit that is connected to the input / output port and selects input / output of two ports via the input / output circuit, and sequentially selects each of the plurality of input / output ports for input / output. On the other hand, the semiconductor memory device is characterized in that the digit lines of the plurality of input / output ports are sequentially precharged at different timings. 2. A 2-port memory cell arranged in an array, a RAM control circuit for creating word line and digit line information by an address signal, and word line information to be selected by control of the RAM control circuit. A decoder,
A decoder selection circuit for selecting one of the two-port word line outputs connected to the two-port memory cells based on the decoder output, and a two-port input / output circuit connected to a plurality of input / output ports, An input / output selection circuit connected to the two-port memory cell and selecting two-port input / output; one of the plurality of input / output ports is sequentially selected for input / output; A semiconductor memory device characterized in that digit lines of the plurality of input / output ports are sequentially precharged at different timings.