JPH11149767A - Dram, integrated circuit including the same and test method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate control at the time of continuous read/write in page mode by reading/writing a data with a signal where the first input has a first logical level every time when the clock input is changed and the column address is synchronized with a clock when the second input has a predetermined logical level. SOLUTION: When a clock input is changed from L level to H level, both first and second inputs have L level and if/write enable signal has H or L level, a data in a memory cell selected by a row address or column address is read out or a data is written in a selected memory cell. When both first and second inputs are set at L level and the column address is provided in synchronism with the clock input, the data can be read out/written in continuously in page mode every time when the clock input is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit in which a logic circuit such as a DRAM (Dynamic Random Access Memory) and a microcomputer or an ASIC (Application Specific Integrated Circuit) is integrated into one chip, and a burn-in test method therefor.

[0002]

2. Description of the Related Art FIG. 10 shows a system configuration of a conventional general DRAM. In this figure, an address signal externally input to an address terminal Ad is supplied to a row selection circuit (row decoder) 104 and a column selection circuit (column decoder) 105 via a row address buffer 102 and a column address buffer 103. Data is written or read from or to a memory cell in the memory cell array 106 selected by the row address signal and the column address signal. The sense amplifier 107 is a sense amplifier that amplifies a small data signal of a memory cell in the memory cell array 106 in response to a control signal input Din and outputs the amplified signal to an output Dout.

FIG. 11 shows the conventional DRAM of the above-described type.
6 is a timing chart of a page mode read operation of a DO (Extended Data Out) method. At time h, the row address control signal changes from H (high) level to L (low) level, and the row address ROW1 on the address Ad line is taken in, thereby selecting one row of memory cells. Next, at time i, the column address control signal changes from the H level to the L level, and the column address COL1 on the address Ad line is fetched to select the column address. Row address ROW1 and column address COL1
The data D1 of the memory cell selected by the
output to ut.

Next, at time j, when the column address control signal changes from H level to L level again, address A
The column address COL2 on the d-line is fetched. At this time, since the row address ROW1 has not changed, the data D2 of the memory cell selected by the row address ROW1 and the column address COL2 is output. At this time, the data D1 output to the output Dout at the time j is closed to be in a high impedance state, and thereafter, the data D2 of the newly selected memory cell is output. Similarly,
Column addresses COL3, CO at the same row address ROW1
L4 is sequentially fetched at time k and time m, and the data D3 and D4 of the selected memory cell are sequentially output correspondingly.

As described above, there is an address multiplexing system in which the address Ad is used as a row address and a column address, and a row address and a column address are provided in a time-division manner using a row address control signal and a column address control signal. General. According to this method, the number of address terminals, which increases with an increase in the capacity of the DRAM, can be halved.

[0006]

However, in the conventional configuration as described above, when data is read or written in the page mode, the column address control signal is changed from H level to L level every time the column address is changed. Since the input signal of the DRAM must be changed, it is difficult to generate an operation timing signal inside the DRAM because the input signal of the DRAM is asynchronous. Further, in the conventional configuration, since the row address and the column address are multiplexed and input to a common address input, it is difficult to control the address. A circuit for multiplexing and outputting the row address and the column address is required in the logic unit, and there is a problem that power consumption increases.

It is an object of the present invention to synchronize the external input of the DRAM with the clock input, thereby facilitating the control of the DRAM when reading or writing in the DRAM page mode is performed continuously.

In an integrated circuit in which a DRAM and a logic section are integrated into one chip, an address control method for a normal operation in which the logic section controls the DRAM address and a test method for directly controlling the DRAM address from outside are described. It is also an object of the present invention to facilitate the address control inside the integrated circuit by switching, thereby simplifying the circuit and reducing power consumption.

[0009]

SUMMARY OF THE INVENTION An integrated circuit according to the present invention comprises a clock input, a first input for controlling a row address, a second input for controlling a column address, and a read or write target for a row address and a column address. A memory cell array in which a memory cell is specified, and a sense amplifier for amplifying data of the memory cell output to a column line of the memory cell array, wherein a signal whose first input is synchronized with a clock input changes to generate a first signal As the logic level is reached, the data of the memory cell connected to the selected row line is amplified by a sense amplifier by a signal in which the row address is synchronized with the clock input,
Subsequently, each time the clock input changes, if the first input is at the first logic level and the second input is at the predetermined logic level, the column address is selected by a signal synchronized with the clock. Data is read or written by a sense amplifier connected to the selected column line.

According to the above-described configuration, when reading or writing is continuously performed in the page mode of the DRAM, a clock is applied to the clock input and, for example, the first input which is a row address control signal is set to the L level. If the second input which is a column address control signal is set to L level and the column address is given in synchronization with the clock input, data can be read or written continuously every time the clock input changes. . When the logic levels of the first and second inputs do not satisfy the above condition, the reading or writing of the DRAM ends. Thus, the DRAM
Can be easily controlled. Further, the first input which is a row address control signal, the second input which is a column address control signal, the row address, the column address, the input data, and the / write enable signal are synchronized with the clock input. The rising and falling timings of the read and write control timing signals are generated only by clock input, and the timing generation circuit can be realized with a simple circuit configuration.

An integrated circuit according to the present invention includes a DRAM having a row address and a column address, and a logic section. The logic section supplies a row address and a column address to the DRAM during a normal operation, and a row address during a DRAM test. A signal obtained by multiplexing an address and a column address is externally supplied. This facilitates address control inside the integrated circuit, simplifies the circuit in the logic section and reduces power consumption, while suppressing the increase in external input terminals required for testing the built-in DRAM. it can.

Preferably, there is provided a signal selection circuit for selecting one of an address signal from an external input terminal and an address signal from a logic section and applying the selected signal to the DRAM, and a row address output from the logic section during normal operation. And a signal of a column address are simultaneously selected by a signal selection circuit to provide a DRAM.
In the test of the DRAM, a signal in which the row address and the column address input from the external input terminal are time-division multiplexed is selected by the signal selection circuit and supplied to the DRAM, and the determination circuit in the DRAM is time-division multiplexed. Separate signals into row and column addresses. Thereby, the number of external terminals at the time of a test can be reduced.

Another configuration of the integrated circuit according to the present invention is the DR
AM, a logic section, a test pattern generation circuit for performing a burn-in test of the DRAM, and a mode for performing a burn-in test of the DRAM or a mode for performing a burn-in test of the logic section based on a signal generated by the test pattern generation circuit. And an external input terminal. According to this configuration, the DRAM
The only external signals required during the burn-in test are a DRAM clock signal and a burn-in switching signal.

Preferably, the semiconductor device includes a plurality of external terminals shared by a DRAM, a logic unit, and a test pattern generation circuit, and a signal selection circuit for the external terminals. The signal selection circuit sets the connection destination of the external terminal so that the external terminal is used by the DRAM during the operation test of the DRAM and the external terminal is used by the test pattern generation circuit and the logic unit during the burn-in test of the DRAM by the test pattern generation circuit. Switch.
Even if the capacity and bit width of the built-in DRAM increase with the advancement of semiconductor miniaturization technology and the number of dual-purpose terminals for testing the DRAM increases, it can be used as an external terminal for performing a burn-in test of the logic part. Since the dual-purpose terminal can be used, the burn-in test of the logic unit can be performed in parallel with the burn-in test of the DRAM. Thus, the burn-in test time can be reduced.

Further, the burn-in test method for an integrated circuit according to the present invention is characterized in that a predetermined external input signal of an integrated circuit including a DRAM, a logic unit, and a test pattern generation circuit for performing a burn-in test of the DRAM is firstly inputted. , The DRAM is written and read based on the signal generated by the test pattern generating circuit, and a burn-in test of the DRAM is performed by applying stress to the memory cell, and the external input signal is set to the second level. The burn-in test of the logic section is performed by setting the logic level to

Preferably, in the burn-in test of the logic section, a test is performed based on a test pattern previously written in the built-in DRAM. High-speed operation is possible and test time can be shortened, as compared with the case where a test is applied from outside to perform a test.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 shows a configuration of an integrated circuit according to Embodiment 1 of the present invention. The integrated circuit 200 includes a DRAM 1
A burn-in pattern generation circuit 11 for generating a test signal at the time of a burn-in test of the DRAM 1 and a logic unit 12 composed of a microcomputer or a logic circuit are integrated on one chip. 13 is a logical product (AN
D) circuits, 14 and 16 are inverter circuits,
Reference numeral 15 denotes a logical sum (NOR) circuit. Reference numeral 34 denotes a signal selection circuit that controls an input signal of the logic unit 12 and switches an input signal to the DRAM 1. 17-2
Reference numerals 1 and 115 denote 1-input inverted 2-input AND circuits.
2 to 33, 113 and 114 are selectors, and 116 is a tri-state buffer.

FIG. 2 shows the DRA included in the integrated circuit 200.
1 shows a system configuration of M1. In FIG. 2, 2 is DRA
A control circuit for controlling the operation of M1; 3 a row selection circuit for selecting a row address; 4 a column selection circuit for selecting a column address; 5 a memory cell array; 6 a sense for amplifying a small signal from the memory cell array; An amplifier 7 is a main amplifier.

FIG. 3 shows a control circuit of the DRAM 1. 3, 41 to 43, 48, 49, 64, 67, 7
1, 77, 81 and 85 are inverter circuits;
47 and 52 are D-type flip-flop circuits (DFF), and 45 is a composite circuit of AND and NOR. 50 is a row address latch for latching a row address;
62, 65, 68, 69, 72, 78, 83, 84, 1
Numeral 11 denotes an AND circuit, and numeral 53 denotes a column address latch for latching a column address. 54-60, 75, 76,
80, 82 and 86 are delay circuits, 61 is an OR circuit, 63 is a DFF with an enable terminal, and 6
6, 70 and 79 are set reset circuits;
Reference numeral 4 denotes a buffer; 89, a timing generation circuit for generating a timing signal for the DRAM; 118, a discrimination circuit for discriminating and separating a row address and a column address.

FIG. 4 shows a memory cell array 5 of the DRAM 1 and its peripheral circuit configuration. In FIG. 4, WL
0 to WLN are row lines, YL0 to YLM are column lines, and M00 to MNM are memory cells. T00-T2
M is a precharge circuit, S0 to SM are sense amplifiers, T
G00 to TGM1 are data line selection gates, and 93 is a main amplifier. 94 and 95 are DFFs for data latch, 96 and 97 are tri-state buffers, and 9
8 is a tristate inverter circuit, and 112 is a DFF with an enable terminal.

First, the operation of the signal selection circuit in the normal operation of the integrated circuit configured as described above will be described.
In FIG. 1, the test signal is set to L level during normal operation. Therefore, both the switching signal 1 and the burn-in test signal inside the integrated circuit 200 are fixed at L level, and the switching signal 2 is fixed at H level. As a result, the logic unit 12 passes the tri-state buffer 116 from the signals of the external input terminals 1 to 5 and the external input / output terminals via the one-input inversion two-input AND circuits 17 to 21 and 115 of the signal selection circuit 34. A signal is input. Note that the external input terminal 5 and its circuit are provided for a plurality of bits. External input / output terminals and their circuits are also provided for a plurality of bits.

The selectors 28 to 28 of the signal selection circuit 34
32 and 114 select the A input, that is, the signal output from the logic unit 12 by the test signal, and
Give to. Since the output signal of the logic unit 12 is selected as the input of the DRAM 1, the first input is
, A row address control signal 1 which is an output signal from the logic unit 12 is selected, a second input is a column address control signal 1 which is an output signal from the logic unit 12, and a / write enable signal is an output signal from the logic unit 12. / Write enable signal 1 is selected, and the row address is
2 is selected as the first row address, which is the output signal from
The column address is a first signal which is an output signal from the logic unit 12.
Is selected, and the data input is performed by the logic unit 12
Will be selected as the data input / output which is the output signal from. Note that “/” added to the head of the signal name means negative logic. As for the clock input of the DRAM 1, the A input is selected by the selector 25 of the signal selection circuit 34 and the A input is selected by the selector 33.
Is output.

Next, the operation of the DRAM during normal operation will be described with reference to the timing charts of FIGS. First, the timing of a read operation in the page mode of the DRAM 1 is shown in FIG. At time t0, the first input which is the row address control signal is
Since the signal RASL synchronized with the clock by F44 is at L level, the P-channel (Pch) transistors T00 to T0M, T10 to T1M, T20 to T2 in FIG.
M is turned on, and bit lines 0 to M and / bit lines 0 to M are precharged to 1/2 Vdd and equalized.

At time t1, when the signal RASL whose first input is synchronized with the clock rises from L level to H level, the Pch transistors T00 to T0 of FIG.
M, T10 to T1M and T20 to T2M are turned off, and precharge and equalization of the bit lines 0 to M and / bit lines 0 to M are stopped. The row address latch 50 in FIG.
The row address is latched by the clock input, and the row address 3 is output. In FIG. 4, since RASL is at the H level, the row line WLn selected by the row address 3 goes to the H level. In FIG. 3, the sense amplifier enable, which is the output of the delay circuit 1 (54), changes the delay time D from the time t1.
As the level becomes high after LY1, the sense amplifier S0
To the active state, data of the memory cell connected to the row line WLn is read out to the bit lines 0 to M, and differentially amplified by the sense amplifiers S0 to SM.

At time t2, the second input is performed together with the first input.
Input (column address control signal) is at L level,
The outputs of the inverters 41 and 42 in FIG. 3 both go high, and the output of the AND gate 51 goes high. As a result, the column address latch 53 is enabled, the column address is latched at the rising edge of the clock, and the DFF 52
Becomes an H level.

The operation of the timing generation circuit 89 surrounded by a broken line in FIG. 3 will be described. Before time t2, the column flag is at L level and the output of AND gate 65 is at L level, so that the output of set / reset circuit 66 is at L level. Therefore, data line precharge signal / DPRS
Becomes L level, and Pch transistors 90, 91, 9
2 is turned on, and both the data line and the / data line are precharged to Vdd and equalized.

The clock input is delayed by the delay circuit 2 (55) by the delay time DLY2, and this signal is delayed by the delay circuit 3 (5).
6) is input to the inverter 64. Since the column flag is at the H level, a one-shot pulse is output from the AND gate 65, and the set / reset circuit 66 is set.
The / DPRS rises at a timing delayed by the delay time DLY2 from the time t2, the precharge and equalization of the data line are released, and at the same time, the column selection enable signal Y
LEN stands up. In FIG. 4, the column selection circuit 4 sets the column signal YLm selected by the column address 3 to H level, so that the Nch transistors TGm0 and TGm1 are turned on. As a result, the output of the sense amplifier Sm is provided to the data line and / or the data line.

In the timing generation circuit 89 of FIG.
A signal CLKD2 obtained by delaying CLKD1 by the delay time DLY4 by the delay circuit 4 (57) is input to the delay circuit 3 (56) and the inverter 67. Since the column flag is at the H level, a one-shot pulse synchronized with the rise of CLKD2 is output from the AND gate 65, and the set / reset circuit 70 is set. At a timing delayed by the delay time DLY4 from the rise of YLEN, the main amplifier enable signal MAEN rises from L level to H level, and the main amplifier 93 starts operating. As a result, the differential signal voltage of the data line and / or the data line is amplified and output.

In the timing generation circuit 89 of FIG.
A signal CLKD3 obtained by delaying CLKD2 by delay circuit 5 (58) by delay time DLY5 is input to delay circuit 3 (76) and inverter 77. Since the column flag is at the H level, a one-shot pulse synchronized with the rise of CLKD2 is output from the AND gate 78, and the set / reset circuit 79 is set. The data latch clock 1 (hereinafter abbreviated as DCK1) rises from the L level to the H level at a timing delayed by the delay time DLY5 from the rise of the MAEN signal, and the CLKD3 is delayed by the delay circuit 7
The signal CLKD delayed by the delay time DLY7 in (80)
4 is input to the delay circuit 3 (82) and the inverter 81. Since the column flag is at the H level, the AND gate 83
, A one-shot pulse synchronized with the rise of CLKD4 is output, the set / reset circuit 79 is reset, and DCK1 changes from H level to L level.

At the rise of DCK1, the DFF 94 latches the output of the main amplifier 93. A signal C obtained by delaying CLKD3 by the delay time DLY6 by the delay circuit 6 (59)
LKD5 is input to the delay circuit 3 (56) and the inverter 71, and a one-shot pulse synchronized with the rise of CLKD5 is output. The set reset circuits 66 and 70 are reset, MAEN, YLEN, and / PRS fall from H level to L level, and the main amplifier 7 stops operating. The data lines and / or data lines are precharged in preparation for reading of the next data, and the column signals YL0 to YLM are read.
Are all at L level, and Nch transistor TG00
To TGM0 and TG01 to TGM1 are all turned off.

At time t3, the column flag in FIG. 3 is at the H level, the first and second inputs are both at the L level, and the / write enable signal 3 is at the H level.
The output of the ND-NOR composite gate 45 becomes H level.
Since the output of the inverter 48 is at L level and the outputs of the OR gate 61 and the AND gate 62 are both at H level,
When the DFF 63 goes high at time t3, the data output enable signal (hereinafter abbreviated as DOEN) changes from low to high.

In the timing generation circuit 89 of FIG.
A signal obtained by delaying the clock input by the delay circuit 8 by the delay time DLY8 is input to the AND gate 84. Since DOEN is at the H level, as shown in the timing chart of FIG.
Data latch clock 2 at timing delayed by Y8
(Hereinafter, abbreviated as DCK2) changes from the L level to the H level. At this timing, the DFF 94 in FIG.
Is latched by the DFF 95.

At this time, since DOEN is at H level, D
The output of the FF 95 passes through the tri-state buffer 96.
As a result, data D1 is output from the data input / output as shown in the timing chart of FIG. After the column address COL1 corresponding to the data D1 is latched by the clock input at the time t2, the logic unit 12 captures the data D1 at the rise of the clock at the time t4 two clocks later. This completes the reading of data from the memory cell corresponding to the column address COL1.

At times t3, t4 and t5, time t
As in the case of 2, the first
And the second input are both at L level, and the / write enable signal is at H level. Therefore, as described above, the column address is latched at the rising edge of the clock, and the data of the memory cell selected by the latched column address 3 is sequentially read out to the data input / output as shown in the timing chart of FIG. At time t7, the first input and the second input are both at the H level, and the output of the AND / NOR composite gate 45 is at the L level. Therefore, the DFF 63 is at the L level, and the DOEN is at the L level. The output of the output data becomes high impedance.

Next, a write operation in the page mode of the DRAM 1 will be described with reference to a timing chart of FIG. The operation at times t0 and t1 is the same as the read operation in the page mode described above. That is, at time t0, the signal R obtained by synchronizing the first input, which is the row address control signal, with the clock by the DFF 44 in FIG.
Since ASL is at L level, it is precharged to 1/2 Vdd and equalized.

At time t1, the signal RASL whose first input is synchronized with the clock goes high, so that the precharging and equalizing of the bit lines 0 to M and / bit lines 0 to M are stopped, and the row address latch 50 latches the row address by the clock input and outputs the row address 3. Since RASL is at the H level, the row line WLn selected by the row address 3 goes to the H level, and in FIG.
The sense amplifier enable, which is the output of delay circuit 1 (54), goes high after time DLY1 from time t1. As a result, the sense amplifiers S0 to SM are activated and WLn
Is read out to the bit lines 0 to M and differentially amplified by the sense amplifiers S0 to SM.

At time t2, the second input is performed together with the first input.
Is low (column address control signal),
The outputs of the inverters 41 and 42 in FIG.
The AND gate 51 goes high, and the column address latch 53 is enabled. At time t2, the column address is latched at the rising edge of the clock, and the column flag output from the DFF 52 goes high. At the same time, the output of the inverter 43 is latched at the rising edge of the clock in the DFF 47 and the / write enable signal is at the L level, so that the write flag output from the DFF 47 is at the H level
Level, and the read flag output from the inverter 85 becomes L level. Since the output of the inverter 43 is at the H level and the output of the AND gate 51 is at the H level,
The output of the D gate 111, that is, the write data latch enable signal goes high. As a result, the input data is latched at the rising edge of the clock. Since the / write enable signal 3 is at L level, the output of the AND / NOR composite gate 45 becomes L level, the output of the inverter 48 becomes H level, and the output of the OR gate 61 becomes H level. Since the output of the AND gate 62 is at L level, the output of the DFF 63, that is, DOEN, becomes L level at the rise of the clock.

The operation of the timing generation circuit 89 will be described. The clock input is the time DLY by the delay circuit 2 (55).
The signal delayed by two is the delay circuit 3 (56) and the inverter 6
4 is input. Since the column flag is at H level, AND
A one-shot pulse is output from gate 65, and set / reset circuit 66 is set. When / DPRS rises at a timing delayed by the delay time DLY2 from time t2, the precharge and equalization of the data line are released, and the column selection enable signal YLEN rises at the same time.

When YLm, which is the column signal selected by the column address 3 by the column selection circuit 4, goes high, the Nch transistors TGm0 and TGm1 turn on, and the output of the sense amplifier Sm is applied to the data line and / data line. Can be At the same time, since the write flag is at the H level, the output of the set / reset circuit 66 is output from the AND gate 69,
The write input enable signal is delayed for a delay time DL from time t2.
It rises from the L level to the H level at a timing delayed by Y2.

When the write input enable signal goes high, the tri-state buffer 97 and tri-state inverter 98 are enabled in FIG.
The bit line m and / or the bit line m are forcibly rewritten with the information voltage of the signal obtained by latching the data input which is the output of the FF 112, and this information voltage is written to the memory cell Mnm. Since the read flag is at the L level, the AND gate 78 and the AND gate 68 in the timing generation circuit 89 go to the L level, and the set reset circuit 79 and the set reset circuit 70 are not set. Therefore, during the write operation, DCK1 and MAEN are fixed at the LOW level, and the main amplifier 93 stops operating.

Since DOEN is at L level, A
The ND gate 84 goes low, and DCK2 is fixed at the low level. Further, CLKD3 is supplied to delay circuit 6 (59).
, The signal CLKD5 delayed by the delay time DLY6 is input to the delay circuit 3 (56) and the inverter 71,
A one-shot pulse synchronized with the rise of 5 is output. The set reset circuits 66 and 70 are reset,
YLEN and / PRS fall from the H level to the L level, the data lines and / data lines are precharged in preparation for the next data read, all the column signals YL0 to YLM go to the L level, and the Nch transistors TG00 to TG
M0 and TG01 to TGM1 are all turned off.

At times t3, t4 and t5, time t2
Similarly, at the rising edge of the clock input, the first and second inputs are both at the L level and the write enable signal is at the L level. Therefore, as described above, the column address is latched at the rising edge of the clock. Then, the input data latched at the rising edge of the clock is written to the memory cell selected by the latched column address 3.

As described above, when the clock input changes from L level to H level, both the row address control signal (first input) and the column address control signal (second input) are at L level. , / Write enable signal is at H level, the data of the memory cell selected by the row address and the column address is read. When the clock input changes from L level to H level, if both the row address control signal and the column address control signal are at L level and the / write enable signal is at L level,
Data is written to the memory cell selected by the row address and the column address. With such a DRAM circuit configuration, when reading or writing is continuously performed in the page mode of the DRAM, both the row address control signal and the column address control signal are set to L level, and the column address is set to the clock signal. , Data is read or written continuously each time the clock signal changes. Therefore, control becomes easier as compared with the conventional general DRAM described above.

The row address control signal (first input), column address control signal (second input), row address, column address, input data, and / or write enable signal are synchronized with clock input to generate timing. The circuit (89 in FIG. 3) generates the rising and falling timings of the read and write control timing signals of the memory cell only from the clock input. Therefore, the timing generation circuit can be realized with a simple circuit configuration. When the logic section 12 accesses the DRAM 1 by the operation of the signal selection circuit (34 in FIG. 1), the row address and the column address can be given simultaneously from the respective output ports, thereby facilitating the address control. be able to. In other words, a circuit for multiplexing and outputting a row address and a column address in the logic unit is not required, thereby simplifying the circuit and reducing power consumption.

Next, the operation of the signal selection circuit 34 when testing the integrated circuit 200 including the DRAM 1 as described above will be described. In FIG. 1, during a test, an externally applied test signal is at H level, and a test mode signal is at L level.
Therefore, the switching signal 1 inside the integrated circuit 200 is fixed at the H level, and the burn-in test signal and the switching signal 2 are fixed at the L level. Therefore, the selectors 22 to 24, 26, 2 of the signal selection circuit 34
Since the A input is selected at 7, 113, the external input terminal 1
The signals passing through the tri-state buffer 116 are selected from the signals # 3 to # 5 and the external input / output terminal. The selectors 28 to 32 and 114 select the B input, that is, the output signals of the selectors 22 to 24, 26, 27 and 113.

As a result, the DRAM 1 has the external input terminal 1
, 3, 5 and external input / output terminals. That is, the external input terminal 1 is selected as the first input, and the external input terminal 2 is selected as the second input. Also,/
The external input terminal 3 is selected as a write enable signal, the external input terminal 5 is selected as a row address and a column address, and the external input / output terminal is selected as a data input. Further, the selector 25 selects the B input, and the selector 3
Since 3 selects the A input, the signal of the external input terminal 4 is selected as the clock input. At this time, the input of the logic unit is fixed at the L level by the one-input inverted two-input AND circuits 17 to 21, and the logic unit does not operate.

As the address input of the DRAM, both the row address and the column address are input from the external input terminal 5. That is, in order to suppress an increase in the number of external terminals of the integrated circuit 200 for testing the built-in DRAM 1, a signal obtained by multiplexing a row address and a column address is output to the external input terminal 5.
Give from. The operation of the DRAM during the test and the operation of the discrimination circuit for separating the row address and the column address will be described with reference to the control circuit diagram of FIG. 3 and the read operation timing chart at the time of test of FIG.

As described above, during the test, the DRAM is controlled by an external input. That is, a clock input input from the external input terminal 4, a first input input from the external input terminal 1, a second input input from the external input terminal 2, and a write enable input from the external input terminal 3. A signal, a signal obtained by multiplexing a row address and a column address input from the external input terminal 5, and a data input input from the external input / output terminal are input to the DRAM.

As shown in FIG. 8, when a clock input, first and second inputs, a / write enable signal, and a signal obtained by multiplexing a row address and a column address are input,
In the row address latch enable, the signal obtained by inverting the first input in the discrimination circuit of FIG.
Since the signal is latched by the FF 44 and further inverted by the inverter circuit 49, it changes from the H level to the L level a little after the time t1, and similarly changes from the L level to the H level a little after the time t7. Since the row address latch 50 in FIG. 3 takes in data at the rising edge of the clock input when the row address latch enable is at the H level, it takes in the row address data ROW1 at time t1. When the row address latch enable is at the L level, data is held.
ROW1 is output from 1 to t8, and becomes a signal of only the row address.

The column address latch enable is such that the first input in the determination circuit 118 of FIG.
, And the output signal of the AND circuit 51 which receives the signal obtained by inverting the second input by the inverter circuit 42, the second input is changed from the H level to the L level after the time t1.
After changing to L level, it changes from L level to H level,
Similarly, after the time t6, the first input changes from the L level to the H level, and then changes from the H level to the L level.

Since the column address latch 53 takes in data at the rising edge of the clock input when the column address latch enable is at the H level, it takes in the column address data COL1 at time t2, and takes in the column address data COL2 at time t3. At time t4, the column address data COL3 is fetched, and at time t5, the column address data C
OL4 is taken in, and at time t6, the column address data CO
Import L5. Therefore, the column address 3 outputs COL1 to COL5 from time t2 to time t7, and becomes a signal of only the column address. As described above, the signal of the external input terminal 5 obtained by multiplexing the row address and the column address is determined by the determination circuit 118.
Separates into a row address and a column address. In the subsequent operation, data in the memory cell specified by the row address 3 and the column address 3 is read out and output to the external input / output terminal as in the normal operation. At the time of a write operation, similarly, a row address and a column address are separated by the determination circuit 118, and data is written by specifying a memory cell.

As described above, at the time of the DRAM test, a signal obtained by multiplexing the row address and the column address is externally supplied, and the discrimination circuit 118 separates the row address and the column address. The increase in the number of external terminals of the circuit is suppressed.

(Embodiment 2) FIG. 5 shows a system configuration of a burn-in test apparatus 300 for an integrated circuit according to Embodiment 2 of the present invention. In the figure, reference numeral 46 denotes a burn-in test signal generator, which outputs a burn-in test pattern signal and a DR of a logic section (microcomputer or logic circuit).
An AM clock signal and a burn-in switching signal are generated. k00 to kmn are a plurality of sockets for simultaneously testing a plurality of integrated circuits, and are mounted on a burn-in board 100 for a burn-in test.

Hereinafter, a method for performing a burn-in test on an integrated circuit using the burn-in test apparatus 300 will be described. Test mode signal of integrated circuit 200 (see FIG. 1)
Is fixed at the H level on the bind board 100, and when the burn-in test signal generator 46 sets the burn-in switching signal to the L level, the selectors 28 to 32 of the integrated circuit 200
1 is set to a mode in which the DRAM 1 is controlled by a signal of the logic unit 12 to select and output the A input. The burn-in test signal generator 46 supplies a burn-in test pattern signal of the logic section to sockets k00 to kmn on the burn-in board 100,
The clock signal for use is stopped, and a burn-in test of the logic section of the integrated circuit 200 is performed using a DRAM. When the burn-in test of the logic section is completed, the burn-in test signal generator 46 sets the burn-in switching signal to the H level, stops the logic section test pattern signal generator, and outputs the DRAM clock signal to the sockets k00 to kmn.
Is applied. The integrated circuit 200 has the test mode signal H
Level and the burn-in switching signal is H
Therefore, the output of the AND gate 13 goes high, and the burn-in test signal goes high. As a result, the burn-in pattern generation circuit 11 starts operating, and the switching signal 1 output from the NOR gate 15 becomes low.
Level, and the signals of the external input terminals 1 to 5 which are dual-purpose terminals are input to the logic unit 12 via the logic gates 17 to 21.

At this time, since the switching signal 2 output from the inverter 16 becomes H level, the selectors 22 to 27
Selects the B input, and the selectors 28 to 32 select the B input. Therefore, an output signal of the burn-in pattern generation circuit 11 is provided as a first input, a second input, a write enable signal, a clock input, a row address, a column address, and input data of the DRAM 1. As shown in the timing chart of FIG. 9, the burn-in pattern generation circuit 11 supplies the DRAM 2 with the clock 2 obtained by dividing the clock input from the external input terminal 4, and supplies the row address control signal 2, the column address control signal 2. Write enable control signal 2, row address 2, column address 2, and burn-in input data are generated.

In the first write cycle, burn-in input data (data A in FIG. 9) is written to the address specified by row address 2 and column address 2, and data A of the same address is read in the next read cycle. When the read cycle ends, the row address is incremented without changing the column address, and writing and reading are performed in the same manner. Writing and reading of the entire address space are repeated while incrementing the address, and a burn-in test of the DRAM is performed by applying stress to the memory cells.

As described above, since the integrated circuit with a built-in DRAM of the present invention is provided with the burn-in pattern generating circuit for the DRAM test, the external signals necessary for the burn-in test of the DRAM are the clock signal for the DRAM and the burn-in switching signal. Only two are required. Therefore, there is almost no need to change the specifications of the burn-in board between the burn-in of the logic section and the burn-in of the DRAM, and the burn-in test of the logic section and the DRAM can be performed using the same burn-in board. In addition, the mode can be switched between the burn-in of the logic unit and the burn-in of the DRAM by software from outside using the burn-in switching signal, so that the test becomes efficient.

If the burn-in switching signal is set to L level and the logic section is set to the mode in which the DRAM is controlled, the burn-in test of the logic section can be performed by using the DRAM. No need to exchange signals. The number of test pins can be reduced as compared with the case where the burn-in test is performed by the logic alone, and the need to externally create a test pattern to be given to the integrated circuit is eliminated. Furthermore, if the test of the logic portion is performed by writing test pattern data in the DRAM in advance from an internal circuit or an external device, the operation can be performed at a higher speed than in the case where a test pattern is externally provided, so that the test time is reduced. .

(Embodiment 3) Next, a burn-in test of an integrated circuit according to Embodiment 3 of the present invention will be described. When the burn-in switching signal from the burn-in test signal generator 46 is set to H level in FIG. 5 with the test mode signal fixed at H level, the output of the AND gate 13 of the integrated circuit 200 becomes H level in FIG. The burn-in test signal goes high. Further, in the signal selection circuit 34, the switching signal 1 which is the output of the NOR gate 15 becomes L level, and the signals of the external input terminals 1 to 5 which are the shared terminals are changed to the logic gates 17 to 21.
And is input to the logic unit 12.

At this time, since the switching signal 2 output from the inverter 16 becomes H level, the selectors 22 to 27
Selects the B input, and the selectors 28 to 32 select the B input. As a result, an output signal of the burn-in pattern generation circuit 11 is provided as a first input, a second input, a write enable signal, a clock input, a row address, a column address, and input data of the DRAM 1. Since the burn-in test signal is at the H level, the burn-in pattern generation circuit 11 repeats writing and reading of the entire address space while incrementing the address in the same manner as in the second embodiment, and applies stress to the memory cells to thereby increase the DRAM. Burn-in test is performed. At the same time, the burn-in test signal generator 46 gives a burn-in test pattern of the logic section to the sockets K00 to Kmn on the burn-in board by a plurality of signals including the external input terminals 1 to 5. In this way, the burn-in test of the DRAM is performed simultaneously with the burn-in test of the logic unit 12.

As described above, the integrated circuit 2 of the present invention
Since 00 has a DRAM burn-in pattern generation circuit, only external signals required for a DRAM burn-in test are a DRAM clock signal and a burn-in switching signal. Therefore, by switching the external input terminals 1 to 5 and the external input / output terminal so that they can be used in the logic unit by the signal selection circuit 34, even when the burn-in test of the logic unit is performed in parallel with the burn-in test of the DRAM, the clock for DRAM is All external terminals other than the signal, the burn-in switching signal, and the test mode signal can be used for the burn-in test of the logic unit.
In this way, the burn-in test of the logic section requiring many external terminals can be performed in parallel with the burn-in test of the DRAM.

With the advance of semiconductor miniaturization technology, the capacity and bit width of a built-in DRAM have increased,
Even if the number of test signals for the DRAM increases and the number of dual-purpose terminals for testing the DRAM increases, the dual-purpose terminals can be used as external terminals for performing the burn-in test of the logic section. The burn-in test of the logic unit can be performed in parallel without any trouble. As a result, the test time at the time of burn-in can be reduced.

[0063]

As described above, the DRAM of the present invention
According to the circuit configuration of (1), when reading or writing is continuously performed in the page mode, the row address control signal is set to L level, the column address control signal is set to L level, and the column address is given in synchronization with the clock. Data reading or writing is performed continuously every time the clock changes. As a result, control of the DRAM can be facilitated.

Further, since the row address control signal, the column address control signal, the row address, the column address, the input data, and the / write enable signal are synchronized with the clock input, the rising and falling of the control timing signal for reading and writing of the memory cell. A timing generation circuit that generates a falling timing only from a clock input can be realized with a simple circuit configuration.

According to the integrated circuit with a built-in DRAM of the present invention, the address control inside the integrated circuit is facilitated, the circuit in the logic section is simplified, and the power consumption is reduced. Therefore, it is possible to suppress an increase in the number of external input terminals required. Further, according to the burn-in test method for an integrated circuit of the present invention, the test time can be reduced by effectively using the built-in DRAM.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a system configuration diagram of a DRAM built in the integrated circuit of FIG. 1;

FIG. 3 is a control circuit diagram in the integrated circuit of FIG. 1;

FIG. 4 is a circuit diagram of a memory cell and its periphery in the integrated circuit of FIG. 1;

FIG. 5 is a system configuration diagram of a burn-in test apparatus according to Embodiments 2 and 3 of the present invention.

FIG. 6 shows a DRAM during a normal operation of the integrated circuit of FIG.
Timing chart in page mode

FIG. 7 is a diagram illustrating a DRAM during a normal operation of the integrated circuit of FIG. 1;
Timing chart in page mode

8 is a timing chart of a read operation of the DRAM during the test of the integrated circuit of FIG. 1;

9 is a timing chart of a burn-in pattern generation circuit in the burn-in test device of FIG.

FIG. 10 is a system configuration diagram of a conventional general DRAM.

FIG. 11 is a timing chart of a page mode read operation of the conventional DRAM in the EDO system.

[Explanation of symbols]

 Reference Signs List 1 DRAM 2 control circuit 3 row selection circuit 4 column selection circuit 5 memory cell array 6 sense amplifier 7 main amplifier 11 burn-in pattern generation circuit 12 logic section 34 signal selection circuit 46 burn-in test signal generator 50 row address latch 53 column address latch 89 timing Generation circuit 100 Burn-in board 118 Discrimination circuit 200 Integrated circuit 300 Burn-in test device

Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 11/34 371A

Claims (7)

[Claims] 1. A memory cell array in which a memory cell to be read or written is specified by a clock input, a first input for controlling a row address, a second input for controlling a column address, a row address and a column address, and A sense amplifier for amplifying the data of the memory cell output to the column line of the memory cell array, and as a signal synchronized with the first input to the clock input changes to a first logic level, The sense amplifier amplifies data of a memory cell connected to a row line selected by a signal in which the row address is synchronized with the clock input. Subsequently, each time the clock input changes, the first The input is at a first logic level and the second
If the input is a predetermined logical level, data is read or written by a sense amplifier connected to a column line selected by a signal in which the column address is synchronized with the clock. 2. A DR having a row address and a column address.
An integrated circuit including an AM and a logic unit, wherein the logic unit supplies a row address and a column address to the DRAM during a normal operation, and a signal obtained by multiplexing the row address and the column address during a test of the DRAM. An integrated circuit provided externally. 3. An integrated circuit including a DRAM and a logic unit, wherein the signal selection circuit selects one of an address signal from an external input terminal and an address signal from the logic unit and supplies the selected signal to the DRAM. During normal operation, the signal selecting circuit simultaneously selects the row address and column address signals output from the logic unit,
The signal selection circuit selects a signal in which a row address and a column address input from the external input terminal are time-division multiplexed and supplied to the RAM when testing the DRAM.
An integrated circuit provided to an AM, wherein a determination circuit in the DRAM separates the time-division multiplexed signal into a row address and a column address. 4. A DRAM, a logic unit, and the DRA
A test pattern generation circuit for performing a burn-in test for M, and an external circuit for selecting a mode for performing a burn-in test for the DRAM or a mode for performing a burn-in test for the logic unit based on a signal generated by the test pattern generation circuit. An integrated circuit, comprising: an input terminal. 5. A DRAM, a logic unit, and the DRA
An integrated circuit including a test pattern generating circuit for performing a burn-in test of M, a plurality of external terminals shared by the DRAM, the logic unit, and the test pattern generating circuit, and a signal selection of the external terminal. A logic unit normally uses the external terminals during normal operation, uses the external terminals during the operation test of the DRAM, and uses the external terminal during a burn-in test of the DRAM by the test pattern generation circuit. An integrated circuit, wherein the signal selection circuit switches a connection destination of the external terminal so that a terminal is used by the test pattern generation circuit and a logic unit. 6. A DRAM, a logic unit, and the DRA
A burn-in test method for an integrated circuit including a test pattern generation circuit for performing a burn-in test of M. The test pattern generation circuit generates a test pattern by setting a predetermined external input signal to a first logic level. The read / write operation of the DRAM is performed based on a signal to be performed, a burn-in test of the DRAM is performed by applying a stress to a memory cell, and the external input signal is set to a second logic level. A burn-in test for an integrated circuit. 7. The integrated circuit burn-in test method according to claim 5, wherein in said burn-in test of said logic unit, said logic unit accesses said DRAM.