JPH0991192A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent management information from being enlarged by providing a memory controller for mediating a filling processing by a background device and memory access from a CPU. SOLUTION: When a CPU 10 desires to fill a filling area 16 inside a memory 14 with certain filling data, the CPU 10 searches a free entry inside a filling area management table 13, marks the entry while using and then, sets the leading address of the filling area 16, a length and the filling data. At the point of time, the CPU 10 ends a filling operation. When the entry is detected, a background filling device 12 starts the filling processing of the filling area 16. In this case, even while the filling processing to the filling area 16 by the background filling device 12 is performed, the CPU 10 can perform read or write to the filling area 16. Access mediation at the time is performed by this memory controller 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller in a computer system, and more particularly to a controller for filling a memory device with a specific value.

[0002]

2. Description of the Related Art A conventional memory control device of this type is disclosed, for example, in Japanese Patent Laid-Open Publication No. Hei 4-9745.
As described in 5), a technique for simultaneously writing 0 data in parallel to a plurality of memory chips for the purpose of speeding up the memory area zeroization, or further speeding up the memory area zeroing Therefore, as described in Japanese Patent Laid-Open Publication No. "Memory Device" (SHO 59-186015), the memory area is not actually cleared to 0, but 0
A typical technique is to store an address to be cleared in an address memory and, when this address is registered, prevent the read address from being supplied to the memory body and artificially clear the address to zero. .

[0003]

The above-mentioned conventional memory control device has a drawback that the CPU cannot proceed to the previous process until the memory area is completely zeroed in the former case, and the latter has been filled. When writing is performed randomly in the area, there is a problem that the management information of the filled portion and the non-filled portion becomes large.

[0004]

According to a first aspect of the present invention, in a memory control device in a computer system including a CPU and a memory, information on a fill area to be filled with a specified value in the memory according to an instruction from the CPU. A fill area management table for holding the background area, a background fill device for performing a fill processing of the fill area according to the information of the fill area of the fill area management table, a fill processing by the background apparatus, and a memory access from the CPU And a memory controller that arbitrates.

The second invention is the same as the first invention.
The memory controller executes a normal access when the access target of the CPU is outside the fill area, and when the access target is inside the fill area and the access is read. The CPU
It is characterized in that the fill data is returned to, and when the access is writing, the writing operation is executed after waiting until the filling of the access portion is completed.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an operation flow chart of the memory controller 11 in FIG.

Referring to FIG. 1, in this embodiment, a CPU 10 for reading and writing memory, a memory device 14, a memory bus 15, and a fill area management table 13 for holding a memory area to be filled with a designated value. A background fill device 12 that executes memory fill in the background according to the contents of the fill area management table, and a memory controller 11 that arbitrates the fill operation in the background and memory access from the CPU.

The CPU 10 causes the fill area 1 in the memory 14 to be filled.
When you want to fill 6 with certain fill data, CPU10
Searches for an empty entry in the fill area management table 13, marks the entry as being used, and then sets the start address, length, and fill data of the fill area 16. At that point, the CPU 10 finishes the filling operation.
When the background filling device 12 detects this entry, the filling process of the filling device 16 is started. When the filling is completed, the corresponding entry in the fill area management table 13 becomes empty again, and is used when a filling occurs in the future.

Even while the background area filling device 12 is performing the filling process on the filling area 16,
The CPU 10 can read from or write to the fill area 16. The access arbitration at this time is performed by the memory controller 11.

Next, the processing flow of the memory controller 11 will be described with reference to FIG.

In step 21, it is judged whether the access from the CPU is to a part of the fill area.
Step 2 if the access target is outside the fill area
Then, the process proceeds to 6 to execute a normal access and finish the process. If the access target is in the fill area, it is further determined in step 22 whether the access is read or write. If the access is read, step 2
5, the fill data is returned to the CPU, and the process ends. If the access is writing, the process proceeds to step 23, waits until the filling of the access portion is completed, and then proceeds to step 24 to execute the write operation and terminate the process. At this time, it is not necessary to wait for the fill processing up to the end of the fill area.

As described above, according to the present invention, the CPU can read and write even during the memory filling.

[0014]

As described above, the memory control device of the present invention can apparently reduce the memory fill time to 0, and the memory C can be filled while the memory is being filled.
The PU can freely access the memory as if the fill has been completed, and the management information does not become large.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a process flow chart showing an operation of the memory controller of FIG.

[Explanation of symbols]

 10 CPU 11 Memory Controller 12 Background Fill Device 13 Fill Area Management Table 14 Memory 15 Memory Bus 16 Fill Area

Claims (2)

[Claims] 1. In a memory control device in a computer system including a CPU and a memory, a fill area management table holding information on a fill area to be filled with a specified value in the memory according to an instruction from the CPU, A background fill device that executes a fill process of the fill region according to the information of the fill region in the fill region management table, and a memory controller that arbitrates the fill process by the background device and the memory access from the CPU And a memory control device. 2. The memory controller is the CPU
If the access target is outside the fill area, a normal access is executed, and if the access target is inside the fill area and the access is read, the fill data is returned to the CPU. The memory control device according to claim 1, wherein when the access is a write, the write operation is executed after waiting until the filling of the access portion is completed.