JPH0991162A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of preventing data from being initialized when fine abnormality is generated in the data used for controlling a game operation. SOLUTION: In a RAM, the data including the control data of a large winning flag or the like used for controlling the game operation and plural pattern data used for discriminating the abnormality of the control data are stored. Then, the pattern data are read and whether or not the read data are turned to abnormal data is discriminated (SA4, SA5 and SA7). Then, when it is discriminated that all the pattern data among the plural pattern data are abnormal, a processing for initializing the storage data of the RAM is performed (SA9).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine represented by, for example, a pachinko gaming machine, a coin gaming machine, a slot machine, or the like. More specifically, it has a gaming control computer, and a gaming control computer controls the gaming operation. Controlled gaming machine

[0002]

2. Description of the Related Art In this type of gaming machine, a generally known one has a microcomputer for controlling the gaming machine by executing a control program stored in a memory such as a ROM. There was something.
In such a conventional gaming machine, the control data used for controlling the game operation is stored in the RAM which is the storage means, and the control data is used to control the game operation by executing the control program. It was.

In such a gaming machine, the control data stored in the RAM may be rewritten into abnormal data due to the intrusion of noise, which may cause abnormal control of the game operation. there were. Therefore, in the conventional gaming machine, it is determined whether or not an abnormality has occurred in the data stored in the RAM, and if the abnormality has occurred, a process of returning the gaming machine to a normal state has been performed.

As a typical example of the processing for determining the abnormality of the data stored in the RAM and returning the game machine to the normal state, R
A process of checking the stored data in the AM and initializing (clearing) the stored data in the RAM when the checked stored data is abnormal data is performed.

Specifically, the following processing is performed. Two kinds of pattern data (data having a predetermined data pattern) for abnormality determination are written in the RAM,
These pattern data are appropriately sampled, and it is determined whether or not each sampled pattern data and the correct pattern data corresponding to each pattern data match. Then, when it is determined that one of the pattern data does not match the correct pattern data, it is considered that the storage data of the RAM has become abnormal data, and the processing of initializing the storage data of the RAM is performed.

[0006]

However, the conventional game machine of this type, which performs the above-described pattern data abnormality determination processing, has the following problems. If one of the two types of pattern data becomes abnormal, R
Since the stored data of the AM is initialized, for example, when a big hit state (specific game state) advantageous to the player occurs, a slight abnormality that does not greatly hinder the progress of the game operation occurs. However, the game operation may be initialized, which may be disadvantageous to the player.

As described above, in the conventional gaming machine, the stored data in the RAM is initialized even when one of the two types of pattern data becomes abnormal, so that the game operation proceeds. There is a problem that the operation of the gaming machine is initialized even when a slight abnormality that does not cause a large trouble occurs.

The present invention has been conceived in view of such circumstances, and an object thereof is to prevent the data used for game control from being initialized when a slight abnormality occurs. It is to provide a possible game machine. In other words, its purpose is to provide a gaming machine capable of initializing the data used for the game control only when the normal progress of the game control is hindered.

[0009]

The present invention according to claim 1 is a game machine having a game control computer, the game operation of which is controlled by the game control computer.
Storage means for storing data including control data used for controlling the game operation and a plurality of abnormality determination data used for determining an abnormality of the control data, and the plurality of abnormality determination data are read and read. An abnormality determining means for determining whether or not the data is abnormal data,
An initialization unit that initializes the storage data of the storage unit when the abnormality determination unit determines that the specific abnormality determination data out of the plurality of abnormality determination data is abnormal. To do.

According to a second aspect of the present invention, there is provided a game control computer having a game control computer, the game operation of which is controlled by the game control computer. Control data used for controlling the game operation and Storage means for storing data including a plurality of abnormality determination data used for determining abnormality of the control data, and whether or not the plurality of abnormality determination data are read and the read data is abnormal data. And an initialization for initializing the storage data of the storage means when the abnormality determination means determines that all the abnormality determination data of the plurality of abnormality determination data are abnormal. And means.

According to a third aspect of the present invention, there is provided a game control computer, and when the game operation is controlled by the game control computer and a predetermined condition is satisfied, an advantageous specification for the player is specified. A gaming machine controlled to a gaming state, storing means for storing data including control data used for controlling the game operation and a plurality of abnormality determination data used for determining an abnormality of the control data; Abnormality determination means for reading a plurality of abnormality determination data and determining whether or not the read data is abnormal data, and a plurality of the abnormality determination means in a state where the gaming machine is not controlled to the specific gaming state. When the specific abnormality determination data of the abnormality determination data is abnormal by the abnormality determination means, the storage data of the storage means is initialized. In the state where the initialization unit 1 and the gaming machine are controlled to the specific game state, the abnormality determination unit determines that a predetermined number of abnormality determination data are abnormal in addition to the specific abnormality determination data. And a second initialization means for initializing the data stored in the storage means.

According to a fourth aspect of the present invention, a game control computer is provided, and when the game operation is controlled by the game control computer, and a predetermined condition is satisfied, an advantageous specification for the player is specified. A gaming machine controlled to a gaming state, having a plurality of storage areas for storing control data used for controlling the gaming machine, and a specific gaming control indicating whether or not to control the specific gaming state. Storage means for storing data in a distributed manner in the plurality of storage areas;
Consistency determining means for reading out the plurality of specific game control data distributed and stored in the plurality of storage areas of the storage means and determining whether or not the read data match.
It is characterized by including an initialization means for initializing the storage data of the storage means when the match determination means determines that the plurality of specific game control data do not match.

[0013]

According to the present invention as set forth in claim 1, the storage means stores data including control data used for controlling the game operation and a plurality of abnormality determination data used for determining abnormality of the control data. It By the function of the abnormality determination means, a plurality of abnormality determination data are read and it is determined whether or not the read data is abnormal data. When the abnormality determination means determines that the specific abnormality determination data of the plurality of abnormality determination data is abnormal, the storage data of the storage means is initialized by the function of the initialization means. Therefore, when it is determined that the abnormality determination data other than the specific abnormality determination data is abnormal,
The data stored in the storage means is not initialized.

According to the second aspect of the present invention, the storage means stores the data including the control data used for controlling the game operation and the plurality of abnormality determination data used for determining the abnormality of the control data. It Due to the function of the abnormality determination means, a plurality of abnormality determination data are read and it is determined whether or not the read data is abnormal data. When all the abnormality determination data of the plurality of abnormality determination data are determined to be abnormal by the abnormality determination means, the storage data of the storage means is initialized by the function of the initialization means. Therefore, even if a part of the abnormality determination data among the plurality of abnormality determination data becomes abnormal, the storage data of the storage unit is not initialized.

According to the third aspect of the present invention, the storage means stores the data including the control data used for controlling the game operation and the plurality of abnormality determination data used for determining the abnormality of the control data. It Due to the function of the abnormality determination means, a plurality of abnormality determination data are read and it is determined whether or not the read data is abnormal data. The function of the first initialization unit when the abnormality determination unit determines that the specific abnormality determination data of the plurality of abnormality determination data is abnormal in the state where the gaming machine is not controlled to the specific game state Thereby, the storage data of the storage means is initialized. In the state where the gaming machine is controlled to the specific gaming state, when the abnormality determining unit determines that the predetermined number of abnormality determining data is abnormal in addition to the specific abnormality determining data, the second initializing unit By work,
The storage data of the storage means is initialized. Therefore, in the state where the gaming machine is controlled to the specific gaming state,
Compared with the state in which the gaming machine is not controlled to the specific game state, the stored data in the storage means is less likely to be initialized.

According to the present invention as set forth in claim 4, in the storage means having a plurality of storage areas in which the control data used for controlling the game operation is stored, it is indicated whether or not the specific game state is controlled. Specific game control data is distributed and stored in a plurality of storage areas. By the operation of the match determination means, a plurality of specific game control data stored in the storage area of the storage means in a distributed manner are read, and it is determined whether or not the read data match. When the match determination means determines that the plurality of specific game control data do not match, the operation of the initialization means initializes the storage data of the storage means. Therefore, the control of the specific game state due to a malfunction is suppressed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In the following embodiments, a pachinko game machine is shown as an example of a game machine, but the present invention is not limited to this, and may be a coin game machine, a slot machine, or the like, and a game control microcomputer. It is possible to apply to any gaming machine that has a game control operation by the game control microcomputer.

FIG. 1 is a front view showing a structure of a gaming board surface of a pachinko gaming machine which is an example of the gaming machine according to the present invention. A game area 3 is formed on the front surface of the game board 1 of the pachinko gaming machine. The pachinko gaming machine is provided with a batting ball operation handle (not shown) for the player to operate a batting ball, and by operating the batting ball operation handle, a pachinko ball can be launched one by one. it can. The fired pachinko balls are guided into the game area 3 between the section rails 2. The pachinko balls that are hit in the game area 3 are called "hit balls" in the following description.

At the center of the game area 3, there is provided a variable display device 4 for variably displaying a plurality of types of images including identification information (special symbols) consisting of a plurality of types of symbols and the like.
The variable display device 4 has a variable display section 5 composed of a CRT in this embodiment. An image is displayed on the variable display unit 5.

The special symbols displayed on the variable display device 4 are:
For example, three. That is, the special symbol is displayed on the left, middle, and right variable display sections on the screen of the variable display section 5. In the variable display unit 5, a background image is displayed, and special symbols (hereinafter, left symbol, middle symbol, right symbol) of the left, middle, and right variable display units are displayed in a row in a row at predetermined intervals in front of them. It These left, middle, and right symbols are also called left reel, middle reel, and right reel, respectively. Below the variable display device 4, a variable winning ball device 11 is provided. A variable starting port device 16 having a so-called electric accessory is provided at a position on the left side of the variable winning ball device 11 which is generally called a “sleeve portion”.

Side lamps 18 are provided at the left and right ends of the game area 3, respectively. A windmill lamp 30 is provided diagonally above each side lamp 18. In the upper part of the variable display device 4, a normal winning opening 9 is provided. Further, a normal winning opening 10 is provided at a position called "sleeve" at the lower right of the game area 3.

Next, the variable winning ball device 11 will be described in detail. The variable winning prize ball device 11 is provided with an opening / closing plate 14 that can be tilted in a predetermined range in the front-rear direction of the game area 3. The opening / closing plate 14 is driven by a solenoid 24 (shown by a broken line) provided on the back surface of the game board 1.

In the variable winning ball device 11, the opening / closing plate 14 is normally closed, which is disadvantageous to the player who does not win or is unlikely to win a ball (hereinafter, this condition is referred to as the "second condition"). That is). On the other hand, based on the fact that a hit ball has been won in the starting port 19 of the variable starting port device 16 or the starting port 13 provided on the upper part of the variable winning ball device 11, three special characters are displayed on the display unit 5 of the variable display device 4. A variable display (variable display) of the symbol is performed. When the variable display is stopped, a "big hit" occurs when the combination of the three special symbols becomes a predetermined specific combination (for example, 777). This big hit state is called a specific game state.

When a big hit occurs, the variable winning ball device 1
In the first state, the opening / closing plate 14 is in the opened state, and the first state is advantageous to a player who can win a ball at the large winning opening of the variable winning ball apparatus 11 that appears by the opening.

The first state of the variable winning ball apparatus 11 is that a predetermined time, for example, 29.5 seconds has elapsed after the opening / closing plate 14 is in the open state, or the large winning of the variable winning ball apparatus 11 is achieved. The process ends when a predetermined number (for example, 10) of hitting balls in the mouth is won, whichever comes first. That is, when the above conditions are established, the opening / closing plate 14 is closed and the variable winning ball device 11
Is the second state.

The hit balls that have won the special winning opening are detected by a prize winning detector 23 (shown by a broken line) provided on the back surface of the game board 1. In response to this detection, a predetermined number of pachinko balls (prize balls) are paid out. On the other hand, in the central portion inside the special winning opening, a specific area commonly called "V pocket" is provided. When the hit ball that has entered the special winning opening wins the specific area, the winning ball is detected by a specific ball detector 22 (shown by a broken line) provided on the back surface of the gaming board 1.

If a hit ball that has entered during the period in which the variable winning ball device 11 is in the first state wins the specific area and is detected by the specific ball detector 22, the first of the times (rounds). After waiting for the end of the above state, the second state is temporarily entered, and the repetitive continuation control for setting the variable winning ball apparatus 11 to the first state again is executed. The upper limit value of the number of times (round number) of the repetition continuation control is set to, for example, 15 times. The number of hit balls that have won the variable winning ball device 11 is as follows:
The number is displayed by the number display 15 composed of a seven-segment display.

Next, the starting winning will be described. Winning a ball at the starting opening 13 or 19 is particularly called "starting winning". The shot that wins the starting port 13 or 19 is
Starting ball detector 21 or 2 provided on the back of game board 1
5 (shown by broken lines). The variable display of the special symbol is started on the variable display unit 5 of the variable display device 4 in response to the fact that the ball is hit in the starting port 13 or 19. When a specific combination of special symbols (for example, 777) is displayed when the variable display is stopped, the variable winning ball device 11 enters the first state as described above.

While the variable display of the special symbol is being performed and while the variable winning ball device 11 is in the first state based on the result of the variable display of the special symbol, a ball is hit at the starting opening 13 or 19. If a prize is won, the starting prize is stored in a RAM (described later). This is called start memory (or start winning memory). The number of start memories is notified to the player by lighting of the start memory display 6 composed of an LED. The upper limit of the starting storage number is set to a predetermined number (for example, four). If there is a start memory, after the variable display of the special symbol on the variable display unit 5 is stopped or after the big hit state of the variable prize ball device 11 ends, the special symbol by the variable display unit 5 is again based on the start memory. Is started.

Next, the structure of the variable starting port device 16 will be described in detail. The variable starting port device 16 has the starting port 19 as described above. When a hit ball that has won the starting port 19 is detected by the starting ball detector 25 (shown by a broken line), variable display by the variable display device 4 is started. The variable starting port device 16 includes a pair of movable pieces 17 that can be opened and closed.
When the movable piece 17 is opened, a ball can be hit in the starting port 19.

A passage port 20 is provided in the left side area of the game area 3. The variable starting port device 16 is provided with a normal symbol variable display device 28. This ordinary symbol variable display device 28 is composed of, for example, a 7-segment display,
A plurality of types of identification information (normal symbols) can be variably displayed.

Whether or not the movable piece 17 is opened in the variable starting port device 16 is determined as follows. When the hit ball passes through the passage opening 20, the hit ball is detected by the passing ball detector 27.
(Shown by broken lines). The variable display of the ordinary symbol variable display device 28 provided on the variable starter device 16 is started based on the detected output. The variable display is continued for a predetermined time (for example, 25 seconds).

When the display result when the variable symbol display device 28 is normally stopped becomes the predetermined specific identification information (for example, 7), the movable piece 17 of the variable starting port 16 is operated by the solenoid 26 (shown by a broken line). It is driven and opened, and the ball is in an advantageous state for the player who can win the start ball 19. The opening period is a predetermined time (for example, 0.6
Seconds), or until a predetermined number of prizes have been won. When a ball hits in the starting port 19 of the variable starting port device 16, the hit ball is detected by a starting ball detector 25 (shown by a broken line). The variable display of the variable display unit 5 of the variable display device 4 is started based on the detection output.

If the ball hitting the ball again passes through the passage port 20 and is detected by the passing ball detector 27 while the normal variable design display 28 is variably displaying, the passing ball is stored.
Then, after the variable display of the ordinary symbol variable display device 28 is stopped, the variable display can be started again, and then the ordinary symbol variable display device 2 is again stored based on the storage of the passing balls.
8, the variable display is started. The storage of the passing balls is set to a predetermined number (for example, up to “4”). The stored number of passing balls is displayed by turning on a normal symbol start storage display 29 made of an LED.

To the left and right of the lower position of the variable display device 4, there are provided members for guiding the hitting balls, which are named warp entrances 7. The hit ball that has won the warp entrance 7 is guided to the warp exit 8 provided above the starting port 13 and is released again into the game area 3 and falls. For this reason, the hit ball that has entered the warp entrance 7 is relatively easy to win the starting opening 13. The provision of the warp entrance 7 and the warp exit 8 has an effect that the interest of the player becomes higher than in the case where they are not provided.

On the left and right sides of the variable winning ball device 11, normal winning holes 12 are provided. An out port 30 for accommodating out balls is provided at the lower center of the game area 3. In the vicinity of the warp exit 8, a decoration LED 31 is provided.
The decorative LED 32 is also provided on the opening / closing plate 14. In the vicinity of the winning opening 10, there is a sleeve lamp 33.
Is provided. A center lamp 34 is provided near the start memory display 6. A decoration LED 35 is provided below the winning opening 12, and decoration LEDs 36 are also provided on the left and right of the number display 15.

Next, the control circuit provided in this pachinko gaming machine will be described. First, a control circuit for performing game control of a pachinko gaming machine will be described. FIG. 2 and FIG.
It is a block diagram which shows the control circuit which performs the game control of a pachinko gaming machine. The control circuits shown in FIGS. 2 and 3 are formed on the main substrate.

With reference to FIGS. 2 and 3, this game control circuit includes a basic circuit 40, an input circuit 41, and an information output circuit 4.
2. Initial reset circuit 43, periodic reset circuit 44, address decode circuit 45, LED circuit 46, solenoid circuit 47, lamp circuit 48, illumination signal circuit 49, CRT
It includes a circuit 50, a voice synthesis circuit 51, a volume amplification circuit 52, a winning ball number signal output circuit 53, and a power supply circuit 54. Further, a CRT display 55 is connected to the CRT circuit 50.

Inside the basic circuit 40, a ROM 401 for storing a control program, a CPU 402 for performing a control operation according to the control program, and its C
RAM 40 functioning as work memory of PU 402
3 and an I / O port (not shown).

The address decoding circuit 45 is the basic circuit 4
Decode the address signal sent from 0
The ROM 401, RA included in the basic circuit 40
M403, a circuit for outputting a signal for selecting one of the I / O port and the like. Initial reset circuit 4
A circuit 4 outputs an initial reset pulse for resetting the basic circuit 40 when the power is turned on. The basic circuit 40 initializes the RAM 403 and the I / O port in response to the initial reset pulse sent from the initial reset circuit 44.

The regular reset circuit 44 outputs a reset pulse, which is a clock pulse for regular reset, to the basic circuit 40.
It is a circuit for supplying to. CPU 4 of basic circuit 40
Reference numeral 02 performs a reset process for repeatedly executing a predetermined control program from the beginning in response to a reset pulse periodically sent from the regular reset circuit 44. The reset pulse from the periodic reset circuit 44 is sent, for example, every 0.002 seconds.

The input circuit 41 includes starter ball detectors 21, 2
5, the winning ball detector 23, the specific ball detector 22, the passing ball detector 27, etc. are connected. If a hit ball is awarded in the starting port 13 and detected by the starting ball detector 21, a detection signal thereof is input to the basic circuit 40 via the input circuit 41. If the hit ball is awarded in the starting port 19 and is detected by the starting ball detector 25, this detection signal is input to the basic circuit 40 via the input circuit 41. If the hit ball wins the big winning opening and is detected by the winning ball detector 23, the detection signal is input to the basic circuit 40 via the input circuit 41. When a hit ball is awarded in a specific area and detected by the specific ball detector 22, the detection signal is sent to the basic circuit 4 via the input circuit 41.
Input to 0.

This pachinko gaming machine is provided with a payout control board (not shown) for carrying out payout control for paying out prize balls in association with winning. And the variable winning ball device 1
If one hit ball wins, for example, 1 per hit ball
The payout control of five premium balls (prize balls) is performed. In addition, in the case of winning in the other winning openings, for example, five prize balls (prize balls) are controlled to be paid out per one winning ball.

As described above, in this pachinko gaming machine, the winning regions are classified into a plurality of types so that the number of prize balls paid out in accordance with the winning is different. When a hit ball is won, a hit ball signal A or a hit ball signal B for specifying to which category the hit ball belongs in the payout area is input to the input circuit 41 from the payout control board. Then, the signal is input to the basic circuit 40.

In the basic circuit 40, the prize ball number signals 0 to 3, which are the number of prize balls to be paid out, are paid out through the prize ball number signal output circuit 53 according to the type of the hit ball signal inputted. Output to control board. This prize ball number signal 0-3
Is composed of 4-bit signals of 0, 1, 2, and 3.

A probability setting key switch (not shown) is also connected to the input circuit 41. This probability setting key switch is constituted by a key switch. By inserting a predetermined key into this probability setting key switch and operating a key by a staff at the game arcade, the probability of generating a big hit in three stages of setting 1, setting 2, and setting 3 can be variably set as described later. Become.

The basic circuit 40 includes a quantity indicator 15, a start memory indicator 6, and a decorative LED 3 via an LED circuit 46.
6, 31, 32, 35, an ordinary symbol variable display device 28, and an ordinary symbol start storage display 29,
The display of each of these displays is controlled. Basic circuit 40
Are connected to the solenoids 24 and 26 via a solenoid circuit 47.
To control the excitation of these solenoids.

The basic circuit 40 outputs effective starting information, big hit information and probability variation information via the information output circuit 42.
Output to the hall management computer, which is the host computer. Here, the valid starting information is information for indicating the number of winning hits of the hit balls that enter the starting openings 13 and 19, which is actually used for starting the variable display of the symbols on the variable display device 4. The big hit information is information about the occurrence of a big hit due to the variable display of the variable display device 4. The probability variation information is information relating to the occurrence of a high probability state (probability improvement state) described later.

The basic circuit 40 outputs a command signal for display control to the CRT display 55 through the CRT circuit 50.
The CRT circuit 50 receives the command signal and causes the CRT display 55 to display an image. Then, the CRT display 55 displays an image so that the variable display section 5 displays the image. The signals transmitted from the basic circuit 40 to the CRT display 55 via the CRT circuit 50 include command data (variable display command information) CD0 to CD7 and an interrupt signal INT which is a trigger signal for display control communication. And are included. Further, a signal line connecting the CRT circuit 50 and the CRT display 41 has +5 V for supplying a power supply voltage.
Line, + 12V line and GND line (ground signal line).

The basic circuit 40 controls, via the lamp circuit 48, various lamps such as the windmill lamp 30, the side lamp 18, the center lamp 34 and the sleeve lamp 33 to be lit or blinked.

The basic circuit 40 outputs a sound data signal to the speech synthesis circuit 51, and the speech signal is supplied from the speech synthesis circuit 51 to the volume amplification circuit 52. The volume amplification circuit 52 amplifies the sound signal and supplies it to an electric circuit board (not shown). Thereby, a sound effect or the like is emitted from a speaker or the like provided in the pachinko gaming machine.

The power supply circuit 54 is connected to an AC 24V AC power supply, and is + 30V, + 21V, + 12V, + 5V, G.
It is a circuit for supplying a power supply voltage, which is a plurality of types of DC voltage such as ND, to each circuit. The power supply voltage of +30 V and GND generated from the power supply circuit 54 is supplied to a CRT unit (included in the CRT display 55).

The illumination signal circuit 49 receives a control signal from the basic circuit 40 and, in response to the control signal, controls the lighting state of a plurality of types of illumination (not shown) provided on the pachinko gaming machine. The lamp control data D0 to D3 are transmitted to the decorative substrate. The lamp control data D0 to D3 are data for controlling the lighting state of the electric decoration, and specify the lighting state of the electric decoration at the time of a big hit or a high probability state. The lamp control data common is a common line signal.

The above-mentioned CRT display 55 includes a display control board (not shown). A control circuit for controlling display of an image displayed on the variable display section 5 is formed on the display control board. Next, a control circuit formed on the display control substrate will be described in detail.

FIG. 4 is a block diagram showing a control circuit formed on the display control board. The display control board has a CRT
Control circuit 60, reset circuit 61, oscillation circuit 6
2. VDP (Video Display Processor) A63, VD
It includes a PB 64 and a video switching circuit 67.

The reset signal from the reset circuit 61 is CR
It is input to the T control circuit 60. A clock signal is input from the oscillation circuit 62 to the CRT control circuit 60. The CRT control circuit 60 includes a CPU 601, which performs calculation and control, a RAM 602 used as a work area, and a ROM which stores a control program.
Including 603. In the CRT control circuit 60, the CPU 601 sets the ROM based on the received command data.
The RAM 602 executes the control program 603 as appropriate.
Is used as a work area to control the entire control circuit.
The CRT control circuit 60 operates in response to a reset signal and a clock signal.

VDP A63 is a VRAM (video RA
M) 631 is built in. VDPB64 is a VRAM
641 built-in. Character ROMs 65 and 6
Image data of an image displayed on the variable display device 4 is stored in advance in each of 6. The image data includes image data of special symbols, image data of characters other than special symbols, image data of background images, and the like.

The CRT control circuit 60 uses the VDP
A63 gives various command signals to transfer the image data stored in the character ROM 65 to the VRAM 631, and transfers this image data to the CRT via the video switching circuit 67.
Control to output to the display unit 70 is performed. Furthermore, CRT
The control circuit 60 transmits various command signals to the VDP B6
4 to transfer the image data stored in the character ROM 66 to the VRAM 641 and output the image data to the CRT display unit 70 via the video switching circuit 67. The CRT control circuit 60
Video switching circuit 6 from DP A63 and VDP B64
7 is controlled so as to switch the image data supplied thereto and output the data.

The CRT control circuit 60 receives the command data COM0 sent from the basic circuit 40 of the main board.
COM7 and the interrupt signal INT, and the interrupt signal IN
An interrupt operation according to the input of T is performed, and the command data C
OM0 to COM7 are read inside. Then, based on the read command data, the control as described above is performed to display an image on the variable display device 4.

The main exchanges of signals in this display control board are as follows. The CRT control circuit 60 appropriately supplies the VDP A 63 with a VDP A address signal, a VDP A read signal, a VDP A write signal, and a video synchronization signal. And VDP A
From 63, VPPA data is supplied to the CRT control circuit 60. Similarly, the CRT control circuit 6
0 supplies a VDP B address signal, a VDP B read signal, a VDP B write signal, and a video synchronization signal to the VDP B 64 as appropriate. VDP B64 to C
The VDP B data is supplied to the RT control circuit 60.

The VDP A 63 outputs the image data stored in the designated address in the VRAM 631 to the video switching circuit 67 in accordance with the VDP A address signal sent from the CRT control circuit 60. VD
Similarly, the PB 64 generates the VR according to the VDP B address signal transmitted from the CRT control circuit 60.
The image data stored at the designated address in the AM 641 is output to the video switching circuit 67.

The VDP A63 is a character ROM 65.
To the VROM A address signal. Character RO
M65, according to the VROM A address signal, converts the VROMA data signal, which is the image data stored at the designated address in the character ROM 65, into the VDP A6 signal.
Give to 3. As a result, the image data in the character ROM 65 is transferred to the VRAM 631. VDP B64
Transmits the VROM B address signal to the character ROM 66
Give to. The character ROM 66 stores the image data stored at the designated address in the character ROM 66 in accordance with the VROM B address signal.
Give to 4. As a result, the image data stored in the character ROM 66 is transferred to the VRAM 641.

The CRT control circuit 60 outputs the video A / B selection signals to the video switching circuit 67. This selection signal is a signal for instructing which of the image data sent from the VDP A 63 and the image data sent from the VDP B 64 to select and display. The video switching circuit 67 selects the image data sent from one of the VDPs according to the video A and B selection signals, and converts the RGB signals corresponding to the video data into a color CRT C.
Output to the RT display unit 70. Thereby, the image of the special symbol and the image such as the background image are controlled to be displayed on the variable display section 5 of the variable display device 4.

Thus, in this pachinko gaming machine, from the basic circuit 40 having the CPU 402 on the main board,
Unidirectional data transfer is performed to the CRT control circuit 60 having the CPU 601 on the display control board.
Then, on the display control board, the CRT control circuit 60 controls the display image based on the data thus transferred, so that the image displayed on the variable display unit 5 of the variable display device 4 is controlled. It is done.

FIG. 5 is an explanatory diagram for explaining various random counters used for game control and variable display control of the variable display device 4. There are five types of random counters related to the display of special symbols, as shown below. Each of the random counters is counted by the basic circuit 40 described above.

WC RND1 is used to predetermine whether or not to generate a big hit state (specific game state), and counts up from "0" to its upper limit (293.
377 or 407) and count up again from “0”. The count upper limit value of this WC RND1 is set at 1,
The settings 2 and 3 are different from each other. The setting 1 is “293”, the setting 2 is “377”, and the setting 3 is “4”.
07 ”. These settings 1, 2, 3
As described above, a probability setting key switch (not shown) provided at a position where a player cannot operate and a staff member of a game hall can operate such as a place on the back side of a game board of a pachinko gaming machine or a mechanism board. ), The staff of the game hall sets three levels.

The addition update of the count up of WC RND1 is performed by adding 1 to WCRND1 every 0.002 seconds. The CPU 402 provided in the basic circuit 40 receives a reset signal from the periodic reset circuit 44 at regular intervals (every 0.002 seconds), executes the program from the beginning, and waits for a reset at an address executed to the end. The reset signal is input, the program is repeatedly executed from the beginning again, and the execution of the program from the beginning to the end is repeated for each input of the reset signal, thereby providing the pachinko game machine. The game state is configured to be controllable.

If there is a start memory, WC at that time
The value of RND1 is stored in the big hit random storage bank of the RAM 403 of the basic circuit 40. The jackpot random storage bank is composed of first to fourth four banks, and if there is a start memory, W
The value of C RND1 is stored. Then, every time the start memory is exhausted by performing the variable display based on the start memory of the first bank, the data stored in each of the jackpot random storage banks is shifted from the fourth bank to the first bank by one. The storage location is changed in such a manner that the bank moves by bank.

WC RND L is used to predetermine the left symbol (left scheduled stop symbol) of the special symbol displayed when the left variable display portion is stopped. This WC RND
L is counted up from "0", counted up to "12" which is the upper limit, and then counted up again from "0". This WC RNDL
Is incremented and updated by one every 0.002 seconds as in WC RND1. The value of this WC RND L is also WC
Like RND1, it is stored in the aforementioned jackpot random storage bank. The details will be described later.

WC RND C is used to predetermine a medium symbol (middle scheduled halt symbol) of the special symbol displayed when the medium variable display portion is stopped. This WC RND
C is configured to count up from "0", count up to its upper limit of "15", and then restart counting from "0" again. The game program for the pachinko gaming machine is started from the beginning every 0.002 seconds and executed until the end of the program, and the game control is executed by repeatedly executing the program every 0.002 seconds. Since the execution from the beginning to the end of the program usually takes less than 0.002 seconds, there is extra interrupt processing time until the end of 0.002 seconds. This WC RND C is 0.00
The addition is updated every two seconds, and the addition is updated by an infinite loop using the remaining time of the interrupt processing.

WC RND R is used to predetermine the right symbol (right scheduled stop symbol) of the special symbol displayed when the right variable display portion is stopped. This WC RND
R is configured to count up from “0”, count up to “12” which is the upper limit thereof, and count up again from “0”. This WC RN
DR is added and updated one by one at the time of carry of WC RND C. That is, when the value of WC RND C is “1”
When WCRND changes from “5” to “0”, this WCRND is incremented by one.
R is added and updated.

In the WC RND RCH, the reach (for example, a part of the display results of the left, middle, and right variable display portions is not yet derived and displayed, and the display result that is already derived and displayed is the specific display. It is possible to derive and display a specific combination such as a display state that satisfies the condition of a combination of modes 1
(The state before the stage). The WC RND RCH is counted up from “0”, counted up to the upper limit “9”, and then counted up again from “0”.

The updating of the count-up of the WC RND RCH is executed every 0.002 seconds and at the time of the interrupt processing, like the WC RND C. This WC
The value of RND RCH and the type of reach are associated in advance, and the type of reach is determined according to the extracted value. In this pachinko machine, reach 1
Six types of reach 6 are set.

In these reaches, the display image of the variable display device 4 in the reach state is different for each reach. It should be noted that the hit determination of the ordinary symbol is also performed using a predetermined random counter. The value of the random counter for normal symbol hit determination is also stored in the random storage bank (for normal symbols), as in the case of WC RND1. The bank is divided into four banks corresponding to the start memory.

FIG. 6 is an explanatory diagram showing an arrangement of symbols variably displayed on the variable display device 4. In FIG. 6, the extracted values of WC RND L, C, R,
The relationship between the middle and right symbols is shown. The left symbol which is a special symbol displayed on the left variable display portion and the right symbol which is a special symbol displayed on the right variable display portion are 0-9, respectively.
There are 13 types of patterns: flowers, drinks and shells.
The arrangement of the symbols is also the same in the left and right symbols. Those symbols are WC RNDL, R 0
~ 12.

In addition, the medium pattern which is the special symbol displayed on the medium variable display portion is 0-9, flower, drink, shellfish, CHAN.
CE, NG! , BAD are set for 16 types of symbols. These symbols are assigned to WC RND C 0-15. The symbol at the location that matches the number of each of the extracted values of WC RNDL, C, and R is selected and determined as the scheduled stop symbol. In this pachinko gaming machine, a big hit state occurs when the left, middle, and right symbols are aligned with the same symbol.

Next, the procedure for predetermining whether or not to generate a big hit based on the value of the random counter will be described separately for the big hit occurrence probability setting 1, setting 2, and setting 3. FIG. 7 is a flowchart showing a procedure for determining in advance whether or not to generate a big hit based on the value of the random counter in the case of setting 1. The hit ball wins the starting port 13 and is detected by the starting ball detector 22 or
If a hit ball is awarded in the starting opening 19 and is detected by the starting ball detector 25, the value of the WC RND1 at that time is extracted, and it is predetermined to generate a big hit when the value is "7". You. In that case, the symbol to be a big hit is determined by the extracted value of WC RND L.

On the other hand, when the extracted value of WC RND1 is other than "7", the deviation is predetermined. In that case,
The left scheduled stop symbol is determined by the extracted value of WC RND L, the middle scheduled symbol is determined by the value of WC RND C, and the right scheduled stop symbol is determined by the extracted value of WC RND R.

When these three scheduled stop symbols are determined, the determined contents are, for example, randomized and the combination of symbols for generating a big hit coincides with the extracted value of WC RND C. "1" is added to forcibly control so that the pattern is out of alignment.

When the gaming state is the probability improving state (hereinafter referred to as the high probability state), the extracted value of WCRND1 is
It is determined in advance that a big hit should occur at "7, 11, 79", and at other times, a miss is predetermined.

Here, the high probability state will be described. The high-probability state is a state in which the probability of occurrence of a big hit has been improved, and is called a probability-improved state or a probability fluctuation state. In the high probability state, the following control is performed. The display result of the variable display device 4 at the time of occurrence of the big hit state is a combination of predetermined special identification information (in this embodiment, “111”, “333”, “555”, “7”).
77 "), the state is controlled to a high probability state in which the probability of occurrence of a subsequent big hit is improved.

In this high probability state, a combination of specific identification information that is predetermined so as to be a big hit displayed by the variable display device 4 (specific display mode)
Is improved, and when a specific combination of identification information is displayed by the variable display device 4, the big hit control is restarted.

Further, in this high probability state, it is controlled so that the probability of hitting (that the display result becomes specific identification information) in the normal symbol variable display device 28 becomes high. This hit is also called a small hit. When such control is performed, the movable piece 1 of the variable starting port device 16
7 frequently opens, a large number of hit balls start winning, and the variable display frequency (the extraction frequency of the WC RND1) of the variable display device 4 increases, so that a big hit easily occurs, and in this state, the starting winning increases. As a result, the number of payout balls to be paid out from the gaming machine increases, so that the player can play a game without reducing the number of balls (game balls owned by the player), which is advantageous for the player.

Further, in this pachinko gaming machine, a variable time shortening control (shortening mode) for shortening the variable display period of the special symbol is also performed. The fluctuation time reduction control is executed, for example, on condition that the number of start storages reaches a predetermined number. When the control is performed, useless starting winnings can be reduced.

Next, the case of setting 2 will be described. FIG.
10 is a flowchart illustrating a procedure for determining in advance whether to generate a big hit based on the value of a random counter in the case of setting 2. Here, differences from the case of setting 1 shown in FIG. 7 will be described.

The case of setting 2 is different from the case of setting 1 in the following points. First, the upper limit of WC RND1 (37
7) is different. Furthermore, the extracted value of WC RND1 that causes a big hit in the high probability state is different. That is,
In the high probability state, the extracted value of WCRND1 is 7,
At 11, 79, 307, 311, 331, and 373, it is determined in advance that a big hit will occur, and at other times, departure will be determined in advance. As described above, in the case of the setting 2, the probability of generating a big hit in a normal state (when the state is not the high probability state) is lower than in the case of the setting 1, but the probability of generating a big hit in the high probability is higher.

Next, the case of setting 3 will be described. FIG.
11 is a flowchart illustrating a procedure for determining in advance whether a big hit is to be generated based on the value of a random counter in the case of setting 3. Here, differences from the setting 1 and the setting 2 will be described.

The setting 3 is different from the setting 1 and the setting 2 in the following points. First, the upper limit of WC RND1 (407)
Is different. Furthermore, the extracted value of WC RND1 that is predetermined to generate a big hit in the high probability state is different. That is, in the high probability state, WC RND
The extracted value of 1 is 7, 11, 79, 307, 311, 33
At 1,373,401, it is determined in advance that a big hit should occur, and at other times, a miss is predetermined. As described above, the setting 3 has a lower probability of generating a big hit in a normal state than the setting 1 and the setting 2 but has a higher probability of generating a big hit in a high probability state.

Here, the big hit symbol set so as to shift to the high probability state will be described. As previously mentioned,
The jackpot design is "1,1,1"-13 of "shellfish, shellfish, shellfish"
There are types. Of these 13 types of jackpot designs,
"1,1,1", "3,3,3", "5,5,5",
“7, 7, 7” is a big hit symbol that shifts to the high probability state.

Next, the contents stored in the RAM included in the basic circuit 40 will be described in detail. FIG. 10 is a memory map showing the storage contents of the RAM 403.

Referring to FIG. 10, RAM 403 is RA
Each M address has an 8-bit storage area. RA
Various data such as control data is stored in M403 using a single address or a plurality of addresses. More specifically, referring to FIG. 10, as the control data, for example, control data such as big hit flags 1 to 3 and a process flag are stored at a predetermined address.

The big hit flag is flag data indicating whether or not a big hit state (specific game state) is generated.
The values of the big hit flag 1 to the big hit flag 3 are, for example, "00H" (when not a big hit) or "01H".
It can take any value (if it is a big hit). The big hit flag 1 to the big hit flag 3 store data of the same value depending on whether or not a big hit is generated. These jackpot flags are set in the normal processing shown in FIGS. 45 and 46 described later. The control operation of the game control of this pachinko gaming machine is divided into a plurality of stages of processing processes as described later. The process flag is flag data indicating a processing process to be executed. The control data represented by the big hit flag 1 to the big hit flag 3 and the process flag are stored in an address called a work area of the RAM 403.

In the work area of the RAM 403,
Pattern data 1 and pattern data 2 are stored as a plurality of types of pattern data. Each of the pattern data 1 and the pattern data 2 is data having a predetermined data pattern and is distributed and stored in the storage area of the RAM 403. For example, data of "55AAH" is written in the area of pattern data 1, and data of "1068" is written in the area of pattern data 2.
The data of "H" is written. These data are fixedly stored and cannot be rewritten in principle during a normal game. The pattern data 1 and the pattern data 2 are used for determining abnormality of the data stored in the RAM 403.

The pattern data 1 is stored at an address in the vicinity of an address where control data such as the big hit flag 1 to the big hit flag 3 and the process flag, which are important for game control of the gaming machine, are stored. The pattern data 2 is stored at an address in the vicinity of the address at which the control data is stored so as not to greatly affect the progress of the game control when the control data becomes abnormal.

The reason why the big hit flag and the process flag are important control data for the game control of the pachinko gaming machine is as follows. In this pachinko gaming machine, when a big hit state occurs, it becomes an advantageous state for the player, but the big hit flag 1 to big hit flag 3 are flags indicating whether or not such a big hit state is generated, and the game is played. 1 of control data that has a significant effect on machine control
One. Since the game control of this pachinko gaming machine is divided into processing processes of multiple stages, normal game operation is not performed when the value of the process flag becomes an abnormal value, so the process flag is also a game. It is one of the control data important for control.

When noise enters the basic circuit 40, the data stored in the RAM 403 may be overwritten with abnormal data. Rewriting to abnormal data due to noise often occurs not only at one address but at a certain range of addresses in the RAM 403. Therefore, when an abnormality occurs in the control data such as the big hit flag 1 to the big hit flag 3 and the process flag, which are important for game control, the pattern data 1 also becomes abnormal. Similarly, the pattern data 2 also becomes abnormal data when an abnormality occurs in the control data of an address in the vicinity thereof.

Therefore, when the data of the pattern data 1 becomes abnormal, it is considered that the important control data such as the big hit flag 1 to the big hit flag 3 and the process flag have an abnormality. Similarly, when the data of the pattern data 2 becomes abnormal data, it is considered that the control data stored at the address in the vicinity thereof has an abnormality.

Incidentally, in FIG. 10, the big hit flag 1
Although the case where the big hit flag 3 is stored in the storage areas of the adjacent addresses is shown, the big hit flag 1 to the big hit flag 3 are distributed in the storage area of the RAM 403 so that the storage areas are not adjacent to each other. May be stored. By doing so, the occurrence of an erroneous big hit state due to an abnormal state of the RAM 403 can be prevented with higher sensitivity than in the case where the big hit flag is stored adjacently.

Next, the types of command data COM0 to COM7 transmitted from the basic circuit 40 of the game control board to the CRT control circuit 60 of the display control board will be described. FIG. 11 is a diagram showing the types of command data COM0 to COM7 in a table format.

Referring to FIG. 11, COM0 is a header command. The CRT control circuit 60 uses this C
By reading OM0, it is determined that command data has been sent from the basic circuit 40. COM1 is a main status, and is a command for specifying the type (code) of display control of the variable display section 5 of the variable display device 4. The types of display control designated by the COM1 include screen off, demo display, game display, fever start display, fever round display, end demo, error display, and fever round title display. These controls are designated according to the data value of COM1.

"Screen off" means to turn off the display screen. The demo display means the display of the demonstration screen. The game display indicates a display related to the game such as fluctuation and stop of the special symbol, and the stop type of the special symbol includes the reach type. The fever start display indicates a big hit state start display. The fever round display is a display of each round of the repeated continuous control in the big hit state. The end demo is a demonstration display at the end of the big hit state. The error display means displaying the occurrence of a failure (fault). The round title display refers to the display of the title of each round in the big hit state.

COM2 is a command for designating the stop symbol of the left symbol in the variable display of the special symbol. C
OM3 is a command for designating the stop symbol of the medium symbol in the variable display of the special symbol. COM4 is a command for designating the stop symbol of the right symbol in the variable display of the special symbol. COM5 is a command for designating the variable time (variable display time) of the special symbol. C
OM6 is a command for specifying the color of image display. COM7 is a command for designating execution of checksum.

Such command data COM0 to COM
The communication of M7 is performed by 8-bit parallel transfer. 1
8-bit data is transferred by one transfer. Also,
In order to transfer necessary data, one command is composed of blocks described below.

First, one command is always transferred at a fixed time interval. The data length and data order of the command block are the same in all sequences.
Furthermore, as described above, the command data has the checksum command added to the last byte, so that the command data can be received more reliably. The CRT control circuit 60 on the command data receiving side starts receiving a new command by receiving the header command COM0, receives command data of a specified byte, and then checks the command data by a checksum. Here, the command block length is fixed at 8 bytes, valid command data is 7 bytes, and checksum is 1 byte.

Next, a method of transferring command data will be described. FIG. 12 is a timing chart for explaining the command data transfer method.

Referring to FIG. 12, the command block is
The command data is transmitted continuously with 8 bytes, and the command data interval is 2 msec. The signal output from the basic circuit 40 is composed of a total of nine unidirectional buses including an 8-bit data line and one interrupt signal INT line. When the basic circuit 40 on the transmission side outputs the command data COM0, which is output data, to the data line (the data line is a latch output), the interrupt signal INT is transmitted at the H level for 500 μS each time.
Thereafter, similarly, the command data COM1, the command data COM2 to the command data COM7 are sequentially arranged in the basic circuit 40.
To the CRT control circuit 60. In addition,
The beginning of the command block is CO, which is a header command.
It is determined by M0.

Next, the CP of the CRT control circuit 60
A memory map of addresses viewed from U601 will be briefly described. FIG. 13 is a memory map of addresses viewed from the CPU 601 of the CRT control circuit 60.

Referring to FIG. 13, this memory map is
It is divided into the areas described below. Address 0000
Areas starting from 0h are a program area and a data area. The area starting from 06000h is the area of the sprite management table and the slot pattern management table. Here, the sprite refers to a special symbol that is displayed in front of the background image and is movable on the screen, and means each symbol of left, middle, and right. The sprite management table is a table that manages the position of the sprite on the screen and the like. What is the slot pattern management table?
It is a table for managing the pattern pattern of the sprite.

Area starting from 0F000h is VDP
This is the area of the internal register of A63. 0F100h
The area starting with is the area of the internal register of VDP B64. The area starting from 0F200h is the area of the port for switching the memory bank of the character ROM 65. The area starting from 0F300h is an area of a port for switching the memory bank of the character ROM 66.

The area starting from 0F400h is the area of the port used for setting H data (data of the horizontal display position of the image). The area starting from 0F500h is the area for the port for setting the H data and the port for switching the image display mode. Each of the area starting from 0F600h and the area starting from 0F700h is an area of a port used for setting V data (data of a vertical display position of an image). The area starting from 0FC00h is the I / O port area.

The area starting from 0FDC0h is a work area and a stack area, and constitutes a RAM area. The area starting from 10000h is the area of the pattern management table and constitutes the ROM area.
The pattern management table is a data table that manages the images of the round display during the repeated continuous control at the time of a big hit, and is for managing the addresses where the images used for the display of each round are stored. .

Next, the contents of the game control executed by the basic circuit 40 of the main board will be described. 14 to 83
Is a flowchart showing a processing procedure of a control program for game control stored in the ROM 401 of the basic circuit 40. The basic circuit 40 performs game control according to the flowcharts described below.

FIG. 14 is a flowchart showing the processing procedure of the main program for performing game control. When the CPU 402 in the basic circuit 40 executes the main program in the control program read from the ROM 401, the initialization process is first performed (EE12).
H). Next, probability setting processing is performed (EE15
H). Next, the hit ball signal processing is executed (EE18
H). Next, a data output process is executed (EE1B
H). Next, sound processing is executed (EE1EH). Next, the display control process is executed (EE21H). next,
Output data control processing is executed (EE24H). Next, output data set processing is executed (EE27
H). Next, a warning process is executed (EE2AH).

Then, the information output process is executed (EE2DH). Next, the display symbol random update process is executed (EE30CH). Next, process processing is executed (EE33H). Next, normal symbol process processing is executed (EE36H). Next, a random update process for hit determination is executed (EE39H). Next, the switch process is executed (EE3CH). Finally, the display symbol random update process is repeatedly executed (EE3FH). Each of these processes is a subroutine program. Hereinafter, each process will be described in detail.

Next, the symbol process process (each process process) executed in association with the above process process will be described. FIG. 15 is a flowchart showing the processing procedure of the symbol process processing. Referring to FIG. 15, first, a symbol process is branched (F001H). The branch of the symbol process is performed by WF PRO which is a process flag stored in the RAM 403 of the basic circuit 40.

First, when the value of WF PRO is "00H", the normal processing described later with reference to FIGS. 45 and 46 is executed (F1CFH). Further, when the value of WF PRO is “05H”, a medium reel stop process described later with reference to FIG. 53 is executed (F356H). After the normal time process or the middle reel stop process is finished, the symbol process process is finished.

Next, when the value of WF PRO is "01H", a fluctuation start process described later with reference to FIG. 47 is executed (F259H). Also, the value of WF PRO is "06H".
At this time, the fever check process described later with reference to FIG. 58 is executed (F3FFH). After the variation start process or the fever check process is finished, the symbol process process is finished.

Next, when the value of WF PRO is "02H", the all-reel variation process described later with reference to FIG. 50 is executed (F2F5H). In addition, the value of WF PRO is "07
When it is "H", a special winning opening opening pre-process described later with reference to FIG. 59 is executed (F434H). After all reel variation processing or special winning opening opening preprocessing is finished, the symbol process processing is finished.

Next, when the value of WF PRO is "03H", the left reel stop processing which will be described later with reference to FIG. 51 is executed (F326H). In addition, the value of WF PRO is "08
When it is "H", a special winning opening opening process, which will be described later with reference to FIG. 60, is executed (F44EH). After the left reel stop process or the special winning opening opening process is finished, the symbol process process is finished.

Next, when the value of WF PRO is "04H", the right reel stop processing which will be described later with reference to FIG. 52 is executed (F335H). In addition, the value of WF PRO is "09
When it is "H", a special winning opening opening post-processing described later with reference to FIG. 61 is executed (F473H). After the right reel stop process or the special winning opening open process is completed, the symbol process process is completed.

Next, the normal symbol process processing will be described. FIG. 16 is a flowchart showing a processing procedure of normal symbol process processing. Referring to FIG. 16, first, the normal symbol process is branched (F5B1H). The branch of the normal symbol process is the RAM 403 of the basic circuit 40.
WF PR which is a normal symbol process flag stored in
It is based on OF.

First, when the value of WF PROF is "00H", a normal symbol normal time process which will be described later with reference to FIG. 67 is executed (F5C3H). Further, when the value of WF PROF is “01H”, the normal symbol variation time process, which will be described later with reference to FIG. 68, is executed (F5FDH). Also, WF P
When the value of ROF is "02H", the normal symbol fever check process described later with reference to FIG. 69 is executed (F
63BH). After one of these processes is completed, the normal symbol process process is completed.

FIG. 17 is a flow chart showing the processing procedure of the timer interrupt processing. The timer interrupt process is a process of performing a timer interrupt. First, the indicator interrupt signal (interrupt signal INT) is output (EE00H). Next, the interrupt signal INT is cleared (EE09H).

Next, the main program shown in FIG. 14 will be described in more detail. FIG. 18 is a flowchart showing the processing procedure of the main processing. The main process is a process executed every reset (every 2 msec) to set the stack pointer and execute each module.

First, the address of the stack pointer is set (EEDFH). Next, the RAM data check process is executed (EE10H). The RAM data check process will be described later with reference to FIG. Next, initialization processing (PINI) is executed (EE12H). The initialization process will be described later with reference to FIGS. Next, the probability setting process (PRDST) is executed (EE15H). The probability setting process will be described later with reference to FIG. Next, the hit ball signal processing (PSIG) is executed (EE18H). Figure 8 for the hit ball signal processing
3 will be used later. Next, the data output process (P OU
T) is executed (EE1BH). The data output process will be described later with reference to FIG.

Next, sound processing (P SOUND) is executed (EE1EH). The sound processing will be described later with reference to FIG. Next, the display control process (P DISP) is executed (EE21H). FIG. 27 shows the display control process.
Will be described later. Next, the output data control process (PL
CNT) is executed (EE24H). The output data control process will be described later with reference to FIG.

Next, the output data set process (P LSE
T) is executed (EE27H). The output data set process will be described later with reference to FIG. Next, a warning process (PWAR) is executed (EE2AH). The warning process will be described later with reference to FIG. Next, the information output process (P JYOUHOU) is executed (EE2DH).
The information output process will be described later with reference to FIG. Next, a display symbol random update process (PRND ZU) is executed (EE3DH). The display symbol random update process will be described later with reference to FIG. Next, the process process (P PROC) is executed (EE33H). The process processing will be described later with reference to FIG.

Next, the normal symbol process process (P PRO
CF) is executed (EE36H). The normal symbol process processing will be described later with reference to FIG. 66. Next, a random update process (PRANDOM) is executed (EE3
9H). The random update process will be described later with reference to FIG. Next, the switch process (P SWCK) is executed (EE3CH). The switch process will be described later with reference to FIG. Next, a loop process having the contents shown in FIG. 19 is executed.

FIG. 19 is a flow chart showing the procedure of loop processing in the main processing shown in FIG. With reference to FIG. 19, in this loop process, a display symbol random update process (PRND ZU) is repeatedly executed (EE3FH). The display symbol random update process will be described later with reference to FIG.

FIG. 20 is a flow chart showing the processing procedure of the RAM data check processing. The RAM data check process is a process of determining an abnormality in the data stored in the RAM 403 included in the basic circuit 40.

First, in step SA (hereinafter, simply referred to as SA) 1, it is determined whether or not the big hit flag 1 to the big hit flag 3 are abnormal. Specifically, it is determined whether or not the values of the big hit flag 1 to the big hit flag 3 match. Here, jackpot flag 1 to jackpot flag 3
If it is determined that the values do not match, the jackpot flag is considered to be abnormal. On the other hand, when the values of the big hit flag 1 to the big hit flag 3 match, it is determined that the big hit flag is not abnormal.

When it is determined that the big hit flag 1 to the big hit flag 3 are abnormal, the processing proceeds to SA2, and the processing of rewriting the value of the big hit flag in which the abnormality has occurred is performed. Specifically, among the values of “00H” or “01H”, the values indicated by a large number (two) of the big hit flag 1 to the big hit flag 3 are regarded as correct values, and the value of the small number (one) is set. Is rewritten to the value of a larger number of flags. After that, the RAM data check process ends.

On the other hand, if it is determined at SA1 that the big hit flag is not abnormal, then the processing advances to SA3, at which it is judged whether or not the big hit state is present. Specifically, it is determined whether or not it is a big hit based on the values of the big hit flag 1 to the big hit flag 3. If it is determined in SA3 that the jackpot is not a big hit, the process proceeds to SA10 described later. On the other hand, if it is determined that the jackpot is a big hit, the process proceeds to SA4.

At SA4, it is judged whether the pattern data 1 is abnormal data. Specifically, the pattern data 1 stored in the RAM 403 is sampled, and it is determined whether or not the sampled value and the correct pattern data 1 value match. As a result, if the data do not match, it is determined that the pattern data 1 is abnormal, while if it is determined that the data match, it is determined that the pattern data 1 is normal. If it is determined that the pattern data 1 is abnormal, the process proceeds to SA7 described later.

On the other hand, if it is determined that the pattern data 1 is not abnormal, the flow proceeds to SA5 and the pattern data 2
It is judged whether or not is abnormal data.
Specifically, the pattern data 2 stored in the RAM 403 is sampled, and it is determined whether or not the sampled value and the correct pattern data 2 value match. As a result, when it is determined that the data do not match, it is determined that the pattern data 2 is abnormal data, and when the data match, it is determined that the pattern data 2 is normal data. It

When it is determined in SA5 that the pattern data 2 is not abnormal data, both the pattern data 1 and the pattern data 2 are normal data, and therefore the RAM data check process is terminated. On the other hand, if it is determined in SA5 that the pattern data 2 is abnormal data, the process proceeds to SA6, in which the abnormal pattern data 2 is rewritten to normal data, and then the RAM data check is performed. The process ends.

SA executed when it is determined in SA4 that the pattern data 1 is abnormal data
At 7, it is determined whether the pattern data 2 is abnormal data. Specifically, SA5 described above
The same judgment is made. SA7, pattern data 2
If it is determined that is not abnormal data,
In SA8, the pattern data 1 in which the abnormality has occurred is rewritten to normal data, and then the RAM data check process ends.

On the other hand, when it is determined in SA7 that the pattern data 2 is abnormal data, the processing proceeds to SA9, and the initialization flag 1 is cleared to "0000H" (0 is cleared). The initialization flag 1 is a flag used in the initialization process (EE12H) and the like described later with reference to FIGS. 21 to 25. Initialization flag 1 is 0
If it is cleared, RA is
A process of initializing (clearing to 0) the storage data of M403 is executed. Therefore, when it is determined that both the pattern data 1 and the pattern data 2 are abnormal data in the big hit state, R is set in the initialization process.
The data stored in the AM 403 is initialized.

In SA10, which is executed when it is determined that the jackpot is not a big hit, in SA10, the pattern data 1
It is judged whether or not is abnormal data.
Specifically, the same determination as in SA4 described above is performed. When it is determined that the pattern data 1 is abnormal data, the process proceeds to SA11, and the initialization flag 1 is cleared to 0. Specifically, the same processing as SA9 is performed. In this way, when an abnormality occurs in the pattern data 1 when not in the big hit state,
The data stored in the RAM 403 is initialized in the initialization process described later.

On the other hand, in SA10, the pattern data 1
If it is determined that is not abnormal data,
In SA12, it is determined whether the pattern data 2 is abnormal data. Specifically, the same judgment as in SA5 and SA7 described above is performed.

If it is determined by SA12 that pattern data 2 is not abnormal, both pattern data 1 and pattern data 2 are not abnormal, and the RAM data check process is terminated. On the other hand, SA1
If it is determined in step 2 that the pattern data 2 is abnormal data, the process proceeds to SA13, the pattern data 2 is rewritten to normal data, and then R
The AM data check process ends.

In this way, when only the pattern data 2 is abnormal data when it is not a big hit, R
A process of rewriting only the pattern data 2 in which abnormality has occurred into normal data is performed without initializing the AM 403. The reason is that the pattern data 2 is the data for abnormality determination corresponding to the control data that does not greatly affect the progress of the game in the control of the game operation, and therefore even if an abnormality occurs in this data, it is currently in progress. This is because it is appropriate to continue the game operation.

By carrying out the RAM data check process shown in FIG. 20, the following effects can be obtained. First, when the big hit flag 1 to the big hit flag 3 are abnormal data, the big hit flag in which the abnormality has occurred is rewritten to normal data. Therefore, for example, when the big hit state occurs, It is possible to prevent the inconvenience that the big hit state ends due to a slight abnormality.

Further, in the case of not the big hit state, the storage data of the RAM 403 is initialized only when the abnormality of the pattern data 1 corresponding to the control data which may greatly hinder the progress of the game operation occurs. It is possible to prevent the stored data in the RAM 403 from being initialized due to a slight abnormality in the data. In other words,
The stored data in the RAM 403 can be initialized only when an abnormality occurs in the data that hinders the normal progress of the game control.

Also, in the case of a big hit state, the data stored in the RAM 403 is initialized only when both the pattern data 1 and the pattern data 2 become abnormal data. It is possible to prevent the stored data in the RAM 403 from being initialized when a large abnormality occurs.

In addition, when it is not the big hit state, only when the pattern data 1 becomes abnormal data, the RAM 4
The storage data of 03 is initialized, while in the case of a big hit, the storage data of the RAM 403 is initialized only when both the pattern data 1 and the pattern data 2 become abnormal data. . That is, in the case of the big hit state, the sensitivity for determining the abnormality of the data is lower than that in the case of not the big hit state. For this reason, it is possible to prevent a situation that is disadvantageous to the player that the big hit state ends due to a slight abnormality in the control data when the big hit state is not generated.

In the RAM data check process of FIG. 20, when the big hit flag 1 to big hit flag 3 are abnormal values, a process of rewriting the value of the abnormal big hit flag to a correct value will be described. did. However, not limited to this, the process when the big hit flag is abnormal may be performed as follows.

That is, the jackpot flag is set to data that can take three values. Then, the values of the big hit flag 1 to the big hit flag 3 are compared with each other, and when the values do not match, the following control is performed. When the values of the two big jackpot flags out of three match, the value of the small number (one) of big hits that do not match is rewritten to the value of the majority (two) that matches. On the other hand, when the respective values of the big hit flag 1 to the big hit flag 3 are all different, the storage data of the RAM 403 is initialized by performing a process of clearing the initialization flag 1 to 0.

By performing such processing, the following effects can be obtained. That is, if there is a slight abnormality in the data of the big hit flag 1 to the big hit flag 3, the big hit flag ends in the big hit state by rewriting the big hit flag in which the abnormality has occurred to a normal value. It is possible to prevent a situation inconvenient for the user, and further, when a serious abnormality occurs in the big hit flag 1 to the big hit flag 3, by initializing the storage data of the RAM 403, the big hit state erroneously occurs due to the abnormality of the data. Inconvenience can be prevented.

In the RAM data check process of FIG. 20, the process of clearing the initialization flag 1 to 0 when only the pattern data 1 becomes abnormal when not in the big hit state has been described, but the present invention is not limited to this. Such processing of clearing 0 may be performed when one of the pattern data 1 and the pattern data 2 becomes abnormal.

FIG. 21 is a flow chart showing the processing procedure of the initialization processing. The initialization process is a process of determining the initialization flag 1 and the initialization flag 2 and branching to various initialization processes. First, it is determined whether or not the initialization is started (EE44H). Specifically, the initialization flag 1 indicates “1068H” indicating that the initialization has been completed.
Whether the flag is set to 0 and the initialization flag 2
However, it is judged whether or not it is set to "01H". If the initialization flag 1 is set to "1068H" and the initialization flag 2 is set to "00H", it is determined that the initialization is not yet started, otherwise, the initialization is performed. It is judged that it is not before the start.

If it is judged that the initialization is not yet started,
A register initial value setting process shown in FIG. 25, which will be described later, is executed. On the other hand, if it is determined that the initialization is not yet started, then it is determined whether the initialization is in progress (EE54).
H). Specifically, it is determined whether the initialization flag 1 is set to "55AAH" indicating that the initialization is in progress. When the initialization flag 1 is "55AAH", it is determined that the initialization is in progress. If it is determined that the initialization is in progress, the first initialization process shown in FIG. 22, which will be described later, is executed.

On the other hand, if it is determined that the initialization is not in progress, the initialization flag is set (EE).
5BH). Specifically, the initialization flag 1 is set to "55AA
It is set to "H", and the initialization flag 2 is cleared to "00H". Next, the interrupt waiting process is repeated (EE6
3H).

FIG. 22 is a flow chart showing the processing procedure of the first initialization processing. The first initialization process is a process of clearing the data in the RAM 403 incorporated in the basic circuit 40.

First, it is determined whether or not the RAM 403 has been initialized (EE65H). Specifically, it is determined whether the initialization flag 2 is “00H”. If the initialization flag 2 is "00H", it is determined that the initialization has not been performed. On the other hand, if the initialization flag 2 is not "00H", it is determined that the initialization has been performed.

If it is determined that the initialization has been completed, the second initialization process is executed. The second initialization process will be described later with reference to FIG. On the other hand, if it is determined that the initialization has not been completed, a process of setting initialization preparation is performed. Next, processing for clearing the address 00 of the RAM 403 is performed (EE6DH). Next, RAM403
The processing for updating (-1) the address to be initialized is performed (EE6FH).

Next, it is determined whether or not initialization is in progress (EE70H). If it is determined that initialization is in progress,
The RAM 403 is cleared and the initialization address is updated repeatedly. On the other hand, if it is determined that the initialization is not in progress, then the process of setting the initialization flag to indicate that the initialization is in progress is performed (EE72H). Specifically, the initialization flag 1 is set to "55AAH" and the initialization flag 2 is set to "01H". Next, the interrupt waiting process is repeated (EE7BH).

FIG. 23 is a flow chart showing the processing procedure of the second initialization processing. The second initialization process is a process of setting initial value data. First, it is determined whether the initialization flag is normal (EE7DH). Specifically, it is determined whether the initialization flag 2 is "01H". When the initialization flag 2 is “01H”, it is determined that the initialization flag is normal. On the other hand, when the initialization flag 2 is other than "01H",
It is determined that the initialization flag is not normal. If it is determined that the initialization flag is not normal, initialization failure processing is executed. The initialization failure process will be described later with reference to FIG.

On the other hand, if it is determined that the initialization flag is normal, the process data / timer process (P PRO) is performed in order to set the process data for the normal demo display.
TM) is executed (EE80H). The process data / timer processing will be described later with reference to FIG. Next, in order to initialize the data of the reel symbol (special symbol), a data set process (P DATASET) is executed (EE86H). The data set process will be described later with reference to FIG.

Next, the initialization flag is set (EE8CH) to indicate that the initialization is completed. Specifically, the initialization flag 1 is set to "1068H" and the initialization flag 2 is cleared to "00H". Next, processing for setting the effective time of the count switch (winning prize detector 23) is performed (EE94H). This process is performed by the winning ball detector 2 within the effective time after the power is turned on.
3 is a process for preventing error setting even if a winning ball is detected. Next, the interrupt waiting process is repeated (EE99H).

FIG. 24 is a flow chart showing the processing procedure of the initialization failure processing. The initialization failure process is a process that is performed when the initialization fails, and is a process that clears the initialization flag so that the initialization can be performed again from the beginning when the initialization is not normally performed. First, a process of setting an initialization flag to indicate that initialization has failed (clearing the initialization flag) is performed (EE
9BH). Specifically, the initialization flag 1 is set to "0000.
Set to “H” (clear to 0) and set initialization flag 2 to “00
Processing for clearing to "H" is performed. Next, the interrupt waiting process is repeated (EEA3H).

FIG. 25 is a flow chart showing the processing procedure of the register initial value setting processing. The register initial value setting process is a process of initializing a device register incorporated in the CPU 402 of the basic circuit 40. First, a data set process (P DATASET) for setting data in the built-in device register is executed (EEA5H). For the data set processing, see FIG.
Will be described later. After that, the register initial value setting process outputs.

FIG. 26 is a flow chart showing the processing procedure of the data output processing. The data output process is a process of outputting data such as output data to the output port of the basic circuit 40. First, processing for clearing the digit output is performed (EEACH). Next, processing for clearing the display data corresponding to the digit is performed (EEB5H). Next, in order to update the digit counter, the counter update process (P
COUNT) is executed (EEBBH). Next, the process of setting the data corresponding to the digit is performed (EE
C3H). Next, a process of setting digit data is performed (EECDH). Next, a data output process for setting the set digit data in each output port is performed (EED9H). Then, the data output process ends.

FIG. 27 is a flow chart showing the processing procedure of the display control processing. The display control process is a process of outputting a display control code, that is, command data COM0 to COM7 relating to display control of the variable display device 4.
First, a process of setting a display communication command header (header command) is performed (EEE9H). Next, a process of outputting command data corresponding to display control is performed (EEEEDH).

Next, a process for updating the checksum data is performed (EEFAH). Next, it is judged whether or not it is other than the time of transferring the header command (EF00
H). If it is determined that it is not during the transfer of the header command, the checksum data is cleared (EF04H). When it is determined that the checksum data has been cleared or when the header command has not been transferred, the counter update process (P COUNT) is executed to update the display control transfer counter (EF06H). For the counter updating process, see FIG.
Will be described later. The display control transfer counter is a counter that counts the command data to be output, and the type of command data is recognized based on the count value.

Next, an interrupt signal INT is used by utilizing interrupt processing.
Is output for 500 μs, the process of setting a timer interrupt is performed. Next, interrupt signal (display interrupt signal)
Processing for clearing INT is performed. Next, the processing for permitting the timer interrupt set as described above is performed (EF25H). Then, the display control process ends. By performing this display control process, the command data COM0 to COM7 are output every 2 ms,
The interrupt signal INT is output for a predetermined period of 500 μs.

FIG. 28 is a flow chart showing the processing procedure of the output data control processing. The output data control process is
This is processing for controlling display data of LEDs, lamps, segment LEDs, and the like.

First, it is determined whether the lamp timer (lamp timer) has expired (EF27H). Specifically, it is determined whether or not the value of the lamp timer stored in the RAM 403 of the basic circuit 40 is 0. That is, the value of the lamp timer is subtracted and updated as time passes. If it is determined that the lamp timer has not expired, a process of subtracting and updating (-1) the lamp timer is performed (EF2BH). Next, it is determined whether or not the lamp timer is under calculation (during subtraction) (EF2EH). If the lamp timer is in operation, the output data control process ends.

On the other hand, when the lamp timer is not in operation or when the lamp timer expires, the address of the lamp data is added and updated (+5) (EF30).
H). As a result, the address of the lamp data is updated to the address of the next lamp data. Next, it is determined whether it is other than the end of the lamp data. That is, it is determined whether or not the lamp data is in operation. If it is the end of the ramp data, the start address of the ramp data is set. Next, when it is other than the end of the lamp data or when the setting of the head address of the lamp data is completed, the updated value of the address of the lamp data is set (EF3BH). Next, the lamp timer is set (EF3DH). After setting the lamp timer, the output data control process ends.

FIG. 29 is a flow chart showing the processing procedure of the output data set processing. The output data setting process is a process of converting each output data into an output format and setting it.

First, the processing for adding and updating (+1) the general-purpose timer is performed (EF42H). The general-purpose timer is a general-purpose timer. Next, processing for setting the data of port C is performed (EF45H). The port C is a port used for controlling the decorative LEDs 32 and 36 and the like. Next, a process of setting the digit 2 output data (decorative LED output data) is performed (EF51H).

Next, it is judged whether or not the error is not occurring. When it is not during the error (when the error is occurring), it is judged whether or not the display switching timing is being performed (EF5FH). If it is determined that it is not during the display switching timing, the error display (E display) is offset (EF63H). That is,
Processing for displaying the error display at a position different from the normal position is performed.

Next, a process of calculating the count data of the number of winning prizes is performed (EF67H). After the calculation of the winning number count data or during the display switching timing, the digit 1 output (number display output) data is set (EF69H). Next, a process of setting digit 2 output data (starting memory display data) is performed (EF71H). Next, processing for setting the digit 3 output data (decorative LED display data) is performed (EF7DH). Next, a process of setting the digit 4 output data (normal symbol display data) is performed (EF
83H). Next, a process of setting the digit 5 output data (normal symbol start memory display data) is performed (EF9
4H). Next, processing for setting the lamp control data in the port D is performed (EFA0H). After that, the output data set process ends.

FIG. 30 is a flow chart showing the processing procedure of the warning processing. The warning process is a process of monitoring a warning flag and setting a warning state. First, the warning flag is checked, and it is determined whether or not an error is occurring (EFBDH). When it is determined that the error is not occurring (when the error is not occurring), the warning process ends. When it is determined that the error is not other than the error (when the error is occurring), the process of setting the warning lamp data is performed (EFC1H). As a result, the lamp data used at the time of warning is set. Next, the process of setting the data at the time of warning of the display is performed (EFD0H).
This sets the data displayed at the time of warning. Next, the warning sound is set (EFD4H).
As a result, the sound generated at the time of warning is set. Then, the warning process ends.

FIG. 31 is a flow chart showing the processing procedure of the information output processing. The information output process is a process of setting each information output data signal.

First, a process for clearing the information output is performed (EFD9H). Next, it is determined whether or not the fever check is being performed (EFDCH). If it is not during the fever check (if the fever check is in progress), it is determined whether or not the valid start information timer has expired (EFE2H). The valid starting information timer is a timer that defines a period for outputting the valid starting information, and the value of the timer is stored in the RAM 403 of the basic circuit 40. The valid start information timer is updated by subtracting from the predetermined value.

When it is determined that the valid starting information timer has not expired, the valid starting information timer is decremented and updated (-
The process of 1) is performed (EFE6H). Next, a process of setting valid start information is performed (EFE9H). If it is not during the fever check, if the valid start information timer has expired, or if the valid start information has been set, whether or not the process state indicated by the process flag is the state before the special winning opening is opened. Is judged (E
FECH). When it is determined that the state is not before the opening of the special winning opening, processing for setting the big hit information is performed (EFF2H).

When it is judged that the state is before the special winning opening is opened or after the big hit information is set, it is judged whether or not the present state is a state other than the probability changing (high probability state). (EFF5H). When it is determined that the state is other than the probability variation, the information output process ends.
On the other hand, if it is determined that the state is not the state other than the probability variation (if the probability variation is occurring), the process of setting the probability variation information is performed (EFF9H). Then, the information output process ends.

FIG. 32 is a flow chart showing the processing procedure of the process processing. The process process is a process in which the process flag WF PRO is judged and each module is branched and executed for each game execution. First, it is determined whether or not an error is occurring (EFFFDH). Specifically, it is determined whether the warning flag is set. When it is determined that the error is not occurring, each process process is executed (F001H). Each process process is as shown in FIG.
It is the symbol process process shown in 5, each process process is executed according to the process flag. After each process process is executed, or when it is determined that an error is occurring, the process process ends.

FIG. 33 is a flowchart showing the processing procedure of the random creation processing. Random creation process is a process of updating the random counter WC RND1 (random counter 1) for big hit determination, a random counter for normal symbol determination (random counter 2), and a random counter WC RNDL for left symbol display. is there.

First, the value of the random counter 1 is updated (+
The process of 1) is performed (F021H). Next, it is determined whether the value of the random counter 1 is less than the maximum value that the counter can take (F024H). If it is determined that the value of random counter 1 is not less than the maximum value,
Processing for clearing the random counter 1 is performed (F0
28H).

After the random counter 1 is cleared, or when it is determined that the random counter 1 is less than the maximum value, a process of setting the updated value of the random counter 1 is performed (F02BH). Next, a process of updating (+1) the value of the random counter 2 is performed (F0
2DH). Next, it is determined whether the value of the random counter 2 is less than or equal to the maximum value that the random counter 2 can take (F030H).

If it is determined that the value of the random counter 2 is not less than or equal to the maximum value, the process of calculating the minimum value of the random counter 2 is performed (F034H). After the calculation of the minimum value of the random counter 2 or when it is determined that the value of the random counter 2 is less than or equal to the maximum value, a process of setting the updated value of the random counter 2 is performed (F036H). Next, a counter update process (P COUNT) is executed to update the value of the random symbol WC RND L for the left symbol display (F038H).
The counter updating process will be described later with reference to FIG.
Then, the random creation process ends.

FIG. 34 is a flow chart showing the processing procedure of the switch processing. The switch process is a process of performing a logic determination process for each switch of the detection switch (detector). First, it is determined whether or not the current state is the probability setting (F041H). When it is determined that the probability is not being set, it is determined whether an error is being made (F045H). Specifically, it is determined whether the warning flag is set. When it is determined that the error is not occurring, the first-class starting opening switch 1 process (P
SW1 1) is executed (F049H). This process will be described later with reference to FIG.

Next, the first type starting port switch 2 process (P
SW12) is executed (F04CH). This processing will be described later with reference to FIG. Next, the normal symbol switch process (P SWZU) is executed (F04F
H). This processing will be described later with reference to FIG.

After execution of the normal symbol switch process, when it is determined that the probability is being set, or when it is determined that there is an error, the count switch process (P
SW09) is executed (F052H). This processing will be described later with reference to FIG. Next, a specific area switch process (P SWV) is executed (F055).
H). This processing will be described later with reference to FIG.
Then, the switch process ends.

FIG. 35 is a flow chart showing the processing procedure of the first type starting opening switch 1 winning determination processing. In the first-class starting opening switch 1 winning determination processing, the first-class starting opening switch 1 (starting ball detector 21) is determined to win, and the value of the random counter WC RND1 is stored in the big hit random storage bank. Is.

First, the switch check processing (P SW
CHK) is executed (F059H). This processing will be described later with reference to FIG. Next, it is determined whether or not the value is other than the switch-on check value (a case where it is checked that the switch is turned on in the switch check process and is used in the same meaning in the following description) (F05FH). When the value is other than the switch-on check value (when the switch is in the off state), the first-type starting opening switch 1 winning determination process ends. On the other hand, if the value is other than the switch-on check value, a random storage process (P BANK SET) is executed (F061).
H). This processing will be described later with reference to FIG.
After that, the first-class starting opening switch 1 winning determination process ends.

FIG. 36 is a flow chart showing the processing procedure of the first type starting opening switch 2 winning determination processing. In the first-type starting opening switch 2 winning determination process, the first-type starting opening switch 2 (starting ball detector 25) is determined to win, and the value of the random counter WC RND1 is stored in the big hit random storage bank. Is.

First, the switch check processing (P SW
CHK) is executed (F064H). This processing will be described later with reference to FIG. Next, it is determined whether the value is other than the switch-on check value (F06A).
H). When it is determined that the value is other than the switch-on check value, the first-type starting opening switch 2 winning determination processing ends. On the other hand, if it is determined that the value is other than the switch-on check value, a process of incrementing (+) the electric prize winning counter is performed (F06CH). The electric prize winning counter is a counter for counting the number of ball hits in the variable starting opening device 16. Next, a random storage process (P BANK SET) is executed (F06FH). This processing will be described later with reference to FIG.

FIG. 37 is a flow chart showing the processing procedure of the random storage processing. Random storage processing, the value of the random counter WC RND1 for big hit determination and the left symbol display random counter WC RND L
This is a process of storing the value of “?” In the big hit random storage bank.

First, it is determined whether or not the number of stored winning awards for winning is the maximum value (F072H). If the number of stored winning awards is the maximum value, the random storage process ends.
On the other hand, if the number of stored winning prizes for winning is not the maximum value, processing for calculating the big hit random storage bank of the storage destination of the value of the random counter 1 is performed based on the current number of stored winning prizes (F078H).

Next, the value of the random counter 1 is stored in the calculated jackpot random storage bank (F081H). Next, the value of the left symbol display random counter WCRND L is stored in the calculated jackpot random storage bank (F085H). Next, a process for incrementing and updating (+1) the winning storage counter is performed (F089H). The winning prize memory counter is a counter for counting the number of starting winning prize memories. After that, the bank storing process ends.

FIG. 38 is a flowchart showing the processing procedure of the count switch winning determination processing. The count switch winning determination process is a process of determining the winning of the count switch (winning prize detector 23) and performing the counting process.

First, it is determined whether or not an error is occurring (F08DH). Specifically, it is determined whether the warning flag is set. If it is determined that an error is not occurring, it is determined whether the count switch valid timer has expired (F091H). The counter and the switch valid timer are timers that define the period during which the winning ball detector 23 detects the winning ball.

If it is determined that the count switch valid timer has not expired, the count switch valid timer is subtracted and updated (-1) (F095).
H). After the subtraction update of the count switch valid timer, when it is determined that an error is occurring, or when the count switch valid timer is determined to have ended, the switch check processing ( P SW CHK) is executed (F098H). This processing will be described later with reference to FIG.

Next, it is judged whether the value is other than the switch-on check value (F09EH). When it is determined that the value is other than the switch-on check value, the count switch winning determination process ends. On the other hand, if it is determined that the value is other than the switch-on check value, a process of incrementing and updating (+1) the prize ball storage counter is performed (F
0A0H). The prize ball storage counter is a counter that stores the number of prize balls.

Next, it is determined whether or not the time is other than the time of illegal winning (F0A3H). When it is determined that the prize is other than the illegal prize (the illegal prize), a process of setting an illegal prize error is performed (F0A7H). As a result, the warning flag for illegal winning is set.
Next, after the fraudulent winning error is set or when it is determined that the prize is not the fraudulent winning, the counting process (P
NINE) is executed (F0AAH). This processing will be described later with reference to FIG. After that, the count switch winning determination process ends.

FIG. 39 is a flowchart showing the processing procedure of the specific area switch winning determination processing. The specific area switch winning determination process is a process of determining a winning of the specific ball detector 22 and performing a specific region operating process.

First, a switch check process is executed for the specific ball detector 22 (F0AEH). Next, it is determined whether the value is other than the switch-on check value (F
0B4H). If it is determined that the value is other than the switch-on check value, the specific area switch winning determination process ends. On the other hand, when it is determined that the value is other than the switch-on check value, the prize ball storage counter is incremented and updated (+1).
Processing is performed (F0B6H).

Next, it is determined whether or not there is an illegal prize (F0B9H). Specifically, it is determined whether the count switch valid timer has expired. If it is determined that the prize is other than the illegal prize (if the prize is judged to be illegal), the illegal prize error set is performed (F0).
BDH). Specifically, the warning flag is set. When it is determined that the prize is other than the illegal prize or the illegal prize error setting is performed, it is determined whether the error is occurring (F0C0H). Specifically, it is determined whether the warning flag is set.

If it is determined that an error is not occurring, it is determined whether or not it is during the valid time of winning the specific area (F0C4H). Specifically, the RA of the basic circuit 40
It is determined whether or not the value of the specific area switch valid timer stored in M403 is 0 (whether or not the timer has expired). If it is determined that it is not during the valid time of the specific area, the specific area switch winning determination process ends.

On the other hand, when it is determined that it is not during the valid time of the specific area, it is determined whether or not the number of times of opening the variable winning ball device 11 is the maximum value (15 times) or more (F).
0C8H). Specifically, the RAM 403 of the basic circuit 40
The value of the release counter stored in is checked. The opening number counter is a counter that counts the number of times the opening / closing plate 14 is opened in the large-sized state.

When it is determined that the number of times of opening is not more than the maximum value, it is determined whether or not the specific area switch-on flag is set (F0CEH). In particular,
In response to the detection by the specific ball detector 22, it is determined whether or not the specific area switch-on flag is set. The specific area switch-on flag is a flag indicating that the specific ball detector 22 has detected a winning ball. If it is determined that the specific area switch-on flag is not set, a process of setting the specific area switch-on flag is performed (F0D2H).

If it is determined that an error is occurring, if the number of times of opening is greater than or equal to the maximum value, if it is determined that the specific area switch-on flag is set,
Alternatively, after the specific area switch-on flag is set, the count processing (PNINE) is executed (F0D5H). The count process will be described later with reference to FIG. After that, the specific area switch winning determination process ends.

FIG. 40 is a flow chart showing the processing procedure of ordinary symbol switch winning determination processing. In the normal symbol switch winning determination process, the passing ball detector 27 determines the winning, and if the starting winning memory of the ordinary symbol is less than the maximum value, the value of the random counter (random counter 2) for determining the winning of the ordinary symbol is set. It is a process of storing, and further, in this process, the addition update of the normal symbol winning award memory counter (+1)
Is also done.

First, a switch check process (P SW CHK) is executed for the passing ball detector 27 (F0
D9H). The switch check process will be described later with reference to FIG. Next, it is determined whether the passing ball detector 27 is in the off state (F0DFH). When it is determined that the passing ball detector 27 is in the off state, the normal symbol switch winning determination process ends.

On the other hand, when it is judged that the passing ball detector 27 is not in the off state, it is judged whether or not the normal symbol starting memory number is the maximum value or more (F0E1H). When it is determined that the value is equal to or larger than the maximum value, the normal symbol switch winning determination process ends. On the other hand, if it is determined that the value is not greater than or equal to the maximum value, the process of calculating the address of the normal symbol random storage bank of the RAM 403 that stores the value of the random counter 2 is performed (F0E7H).

Next, a process of storing the value of the random counter 2 in the calculated normal symbol random storage bank is performed (F0EDH). Next, a process of adding and updating (+1) the normal symbol winning a prize memory counter is performed (F0F1H).
After that, the normal symbol switch winning determination process ends.

FIG. 41 is a flow chart showing the processing procedure of sound processing. The sound process is a process of updating the performance data pointer and performing a sound performance process. The data of sounds used for performance is set in a data table stored in the ROM 401. First, regarding the sound data table, the address of the designated sound data is calculated (F0F5
H). The sound performance is divided into channel 1 performance and channel 2 performance.

Next, it is judged whether or not the channel 1 performance is designated (F105H). When it is determined that the channel 1 performance is not designated, a process of calculating an address designating the channel 2 performance is performed (F10).
8H). If it is determined that the channel 1 performance has been designated or after the address designating the channel 2 performance has been calculated, it is determined whether or not the performance is based on the performance data designated for the channel 1 performance. Is determined (F10DH). If it is determined that the performance is not being performed, the new address of the sound data table and the performance timer are set (F111H). As a result, sound data is set for the channel 1 performance. Next, a tone performance process (P PLAY) for performance data output is executed for the channel 1 performance (F1).
19H). The sound performance processing will be described later with reference to FIG.

Next, processing for setting the performance data of the channel 2 performance is performed (F124H). Next, it is determined whether or not the performance is based on the designated data of the performance of channel 2 (F127H). When it is determined that the performance is not being performed, a new address of the sound data table is set for the performance of channel 2 (F12BH).
As a result, new sound data is set for the channel 2 performance.

Next, it is judged whether or not there is no performance designation for the channel 2 performance (F12FH). When it is determined that the performance is not designated, the sound processing ends.
On the other hand, if it is determined that the performance is not designated, a new performance timer is set for the channel 2 performance (F131H). If it is determined that the performance is being performed based on the specified data of channel 2 or after a new performance timer for channel 2 is set, the sound performance processing (P PLAY) is executed (F135
H). The sound performance processing will be described later with reference to FIG. Then, the sound processing ends.

FIG. 42 is a flow chart showing the processing procedure of the sound performance processing. The sound performance processing is processing for performing the sound performance processing according to the performance code. The details are as follows. Based on the performance data output in the sound processing, the operation is performed while calculating the operation code in the designated sound data table, and the sound data and the sound IC are controlled according to the performance control code.

First, a process of outputting performance preparation data is performed to prepare for performance (F141H). Next, it is determined whether or not there is a sound timer (F14AH). The sound timer is a timer used for playing a sound, and when the timer ends, the sound playing process ends. If it is determined that there is no sound timer, the sound performance process ends. On the other hand, if it is determined that there is a sound timer, the sound timer is decremented and updated (-1), and it is determined whether or not a performance is being performed (F14DH).

If it is determined that the musical performance is being performed, the musical performance processing is terminated. On the other hand, if it is determined that the performance is not being performed, it is determined whether or not the sound data used for the performance has ended in the sound data table (F150H).
If it is determined that the sound data has ended, the sound performance processing ends. On the other hand, if it is determined that the sound data has not ended, it is determined whether or not it is other than the performance jump code (F154H). What is a performance jump code?
This is one type of operation code and is a code for jumping an address in the sound data table. If it is determined that the code is not the performance jump code, a process of calculating the address of the performance jump destination is performed (F1).
5AH). In that case, it is determined whether the sound data has ended, and the following processing is repeated.

On the other hand, if it is determined that the code is other than the performance jump code, it is determined whether the code is other than the performance reset code (F15EH). The performance reset code is one type of operation code and is a code for resetting the performance. If it is judged that it is not a performance reset code (it is a performance reset code),
Reset designation output processing for setting a reset signal is performed (F162H).

Next, the process of calculating the address and timer of the new sound data is performed (F169H). As a result, the sound data and the sound timer are updated. next,
A reset designation canceling process for clearing the reset signal is performed (F16CH). After that, the sound performance process ends.

On the other hand, if it is judged that the code is other than the performance reset code, it is judged whether or not it is the performance waiting code (F175H). The performance waiting code is a kind of operation code and is a code for moving the sound data to the next address. If it is determined that the chord is not a performance waiting chord, a process of outputting sound data is performed (F1).
7BH). Next, it is determined whether or not the performance of the channel 1 is not designated (F180H). If it is determined that the performance is other than the performance on channel 1, the output for designating the performance on channel 2 is performed (F184H).
When it is determined that the performance is other than the designation of the performance of channel 1 or after the designation output of the performance of channel 2 is performed, the process of outputting the write signal is performed (F18DH).

Next, processing for latching the output is performed (F194H). When it is judged that the chord is a performance waiting code or after the output has been latched, the processing of updating (+2) the address of the sound data is performed (F19B).
H), the sound performance process ends.

FIG. 43 is a flowchart showing the processing procedure of the random update processing. The random update process is a process for updating various random counters for normal symbol display, reach operation designation, middle symbol display, and right symbol display.

First, a counter update process (P COUNT) to update the random counter for normal symbol display
Is executed (F19EH). The counter updating process will be described later with reference to FIG. Next, a random counter update process (P COUNT
T) is executed (F1A5H). Next, a counter update process (PCOUNT) is executed to update the random counter WC RND C for displaying the middle symbol (F1).
ACH).

Next, it is judged whether or not there is a carry of WC RND C (F1B3H). If it is determined that there is no carry, the random update process ends. on the other hand,
If it is determined that there is a carry, a random counter update process P COUNT is executed to update the random counter WC RNDR for right symbol display (F1
B5H). Then, the random update process ends.

FIG. 44 is a flow chart showing the processing procedure of the counter update processing. The counter updating process is a process of updating the count values of various counters. First, a process of adding and updating the counter value (+1) is performed (F
1BDH). Next, it is determined whether the updated counter value is less than the maximum value. If it is determined that the value is not less than the maximum value, the value of the counter is cleared (F1C3H). If it is determined that the counter value is less than the maximum value or after the counter value has been cleared, a process of setting the updated counter value is performed (F1C4H). After that, the counter updating process ends.

45 and 46 are flowcharts showing the processing procedure of the normal time processing. The normal process is a process having the following contents. When there is no starting memory (winning memory), normal process data setting processing is performed. When there is a start memory, the execution mode of the shortened mode is determined, the hit determination table corresponding to the probability setting, the big hit determination process, and the bank shift process are performed, and the number of start memories is subtracted.

First, the data set process (P DATASET) is executed for normal work (F1C7).
H). Next, it is determined whether or not there is a winning memory (F1CDH). When it is determined that there is no winning memory, the process / timer processing (P PRO for normal time) is performed.
TM) is executed (F1D1H), and the normal processing ends.

On the other hand, if it is determined that there is a winning record, a process for setting a valid start information output timer is performed (F1D9H). The valid start information output timer is a timer that defines the output time of valid start information. Next, processing for clearing the shortened mode execution flag is performed (F1
DDH). The shortening mode execution flag is a flag indicating whether or not the shortening mode is being executed.

Next, it is determined whether or not the number of winning prizes stored is equal to or greater than a predetermined number of shortened executions for determining whether the shortened mode is executed (F1E3H). When it is determined that the number of winning executions is not more than the number of shortened executions, it is determined whether or not the number of winning prizes is equal to or more than a predetermined number of shortened effective numbers for determining whether or not the continuation of the shortening mode is valid. Done (F1E9
H). If it is judged that it is not more than the shortened effective number,
Processing for clearing the shortened mode valid flag is performed (F
1EDH). The shortened mode valid flag is a flag indicating whether or not the shortened mode is permitted. After that, the process proceeds to a big hit flag clearing process (F200H) described later.

On the other hand, when it is determined that the number of winning prizes stored is equal to or greater than the number of shortened executions, it is determined whether the shortened mode is other than valid (F1F2H). Specifically, it is determined whether or not the shortened mode valid flag is set. If it is determined that the mode is other than the shortened mode valid, the process of setting the shortened command for the display is executed to execute the shortened mode (F1F6H). Next, a process of setting the shortened mode execution flag is performed (F1
FAH).

[0230] If the number of prize winning memories is equal to or greater than the shortened effective number
When the mode is other than the shortened mode valid or after the setting of the shortened mode execution flag, the process of setting the shortened mode valid flag is performed (F1FDH). When the number of winning prizes stored is equal to or greater than the shortened effective number or after the shortened mode effective flag is set, the jackpot flag is cleared (F200H). The big hit flag is a flag for indicating that a big hit has occurred.

Next, the process of calculating the normal probability hourly judgment value table is performed (F203H). The hit determination value table is a table for determining a big hit, and is set in advance for normal time and high probability time. As the hit determination table at the time of high probability, three kinds of hit determination tables of setting 1, setting 2 and setting 3 are preset.
Next, it is determined whether or not the probability is not changing (F206H). Specifically, it is determined whether or not there is a high probability. When it is determined that the probability is not during the probability change, a random check end process (F2
1FH). On the other hand, if it is determined that the probability is other than during the probability change, a process of calculating the hit determination table at the time of high probability of setting 3 is performed (F20AH).

Next, it is determined whether the probability setting is setting 3 (F20DH). When it is determined that the setting is 3, the random check end processing (F2
1FH). On the other hand, if it is determined that it is not the setting 3, the process of calculating the hit determination table at the high probability of the setting 2 is performed (F213H). Next, it is determined whether the probability setting is setting 2 (F216H). If it is determined that the setting is 2, the process proceeds to a random check end process (F21FH) described below. On the other hand, if it is determined that it is not the setting 2, the process of calculating the hit determination table at the time of the high probability of the setting 1 is performed (F21C).
H).

Next, it is judged whether or not the check (random check) for the hit determination based on the calculated hit determination table is completed (F21FH). If it is judged that the random check is not completed, WC RN
It is determined whether D1 is other than the jackpot value (F
227H). When it is determined that the WC RND1 is other than the jackpot value (the jackpot value), the jackpot flag (jack jack flag 1 to jackpot flag 3) is set (F22CH).

When it is determined that the value of WC RND1 is other than the jackpot value or after the jackpot flag is set, the address to be checked in the hit determination table is added and updated (+2) ( F2
2FH), and returns to the process (F21FH) of determining whether or not the random check is completed. The above random value check is repeated until the end of the random check.

On the other hand, when it is determined that the random check is completed, bank shift processing is performed (F23).
3H). Here, a process of clearing the random value after the jackpot determination is completed and shifting the data in the jackpot random storage bank one bank at a time for the jackpot determination of the next random value is performed. Next, subtract and update the winning memory count (-
The process of 1) is performed (F24FH). Next, the process of updating (+1) the process flag is performed (F252).
H). This causes the process to proceed to the next processing. Then, the normal-time process ends.

FIG. 47 is a flow chart showing the processing procedure of the fluctuation start processing. The variation start process is a process of performing a variation start (variable start) process of the special symbol. First, process data / timer processing (P
PRO ™) is executed (F259H). This processing will be described later with reference to FIG.

Next, it is determined whether the process timer is in operation (F25FH). If it is determined that the calculation is in progress, the fluctuation start process ends. On the other hand, when it is determined that the calculation is not in progress, the stop symbol setting process (P ZUSET) is executed (F261H). This processing will be described later with reference to FIG.

Next, it is judged whether or not the probability is changing (during a high probability state) (F264H). If it is determined that the probability fluctuation is not occurring, the reach operation setting process (PR
CHSET) is executed (F268H). This processing will be described later with reference to FIG. 49. On the other hand, when it is determined that the probability is changing, it is determined whether or not the mode is other than the shortening mode (F26DH). Specifically, it is determined whether or not the shortened mode execution flag is set.

When it is determined that the symbol is not in the shortened mode, a process for calculating a flag for stopping all symbols of the special symbol at once is performed (F272H). If it is determined to be in a mode other than the shortening mode or if all symbol simultaneous stop flags have been calculated, it is determined whether or not the winning symbol is not a front / rear stop in the probability variation reach (F274H).
If it is determined in the stochastic variation reach that it is other than the stop before and after the hit, the process of calculating the flag indicating the reach 4 is performed (F286H).

If it is determined in the probability change reach that the hit symbol is other than the stop before or after, or if the flag for reach 4 has been calculated, the reach flag is set (F288H). After the reach operation setting process or after the reach flag is set, the process flag is updated (+1) (F28AH). By updating this process flag, the process shifts to the all reel variation process. Then, the fluctuation start process ends.

FIG. 48 is a flow chart showing the processing procedure of the stop symbol setting processing. The stop symbol setting process is a process of setting stop symbol data of a special symbol and setting of reach operation.

First, a process of clearing the reach selection flag is performed (F291H). The reach selection flag is a flag indicating whether or not a reach is selected. Next, it is judged whether or not it is a jackpot (F294).
H). Specifically, it is determined based on the big hit flag whether or not it is a big hit. When it is determined that it is not the big hit, the big hit stop symbol is set (F298H). Next, the process of setting the reach selection flag at the time of a big hit is performed (F2A0H). Then, the stop symbol setting process ends.

On the other hand, if it is determined that it is not a big hit, a process of setting the left stop symbol is performed (F2A
6H). Next, the process of setting the right stop symbol is performed (F2AAH). Next, a process of setting a medium stop symbol is performed (F2AEH). Next, it is determined whether or not the left, middle, and right stop symbols do not match the big hit symbol (F).
2B2H). When it is determined that it matches the big hit symbol, a counter updating process (P COUNT) for shifting the medium stop symbol from the big hit symbol is executed (F2BC).
H). This counter updating process has been described with reference to FIG.

When it is determined that each symbol does not match the jackpot symbol or after the counter updating process for shifting the medium stop symbol is executed, the flag for selecting normal reach is set (F2C4H). ). Next, for the medium symbol, a process of calculating the distance from the big hit symbol is performed (F2C8H). Next, it is determined whether or not the middle stop symbol is other than the one symbol of the big hit symbol (F2D).
1H), when it is determined that it is not one symbol front of the big hit symbol, a flag for selecting the one symbol front reach is set (F2D5H).

When it is determined that it is other than the one symbol of the big hit symbol or after the flag for selecting the one symbol reach is set, the medium stop symbol is other than the one symbol of the big hit symbol. It is judged whether or not (F
2D9H). When it is determined that it is other than one symbol of the big hit symbol, the stop symbol setting process ends. on the other hand,
When it is determined that the jackpot pattern is not other than one symbol too much, the flag for selecting the one symbol too much reach is set (F2DDH). In this way, the reach selection flag is changed depending on the distance from the big hit symbol of the medium stop symbol. Then, the stop symbol setting process ends.

FIG. 49 is a flow chart showing the processing procedure of the reach operation setting processing. Reach operation setting process
This is a process for setting the reach operation. First, it is determined whether or not the reach selection flag is set (F2E2H). When it is determined that the reach selection flag is other than set (when it is determined that the reach selection flag is set), the process for calculating the reach operation selection table is performed (F2E6H). The reach operation selection table is a table for selecting a reach operation.

Next, the WC for determining the type of reach operation
A process for calculating a pointer for determining the type of reach is performed based on the value of RND RCH (F2ED
H). Next, the process of calculating the reach operation flag indicating the type of reach is performed based on the calculated pointer (F2F0H).

If it is determined that the reach selection flag is not set, or if the reach operation flag has been calculated, the reach operation flag is set (F2F2H). Here, when the reach selection flag has not been set, “0” is set in the reach operation flag, and when the reach operation flag is calculated, the reach operation flag indicating the calculated reach type is set. To be done. Then, the reach operation setting process ends.

FIG. 50 is a flow chart showing the processing procedure of the all reel variation processing. The all-reel changing process is a process for executing the process data of the all-reel changing process. In this process, process data to be executed in normal time, probability change, and shortening mode is calculated.

First, a process for calculating all reel variation process data is performed (F2F5H). Next, it is determined whether or not the shortened mode execution flag is set (F2F8H). When it is determined that the shortened mode execution flag is set, a process of calculating shortened variation process data that is the process data in the shortened mode is performed (F2FCH). When the shortened mode execution flag is not set or after the calculation of the shortened variation process data, it is determined whether the probability variation (during high probability state) is not performed (F2FFH).

If it is determined that the probability is other than during the probability change, it is determined whether or not the reach 4 is set (F303H). If it is determined that the reach 4 is not set, the process of calculating the shortened process data at the time of probability variation is performed (F309H). The shortened process data at the time of probability change is the process data of symbol change at the time of high probability.

If it is determined that the probability is not changing,
If it is determined that Reach 4 is set, or
If it is after the calculation of the shortened process data at the time of probability fluctuation, the process data / timer set process (P PRO
TM) is executed (F30CH). This processing will be described later with reference to FIG. Next, it is determined whether the process timer is in operation (F30FH).
If it is determined that the calculation is being performed, the all reel variation process ends. On the other hand, when it is determined that the calculation is not being performed, it is determined whether or not the mode is the shortening mode in which the probability is changing (F311H).

When it is determined that the mode is not the shortening mode during the probability change, it is determined whether or not the type of reach other than the reach 5 is set (F317H). If it is determined that the type of reach other than the reach 5 is not set, or if it is determined that the mode is the shortening mode in which the probability is changing, the process of setting the right reel stop processing process is performed (F31BH). As a result, the process is set to shift to the right reel stop processing process. When a reach other than the reach 5 is set, or when the right reel stop process is set, the process flag is updated (+1) (F31F).
H). After that, the all reel variation process ends.

FIG. 50 is a flow chart showing the processing procedure of the left reel stop processing. The left reel stop process is a process of performing a stop process of the left reel (left symbol of the special symbol). First, process data / timer set processing (PP
RO ™) is executed (F326H). This processing will be described later with reference to FIG. Next, it is judged whether the process timer is in operation (F32C).
H). When it is determined that the calculation is being performed, the left reel stop processing ends. On the other hand, if it is determined that the process is not being performed, the process flag is updated (+1) (F32EH). After that, the left reel stop processing ends.

FIG. 52 is a flow chart showing the processing procedure of the right reel stop processing. The right reel stop process is a process of performing a stop process of the right reel (the right symbol of the special symbol). First, the process of calculating the right symbol stop process data at normal time is performed (F335H). Normal right symbol stop process data is the process data for stopping the right symbol at normal time.

Next, it is judged whether or not the state is other than the reach state (F338H). If it is determined that the state is not the reach state, the process of calculating the reach advance notice process data is performed (F33EH). The reach announcement process data is process data for giving an advance notice of reaching the reach state. Next, it is determined whether or not the state is reach 2 (F341H). If it is determined that the data is other than the reach 2, the process for calculating the reach 2 advance notice process data is performed (F347H). The reach 2 notice process data is process data for giving notice that the state of reach 2 will occur.

If it is determined to be other than reach, if it is determined to be other than reach 2, or if the reach 2 notice process data has been calculated, the process data / timer set process (P PRO TM ) Is executed (F34AH). This processing will be described later with reference to FIG. Next, it is judged whether the process timer is in operation (F34DH). If it is determined that the calculation is in progress, the right reel stop processing ends. On the other hand, if it is determined that the calculation is not in progress, the process flag is updated (+1) (F34F).
H). After that, the right reel stop processing ends.

FIG. 53 is a flow chart showing the processing procedure of the middle reel stop processing. The middle reel stop process is a process of performing a stop process of the middle reel (the middle symbol of the special symbol). First, reach 1 fluctuation time calculation processing (PRCH1
TIME) is executed (F356H). This processing will be described later with reference to FIG. Next, it is determined whether or not the reach flag indicates reach with a number less than reach 2 (F359H). Reach flag is reach 2
Reach 3 if determined not to reach
The variable time calculation process (PRCH2 TIME) is executed (F35FH). This processing will be described later with reference to FIG.

If it is determined that the reach flag is less than reach 2, or if the reach 3 variable time calculation process has been executed, it is determined whether the reach flag indicates a reach number less than reach 4. Is done (F362
H). If it is determined that the reach flag is not less than reach 4, the reach 6 fluctuation time calculation process (PRCH3
TIME) is executed (F368H). If the reach flag is determined to be less than reach 4 or reach 6
If the variation time calculation process has been executed, it is determined whether a reach other than the reach 4 is set (F36BH). If it is determined that the time is other than reach 4, the reach 4 fluctuation time calculation process (PRCH4 TI
ME) is executed (F371H).

If it is determined that the reach time is other than reach 4, or if the reach 4 change time calculation process is executed,
Processing for calculating middle symbol stop process data is performed (F374H). The medium symbol stop process data is process data for stopping the medium symbol. Next, process data / timer set processing (P PRO ™)
Is executed (F37DH). This process has been described with reference to FIG. Next, it is determined whether the process timer is in operation (F380H). If it is determined that the calculation is in progress, the middle reel stop processing ends.
On the other hand, if it is determined that the calculation is not in progress, the process flag is updated (+1) (F382).
H). Then, the middle reel stop process ends.

FIG. 54 is a flow chart showing the processing procedure of the reach 1 operation time calculation processing. The reach 1 operation time calculation process is a process of calculating the reach 1 operation time. First, the process of calculating the reach 1 stop time table address is performed (F389H). The reach 1 stop time table is a data table of stop times of special symbols in the case of reach 1, and the address thereof is calculated here.

Next, the process of calculating the distance of the medium stop symbol from the big hit symbol is performed (F38CH). Next, a process of calculating the address of the stop time according to the calculated distance is performed (F395H). Next, the reach 1 stop time obtained based on the calculated stop time address is set (F398H). Then, the reach 1 operation time calculation process ends.

FIG. 55 is a flow chart showing the processing procedure of the reach-3 operation time calculation processing. The reach 3 operation time calculation process is a process of calculating the reach 3 operation time. First, a process for calculating the reach 3 stop time table address is performed (F39DH). The reach 3 stop time table is a data table of stop times in the reach 3. Here, the address of the table is calculated. Next, the distance from the big hit symbol of the medium symbol is calculated (F3A0H).

Next, processing for calculating the address of the stop time is performed based on the calculated distance (F3A9).
H). Next, the process of setting the reach 3 swimsuit upper time is performed. Here, the reach-on-3 swimsuit running time is the operation time of the image peculiar to reach 3. Next, a process for setting the normal reach time of reach 3 obtained based on the calculated stop time address is performed (F3B5H). After that, the reach 3 operation time calculation process ends.

FIG. 56 is a flow chart showing the processing procedure of the reach 6 operation time calculation processing. The reach 6 operation time calculation process is a process of calculating the reach 6 operation time. First, the process of calculating the address of the reach 6 stop time table is performed (F3BAH). The reach 6 stop time table is a data table of the stop time of the reach 6. Here, the address of the table is calculated. Next, a process of calculating the distance of the medium symbol from the big hit symbol is performed (F3BDH). Next, processing for calculating the stop time address is performed based on the calculated distance (F3C6H). Next, a process of holding the operation time obtained based on the calculated stop time address as the calculation basic time is performed (F3C9H).

Next, the operation time obtained based on the calculated stop time address is set in the timer (F3CFH, F3D5H). Then, the reach 6 operation time calculation process ends.

FIG. 57 is a flow chart showing the processing procedure of the reach 4 stop position flag setting processing. Reach 4
The stop position flag setting process is a process of setting the stop position flag in the reach 4.

First, a process for clearing the reach 4 stop position flag is performed (F3DDH). The reach 4 stop position flag is a flag indicating the stop position of the middle symbol in the reach 4. Next, a process of calculating the distance of the medium symbol from the big hit symbol is performed (F3E0H). Next, based on the calculated distance, it is determined whether or not the stop position of the right symbol is a stop before the big hit symbol (F3E5H). If it is judged that the stop is before the big hit symbol,
A process of setting the one symbol front stop position flag is performed (F3FAH). Then, the reach 4 stop position flag setting process ends.

On the other hand, when it is determined that the stop is not before the big hit symbol, it is determined whether the stop is other than the big hit symbol (F3EBH). When it is determined that it is not the stop other than the big hit symbol, the big hit symbol stop position flag is set (F3EE).
H). Then, the reach 4 stop position flag setting process ends. On the other hand, when it is determined that the stop is other than the big hit symbol, a process of setting the one-symbol too-stop position flag is performed (F3F4H). Then, the reach 4 stop position flag setting process ends.

FIG. 58 is a flow chart showing the processing procedure of the fever check processing. The fever check process determines whether or not it is a big hit, and when it is determined to be a big hit, the probability change flag is set at the time of a big hit in the probability change pattern, and the process process thereafter is set. This is the process of

First, process data / timer set processing (P PRO TM) is executed (F3FFH). This processing will be described later with reference to FIG. Next, it is determined whether or not the process calculation is in progress (F405).
H). If it is determined that the calculation is in progress, the fever check process ends. On the other hand, if it is determined that the calculation is not in progress, it is determined whether or not the jackpot is in the jackpot state based on the jackpot flag (F407H).

If it is determined that the jackpot is not a big hit, processing for clearing the process flag is performed (F40B).
H). Next, a process data set process (PPRO SET) is executed to display a symbol (F40EH).
This processing will be described later with reference to FIG. 63. next,
The process of setting the process data address is performed (F414H). Here, the process of setting the reel display process data at the normal time and setting the head address to the demo display (demonstration display) process is performed.

On the other hand, if it is determined that the jackpot is a big hit, the process flag is updated (+1) (F41BH). As a result, the process flag is updated to the one corresponding to the special winning opening opening preprocessing. Next, it is determined whether or not the big hit symbol is other than the probability variation symbol (F41EH). The stochastic fluctuation symbol is a jackpot symbol that shifts to a high probability state. When it is determined that the symbol is not the probability variation symbol, the probability variation flag is set (F428H). The probability changing flag is a flag that indicates a high probability state.

After the process data address is set, when it is determined that the pattern is not the probability variation pattern, or when the probability variation flag is set, a process of clearing each usage flag is performed ( F42CH).
Each use flag here includes a big hit flag, a reach operation flag, and a display control transfer counter. Then, the fever check process ends.

FIG. 59 is a flowchart showing the processing procedure of the special winning opening opening preprocessing. Pre-opening process
This is a process for performing settings before opening the special winning opening. First, the process of calculating the address of the process before opening the special winning opening is performed (F434H). Next, process data / timer set processing (P PRO TM) is executed (F43D).
H). This processing will be described later with reference to FIG.

Next, it is determined whether or not the process operation is in progress (F440H). When it is determined that the calculation is in progress, the special winning opening opening preprocessing is ended. On the other hand, when it is determined that the calculation is not in progress, a process of clearing the work area data of the RAM 403 used during the big hit is performed (F442H). The works in this case include the work of the specific area switch-on flag and the work of the winning number counter. Next, processing for updating (+1) the process flag is performed (F447H). As a result, the process is updated to the special winning opening opening process. Then, the special winning opening pre-processing is completed.

FIG. 60 is a flowchart showing the processing procedure of the special winning opening opening processing. Processing during the opening of the special winning prize,
This is a process for performing the process of opening the special winning opening. First, a process of setting the count switch effective time is performed (F44EH). Next, a process of setting the specific area effective time is performed (F453H).

Next, it is judged whether or not the winning number indicated by the value of the winning number counter is equal to or more than the maximum value (F45).
8H). When it is determined that the number of winning prizes is not equal to or more than the maximum value, a process for calculating the special winning opening opening process address is performed (F45EH). As a result, the value of the opening counter is obtained. Next, process data / timer set processing (P PRO TM) is executed (F467).
H). This processing will be described later with reference to FIG.

Next, it is determined whether the process timer is in operation (F46AH). When it is determined that the calculation is being performed, the special winning opening opening process is ended. When it is determined that the winning number is equal to or more than the maximum value or when it is determined that the calculation is not in progress, the process flag is updated (+1) (F46CH). As a result, the process flag is updated to the one corresponding to the special winning opening opening post-processing. After that, the special winning opening opening process ends.

FIG. 61 is a flowchart showing the processing procedure of the special winning opening post-processing. After opening the special winning opening,
This is a process of performing the process process after opening the special winning opening and updating the probability variation frequency (-1).

First, a process of setting the count switch effective time is performed (F473H). Next, it is determined whether or not the specific area is not valid (F478).
H). When it is determined that the time is not during the specific area effective time, the value of the specific area effective time timer is updated (-1) (F47CH).

Next, it is determined whether or not the specific area effective time timer is being calculated (F47FH). When it is determined that it is not during the specific area effective time or when it is determined that the calculation is not being performed, it is determined whether or not there is no prize in the attacker (special winning opening) (F481).
H). Here, it is determined whether or not the count value of the winning number counter is 0. If it is determined that the prize has been won in the attacker, a process of setting the count switch shift warning flag is performed (F485H). The count switch shift warning flag is a flag that warns that the count switch has been illegally shifted from the attacker winning passage.

If it is determined that the above calculation is in progress, if it is determined that no prize has been won in the attacker, or if the count switch shift warning flag has been set, then no prize has been won in the specific area. It is determined whether there is any (F488H). Here, it is determined whether or not the specific area switch-on flag is set. If it is determined that the winning is in the specific area, the process flag is set to a value before opening the special winning opening (F48CH). Next, update the release counter (+
The process of 1) is performed (F493H). After that, the process after opening the special winning opening ends.

On the other hand, if it is determined that no prize has been won in the specific area, the process data is set (F498H). Next, it is determined whether the process timer is in operation (F49EH). If it is determined that the calculation is in progress, the special winning opening post-processing is ended. On the other hand, if it is determined that the calculation is not in progress, the process of clearing the process flag is performed (F4A0).
H). Next, a process of updating (-1) the number of times of probability variation is performed (F4A5H). Next, a process data / timer set process (P PRO SET) is executed to display a symbol (F4ACH). Next, the process of setting the address of the process data for the demonstration display (demonstration display) is performed (F4B2H). afterwards,
After the special winning opening is opened, the processing ends.

FIG. 62 is a flow chart showing the processing procedure of process data / timer processing. In the process data / timer processing, processing for executing process data is performed.

First, process data set processing (P P
RO SET) is executed (F4B8H). This processing will be described later with reference to FIG. 63. Next, it is determined whether the process timer has expired (F4BB
H). If it is determined that the process timer has not expired, the process timer is updated (-1) (F4BFH). Next, it is determined whether the process timer is in operation (F4C2H). When it is determined that the calculation is not in progress, the process data address is updated (+5) (F4C4H). Next, it is determined whether the process data has ended (F4CBH).

If it is determined that the process timer has expired or if the process data has been terminated, a process of setting a new process address and process timer is performed (F4CFH). After that, the process data / timer processing ends.

On the other hand, when it is determined that the process data has not ended, it is determined whether the process data is other than the external timer reference code (F4DAH). If it is determined that the code is other than the external timer reference code, reach 4
It is determined whether the code is a code other than the code corresponding to (F4DEH). When it is determined that the code is other than the code corresponding to the reach 4, it is determined whether or not it is the process end position (stop position of the reach 4) (F
4E5H). When it is determined that the process end position is not reached, a process of setting the basic timer of the reach 4 is performed (F4EBH). The basic timer of the reach 4 is a timer that defines the movement time of one symbol of the reach 4.

If it is determined that the process end position has been reached or if the reach 4 basic timer has been set, a process for calculating the process at the time of disconnection stop is performed (F4F2H). Next, it is determined whether or not it is other than the stop at the big hit position (F4F5H). When it is determined that the operation is other than the big hit stop, a process of calculating the process at the big hit stop is performed (F4F9H). If it is determined that the process is not at the big hit position stop, or if it is after the process calculation at the time of the big hit stop, processing for setting the process data address is performed (F4FC
H).

If it is determined that the code is other than the external timer reference code in the above-described determination as to whether the code is other than the external timer reference code or if the process data address has been set, a new process timer is set. Processing is performed (F50BH).

If it is determined that the code is other than the code corresponding to the reach 4, it is determined that the code is not the code corresponding to the reach 4, the process for setting the external reference timer is performed ( F500H). When it is judged that the process timer is being calculated or not, after the external reference timer has been set, or when the new process timer has been set. Performs processing for setting a display communication command (command data) (F511H). Next, processing for setting the in-operation flag is performed (F51
BH). After that, the process data / timer processing ends.

FIG. 63 is a flow chart showing the processing procedure of process data set processing. The process data set process is a process of determining / setting a process data pointer and setting data.

First, it is determined whether the process is currently being executed (F51DH). If it is determined that the process is not currently being executed, a process of setting a new process address is performed (F521H). Next, it is determined whether the command is other than the external reference command (F525H). When it is determined that the command is not the external reference command, the process of calculating the external reference timer is performed (F52FH). If it is determined that the command is other than the external reference command or if the external reference timer has been calculated, the process of setting the process timer is performed (F536H).

If it is determined that the process is currently running, or after the process timer has been set,
The process of calculating the address of the lamp data is performed (F
538H). Next, it is determined whether the lamp data is currently being executed (F541H). If it is determined that the lamp data is not currently being executed, processing for setting a new lamp data address is performed (F54).
7H). Next, a new lamp timer (lamp timer)
Is set (F54BH). If it is determined that the lamp data is currently being executed, or if the new lamp timer has been set, a process of setting the sound performance flag is performed (F54FH). Then, the process data set processing ends.

FIG. 64 is a flow chart showing the processing procedure of the switch check processing. The switch check process is a process of determining the operation and setting the operation of each switch.

First, a process of calculating data input from the input port is performed (F556H). Next, it is determined whether or not the designated switch is on (F5
5CH). When it is determined that the designated switch is not turned on, processing for clearing the designated error (warning flag) is performed (F563H). Next, processing for clearing the switch counter is performed (F56A
H). After that, the process proceeds to a switch counter setting process described later.

On the other hand, when it is determined that the designated switch is on, it is determined whether the switch counter is less than the maximum value (F56FH). When it is determined that the switch counter is not less than the maximum value, the process of setting the designated error flag (warning flag) is performed (F578H). This post-processing proceeds to switch counter setting processing, which will be described later. On the other hand, when it is determined that the switch counter is less than the maximum value, the process of updating (+1) the switch counter is performed (F
582H).

After the switch counter has been cleared, after the designated error flag has been set, or after the switch counter has been updated, processing for setting the switch-on counter is performed (F588H). Next, a process for performing a switch-on check is performed (F58BH). Then, the switch check process ends.

FIG. 65 is a flow chart showing the processing procedure of the count processing. The count process is a process of updating the counter. Specifically, in order to update the winning number counter, the shift warning flag is cleared and the update condition of the counter is determined.

First, the count switch shift warning flag is cleared (F590H). Next, it is determined whether or not the process is in a state before the special winning opening is opened (F593H). When it is determined that the special winning opening has not been opened, the counting process ends. On the other hand, when it is determined that it is not before the opening of the special winning opening, it is determined whether or not the state is other than the opening of the special winning opening (F
599H). When it is determined that it is not during the opening of the special winning opening, it is determined whether there is a first opening operation of the special winning opening (F59BH).

If it is determined that there is no opening operation for the first time, the counting process ends. When it is determined that it is not during the opening of the special winning opening, or when it is determined that the first opening operation has been performed, it is determined whether the number of winning prizes is the maximum value or more (F5A0H). When it is determined that the number of winning prizes is equal to or more than the maximum value, the counting process ends. On the other hand, if it is determined that the winning number is not greater than or equal to the maximum value, the winning number counter is updated (+1) (F5A6H), and the counting process ends.

FIG. 66 is a flow chart showing the processing procedure of normal symbol process processing. The normal symbol process process is a process of judging the normal symbol process flag and branching and executing each module for each game execution. First, it is determined whether or not an error is occurring by determining whether or not the warning flag is set (F5AA
H). If it is determined that an error is occurring, the normal symbol process processing ends.

On the other hand, if it is determined that the error is not occurring, a process of clearing the electric accessory solenoid data is performed (F5AEH). The electric accessory solenoid data is data for driving the solenoid 26. Next, processing for executing each process routine is performed according to the normal pattern process data (F5B1H). After that, the normal symbol process process ends.

FIG. 67 is a flow chart showing the processing procedure of normal symbol normal time processing. Ordinary symbol winning memory number (starting memory number) determination process and update process, normal symbol random counter value hit determination process, normal symbol start memory data bank shift process.

First, it is determined whether or not there is a normal symbol winning memory (F5C3H). When it is determined that there is no normal symbol winning award memory, the normal symbol normal time process ends. On the other hand, when it is determined that there is a normal symbol winning award memory, each data such as a normal symbol check value (hit determination value) and a normal symbol variation time is extracted (F
5C7H).

Next, it is judged whether the probability changing flag is not set (= 0) (F5CC).
H). When it is determined that the probability variation flag is not set, it is determined whether or not the special symbol process is in a state before the special winning opening is opened (F5D).
OH). If it is determined that it is not before the big winning opening, normal symbol check value (hit judgment value) at the time of probability fluctuation
And each data such as normal symbol variation time is extracted (F5D6H).

If it is determined that the probability fluctuation flag is not set, if it is determined that the special symbol process is before the special winning opening is opened, or after the extraction of each data relating to the normal symbol at the time of probability variation. In this case, the process of setting the variation time of the normal symbol is performed (F5DBH).

Next, a process of updating (-1) the normal symbol winning award memory counter is performed (F5DDH). Next, a process of designating a normal symbol hit stop symbol is performed (F5).
E0H). Next, it is determined whether or not the random value stored in the normal symbol random storage bank is a winning value (F5E2H). If it is judged that it is not a hit,
The process of designating the stop symbol of the normal symbol is performed (F
5E6H). If it is determined that the value stored in the normal symbol random storage bank is a hit, or if the normal symbol deviation stop symbol has been designated, a process of setting a stop symbol of the normal symbol is performed (F5EDH).

Next, the normal symbol process flag is updated (+
The process of 1) is performed (F5EFH). Next, a process of shifting the stored values of the normal symbol random storage bank one by one is performed (F5F2H). After that, the normal symbol normal time processing ends.

FIG. 68 is a flow chart showing the processing procedure of normal symbol variation time processing. Ordinary symbol fluctuation process,
It is a process of updating the normal symbol variation timer and performing a variation process of the normal symbol.

First, it is judged whether or not the normal symbol variation timer has ended (F5FDH). The normal symbol variation timer is a timer that defines the variation time (variable display time) of the ordinary symbol, and down counts with the passage of time. If it is determined that the normal symbol variation timer has not ended, the process of updating (-1) the value of the normal symbol variation timer is performed (F601H). next,
Normally, it is determined whether or not the symbol variation timer has ended (F602H).

When it is judged that it has ended in the judgment of the end of the first normal symbol fluctuation timer (F5FDH) or the judgment of the end of the second normal symbol fluctuation timer (F60
When it is determined that the process is finished in 2H), the process of setting the normal symbol variation timer is performed (F60).
6H). Next, a counter updating process (P COUNT) for the decorative symbol counter is executed (F60AH).
If it is determined that the normal symbol variation timer has not expired or if the decorative symbol counter updating process has been executed, the normal symbol process timer process (PFTIM) is executed (F612H).

Next, it is judged whether the process timer is being calculated (F615H). When it is determined that the calculation is in progress, the normal symbol variation time process ends. On the other hand, when it is determined that the calculation is not in progress, the process of setting the stop symbol of the normal symbol is performed (F617H).
Next, processing for extracting the process time depending on each state of the game is performed (F61BH).

Next, a process for setting the electric accessory release time is performed (F62FH). The electric accessory opening time means an opening time of the movable piece 17 of the variable starting opening device 16.
Next, a process of clearing the electric prize winning counter is performed (F634H). The electric prize winning counter is a counter of the number of winning prizes detected by the starting ball detector 25 after winning the variable starting opening device 16. Next, the process of updating (+1) the normal symbol process control flag is performed (F
637H). After that, the normal symbol variation process ends.

FIG. 69 is a flow chart showing the processing procedure of normal symbol stop processing. Ordinary symbol stop process,
It is a process of performing a hit determination process of a normal symbol, an output process of solenoid output data, and a stop time determination process of a normal symbol.

First, a process of clearing the electric accessory solenoid output is performed (F63BH). Next, it is judged whether or not the stop symbol of the normal symbol is a winning symbol (F6).
3EH). When it is determined that the stop symbol is the winning symbol, a process of setting the electric accessory solenoid output to open the movable piece 17 is performed (F644H). Next, it is determined whether or not the number of winning prizes for the electric accessory is less than the maximum value (F647H).

When it is determined that the stopped symbol is not a winning symbol or when the number of winning the electric accessory is less than the maximum value, the normal symbol process timer process (PFT)
IM) is executed (F34DH). The normal symbol process timer processing will be described later with reference to FIG. Next, it is determined whether the process timer is being calculated (F650H). When it is determined that the calculation is in progress, the normal symbol stop processing ends.

When it is determined that the number of winning electric prizes is less than the maximum value or when it is determined that the process timer is not being calculated, each data of the normal symbol process flag and electric prize data is cleared. Processing is performed (F652H). The electric accessory data is data relating to the driving of the variable starting opening device 16. After that, the normal symbol stop process ends.

FIG. 70 is a flow chart showing the processing procedure of normal symbol process timer processing. Normal symbol process timer process is a process of performing the determination process and update process of the normal symbol process timer. First, it is determined whether the normal symbol process timer is 0 (F65).
9H). If it is determined to be "0", the normal symbol process timer process ends. On the other hand, when it is determined that it is not "0", the process of updating the normal symbol process timer (-1) is performed (F65DH), and the normal symbol process timer process is ended.

FIG. 71 is a flow chart showing the processing procedure of data set processing. The data set process is a process of storing specified data in a work to which the data is transferred.

First, a process of calculating the number of transfer data is performed (F661H). Next, a process of calculating transfer data is performed (F664H). Next, a process of calculating the transfer destination address is performed (F666H). Next, a process of setting transfer data is performed (F669H). Next, a process of updating (+3) the address designating the transfer data is performed (F66CH). Next, a process of updating (-1) the number of remaining data is performed (F66FH). The number of remaining data means the number of transfer data which has not been transferred yet and remains.

Next, it is judged whether or not the transfer of all transfer data has been completed (F670H). If it is determined that the transfer of the transfer data is not completed, the process returns to the transfer data calculating step, and the above-described processing is repeated until the transfer of all the transfer data is completed. On the other hand, if it is determined that the transfer of all transfer data has been completed, the data set processing ends.

FIG. 72 is a flow chart showing the processing procedure of the probability setting processing. The probability setting process is a process of setting the probability of the big hit determination. Here, the configuration of the probability setting key switch will be briefly described. The probability setting key switch is designed so that a probability of jackpot determination can be set by inserting a key into a key hole of the probability setting key switch and turning the key. The key can be turned to the left and right, and the probability is set by operating the key to the left position, the right position, and their neutral position. In addition, in the vicinity of the probability setting key switch, setting 1,
A display unit is provided to display which of the setting 2 and the setting 3 is set by lighting the LED.

First, a switch check process (P SW CHK) is executed to determine the probability setting key switch (F676H). Next, it is determined whether or not the probability setting switch is set to the left (F67C).
H). If it is determined that the probability setting switch is set to the left, the process proceeds to probability setting mode processing described later (see FIG. 73). On the other hand, if it is determined that the probability setting switch is not set to the left side, the switch setting process (P SW CHK) is performed for the probability setting key switch.
Is executed (F67EH). This processing has been described with reference to FIG.

Next, it is determined whether the probability setting switch is set to the right (F684H). If it is determined that the probability setting switch has been set to the right, the process proceeds to the probability changing mode process (see FIG. 74). on the other hand,
If it is determined that the probability setting switch is not set to the right, a process of clearing the probability setting work is performed (F686H).

Next, it is judged whether the probability setting is the normal time (F68BH). If it is determined that it is the normal time, the probability setting process ends. On the other hand, if it is determined that it is not the normal time, it is determined whether the probability setting display timer has expired (F690).
H). The probability setting display timer is a timer that defines a period in which the probability setting 1 to 3 is displayed.

When it is determined that the probability setting display timer has not expired, the probability setting display timer is updated (-1).
Processing is performed (F694H). Next, it is determined whether or not the probability setting display has ended (whether or not the probability setting display timer has ended) (F697H). If it is determined that the probability setting display has not ended, the process proceeds to display data set processing described later (see FIG. 77).

On the other hand, if it is determined that the probability setting display has ended or if the probability setting display timer has ended (F690H), the probability setting flag is cleared. Done. The probability setting flag is a flag indicating that the probability is being set.

Next, the serial ROM read processing (LRO
MREAD) is executed (F69CH). This processing will be described later with reference to FIG. 81. Next, a probability / probability setting display setting process (PSET RND) is executed (F69FH). This processing will be described later with reference to FIG. 78. Next, it is placed in an interrupt waiting state (F6A2
H).

If it is determined that the probability setting switch is set to the left side in the determination as to whether it is on the left side or not, the process proceeds to the probability setting mode process. FIG. 73 is a flowchart showing the processing procedure of the probability setting mode processing. The probability setting mode process is a process of setting probability display data.

First, it is judged whether or not the probability setting flag is normally set (F6A4H). If it is determined that the flag is normally set, the process proceeds to display data setting processing described later (see FIG. 77). On the other hand, if it is determined that the flag is not set at the normal time, it is determined whether the probability is being set (F6A8H).

When it is determined that the probability is being set,
Proceed to the display data set process described later (see FIG. 77).
On the other hand, if it is determined that the probability is not being set, the probability setting rewriting step counter is updated (+1) (F6ACH). The probability setting rewriting step counter is a counter used for rewriting (changing) the probability setting. Next, a process of setting the probability setting display timer is performed (F6AFH). After that, the process proceeds to the probability / probability setting display setting process (see FIG. 78).

When it is determined that the probability setting switch is on the right side as described above,
Proceed to the probability changing process (step 1). FIG. 74 is a flowchart showing the processing procedure of the probability changing processing (step 1). (Probability changing process step 1) is a process of executing step 1 of the probability changing process.

First, it is judged by the probability setting flag whether it is a normal time or not (F6B6H). If it is determined that it is normal time, probability change processing (step 1)
Ends. On the other hand, if it is determined that the probability setting display timer is not normal, it is determined whether the probability setting display is completed by checking the probability setting display timer (power-on switch right) (F6BAH).

If it is determined that the display has been completed, the process proceeds to the probability / probability setting display setting process described later (see FIG. 78). On the other hand, if it is determined that the display has not ended, a process of setting the probability setting display timer is performed (F6BEH). Next, it is judged whether the probability setting rewriting step counter is other than 1 (F6C3).
H). When it is determined that the value of the probability setting rewriting step counter is other than 1, the process proceeds to a probability changing process (step 2) described later (see FIG. 75). On the other hand, when it is determined that the value of the probability setting rewriting step counter is 1,
Regarding the probability setting rewriting step counter, counter updating processing (P COUNT) is executed (F6C7H). This processing has been described with reference to FIG.

Next, the serial ROM preparation processing (LROM
SET) is executed (F6CFH). This processing will be described later with reference to FIG. Next, a process of updating (+1) the probability setting rewriting step counter is performed (F
6D4H). Then, the process proceeds to the display data set process described later (see FIG. 77).

FIG. 75 is a flow chart showing the processing procedure of the probability changing processing (step 2). The probability changing process (step 2) is a process of executing step 2 of the probability changing process.

First, it is determined whether or not the probability setting rewriting step counter is other than step 2 (2) (F).
6D9H). If it is determined to be other than step 2, the process proceeds to the probability setting process (step 3) (see FIG. 76). On the other hand, when it is determined to be step 2,
Serial ROM preparation processing (LROMSET) is executed (F6DCH). This processing will be described later with reference to FIG.

Next, the serial ROM write processing (ROM
WRITE) is executed (F6E1H). This processing will be described later with reference to FIG. Next, the probability setting rewriting step counter is updated (+1) (F6E6H). Then, the process proceeds to the display data set process (see FIG. 77).

FIG. 76 is a flow chart showing the processing procedure of the probability changing processing (step 3). The probability changing process (step 3) is a process of executing step 3 of the probability changing process.

First, the probability setting rewriting step counter is decremented and updated (-1), and it is judged whether or not the counter is other than step 3 (3) (F6EBH). If it is determined to be other than step 3, the probability changing process (step 3) ends. On the other hand, if it is determined to be step 3, it is determined whether or not the serial ROM operation is being written (F6EEH). If it is determined that writing is in progress, probability change processing (step 3)
Ends. On the other hand, if it is determined that the writing is not in progress, the serial ROM preparation processing (LROMSET) is executed (F6F5H). This processing will be described later with reference to FIG.

Next, the probability / probability setting display setting process (PS
ET RND) is executed (F6FAH). This processing will be described later with reference to FIG. 78. Next, a process of adding and updating (+1) the probability setting rewriting step counter is performed (F6FDH). Then, the process proceeds to the display data set process (see FIG. 77).

FIG. 77 is a flow chart showing the processing procedure of the display data set processing. The display data setting process is a process of setting probability setting display data. In this processing, processing for setting probability setting display data is performed (F700H). Then, the display data set process ends.

FIG. 78 is a flow chart showing the processing procedure of the probability / probability setting display setting processing. The probability / probability setting display setting process is a process of setting a probability and setting probability setting display data.

First, the probability setting table address is calculated (F705H). The probability setting table is a data table of probability setting data. Here, the process of calculating the address of the probability setting data corresponding to the value of the probability setting flag is performed. Next, in the probability setting table, the probability setting data written in the calculated address is set to the probability setting display data (F70EH). Next, based on the probability setting data written in the calculated address, random 1 (WC
A process of setting the maximum value of RND1) is performed (F7).
12H). After that, the probability / probability setting display setting process ends.

FIG. 79 is a flow chart showing the processing procedure of serial ROM write clock processing. Serial R
The OM write clock process is a process for writing serial ROM data. First, a process of setting the serial ROM write data and the SK signal (= 1) to the port I is performed (F717H). (Port I is one output port of the basic circuit 40.) Next, the SK signal (=
0) is set to port I (F71C
H). After that, the serial ROM write clock processing ends.

FIG. 80 is a flow chart showing the processing procedure of the serial ROM preparation processing. The serial ROM preparation process is a process of preparing for the operation of the serial ROM. First, a process of saving the write data to the serial ROM is performed (F722H). Next, a process of setting the CS (chip select) signal to the ON state is performed (F
726H). Next, the serial ROM write clock processing (LSET SK) for turning on and off the SK signal is executed (F72FH). This processing has been described with reference to FIG. 79.

Next, the processing counter is set (F731H). The processing counter is a counter that defines a period during which data output processing is performed. Next, a process of setting write data is performed (F733H). next,
Serial ROM write clock processing (LSET SK) is executed (F73BH). This process is shown in FIG.
It was described using 9. Next, update the processing counter (-
The process of 1) is performed (F73DH).

Next, it is judged whether or not the value of the processing counter is other than 0 (F73EH). If this processing counter is other than 0, data output processing is in progress.
If the processing counter is other than 0, the write data is set (F733H) to the processing counter is updated (F73D).
The processing of H) is repeatedly executed.

On the other hand, when it is determined that the value of the process counter is 0, it is determined whether the process is a process other than the read / write process (F740H). If it is judged that the processing is other than read / write processing, serial RO
The M preparation process ends. On the other hand, if it is determined to be the read / write processing, processing for setting the CS signal to the ON state is performed (F746H).

Next, serial ROM write clock processing for turning the SK signal on and off is executed three times in succession (F7
4FH, F751H, F753H). Each of these processes has been described with reference to FIG. 79. Next, processing for setting the CS signal to the off state is performed (F755H). This completes the preparation for operating the serial ROM. Then, the serial ROM preparation process ends.

FIG. 81 is a flow chart showing the processing procedure of serial ROM read processing. The serial ROM read process is a process of reading (reading) data from a serial ROM (EEPROM). First, serial R
In order to set the OM read command / address, the serial ROM preparation processing (LROMSET) is executed (F75DH). This process has been described with reference to FIG. Next, the CS signal is set to the ON state, the process counter is set, and the read work is cleared (F762H).

Next, the serial ROM write clock processing (LSETSK) described above is executed for the SK signal (F772H). Next, the data is read (F775H). Next, the processing counter is updated (-1) (F780H). Next, it is judged whether or not the value of the processing counter is other than 0. When it is determined that the value of the processing counter is other than 0, the value of the processing counter is 0 in the serial ROM write clock processing (F772H) to the updating processing of the processing counter (F780H).
Is repeatedly executed until.

When it is determined that the value of the processing counter is 0, it is determined whether the read data is less than the maximum value (F785H). When it is determined that the read data is not less than the maximum value, the read data (read data) is cleared (F78AH).
If it is determined that the read data is less than the maximum value or if the read data has been cleared, a process of setting the read data is performed (F78BH). As a result, the probability setting value flag is set. Next, processing for setting the CS signal to the off state is performed (F78DH). After that, the serial ROM read processing ends.

FIG. 82 is a flow chart showing the processing procedure of the serial ROM write processing. The serial ROM write process is a process for performing a data write process on a serial ROM (EEPROM).

First, the process of temporarily storing the read data is performed, and the process counter is set (F797).
H). Next, a process of setting clear data (0 data) and setting the CS signal to the ON state is performed (F79BH). Next, the serial ROM write clock process (LSET SK) is executed (F7A4H). Next, processing for updating (-1) the processing counter is performed (F7A7H).

Next, it is judged whether or not the value of the processing counter is other than 0 (F7A8H). When it is determined that the value of the processing counter is other than 0, the serial RO
The M write clock process (F7A4H) and the process counter update process (F7A7H) are repeatedly executed until the value of the process counter becomes zero.

On the other hand, if it is determined that the value of the processing counter is 0, the processing of setting the processing counter is performed (F7AAH). Next, processing for setting the CS signal to the ON state is performed (F7AEH). Next, a process of setting write data is performed (F7B2H). next,
Serial ROM write clock processing (LSET SK) is executed (F7BAH). This process is shown in FIG.
It was described using 9.

Next, the processing counter is updated (-1) (F7BDH). Next, it is judged whether or not the value of the processing counter is other than 0 (F7BE).
H). When it is determined that the value of the processing counter is other than 0, the write data setting process (F7B2H) to the processing counter updating process (F7BDH) are repeatedly executed until the value of the processing counter becomes zero.

On the other hand, if it is determined that the value of the processing counter is 0, the CS signal is set to the off state, and then the on signal is set to the on state (F7C0).
H). Then, the serial ROM write process ends.

FIG. 83 is a flow chart showing the processing procedure of the hit ball signal processing. The hit ball signal processing is processing for updating the hit ball signal processing counter. First,
Processing for clearing the hit ball signal counter is performed (F7
CFH). The winning ball signal counter is a winning ball (winning ball)
A counter that counts signals.

Next, it is determined whether or not the hitting ball signal input is in the off state (F7D0H). When it is determined that the hit ball signal input is not in the off state (when it is in the on state), it is determined whether the value of the hit ball signal counter is equal to or more than the maximum value (F7D7H). If it is determined that the value is not greater than or equal to the maximum value, a process of adding and updating (+1) the winning ball signal counter is performed (F7DDH).

When it is judged that the hit ball signal input is in the off state, when it is judged that the value of the hit ball signal counter is equal to or larger than the maximum value, or when it is after the addition update of the hit ball signal counter. Sets the hit ball signal counter and designates the number of prize balls to 0 (F
7 DEH).

Next, it is judged whether or not the value of the hitting ball signal counter is 0 (F7E2H). When it is determined that the value of the winning ball signal counter is not 0, it is determined whether the value of the winning ball signal counter is 1 (F7E6H). When it is determined that the value of the hitting ball signal counter is not 1, the hitting ball signal processing ends in order to maintain the signal being output. On the other hand, when it is determined that the value of the hit ball signal counter is 1, the process of designating the number of prize balls to 5 is performed (F7EAH). As a result, the number of prize balls is set to 5.

Next, it is judged whether or not the value of the prize ball storage counter is other than 0 (F7ECH). As described above, the prize ball storage counter is a counter that is added and updated when a hit ball hits the special winning opening. When it is determined that the value of the prize ball storage counter is other than 0, a process for designating the number of prize balls to 15 is performed (F7F0H). As a result, the number of prize balls is set to 15. Next, a process of subtracting and updating (-1) the prize ball storage counter is performed (F
7F2H).

If the hit ball signal counter is determined to be 0, the prize ball storage counter is determined to be 0, or after the subtraction update of the prize ball storage counter has been performed, the number of prize balls is determined. Processing to set the output is performed (F7
F5H). The contents of this output are as follows: When there is no winning ball, the number of prize balls output is 0. If there is a winning ball and there is no memory for the number of prize balls, the number of prize balls is 5
Individual. When there is a winning ball and the number of prize balls is stored, the number of prize balls is 15. After outputting the number of prize balls, the winning ball signal processing is completed.

Next, the contents of the image display control executed by the CRT control circuit 60 of the display control board will be described. 84 to 316 are flowcharts showing the processing procedure of image display control.

Image display control is roughly divided into the following five processes. These processes are general processes, command control processes, screen basic processes, slot display processes, and round display processes. The general processing is the general processing content of the image display control. The command control process is a process for performing control based on command data received by the CRT control circuit 60. The screen basic process is a basic process related to the display screen. The slot display processing is processing relating to variable display of special symbols. The round display process is a process relating to a display image in each round in the repeat continuation control when the big hit occurs. Hereinafter, these processes will be described in order.

General Processing First, the contents of the general processing will be described with reference to FIGS. 84 to 87. FIG. 84 is a flowchart showing the processing procedure of the START processing (start processing).

First, a process of inhibiting an interrupt operation is executed (0100H). Next, processing for setting the stack pointer is performed (0101H). Next, processing for initializing the watchdog timer is performed (0104H). The watchdog timer is composed of software and operates in accordance with the execution of the control program.

Next, a process of checking the data in the RAM 603 is performed (010AH). Next, processing for initializing each register is performed (0111H). Next, VD
Processing for initializing P (VDP A63, VDP B64) is performed (0138H). Next, processing for permitting the interrupt operation prohibited in the previous step is performed (0150).
H). Next, the received command data COM0 to COM
The process of analyzing 7 is repeatedly executed (0175H).

FIG. 85 is a flow chart showing the processing procedure of the interrupt processing from the main. This process is a process related to the interrupt process from the basic circuit 40 (main). First, processing for prohibiting the interrupt operation is performed (017B).
H). Next, a process of receiving the command data COM0 to COM7 is performed (01B5H). Next, processing for setting command data is performed to perform processing based on the received command data (01C2H). Next, a process of permitting the interrupt operation prohibited in the previous step is performed (01D0H). After that, the interrupt processing from the main ends.

In the CRT control circuit 60,
It receives an interrupt signal and command data at regular intervals. When the interrupt signal is received, the interrupt operation is performed to immediately read the command data, and the display image of the variable display device 4 is controlled based on the read command data. By controlling the display image using such an interrupt signal, the following effects can be obtained. That is, since the display control according to the command data is immediately performed in response to the interrupt signal, the progress status of the game,
The relationship with the display image content can be synchronized. Therefore, it is possible to improve the reliability of synchronizing the progress status of the game with the display image.

In CRT control circuit 60, when control is performed based on command data, when interrupt signal INT is received and an interrupt operation is performed in response to the interrupt signal INT, the interrupt signal input thereafter is used. Control is performed to prohibit the new interrupt operation by the interrupt signal, read the command data, and permit the new interrupt operation after the reading is completed.

By carrying out such control,
The following effects can be obtained. That is, even if noise is input irregularly from the interrupt signal input terminal between the input of a certain interrupt signal and the input of the next interrupt signal, Since the interrupt operation in response to the interrupt signal is prohibited, it is possible to prevent an erroneous interrupt operation due to noise. Therefore, regarding the image display control, it is possible to prevent a malfunction due to the intrusion of noise.

FIG. 86 is a flow chart showing the processing procedure of the watchdog timer processing. First, a communication monitoring process for monitoring the communication state from the basic circuit 40 of the main board to the CRT circuit 60 of the display control board is performed (0293).
H). Next, a loop monitoring process for monitoring the loop time of the main loop of the control program for image display control is performed (02A1H). Next, a RAM monitoring process for monitoring the data stored in the RAM 603 is performed (02AF
H).

Next, a voltage monitoring process for monitoring the power supply voltage supplied to the control circuit such as the CRT control circuit 60 formed on the display control substrate is performed (AAAAH).
Next, the process of updating the random number counter used in the image display control is performed (02B7H). The random number counter is a counter used for randomizing the appearance of the characters displayed on the variable display section 4 and randomizing the color change of the display image. Then, the watchdog timer process ends.

Next, the voltage monitoring process executed by the watchdog timer process will be described in detail. FIG. 87 is a flowchart showing the processing procedure of the voltage monitoring processing.

First, the power supply voltage V is checked (S
1). Next, it is determined whether the power supply voltage V has dropped below a predetermined value (S2). If it is determined that the power supply voltage V has not dropped below the predetermined value, the process proceeds to S7, which will be described later. On the other hand, when it is determined that the power supply voltage V has dropped to the predetermined value or less, it is determined whether or not the time is being measured by the voltage monitoring timer (S3). The voltage monitoring timer is a timer that is set in S4, which will be described later, and starts counting time.

If it is determined that the voltage monitoring timer is not counting the time, the voltage monitoring timer is set and the timing is started (S4). If it is determined in S3 that the time is being measured or after the time is started in S4, the value of the voltage monitoring timer is checked to determine whether or not a predetermined time has elapsed after the power supply voltage V has dropped. Judgment is made (S
5). If it is determined that the predetermined time has not elapsed, the voltage monitoring process ends. On the other hand, when it is determined that the predetermined time has passed, the CRT control circuit 60
Processing for resetting the operation of is performed (S6). Then, the voltage monitoring process ends.

On the other hand, when it is determined in S2 that the power supply voltage V has not dropped below the predetermined value, it is determined whether or not the power supply voltage monitoring timer is counting (S).
7). If it is determined that the time is being measured, the voltage monitoring process ends. On the other hand, if it is determined that the time is being measured, the process of resetting the time by the power supply voltage monitoring timer is performed (S8), and the voltage monitoring process ends. In this way, the power supply voltage is monitored using the watchdog timer, and when the power supply voltage drops below a predetermined value for a predetermined time or longer, the operating state of the CRT control circuit 60 is initialized.

By performing such control,
The following effects can be obtained. If the power supply voltage drops, an abnormal image may be displayed during image display.
In such a case, the CPU 601 may run away and the image data may be destroyed as a result. In such a case, the CRT control circuit 60
It becomes difficult to return the control circuit formed on the display control board including the above to the normal state. On the other hand, if the voltage monitoring process described above is performed, the CPU 601 will
The CRT control circuit 60 can be reset before the runaway occurs. When such a reset is performed, it becomes easy to restore the control circuit formed on the display control substrate including the CRT control circuit 60 to the normal state.

Command Control Processing Next, command control processing will be described with reference to FIGS. 88 to 102. 88 and 89 show S of command control processing.
It is a flow chart which shows a processing procedure of TART processing.
The command control process is a process of reading and executing the command data COM0 to COM7 when the interrupt signal INT is input. This START process is a process executed at the start of the command control process.

Referring to FIG. 88, first, a process of inhibiting an interrupt operation is performed (0100H). Next, processing for setting the stack pointer is performed (0101H). Next, processing for stopping the watchdog timer is performed (0104H). This clears the watchdog timer. Next, the RAMCHECK process is executed (010AH). This process is a process of checking the data in the RAM 602, and the details of the process will be described later.

Next, processing for initializing each register used for control is performed (0111H). These registers are registers used in a work area set in the RAM 602. Next, initialization processing is executed (0138H). This process is an initialization process for initializing the table and the like used for image display. Next, a process of permitting the interrupt operation prohibited in the previous step is performed (0150H).

Next, referring to FIG. 89, a process of clearing the interrupt request flag is performed (0151H). The interrupt request flag is a flag indicating whether to request an interrupt operation. Next, it is determined whether command data has been received (0159H). When it is determined that the command data has been received, it is determined whether the received data is command data (015BH).

If it is determined that the received data is command data, the command data is saved (0165H). This sets the command data used for display control. Here, a command reception flag indicating that command data has been received is set.

Next, the command reception flag is cleared (0170H). If it is determined that the command data has not been received, the received data is not the command data, or the command reception flag has been cleared, the command is
The d process is executed (0175H). This processing is processing for executing processing according to the received command, and the processing content will be described later. After the command process is executed, the process returns to the process of clearing the interrupt request flag, and the processes from that process to the command process are repeatedly executed.

FIG. 90 and FIG. 91 show int main.
It is a flow chart which shows a processing procedure of processing. This process is a process of analyzing communication data. Referring to FIG. 90, first, a process of prohibiting an interrupt operation is performed (0
17BH). Next, a process of saving each register is performed (017CH). Next, processing for clearing the communication monitoring timer is performed (0181H). What is the communication monitoring timer?
A timer used for communication monitoring. Next, processing for clearing the interrupt request flag is performed (0194H). Next, a process of reading communication data (LOW) is performed (0
19AH). Next, a process of reading communication data (HIGH) is performed (019FH).

Next, referring to FIG. 91, it is determined whether the command data is a header code (header command) (01AAH). When it is determined that the code is the header code, processing for clearing the command block is performed (01AEH). As a result, the command reception data counter is cleared and new command data can be received.

When it is determined that the received code is not the header code or after the command block has been cleared, processing for calculating the processing address used in the next reception data check processing is performed (01B5H). Next, a reception data check process is executed (01C2
H). The received data check process is a process of checking the received command data. Next, a register release process of returning each register to the original is executed (01CBH).
Next, a process of permitting the interrupt operation prohibited in the previous step is performed (01D0H), and the int main process ends.

FIGS. 92 and 93 show RAMCHECK.
It is a flow chart which shows a processing procedure of processing. This process is a process for checking the data in the RAM 602.

First, a process of setting the data "0AAH" which is the first check data is performed (01E4).
H). Next, processing for setting an address to be checked in the RAM 602 is performed (01E3H). Next, the data set in the previous step is written to the address of the RAM 602 (01EAH). Next, the written data is compared with the data set in the previous step, and it is determined whether or not there is a RAM comparison error (mismatch of compared data) (01ECH). This comparison is performed by sequentially comparing the data of the addresses to be checked.

When it is determined that the RAM comparison error is not generated, it is determined whether or not it is the final address (HL = 0) to be checked (01F5H). If it is determined that the address is not the final address, the data writing process and the comparison process described above are repeatedly executed until the final address is reached.

On the other hand, if it is determined that the address is the final one, the data "55" which is the second check data.
Processing for setting "H" is performed (01F7H). Next, a process of writing the set second check data in the previously set check target address is performed (01FFH). Next, as in the case described above, it is judged whether or not there is a RAM comparison error (0203H).
This RAM comparison error determination step or the above-mentioned RA
When it is determined that the RAM comparison error occurs in the M comparison error determination step, a process of setting a failure command (command indicating error occurrence) is performed (021
CH), the RAMCHECK processing ends.

On the other hand, when it is determined that the RAM comparison error is not generated, the final address to be checked (HL =
It is determined whether it is 0) (020AH). When it is determined that the address is not the final address, the above-described data write processing (01FFH) and RAM comparison error determination processing (0203H) are repeatedly executed up to the final address.

Next, referring to FIG. 93, a process of setting the RAM size of the RAM 602 can be performed (020C
H). Next, a process of setting a start address (start address) for clearing the data in the RAM 602 is performed (020FH). Next, the RAM 602 is cleared from the set start address (work clear) (0214H). The clear process is repeatedly executed (0217H) until it is determined that the final address of the set RAM size has been reached (BC = 0).
After that, the RAMCHECK processing ends.

Next, the processing contents executed in the received data check processing described in the int main processing will be described. The received data check process includes i described below.
stphd treatment, istp cm treatment and ist
pcc processing is included.

FIG. 94 is a flow chart showing the processing procedure of the istp hd processing. This process is a process related to the header command. First, it is determined whether the received data is a header command (0EFH) (0229H). If it is determined that the command is not a header command, the istp hd process ends. on the other hand,
If it is determined that the received command is a header command, a reception step setting process for setting the reception data counter is performed (0233H). The reception data counter is a counter that counts received command data. Next, a sum clear process for clearing the sum check is executed (022EH), and the istp hd process ends.

FIG. 95 is a flow chart showing the processing procedure of the istp cm processing. This process is a process of performing a sum check calculation (checksum) of command data. First, the process of executing the sum check calculation is performed (0246H). Next, a reception step update process for updating the reception data counter is executed (0250
H), istp cm processing is completed.

FIG. 96 is a flow chart showing the processing procedure of the istp cc processing. This process is a process of comparing checksums and saving commands. First, a process of comparing the checksum value calculated by the above istp cm process with a predetermined checksum value is performed (0264H). If it is determined that the compared checksum values are the same, the ICO
The MSET processing is executed (0266H). This processing will be described later. When it is determined that the compared checksum values are not the same or after the ICOMSET processing has been executed, the reception step clear processing for clearing the reception data counter is executed (0269).
H). Then, the istp cc process ends.

FIG. 97 is a flow chart showing the processing procedure of the ICOMSET processing. This process is a process for saving command data. First, it is determined whether the command reception flag is not set (= 0) (0274H). The command reception flag is a flag indicating whether or not command data has been received. If it is determined that the command reception flag is set, the ICOMSET processing ends. On the other hand, if it is determined that the command reception flag is not set, a command transfer process is performed (027).
FH). Next, the command reception flag is set (0281H), and the ICOMSET processing ends.

Next, the watchdog timer process will be described. FIG. 98 is a flowchart showing the processing procedure of the timer processing. This process is a watchdog timer process.

First, a process for obtaining a stack is performed (0288H). Next, it is judged whether or not the acquired stack is the last one (0289H). When it is determined that the stack is not the last one, a process for acquiring the communication monitoring counter (communication monitoring timer) is performed (0
293H). This communication monitoring counter is updated over time, and the int ma associated with the interrupt operation is updated.
It is cleared by executing the in process.

Next, it is judged whether or not the obtained value of the communication monitoring counter is 5.25 seconds or more (029FH). The communication monitoring counter is reset each time an interrupt operation is performed, so
When counting for 5.25 seconds or more, basic circuit 4
It is considered that an error has occurred in the data communication from 0 to the CRT circuit 60. When it is determined that the value does not indicate 5.25 seconds or more, the process for acquiring the loop monitoring counter is performed (02A1H). The loop monitor counter is a timer for monitoring the loop time of the main loop of command control processing, and is cleared each time an interrupt operation is performed.

Next, it is judged whether or not the obtained value of the loop monitoring counter is a value indicating 5.25 seconds or more (02AAH). Since the loop monitoring counter is cleared at each interrupt operation, if 5.25 seconds or more elapse without clearing the loop monitoring counter, it is determined that an abnormality has occurred in the main loop.
If it is judged that 5.25 seconds or more have not elapsed,
The process of acquiring the data of the RAM 602 is performed (02
AFH). Next, it is judged whether or not the acquired data has an error (02B3H).

If it is determined in the above step that the stack is at the end, the value of the communication monitoring counter is 5.
If it is determined that the value indicates 25 seconds or more, if the value of the loop monitoring counter is determined to indicate the value of 5.25 seconds or more, or if there is an error in the RAM data. If it is determined, a process of resetting (initializing) the CRT control circuit 60 is performed (0
2BDH). On the other hand, if it is determined that the acquired RAM data has no error, the process of updating the random number counter is performed (02B7H), and the timer process ends.

99 and 100 are flowcharts showing the processing procedure of the init processing. This process is a process for initializing the display control. First, it is determined whether or not it has already been initialized (02C2).
H). If it is determined that the initialization has not been completed, a vertical synchronization check is performed (02CEH). When it is determined that the initialization has been completed or after the vertical synchronization check, the initialization flag indicating that the initialization is completed is set (02D7H).

Next, processing for selecting the pattern A surface (the pattern surface of VDP A63) is performed (02DC
H). Then, ptn off processing (02DEH), p
tninit processing (02E1H), ptn cls processing (02E4H), spr init processing (02E7)
H), scr init processing (02EAH), mon
The init process (02EDH) is sequentially executed. Each of these processes will be described later.

Next, processing for selecting the pattern B surface (pattern surface of VDP B64) is performed (02FA
H). Then, ptn off processing (02FCH), p
tninit processing (02FFH), ptn cls processing (0312H), spr init processing (0315)
H), scr init processing (0318H), mon
The init process (031BH) is sequentially executed. Each of these processes will be described later. Next, a process of setting V data and H data is performed (0318H), and i
The nit process ends.

FIG. 100 is a flow chart showing the processing procedure of command processing. This processing is processing for executing processing according to a command (command data).
First, a process of acquiring a main command (main status main command) is performed (032FH). Next, it is judged whether or not the data value of the acquired main command is 61H or more indicating a pause display (03).
33H). If it is determined that the data value is 61H or more, the command processing ends.

On the other hand, when it is determined that the data value is not 61H or more, it is determined whether the acquired data value of the main command is 80H or more indicating other than the main command (0337H). When it is determined that the data value of the command is 80H or more, comma
The nd process ends. On the other hand, the data value of the command is 80
If it is determined that the value is not higher than H, the command masking process is performed (033BH). Next, processing for creating the execution address of the command is performed (0340).
H). Next, command execution processing is executed (0345).
H), and then the command processing ends.

FIG. 102 is a flow chart showing the processing procedure of the dsp off processing. This process is a process of turning off the display screen. First, the process of acquiring the main command of the main status is performed (0358H).
Next, a determination is made whether the acquired main command is the same as the previously acquired command. When it is determined that the main command is the same as the previous command, the init process described above is executed (0362H). Next, processing for saving the command is performed (0365).
H).

On the other hand, if it is determined that the acquired main command is not the same as the previous command, or if the command has been stored, the process of inhibiting the display of the pattern A side is executed (036BH). Next, a process of prohibiting display of the pattern B side is executed (0370H), after which the dsp off process ends.

Next, the bank register switching processing in each of VDP A63 and VDP B64 will be described. Each of VDP A63 and VDP B64 is B
It has two types of registers, a bank register named X and a bank register named BY. VD
In P, these bank registers are appropriately switched and used during operation. Such bank register switching processing will be described with reference to FIGS. 103 to 106 below.

FIG. 103 is a flow chart showing the processing procedure of the bx on processing. This process is a process of turning on the bank register BX (a process of bringing it into a selected state).
This process ends after the process of turning on the bank register BX is performed (0374H). FIG. 104 shows bx
It is a flow chart which shows a processing procedure of off processing. This process is a process of turning off the bank register BX (a process of bringing it into a non-selected state). This process ends after the process of turning off the bank register BX (0378H).

FIG. 105 is a flow chart showing the processing procedure of the by-on processing. This process is a process of turning on the bank register BY. This process ends after the process of turning on the bank register BY (the process of bringing it into the selected state) (037CH). FIG. 106 shows by
It is a flow chart which shows a processing procedure of off processing. This process is a process of turning off the bank register BY (a process of bringing it into a non-selected state). This process ends after the process of turning off the bank register BY (0380H).

Screen Basic Processing Next, screen basic processing will be described with reference to FIGS. 107 to 138. FIG. 107 is a flowchart showing the processing procedure of the FVBWAIT processing. By this processing, the start timing of the vertical border period is reset. FIG.
8 is a flowchart showing a processing procedure of PORTGET processing. By this processing, VDPA63 or VD
The port address of P B64 is acquired.

FIG. 109 is a flow chart showing the processing procedure of the PAT CPYZ processing. By this processing, V
The pattern data is copied in DP A63. Copy of pattern data means the connected VDP
Between the character ROM and the character ROM
The pattern data stored in M is VR with VDP built-in.
It means copying to AM.

FIG. 110 is a flow chart showing the processing procedure of SLMSKHI processing. By this processing, the slot mask is set. Fig. 111 shows the PAT
It is a flow chart which shows a processing procedure of CPYH processing. By this processing, the pattern data is copied in the VDPA 63. FIG. 112 shows PABAGETA.
It is a flow chart which shows a processing procedure of processing. By this processing, the pattern management table of VDP A63 is set.

FIG. 113 is a flow chart showing the processing procedure of the PAT CPYST processing. With this process,
The pattern data is set. FIG. 114 shows PA
It is a flow chart which shows the processing procedure of TDCMP processing. By this processing, the pattern data is copied. FIG. 115 is a flowchart showing the processing procedure of PABAPO2 processing. By this processing, the ROM page and the base address for the pattern surface are set.

FIG. 116 is a flow chart showing the processing procedure of the PAT CPYS processing. By this processing, the pattern data is copied. FIG. 117 shows PA
It is a flow chart which shows a processing procedure of TCOPY processing. By this processing, the pattern data is copied. FIG. 118 is a flowchart showing the processing procedure of the PAT CPY2 processing. By this processing, the pattern data for clearing the background image is copied. FIG. 119 is a flowchart showing a processing procedure of PAT CLSH processing. By this processing, the pattern data is cleared (cleared within the designated range).

FIG. 120 is a flow chart showing the processing procedure of SPRCLRA processing. By this process, the process of initializing the sprite table (sprite data table) is performed. FIG. 121 is a flowchart showing the processing procedure of PATCLRA processing. By this processing, the pattern data is cleared (cleared within the designated range). FIG. 122 is a flowchart showing the processing procedure of the SPRADRST processing. By this processing, the sprite address is set.

FIG. 123 is a flow chart showing the processing procedure of PABAPO processing. By this processing, the ROM page and the base address for the pattern surface are set. FIG. 124 is a flowchart showing the processing procedure of the PAT CLS processing. By this processing, the pattern data is cleared (cleared within the designated range).

FIG. 125 is a flow chart showing the processing procedure of the SPR CLS processing. By this process, the sprite table is initialized (cleared). FIG.
26 is a flowchart showing a processing procedure of the MON INIT processing. By this processing, the display monitor (CR
Initialization of T) is performed. Fig. 127 shows SCOLL
It is a flow chart which shows a processing procedure of L processing. By this processing, the vertical scroll address and horizontal scroll address of the image are set.

FIG. 128 is a flow chart showing the processing procedure of the PALLETTE processing. By this processing, the color palette used for image display is changed and set. The color palette is palette data of colors used for color setting of an image, and is changed according to the image to be displayed. FIG. 129 is a flowchart showing the processing procedure of the PTN INIT processing. By this processing, initial setting of the pattern surface (pattern screen) is performed. FIG.
6 is a flowchart showing a processing procedure of PTN CLS processing. By this processing, the pattern surface is cleared.

FIG. 131 is a flowchart showing the processing procedure of the SPR INIT processing. By this process, the sprite table is initialized. FIG.
6 is a flowchart showing a processing procedure of SCR INIT processing. By this processing, the scroll data table used for scroll display of images is initialized.

FIG. 133 is a flow chart showing the processing procedure of PTN OFF processing. By this processing, the display of the pattern surface is prohibited. Figure 134 shows PTN ON
It is a flow chart which shows a processing procedure of processing. By this processing, the display of the pattern surface is permitted. FIG. 135 shows
It is a flow chart which shows a processing procedure of SPR OFF processing. By this process, the process of inhibiting the display of the sprite surface (sprite image) is performed. FIG. 136 shows
It is a flow chart which shows a processing procedure of SPRON processing. By this processing, the display of the sprite surface is permitted. FIG. 137 is a flowchart showing the processing procedure of the SLH SET processing. By this processing, the vertical division size of the screen division scroll of the image is set. FIG.
38 is a flowchart showing a processing procedure of SLV SET processing. By this processing, the horizontal division size of the screen division scroll is set.

Slot Display Process Next, the slot display process will be described with reference to FIGS. 139 to 231. FIG. 139 is a flowchart showing the processing procedure of the GAME processing. This process is the first process executed in the slot display process, and each process corresponding to the command data is executed.

FIG. 140 and FIG. 141 are flowcharts showing the processing procedure of the SLOT processing. By this processing, slot rotation display (variable display) of special symbols is performed. FIG. 142 is a flowchart showing the processing procedure of the SltPutX processing. By this process, a forcible image display process is performed when a failure occurs (when an error occurs). FIG. 143 is a flowchart illustrating a processing procedure of SltPutXX processing. By this processing, processing for slot display (variable display) of all reels (all special symbols) is performed.

FIG. 144 is a flow chart showing the processing procedure of the GetRnd processing. By this processing, processing relating to the counter type random number is performed. 145 and 146 are flowcharts showing the processing procedure of the SLOTSTOP processing. By this processing, processing for stopping the slot display of the special symbol is performed. 147 and 148 are flowcharts showing the processing procedure of the SLOTSTOE processing. By this processing, display control of an animation image or the like, which is performed when the slot display is stopped, is set.

FIG. 149 is a flowchart showing the processing procedure of the BolDnSt processing. By this process, SL
In the OTSTOE process, a process for moving the display position of the special symbol that can be executed when the slot display is stopped is performed. FIG. 150 shows stpChk
It is a flowchart which shows the process sequence of 10 processes. By this processing, processing for deleting the character of the animation image from the screen is performed in the SLOTSTOE processing. FIG. 151 is a flowchart showing a processing procedure of SltCenPs processing. By this processing, processing for changing the display position of the slot display on the screen when the predetermined reach operation is displayed is performed.

FIG. 152 is a flow chart showing the processing procedure of SltStpZ1 processing. By this process, S
In the ltPutX processing, first initialization settings such as clearing various flags are performed. FIG. 153 shows Slt.
It is a flow chart which shows a processing procedure of StpZ2 processing. By this processing, in the SltPutX processing, the second initialization setting such as setting the stop position of the slot display is performed. FIG. 154 is a flowchart showing the processing procedure of the RicNohit processing. With this process,
When the reach state is displayed after the reach state is displayed, an animation image is set.

FIG. 155 is a flowchart showing the processing procedure of the ErrChkZZ processing. By this processing, the forced display image is set. FIG. 156 shows ErrC.
It is a flow chart which shows a processing procedure of hkXX processing.
By this processing, the forced display of the animation image at the time of failure is set. 157 and FIG.
58 is a flowchart showing a processing procedure of the Slot 27 processing. By this processing, the image display is set in the shortened variation mode in the high probability state.

FIG. 159 is a flow chart showing the processing procedure of SltStp2D processing. By this processing, processing for stopping the slot display is performed. FIG.
60 and FIG. 161 are flowcharts showing the processing procedure of the SLTSTART processing. By this processing, processing for starting the slot display of all the special symbols is performed. FIG. 162 is a flowchart showing the processing procedure of the SLOT PROC processing. By this processing, step processing for slot display is performed, whereby each processing for slot display is branched and executed according to the processing step.

FIG. 163 is a flow chart showing the processing procedure of SLT AREA processing. In this processing, processing for setting a processing area related to slot display is performed. FIG. 164 is a flowchart showing the processing procedure of the SLTSTRUP processing. By this processing, processing for accelerating the slot display is performed. FIG. 165
3 is a flowchart showing a processing procedure of a SLOT NOP processing. By this processing, processing for setting the slot display flag is performed.

FIG. 166 is a flow chart showing the processing procedure of the SLTSTUPUP processing. By this processing, the processing steps are stepped up. 167 and 168 are flowcharts showing the processing procedure of the SLT STOP processing. By this processing, processing for stopping the slot display of each of the special symbols on the left, middle, and right is performed.

FIGS. 169 and 170 show ErrChk.
It is a flow chart which shows a processing procedure of 23 processing. By this processing, processing for forcibly setting the display frame of each of the left, middle, and right symbols is performed. FIG. 171 is a flowchart showing a processing procedure of ZU HOSE processing. By this processing, processing for correcting the stop positions of the left, middle, and right symbols is performed. FIG. 172 is a flowchart showing the processing procedure of the SHOW STP processing. By this processing, the stop operation of the animation image is designated.

FIG. 173 is a flow chart showing the processing procedure of the SLOT ERR processing. By this processing, processing for setting the display after the error screen that is forcibly displayed when a failure occurs is performed. 174 and 175
6 is a flowchart showing a processing procedure of RichA1 processing. By this processing, the motion setting of the animation image in reach 1, reach 3, and reach 6 is performed. FIG. 176 is a flowchart showing the processing procedure of PaSetRic processing. By this processing, the sub-processing of the animation image in the reach display described above is performed.

FIG. 177 is a flow chart showing the processing procedure for the AnmTimSt processing. By this processing, the waiting time of the animation operation and the like are set. 178 and 179 are flowcharts showing the processing procedure of the Beach 2A processing. By this processing, the animation image in the reach 4 state is set. FIG. 180 is a flowchart showing a processing procedure of SLTRRICH processing. By this processing, the frame feed of the animation image is performed.

FIG. 181 is a flow chart showing the processing procedure of the SWat2A 2 processing. By this processing, step processing in the reach 4 state is performed. FIG.
Reference numeral 82 is a flowchart showing a processing procedure of SWat2A 0 processing. By this processing, step processing in the reach 4 state is performed. FIG. 183 shows
It is a flow chart which shows a processing procedure of Proc processing.
By this processing, step processing regarding the animation image is performed. FIG. 184 is a flowchart showing the processing procedure of HitChk processing. With this process,
It is checked whether the left, middle, and right symbols are big hit symbols.

FIG. 185 is a flowchart showing the processing procedure of the RichChk processing. By this process,
It is checked whether or not the right pattern is in the reach state. FIG. 186 is a flowchart showing the processing procedure of FriSet processing. By this processing, a flag for returning the display state of the reach 4 to the normal stop state is set. FIG. 187 is a flowchart showing the processing procedure of the HipSet processing. By this process, when the reach 4 is in the disengaged state, 7
A process of setting a flag for starting display from the top is performed.

FIG. 188 is a flow chart showing the processing procedure of NudoSet processing. By this processing, the animation image displayed in the reach 3 state is set. FIG. 189 is a flowchart of the processing procedure of the ShowSctN processing. By this processing, an animation command which is a command relating to the display of the animation image is set. FIG. 190 shows ShowS.
It is a flow chart which shows the processing procedure of ctW processing. By this processing, the animation command is set. FIG. 191
6 is a flowchart showing a processing procedure of ShowSct processing. By this processing, the animation command is set. FIG. 192 is a flowchart showing the processing procedure of the ShowGet processing. By this processing, the animation command is set.

FIG. 193 is a flow chart showing the processing procedure of the BichMon processing. By this processing, the slot display screen in the reach 4 is set. 194 and 195 are flowcharts showing the processing procedure of the CHANCE processing. By this processing, the display image for reach 2 is set. FIG. 196 shows
It is a flow chart which shows a processing procedure of RichE2B processing. By this processing, the setting regarding the display image in the case of reach 5 is performed.

FIG. 197 is a flow chart showing the processing procedure of STP POSI processing. By this processing, processing for setting the coordinates of the stop position is performed for the special symbol displayed in the slot. Figure 198 shows AnmCmSt.
It is a flow chart which shows a processing procedure of processing. By this processing, processing for setting an animation command is performed.

FIG. 199 is a flow chart showing the processing procedure of the SLOT INT processing. By this processing, the slot display screen is initialized. FIG. 200 shows I
It is a flow chart which shows a processing procedure of NTSHOW processing. By this process, the setting for initializing the background image is performed. FIG. 201 is a flowchart showing the processing procedure of StdMon processing. By this processing, the mask screen is set.

FIG. 202 is a flow chart showing the processing procedure of KakuSet processing. By this processing, the color of the display screen and the like when the probability changes (in the high probability state) are set. FIG. 203 is a flowchart showing the processing procedure of Wave processing. By this process, a process of displaying a moving image showing waves on the display screen is performed. FIG.
4 is a flowchart showing a processing procedure of PltSet1 processing. By this processing, the palette of colors used for the display image is set. FIG. 205 shows SLOT MO
It is a flow chart which shows a processing procedure of N processing. By this processing, the slot display screen is initialized. FIG. 206 is a flowchart illustrating the processing procedure of SltMsk03 processing. By this processing, processing for displaying the frame for the mask of the slot display is performed. FIG.
FIG. 7 is a flowchart showing a processing procedure of SltMsk00 processing. By this process, the process of masking the slots is performed.

FIG. 208 is a flow chart showing the processing procedure of NudoPut0 processing. By this processing, the display processing of the animation image displayed in the reach 3 state is performed. FIG. 209 shows NudoPut1.
It is a flow chart which shows a processing procedure of processing. By this processing, the display processing of the animation image displayed in the reach 3 state is performed.

FIG. 210 is a flow chart showing the processing procedure of the Show processing. By this processing, the animation processing of the frame of the animation image is performed. FIG. 211 is a flowchart showing the processing procedure of Tsk3Cra processing. By this processing, the work area used for the animation processing of the top of the animation image is initialized. FIG. 212 shows NextKom.
It is a flow chart which shows the processing procedure of a processing. By this processing, processing for displaying the next frame of the animation image is performed.

FIG. 213 shows KomaPut processing and K
It is a flow chart which shows a processing procedure of omaPut2 processing. Through these processes, a new frame and a direct frame of the animation image are displayed. FIG. 214 is a flowchart showing the processing procedure of the NewSkoma processing. By this processing, the animation frame of the sprite image is set. FIG. 215
6 is a flowchart showing a processing procedure of SPR CLR2 processing. By this process, the sprite is initialized. Here, the sprite address is initialized from the designated address to the last address.

FIG. 216 is a flow chart showing the processing procedure of SLT ABC processing. By this process,
Processing for displaying the special symbols on the inside and the right is performed.
217 and 218 are flowcharts showing the processing procedure of the FLASH processing. Reach flush is performed in this process. The reach flash is a process of flashing the display image by repeating the color of the display image in the reach state to a bright color and a dark color. FIG. 219 is a flowchart showing the processing procedure of the SLTS PDSP processing. By this processing, the speed of slot display (variable display) is set.

FIG. 220 is a flow chart showing the processing procedure of SLTPIOSL processing. By this process, I
/ O port is selected. FIG. 221 shows SLOT MO.
It is a flow chart which shows the processing procedure of V processing. By this processing, the movement amount of the special symbol displayed in the slot is obtained, and the movement position thereof is calculated.

FIG. 222 is a flow chart showing the processing procedure of SLT PGET processing. By this process, a process of obtaining a symbol table which is a data table of special symbols is performed. FIG. 223 is a flowchart showing a processing procedure of GRFTBLGT processing. By this processing, processing for searching the acquired symbol table is performed. FIG. 224 is a flowchart showing a processing procedure of SLT SCL processing. By this processing, the settings for scrolling the slot display are performed.

FIG. 225 is a flow chart showing the processing procedure of SLT PTN processing. By this processing, the pattern setting of the slot (design) is performed. FIG. 226
6 is a flowchart showing a processing procedure of SLT PTH processing. By this processing, the pattern setting of the slot (design) is performed. FIG. 227 is a flowchart showing the processing procedure of the PIC SET processing. By this processing, the special symbol is set.

FIG. 228 is a flow chart showing the processing procedure of the SCLADR processing. By this processing, the scroll data of the special symbol is set. FIG.
FIG. 9 is a flowchart showing a processing procedure of SclAdrB processing. By this processing, scroll data is set. FIG. 230 is a flowchart showing the processing procedure of the SPR CLRA processing. By this processing, with respect to the scroll data setting, the I / O port is acquired and the sprite is initialized. Figure 231 shows the SPR
It is a flow chart which shows a processing procedure of CLR processing.
By this process, the sprite table is initialized.

Round Display Processing Next, the round display processing will be described. 232 and 233 are flowcharts showing the processing procedure of the ROUND processing. By this processing, the image displayed in the big hit state is selected and determined according to the command address of the main status (COM1) of the command data. Specifically, the display image is initialized and the content of the image displayed when the big hit state occurs is selected. FIG. 234 is a flowchart showing the processing procedure of the RNDJMP processing. With this process,
In accordance with the address of the main status of the command data, the process of repeatedly shifting to the display control of each round of continuous control is performed.

FIG. 235 is a flow chart showing the processing procedure of ZUGARA processing. By this processing, a big hit symbol is set. FIG. 236 is a flowchart showing the processing procedure of the ROUND01 processing. By this processing, the display control of the first round of the repeat continuation control is performed. FIG. 237 is a flowchart showing a processing procedure of R12BAK processing. By this processing, the background image for the twelfth round is set. FIG. 238 shows R
It is a flow chart which shows a processing procedure of 11BAK processing. By this processing, the background image for the 11th round is set.

FIG. 239 is a flow chart showing the processing procedure of the R10BAK processing. By this processing,
The background image for the round is set. FIG. 240
6 is a flowchart showing a processing procedure of R09BAK processing. By this processing, the background image for the ninth round is set. FIG. 241 is a flowchart showing the processing procedure of the R07BAK processing. With this process,
The background image for the seventh round is set.

FIG. 242 is a flow chart showing the processing procedure of the R05BAK processing. By this processing, the background image for the fifth round is set. FIG. 243 shows
It is a flow chart which shows the processing procedure of R03BAK processing. By this processing, the background image for the third round is set. FIG. 244 is a flowchart showing the processing procedure of the R01BAK processing. By this process,
The background image for the round is set.

FIG. 245 is a flow chart showing the processing procedure of the R01BAKS processing. By this process,
The pattern of the background image for the round is copied.
Pattern copy means character ROM 65 or 66
To the corresponding VDP A63 VRAM 631 or V
This is the process of copying the pattern data to the VRAM 641 of DP B64.

FIG. 246 is a flow chart showing the processing procedure of the ROUND02 processing. By this processing, the second round display control of the repeat continuation control is performed.
FIG. 247 is a flowchart showing the processing procedure of the PANPGM processing. By this processing, the pattern name (pattern data name) used for the round display is set.

FIG. 248 is a flow chart showing the processing procedure of the ROUND03 processing. By this processing, the display control of the third round of the repeat continuation control is performed. FIG. 249 is a flowchart showing the processing procedure of the ROUND04 processing. By this processing, the display control of the fourth round of the repeat continuation control is performed. FIG. 250 shows RO
It is a flow chart which shows a processing procedure of UND05 processing. By this processing, the display control of the fifth round of the repeat continuation control is performed.

FIG. 251 is a flow chart showing the processing procedure of the ROUND06 processing. By this processing, the display control of the sixth round of the repeat continuation control is performed. FIG. 252 is a flowchart showing a processing procedure of the ROUND07 processing. By this processing, the display control of the seventh round of the repeat continuation control is performed.

FIG. 253 is a flow chart showing the processing procedure for R07BAK2 processing. By this processing,
The pattern of the background image for the round is copied.
FIG. 254 is a flowchart showing a processing procedure of the ROUND08 processing. By this processing, the display control of the eighth round of the repeat continuation control is performed. FIG. 255 shows R
It is a flow chart which shows a processing procedure of OUND09 processing. By this processing, the display control of the ninth round of the repeat continuation control is performed.

FIG. 256 is a flow chart showing the processing procedure of R09BAKA processing. By this process,
The pattern of the background image for the round is copied.
FIG. 257 is a flowchart illustrating a processing procedure of the ROUND10 processing. By this processing, the display control of the tenth round of the repeat continuation control is performed. FIG. 258 shows
It is a flow chart which shows a processing procedure of R10BAKB processing. By this processing, the pattern copy of the background image for the tenth round is performed.

FIG. 259 is a flow chart showing the processing procedure of the ROUND11 processing. By this processing, the display control of the eleventh round of the repeat continuation control is performed.
FIG. 260 is a flowchart showing a processing procedure of the ROUND12 processing. By this processing, the display control of the twelfth round of the repeat continuation control is performed. FIG. 261 shows
It is a flow chart which shows the processing procedure of R12BAKC processing. By this processing, the pattern copy of the background image for the twelfth round is performed.

FIG. 262 is a flow chart showing the processing procedure of the TOMEIPGM processing. By this processing, the processing of clearing the data in the palette work area used for setting the palette data is performed. FIG. 263 shows
It is a flow chart which shows a processing procedure of ROUND13 processing. By this processing, the display control of the 13th round of the repeat continuation control is performed.

FIG. 264 is a flow chart showing the processing procedure of the ROUND14 processing. By this processing, the display control of the 14th round of the repeat continuation control is performed.
FIG. 265 is a flowchart showing a processing procedure of PANPGMD processing. By this processing, pattern copying is performed on the background image of the 14th round. FIG.
6 is a flowchart showing a processing procedure of the ROUND15 processing. By this processing,
Round display control is performed.

FIG. 267 is a flow chart showing the processing procedure of BLACKPGM processing. By this process, the process of clearing the pallet work to black is performed. FIG.
68 is a flow chart showing the processing procedure of the WHITE GGM processing. By this processing, the palette work is cleared to white and the palette data is set. FIG. 269 is a flowchart showing the processing procedure of the TESTPGM processing. By this processing, the fade processing performed in the fifteenth round of the repeated continuation control is performed.

FIG. 270 is a flow chart showing the processing procedure of the PALSET processing. By this processing, the palette data is set. FIG. 271 shows ROUND
It is a flow chart which shows a processing procedure of 16 processing. By this processing, the display control of the 16th round of the repeat continuation control is performed.

FIG. 272 is a flow chart showing the processing procedure of the OPENING processing. By this processing, the display control of the opening display image displayed at the start of the big hit state is performed. FIG. 273 shows RASINIT.
It is a flow chart which shows a processing procedure of processing. By this processing, the initial setting of 16-division scrolling of the background image is performed. FIG. 274 is a flowchart showing the processing procedure of the RAS processing. By this processing, the raster scroll data is set. Figure 275 shows CHRSE
It is a flow chart which shows a processing procedure of T processing. By this processing, the data of the round work area, which is the work area used for the round display, is set.

FIG. 276 is a flow chart showing the processing procedure of CHRSCR2 processing. By this processing, the pattern data of the scroll data used for the opening display is cleared. FIG. 277 shows CHRSC.
It is a flow chart which shows a processing procedure of R1 processing. By this processing, the pattern copy of the scroll data is performed. FIG. 278 is a flowchart showing the processing procedure of CHRSCR processing. By this processing, the pattern copy of the scroll data is performed.

FIG. 279 is a flow chart showing the processing procedure of the ENDDING processing. By this processing, display control of the ending display image displayed at the end of the big hit state is performed. FIG. 280 is a flowchart showing the processing procedure of the SHOUGAI processing. By this processing, display control of the failure occurrence display that is displayed when a failure (error) occurs in the big hit state is performed.
FIG. 281 shows the processing of SHOPGM2 and SHOPGM1.
It is a flow chart which shows a processing procedure of processing. By these processes, the failure display is set.

FIG. 282 is a flow chart showing the processing procedure of the BANZAI processing. By this processing, the display control of the banzai display, which is a display for notifying the occurrence of a big hit with a character image, is performed. FIG. 283 shows
It is a flow chart which shows a processing procedure of CENTER processing. By this processing, the pattern copy relating to the Banzai display is performed. FIG. 284 is a flowchart showing the processing procedure of the CENTER 2 processing. By this processing, the pattern copy relating to the Banzai display is performed.

FIG. 285 is a flow chart showing the processing procedure of the FEVER processing. By this processing, the display control of the image of the fever display that notifies the occurrence of the big hit by the characters of the background image is performed. FIG. 286 shows FL
It is a flow chart which shows the processing procedure of ACH processing. By this process, the process of flashing the color of the image in the big hit state is performed. FIG. 287 is a flowchart showing the processing procedure of the WAIT processing. By this processing, timing waiting in round display is performed. FIG. 288 is a flowchart showing the processing procedure of the SPR SET processing. By this process, the sprite data for displaying the sprite is set.

289 and 290 are flowcharts showing the processing procedure of the HIP processing. By this processing, the display of the tail character drawn by the character on the screen is set. FIG. 291 is a flowchart showing the processing procedure of the RNUMMOVE processing. By this process, a process of moving the number indicating the number of rounds on the screen is performed. FIG. 292 is a flowchart showing the processing procedure of the R ROUND processing. By this process, the process of moving the character indicating the round number "R" on the screen is performed. FIG. 293 is a flowchart showing the processing procedure of the RED ON processing. By this processing, red pallet data is set regarding the display of the tail character.

FIGS. 294 to 296 show TASKINIT.
It is a flow chart which shows a processing procedure of processing and TASKMAIN processing. The task table is initialized by the TASKINIT process. The task table is a data table that tabulates the relationship between command data and tasks executed in round display. By the TASKMAIN processing, processing for executing a task according to command data is performed using the task table. FIG. 297 is a flowchart showing the processing procedure of STEPINC processing. By this processing, each update (addition) of a wait step, which is a wait time step counted by the wait step counter, and a program step, which is a program step counted by the program step counter
Is performed.

FIG. 298 is a flow chart showing the processing procedure of RNDMD01 processing. By this processing, processing corresponding to command 01 is performed. In particular,
The process of infinitely repeating the program is performed. FIG. 29
9 is a flowchart showing a processing procedure of RNDMD02 processing. By this process, the process corresponding to the command 02 is executed. Specifically, the back step of the wait step and program step (subtraction update)
Is repeated infinitely.

FIG. 300 is a flow chart showing the processing procedure of the RNDMCD03 processing. By this process, the process corresponding to the command 03 is executed. In particular,
The process of repeating the wait step and the back step (subtraction update) for the designated number of times is performed. FIG. 301 is a flowchart showing the processing procedure of the RNDMD04 processing. By this process, the process corresponding to the command 04 is executed. Specifically, scroll display is executed.

FIG. 302 is a flow chart showing the processing procedure of the RNDMD05 processing. By this process, the process corresponding to the command 05 is executed. In particular,
A process of setting palette data is performed. Fig. 303
FIG. 14 is a flowchart showing a processing procedure of RNDMD06 processing. By this process, the process corresponding to the command 06 is executed. Specifically, pattern clear processing is performed. FIG. 304 is a flowchart showing the processing procedure of the RNDMD07 processing. With this process,
The process corresponding to the command 07 is executed. Specifically, the process of setting pattern data is performed.

FIG. 305 is a flow chart showing the processing procedure of the RNDMCD08 processing. By this process, the process corresponding to the command 08 is executed. In particular,
A process of setting full-size pattern data is performed. FIG. 306 is a flowchart of the processing procedure of the RNDMD09 processing. By this process, the process corresponding to the command 09 is executed. Specifically, the process of setting the scroll address is performed.

FIG. 307 is a flow chart showing the processing procedure of the RNDMCD0A processing. By this process, the process corresponding to the command 0A is executed. In particular,
The display screen is set to fade-in and fade-out. FIG. 308 is a flowchart illustrating the processing procedure of the RNDMDD0B processing. By this process, the process corresponding to the command 0B is executed. Specifically, the process of setting the data for one palette is performed.

FIG. 309 is a flow chart showing the processing procedure of the RNDMCD0C processing. By this process, the process corresponding to the command 0C is executed. In particular,
A process of setting pattern data for compression is performed.
The pattern data for compression is pattern data in which the data is compressed. FIG. 310 is a flowchart showing the processing procedure of the RNDMCD0D processing. By this processing, processing by the command 0D is executed. Specifically, pattern-on and pattern-off processing is performed.

FIG. 311 is a flow chart showing the processing procedure of the PALCTOW processing. By this processing, processing for fading out the display screen from the current color to white is performed. FIG. 312 is a flowchart showing the processing procedure of the PALWTOC processing. By this processing, processing for fading in the display screen from white to the current color is performed. FIG. 313 is a flowchart showing the processing procedure of the PALCTOB processing. By this processing, processing for fading out the display screen from the current color to black is performed.

FIG. 314 is a flow chart showing the processing procedure of the PALBTOC processing. By this process, a process of fading in the display screen from black to the current color is performed. FIG. 315 is a flowchart showing the processing procedure of the PALMTOC processing. By this process, a process of fading the display screen from the designated color to the current color is performed. FIG. 316 is a flowchart showing the processing procedure of the PALCTOM processing. By this processing, processing of fading the display screen from the current color to the designated color is performed.

The characteristic points of the modified examples of the present invention are listed below. (1) Pattern data 1 and pattern data 2 are
The abnormality determination data for determining the abnormality of the data stored in the RAM 403 constitutes the abnormality determination data.
Not limited to two types, three or more types may be used.

(2) In this embodiment, FIG.
As shown in 0, when the jackpot state (specific game state), all pattern data (abnormality determination data)
It has been mainly explained that the data stored in the RAM 403 is initialized if the error occurs. However, the present invention is not limited to this, and when three or more types of pattern data are stored in the RAM 403 and used, in addition to the pattern data 1 important for game control, the storage of the RAM 403 when a predetermined number of pattern data becomes abnormal. The data may be initialized. Further, not only in the big hit state (specific game state), but also in the case other than the big hit state, when all pattern data (abnormality determination data) becomes abnormal, RA
The storage data of M403 may be initialized.

(3) In this embodiment, FIG.
As shown in 0, the example in which a plurality of big hit flags (specific game control data) 1 to 3 are distributed and stored in storage areas of adjacent addresses has been mainly described. However, not limited to this,
These jackpot flags may be distributed and stored at separate addresses. By doing so, the jackpot flag is RA
Since the data is stored in a wide area of M403 in a distributed manner, it is possible to discriminate abnormality in the data stored in the RAM 403 with high sensitivity.

(4) In this embodiment, FIG.
In the description of the RAM data check process using 0, when the big hit flag can take two values, if the values of the three big hit flags do not match, the value of the big hit flag that takes a decimal value is rewritten. Mainly explained. However, by allowing the big hit flag to take three values and performing a process of initializing the data stored in the RAM 403 when the values of all big hit flags do not match, RA
It is possible to more accurately determine the abnormality of the storage data of M403.

[0490]

[Specific examples of means for solving the problem]

(1) Basic circuit 40 formed on the main substrate shown in FIG.
By this, a game control computer is configured. The RAM 403 included in the basic circuit 40 shown in FIG. 2 constitutes storage means for storing data including control data used for controlling game operations and a plurality of abnormality determination data used for determining abnormality of the control data. Has been done. The pattern data 1 and the pattern data 2 shown in FIG. 10 form abnormality determination data. 20. SA10 and SA12 of the flowchart shown in FIG. 20 constitute an abnormality determination means for reading a plurality of abnormality determination data and determining whether or not the read data is abnormal data. Initialization for initializing the storage data of the storage means when the abnormality determination means determines that the specific abnormality determination data of the plurality of abnormality determination data is abnormal by SA11 shown in the flowchart of FIG. Means are configured.

(2) The basic circuit 40 formed on the main board shown in FIG. 2 constitutes a game control computer. RAM included in the basic circuit 40 shown in FIG.
The storage unit 403 is configured to store data including control data used to control the game operation and a plurality of abnormality determination data used to determine the abnormality of the control data. The pattern data 1 and the pattern data 2 shown in FIG. 10 form a plurality of abnormality determination data. SA4 shown in the flowchart of FIG.
SA5 and SA7 constitute an abnormality determination means for reading a plurality of abnormality determination data and determining whether or not the read data is abnormal data. At SA9 of the flowchart shown in FIG. 20, when the abnormality determining means determines that all the abnormality determining data of the plurality of abnormality determining data are abnormal, the initialization means for initializing the storage data of the storage means Is configured.

(3) The basic circuit 40 formed on the main board shown in FIG. 2 constitutes a game control computer. RAM included in the basic circuit 40 shown in FIG.
The storage unit 403 is configured to store data including control data used to control the game operation and a plurality of abnormality determination data used to determine the abnormality of the control data. The pattern data 1 and the pattern data 2 shown in FIG. 10 form a plurality of abnormality determination data. SA4 of the flowchart shown in FIG.
SA5, SA7, SA10, and SA12 constitute an abnormality determination means for reading a plurality of abnormality determination data and determining whether or not the read data is abnormal data. S in the flowchart shown in FIG.
By A11, when the gaming machine is not controlled to the specific gaming state, when the abnormality determining means determines that the specific abnormality determining data of the plurality of abnormality determining data is abnormal, the storage data of the storage means First to initialize
Is configured. The pattern data 1 shown in FIG. 10 constitutes specific abnormality determination data. According to SA9 of the flowchart shown in FIG. 20,
In the state where the gaming machine is controlled to a specific gaming state,
A second initialization unit is configured to initialize the storage data of the storage unit when the abnormality determination unit determines that a predetermined number of abnormality determination data are abnormal in addition to the specific abnormality determination data. .

(4) The basic circuit 40 formed on the main board shown in FIG. 2 constitutes a game control computer. RAM included in the basic circuit 40 shown in FIG.
By 403, it has a plurality of storage areas in which control data used for controlling the gaming machine is stored, and specific game control data indicating whether or not to control a specific game state is distributed and stored in the storage area. Means are configured. FIG.
The specific game control data is composed of the big hit flag 1 to the big hit flag 3 shown at 0. By SA1 of the flowchart shown in FIG. 20, a match determination means for reading a plurality of specific game control data distributed and stored in the storage area of the storage means and determining whether or not the read data match is configured. ing. Furthermore, when the match determination means determines that the plurality of specific game control data do not match, an initialization means for initializing the storage data of the storage means is included.

[0494]

[Effect of a concrete example of means for solving the problem]
According to the present invention described in, when the specific abnormality determination data among the plurality of abnormality determination data stored in the storage means is determined to be abnormal, the storage data of the storage means is initialized. It is possible to prevent the stored data of the storage means from being initialized when a slight abnormality occurs in the data used for controlling the game operation. In other words, the stored data in the storage means can be initialized only when an abnormality occurs in the data that may hinder the normal progress of the game control.

According to the second aspect of the present invention, when it is determined that all of the abnormality determination data among the plurality of abnormality determination data stored in the storage means are abnormal, the storage data in the storage means Is initialized, it is possible to prevent the stored data of the storage means from being initialized when a slight abnormality occurs in the data used for controlling the game operation.

According to the present invention as set forth in claim 3, when the specific abnormality determination data stored in the storage means is determined to be abnormal in a state where the gaming machine is not controlled to the specific gaming state. The storage data of the storage means is initialized,
On the other hand, in the state where the gaming machine is controlled to the specific gaming state, the storage data of the storage means is initialized when it is determined that a predetermined number of abnormality determination data are abnormal in addition to the specific abnormality determination data. Therefore, it is possible to prevent the stored data of the storage means from being initialized when a slight abnormality occurs in the data used for controlling the game operation. Furthermore, when the gaming machine is controlled to a specific gaming state,
Compared with the case of not being controlled to the specific game state, it is difficult to initialize the storage data of the storage means based on the abnormality of the abnormality determination data, so that a slight abnormality occurs during the specific game state which is advantageous for the player. It is possible to prevent the inconvenience that the operation is initialized.

According to the present invention of claim 4, the storage data of the storage means is initialized when it is determined that the plurality of specific game control data distributed and stored in the storage area of the storage means do not match. Therefore, it is possible to prevent the occurrence of an incorrect specific game state due to the intrusion of noise. Furthermore, the stored data in the storage means can be initialized only when an abnormality occurs in the specific game control data that may hinder the normal progress of the game control.

[Brief description of drawings]

FIG. 1 is a front view showing a configuration of a gaming board surface of a pachinko gaming machine which is an example of a gaming machine according to the present invention.

FIG. 2 is a block diagram showing a control circuit for performing game control of a pachinko gaming machine.

FIG. 3 is a block diagram showing a control circuit for performing game control of a pachinko gaming machine.

FIG. 4 is a block diagram showing a control circuit formed on a display control board.

FIG. 5 is an explanatory diagram for explaining various random counters used for game control and variable display control of the variable display device.

FIG. 6 is an explanatory diagram showing an array configuration of symbols variably displayed on the variable display device.

FIG. 7 is a flowchart showing a procedure for determining in advance whether or not to generate a big hit based on the value of a random counter in the case of setting 1;

FIG. 8 is a flowchart showing a procedure for determining in advance whether a big hit is to be generated based on the value of a random counter in the case of setting 2.

FIG. 9 is a flowchart showing a procedure for determining in advance whether to generate a big hit based on the value of a random counter in the case of setting 3.

FIG. 10 is a memory map showing stored contents of a RAM included in a basic circuit.

FIG. 11 is a diagram showing the types of command data in a table format.

FIG. 12 is a timing chart for explaining a command data transfer method.

FIG. 13 is a memory map of addresses as seen from the CPU of the CRT control circuit.

FIG. 14 is a flowchart showing a processing procedure of a main program for performing game control.

FIG. 15 is a flowchart showing a processing procedure of a symbol process.

FIG. 16 is a flowchart showing a processing procedure of a normal symbol process.

FIG. 17 is a flowchart showing a processing procedure of timer interrupt processing.

FIG. 18 is a flowchart showing a processing procedure of main processing.

FIG. 19 is a flowchart showing a processing procedure of loop processing in the main processing.

FIG. 20 is a flowchart showing a processing procedure of RAM data check processing.

FIG. 21 is a flowchart showing a processing procedure of initialization processing.

FIG. 22 is a flowchart showing a processing procedure of first initialization processing.

FIG. 23 is a flowchart showing a processing procedure of initialization second processing.

FIG. 24 is a flowchart showing a processing procedure of initialization failure processing.

FIG. 25 is a flowchart showing a processing procedure of register initial value setting processing.

FIG. 26 is a flowchart showing a processing procedure of data output processing.

FIG. 27 is a flowchart showing a processing procedure of display control processing.

FIG. 28 is a flowchart showing a processing procedure of output data control processing.

FIG. 29 is a flowchart showing a processing procedure of output data set processing.

FIG. 30 is a flowchart showing a processing procedure of warning processing.

FIG. 31 is a flowchart showing a processing procedure of information output processing.

FIG. 32 is a flowchart showing a processing procedure of process processing.

FIG. 33 is a flowchart showing a processing procedure of random creation processing.

FIG. 34 is a flowchart showing a processing procedure of switch processing.

FIG. 35 is a flowchart showing a processing procedure of a first-class starting opening switch 1 winning determination processing.

FIG. 36 is a flowchart showing a processing procedure of a first-class starting opening switch 2 winning determination processing.

FIG. 37 is a flowchart showing a processing procedure of random storage processing.

FIG. 38 is a flowchart showing a processing procedure of count switch winning determination processing.

FIG. 39 is a flowchart showing a processing procedure of specific area switch winning determination processing.

It is the flowchart which shows the procedure of normal design switch winning a prize decision processing.

FIG. 41 is a flowchart showing a processing procedure of sound processing.

FIG. 42 is a flowchart showing a processing procedure of sound performance processing.

FIG. 43 is a flowchart showing a processing procedure of random update processing.

FIG. 44 is a flowchart showing a processing procedure of counter updating processing.

FIG. 45 is a flowchart showing a processing procedure of normal time processing.

FIG. 46 is a flowchart showing a processing procedure of normal time processing.

FIG. 47 is a flowchart showing a processing procedure of fluctuation start processing.

It is the flowchart which shows the processing procedure of stop design setting processing.

FIG. 49 is a flowchart showing a processing procedure of reach operation setting processing.

FIG. 50 is a flowchart showing a processing procedure of all reel variation processing.

FIG. 51 is a flowchart showing a processing procedure of left reel stop processing.

FIG. 52 is a flowchart showing a processing procedure of right reel stop processing.

FIG. 53 is a flowchart showing a processing procedure of middle reel stop processing.

FIG. 54 is a flowchart showing a processing procedure of reach 1 operation time calculation processing.

FIG. 55 is a flowchart showing a processing procedure of reach 3 operation time calculation processing.

FIG. 56 is a flowchart showing a processing procedure of reach 6 operation time calculation processing.

FIG. 57 is a flowchart showing a processing procedure of reach 4 stop position flag setting processing.

FIG. 58 is a flowchart illustrating a processing procedure of a fever check processing.

It is the flowchart which shows the procedure of the special winning opening pre-processing.

FIG. 60 is a flowchart showing a processing procedure of processing during opening of a special winning opening.

FIG. 61 is a flowchart showing a processing procedure of processing after opening a special winning opening.

FIG. 62 is a flowchart showing a processing procedure of process data / timer processing.

FIG. 63 is a flowchart showing a processing procedure for process data set processing.

FIG. 64 is a flowchart showing a processing procedure of switch check processing.

FIG. 65 is a flowchart showing a processing procedure of count processing.

66 is a flowchart showing a processing procedure of normal symbol process processing. FIG.

67 is a flowchart showing a processing procedure of normal symbol stop processing.

68 is a flowchart showing a processing procedure of normal symbol variation processing.

69 is a flowchart showing a processing procedure of normal symbol stop processing.

FIG. 70 is a flowchart showing a processing procedure of normal symbol process timer processing.

FIG. 71 is a flowchart showing a processing procedure of data set processing.

FIG. 72 is a flowchart showing a processing procedure of probability setting processing.

FIG. 73 is a flowchart showing a processing procedure of probability setting mode processing.

FIG. 74 is a flowchart showing a processing procedure of probability changing processing (step 1).

FIG. 75 is a flowchart showing a processing procedure of probability changing processing (step 2).

FIG. 76 is a flowchart showing a processing procedure of probability changing processing (step 3).

77 is a flowchart showing a processing procedure of display data set processing. FIG.

FIG. 78 is a flowchart showing a processing procedure of probability / probability setting display setting processing.

FIG. 79 is a flowchart showing a processing procedure of serial ROM write clock processing.

FIG. 80 is a flowchart showing a processing procedure of serial ROM preparation processing.

FIG. 81 is a flowchart showing a processing procedure of serial ROM read processing.

FIG. 82 is a flowchart showing a processing procedure for serial ROM write processing.

FIG. 83 is a flowchart showing a processing procedure of a winning ball signal processing.

FIG. 84 is a flowchart showing the processing procedure of START processing.

FIG. 85 is a flowchart showing a processing procedure of an interrupt processing from the main.

[Fig. 86] Fig. 86 is a flowchart illustrating a processing procedure of watchdog timer processing.

FIG. 87 is a flowchart showing a processing procedure of voltage monitoring processing.

FIG. 88 is a flowchart showing the processing procedure of START processing of command control processing.

FIG. 89 is a flowchart showing a processing procedure of START processing of command control processing.

[Fig. 90] Fig. 90 is a flowchart illustrating a processing procedure of int main processing.

FIG. 91 is a flowchart illustrating a processing procedure of int main processing.

FIG. 92 is a flowchart showing a processing procedure for RAMCHECK processing.

FIG. 93 is a flowchart showing a processing procedure of RAMCHECK processing.

[Fig. 94] Fig. 94 is a flowchart illustrating a processing procedure of istp hd processing.

FIG. 95 is a flowchart showing a processing procedure of istp cm processing.

96 is a flowchart showing a processing procedure of istp cc processing. FIG.

FIG. 97 is a flowchart showing a processing procedure of ICOMSET processing.

FIG. 98 is a flowchart illustrating a processing procedure of timer processing.

FIG. 99 is a flowchart showing a processing procedure of init processing.

FIG. 100 is a flowchart showing a processing procedure of init processing.

101 is a flowchart showing a processing procedure of command processing. FIG.

FIG. 102 is a flowchart illustrating a processing procedure of dsp off processing.

FIG. 103 is a flowchart illustrating a processing procedure of bx on processing.

FIG. 104 is a flowchart illustrating a processing procedure of bx off processing.

FIG. 105 is a flowchart illustrating a processing procedure of a by-on processing.

FIG. 106 is a flowchart showing a processing procedure for by off processing.

FIG. 107 is a flowchart showing a processing procedure of FVBWAIT processing.

FIG. 108 is a flowchart showing a processing procedure of PORT GET processing.

FIG. 109 is a flowchart illustrating a processing procedure of PAT CPYZ processing.

FIG. 110 is a flowchart showing a processing procedure of SLMSKHI processing.

FIG. 111 is a flowchart showing a processing procedure of PAT CPYH processing.

FIG. 112 is a flowchart showing a processing procedure of PABAGETA processing.

FIG. 113 is a flowchart showing a processing procedure of PAT CPYST processing.

FIG. 114 is a flowchart showing a processing procedure of PAT DCMP processing.

FIG. 115 is a flowchart showing a processing procedure of PABAPO2 processing.

FIG. 116 is a flowchart showing a processing procedure of PAT CPYS processing.

FIG. 117 is a flowchart showing a processing procedure of PAT COPY processing.

FIG. 118 is a flowchart showing a processing procedure of PAT CPY2 processing.

FIG. 119 is a flowchart showing a processing procedure of PAT CLSH processing.

120 is a flowchart showing a processing procedure of SPRCLRA processing. FIG.

FIG. 121 is a flowchart showing a processing procedure of PATCLRA processing.

FIG. 122 is a flowchart showing a processing procedure of SPRADRST processing.

FIG. 123 is a flowchart showing a processing procedure of PABAPO processing.

FIG. 124 is a flowchart showing a processing procedure of PAT CLS processing.

FIG. 125 is a flowchart showing a processing procedure of SPR CLS processing.

FIG. 126 is a flowchart showing a processing procedure of MON INIT processing.

FIG. 127 is a flowchart illustrating a processing procedure of SCROLL processing.

FIG. 128 is a flowchart illustrating a processing procedure of PALLETTE processing.

FIG. 129 is a flowchart showing a processing procedure of PTN INIT processing.

FIG. 130 is a flowchart showing a processing procedure of PTN CLS processing.

FIG. 131 is a flowchart showing a processing procedure of SPR INIT processing.

FIG. 132 is a flowchart showing a processing procedure of SCR INIT processing.

FIG. 133 is a flowchart showing a processing procedure of PTN OFF processing.

FIG. 134 is a flowchart showing a processing procedure of PTN ON processing.

FIG. 135 is a flowchart showing a processing procedure of SPR OFF processing.

FIG. 136 is a flowchart showing a processing procedure of SPR ON processing.

FIG. 137 is a flowchart showing a processing procedure of SLH SET processing.

FIG. 138 is a flowchart showing a processing procedure of SLV SET processing.

FIG. 139 is a flowchart showing a processing procedure of GAME processing.

FIG. 140 is a flowchart showing a processing procedure of SLOT processing.

FIG. 141 is a flowchart showing a processing procedure of SLOT processing.

FIG. 142 is a flowchart illustrating a processing procedure of SltPutX processing.

FIG. 143 is a flowchart illustrating a processing procedure of SltPutXX processing.

FIG. 144 is a flowchart illustrating a processing procedure of GetRnd processing.

FIG. 145 is a flowchart showing a processing procedure of SLOTSTOP processing.

FIG. 146 is a flowchart showing a processing procedure of SLOTSTOP processing.

FIG. 147 is a flowchart showing a processing procedure of a SLOT STOE processing.

FIG. 148 is a flowchart showing a processing procedure of SLOTSTOE processing.

FIG. 149 is a flowchart illustrating a processing procedure of BolDnSt processing.

FIG. 150 is a flowchart showing a processing procedure of stpChk10 processing.

FIG. 151 is a flowchart showing a processing procedure of SltCenPs processing.

[Fig. 152] Fig. 152 is a flowchart illustrating a processing procedure of SltStPZ1 processing.

FIG. 153 is a flowchart illustrating a processing procedure of SltStPZ2 processing.

FIG. 154 is a flowchart illustrating a processing procedure of RiNohit processing.

FIG. 155 is a flowchart illustrating a processing procedure of ErrChkZZ processing.

FIG. 156 is a flowchart showing a processing procedure of ErrChkXX processing.

FIG. 157 is a flowchart illustrating a processing procedure of Slot27 processing.

FIG. 158 is a flowchart showing a processing procedure of Slot 27 processing.

FIG. 159 is a flowchart showing a processing procedure of SltStp2D processing.

FIG. 160 is a flowchart illustrating a processing procedure of SLTSTART processing.

FIG. 161 is a flowchart showing a processing procedure of SLTSTART processing.

162 is a flowchart showing a processing procedure of SLOT PROC processing. FIG.

FIG. 163 is a flowchart illustrating a processing procedure of SLT AREA processing.

FIG. 164 is a flowchart showing a processing procedure of SLTSTRUP processing.

FIG. 165 is a flowchart showing a processing procedure of a SLOT NOP processing.

FIG. 166 is a flowchart showing a processing procedure of SLTSTUPUP processing.

FIG. 167 is a flowchart showing a processing procedure of SLT STOP processing.

FIG. 168 is a flowchart showing a processing procedure of SLT STOP processing.

FIG. 169 is a flowchart showing a processing procedure of ErrChk23 processing.

FIG. 170 is a flowchart illustrating a processing procedure of ErrChk23 processing.

FIG. 171 is a flowchart showing a processing procedure of ZU HOSE processing.

FIG. 172 is a flowchart showing a processing procedure of SHOW STP processing.

FIG. 173 is a flowchart showing a processing procedure of SLOT ERR processing.

FIG. 174 is a flowchart showing a processing procedure of RichA1 processing.

FIG. 175 is a flowchart showing a processing procedure of RichA1 processing.

FIG. 176 is a flowchart showing a processing procedure of PaSetRic processing.

FIG. 177 is a flowchart showing a processing procedure of AnmTimSt processing.

FIG. 178 is a flowchart illustrating a processing procedure of a Beach 2A processing.

[FIG. 179] FIG. 179 is a flowchart illustrating a processing procedure of a Beach 2A processing.

FIG. 180 is a flowchart showing a processing procedure of SLTRRICH processing.

FIG. 181 is a flowchart showing a processing procedure of SWat2A 2 processing.

FIG. 182 is a flowchart showing a processing procedure of SWat2A 0 processing.

FIG. 183 is a flowchart illustrating a processing procedure of ShowProc processing.

FIG. 184 is a flowchart showing a processing procedure of HitChk processing.

FIG. 185 is a flowchart illustrating a processing procedure of RichChk processing.

FIG. 186 is a flowchart showing a processing procedure of FriSet processing.

FIG. 187 is a flowchart showing a processing procedure of HipSet processing.

FIG. 188 is a flowchart illustrating a processing procedure of NudoSet processing.

FIG. 189 is a flowchart showing a processing procedure of ShowSctN processing.

FIG. 190 is a flowchart illustrating a processing procedure of ShowSctW processing.

FIG. 191 is a flowchart showing a processing procedure of ShowSct processing.

FIG. 192 is a flowchart showing a processing procedure of ShowGet processing.

FIG. 193 is a flowchart illustrating a processing procedure of BichMon processing.

FIG. 194 is a flowchart showing a processing procedure of a CHANCE processing.

FIG. 195 is a flowchart showing a processing procedure of a CHANCE processing.

196] FIG. 196 is a flowchart showing a processing procedure of RichE2B processing.

FIG. 197 is a flowchart showing a processing procedure of STP POSI processing.

FIG. 198 is a flowchart illustrating a processing procedure of AnmCmSt processing.

FIG. 199 is a flowchart showing a processing procedure of SLOT INT processing.

[Fig. 200] Fig. 200 is a flowchart illustrating a processing procedure of an INT SHOW process.

FIG. 201 is a flowchart illustrating a processing procedure of StdMon processing.

FIG. 202 is a flowchart showing a processing procedure of KakuSet processing.

FIG. 203 is a flowchart illustrating a processing procedure of Wave processing.

FIG. 204 is a flowchart illustrating a processing procedure of PltSet1 processing.

FIG. 205 is a flowchart illustrating a processing procedure of SLOT MON processing.

FIG. 206 is a flowchart illustrating a processing procedure of SltMsk03 processing.

FIG. 207 is a flowchart illustrating a processing procedure of SltMsk00 processing.

FIG. 208 is a flowchart illustrating a processing procedure of NudoPut0 processing.

FIG. 209 is a flowchart illustrating a processing procedure of NudoPut1 processing.

FIG. 210 is a flowchart illustrating a processing procedure of Show processing.

FIG. 211 is a flowchart illustrating a processing procedure of Tsk3Cra processing.

FIG. 212 is a flowchart illustrating a processing procedure of NextKoma processing.

[FIG. 213] KomaPut processing and KomaPut
It is a flowchart which shows the process sequence of 2 processes.

FIG. 214 is a flowchart showing a processing procedure of NewSkoma processing.

FIG. 215 is a flowchart showing a processing procedure of SPR CLR2 processing.

FIG. 216 is a flowchart showing a processing procedure of SLT ABC processing.

FIG. 217 is a flowchart showing a processing procedure of FLASH processing.

FIG. 218 is a flowchart showing a processing procedure of FLASH processing.

FIG. 219 is a flowchart showing a processing procedure of SLTSPDSP processing.

FIG. 220 is a flowchart illustrating a processing procedure of SLTPIOSL processing.

FIG. 221 is a flowchart showing a processing procedure of SLOT MOV processing.

FIG. 222 is a flowchart showing a processing procedure of SLT PGET processing.

FIG. 223 is a flowchart showing a processing procedure of GRFTBLGT processing.

FIG. 224 is a flowchart showing a processing procedure of SLT SCL processing.

FIG. 225 is a flowchart showing a processing procedure for SLT PTN processing.

FIG. 226 is a flowchart showing a processing procedure of SLT PTH processing.

FIG. 227 is a flowchart showing a processing procedure of PIC SET processing.

FIG. 228 is a flowchart illustrating a processing procedure of SCLADR processing.

FIG. 229 is a flowchart showing a processing procedure of SclAdrB processing.

[Fig. 230] Fig. 230 is a flowchart illustrating a processing procedure of SPR CLRA processing.

FIG. 231 is a flowchart showing a processing procedure of SPR CLR processing.

FIG. 232 is a flowchart illustrating a processing procedure of ROUND processing.

FIG. 233 is a flowchart showing a processing procedure of ROUND processing.

FIG. 234 is a flowchart showing a processing procedure of RNDJMP processing.

FIG. 235 is a flowchart showing a processing procedure of ZUGARA processing.

FIG. 236 is a flowchart illustrating a processing procedure of ROUND01 processing.

FIG. 237 is a flowchart showing a processing procedure of R12BAK processing.

FIG. 238 is a flowchart showing a processing procedure of R11BAK processing.

FIG. 239 is a flowchart showing a processing procedure of R10BAK processing.

FIG. 240 is a flowchart showing the processing procedure of R09BAK processing.

FIG. 241 is a flowchart showing a processing procedure of R07BAK processing.

FIG. 242 is a flowchart showing a processing procedure of R05BAK processing.

FIG. 243 is a flowchart showing a processing procedure of R03BAK processing.

FIG. 244 is a flowchart showing a processing procedure of R01BAK processing.

FIG. 245 is a flowchart showing a processing procedure of R01BAKS processing.

FIG. 246 is a flowchart showing a processing procedure of ROUND02 processing.

FIG. 247 is a flowchart showing a processing procedure of PANPGM processing.

FIG. 248 is a flowchart illustrating a processing procedure of ROUND03 processing.

FIG. 249 is a flowchart showing a processing procedure of ROUND04 processing.

FIG. 250 is a flowchart illustrating a processing procedure of ROUND05 processing.

FIG. 251 is a flowchart showing a processing procedure of ROUND06 processing.

FIG. 252 is a flowchart showing a processing procedure of ROUND07 processing.

FIG. 253 is a flowchart showing a processing procedure for R07BAK2 processing.

FIG. 254 is a flowchart showing a processing procedure of ROUND08 processing.

FIG. 255 is a flowchart showing a processing procedure of ROUND09 processing.

[Fig. 256] Fig. 256 is a flowchart illustrating a processing procedure of R09BAKA processing.

FIG. 257 is a flowchart showing a processing procedure of ROUND10 processing.

FIG. 258 is a flowchart showing a processing procedure of R10BAKB processing.

[FIG. 259] FIG. 259 is a flowchart illustrating a processing procedure of ROUND11 processing.

[Fig. 260] Fig. 260 is a flowchart illustrating a processing procedure of ROUND12 processing.

FIG. 261 is a flowchart showing a processing procedure of R12BAKC processing.

262] FIG. 262 is a flowchart illustrating a processing procedure of TOMEIPGM processing.

FIG. 263 is a flowchart showing a processing procedure for ROUND13 processing.

FIG. 264 is a flowchart showing a processing procedure of ROUND14 processing.

FIG. 265 is a flowchart showing a processing procedure of PANPGMD processing.

FIG. 266 is a flowchart showing a processing procedure of ROUND15 processing.

FIG. 267 is a flowchart showing a processing procedure of BLACKPGM processing.

[FIG. 268] FIG. 268 is a flowchart illustrating a processing procedure of WHITE EPGM processing.

FIG. 269 is a flowchart showing a processing procedure of TESTPGM processing.

FIG. 270 is a flowchart showing a processing procedure of PALSET processing.

[Fig. 271] Fig. 271 is a flowchart illustrating a processing procedure of ROUND16 processing.

FIG. 272 is a flowchart showing a processing procedure of OPENING processing.

FIG. 273 is a flowchart showing a processing procedure of RASINIT processing.

FIG. 274 is a flowchart showing a processing procedure of RAS processing.

[Fig. 275] Fig. 275 is a flowchart illustrating a processing procedure of a CHRSET processing.

[FIG. 276] FIG. 276 is a flowchart illustrating a processing procedure of CHRSCR2 processing.

[Fig. 277] Fig. 277 is a flowchart illustrating a processing procedure of CHRSCR1 processing.

FIG. 278 is a flowchart illustrating a processing procedure of CHRSCR processing.

[FIG. 279] FIG. 279 is a flowchart illustrating a processing procedure of ENDDING processing.

FIG. 280 is a flowchart showing a processing procedure of SHOUGAI processing.

FIG. 281: SHOPGM2 processing and SHOPGM1
It is a flow chart which shows a processing procedure of processing.

FIG. 282 is a flowchart showing a processing procedure of BANZAI processing.

FIG. 283 is a flowchart showing a processing procedure of CENTER processing.

FIG. 284 is a flowchart showing a processing procedure of CENTER 2 processing.

[FIG. 285] FIG. 285 is a flowchart illustrating a processing procedure of FEVER processing.

FIG. 286 is a flowchart showing a processing procedure of FLACH processing.

FIG. 287 is a flowchart showing a processing procedure of WAIT processing.

FIG. 288 is a flowchart showing a processing procedure of SPR SET processing.

FIG. 289 is a flowchart showing a processing procedure of HIP processing.

FIG. 290 is a flowchart showing a processing procedure of HIP processing.

[Fig. 291] Fig. 291 is a flowchart illustrating a processing procedure of RNUMMOVE processing.

292] FIG. 292 is a flowchart showing a processing procedure of R ROUND processing.

FIG. 293 is a flowchart showing a processing procedure of RED ON processing.

FIG. 294: TASKINIT processing and TASKMA
It is a flow chart which shows a processing procedure of IN processing.

FIG. 295: TASKINIT processing and TASKMA
It is a flow chart which shows a processing procedure of IN processing.

FIG. 296. TASKINIT processing and TASKMA
It is a flow chart which shows a processing procedure of IN processing.

FIG. 297 is a flowchart showing a processing procedure of STEPINC processing.

[FIG. 298] FIG. 298 is a flowchart illustrating a processing procedure of RNDMD01 processing.

FIG. 299 is a flowchart illustrating a processing procedure of RNDMD02 processing.

FIG. 300 is a flowchart illustrating a processing procedure of RNDMD03 processing.

FIG. 301 is a flowchart illustrating a processing procedure of RNDMD04 processing.

FIG. 302 is a flowchart illustrating a processing procedure of RNDMD05 processing.

FIG. 303 is a flowchart illustrating a processing procedure of RNDMD06 processing.

[Fig. 304] Fig. 304 is a flowchart illustrating a processing procedure of RNDMD07 processing.

FIG. 305 is a flowchart illustrating a processing procedure of RNDMD08 processing.

FIG. 306 is a flowchart illustrating a processing procedure of RNDMD09 processing.

[FIG. 307] FIG. 307 is a flowchart illustrating a processing procedure of an RNDMD0A processing.

[FIG. 308] FIG. 308 is a flowchart illustrating a processing procedure of RNDMD0B processing.

FIG. 309 is a flow chart showing a processing procedure of RNDMD0C processing.

FIG. 310 is a flowchart illustrating a processing procedure of RNDMD0D processing.

FIG. 311 is a flowchart showing a processing procedure of PALCTOW processing.

FIG. 312 is a flowchart showing a processing procedure of PALWTOC processing.

FIG. 313 is a flowchart showing a processing procedure of PALCTOB processing.

FIG. 314 is a flowchart showing a processing procedure of PALBTOC processing.

FIG. 315 is a flowchart showing a processing procedure of PALMTOC processing.

FIG. 316 is a flowchart showing a processing procedure of PALCTOM processing.

[Explanation of symbols]

1 is a game board, 3 is a game area, 4 is a variable display device, 5 is a variable display part, 11 is a variable winning ball device, 16 is a variable starting opening device, 40 is a basic circuit, 401 is a ROM, and 402 is a CP.
U, 403 RAM, 50 CRT circuit, 55 CRT
Display, 60 is CRT control circuit, 601 is CP
U, 602 is RAM, 603 is ROM, 63 is VDP
A, 64 is VDP B, 65 is a character ROM, 66
Is a character ROM.

Claims (4)

[Claims] 1. A gaming machine having a game control computer, the game operation of which is controlled by the game control computer, wherein the control data used for controlling the game operation and an abnormality of the control data are determined. Storage means for storing data including a plurality of abnormality determination data to be used, and abnormality determination means for reading the plurality of abnormality determination data and determining whether or not the read data is abnormal data, An initialization unit that initializes the storage data of the storage unit when the abnormality determination unit determines that the specific abnormality determination data out of the plurality of abnormality determination data is abnormal. A gaming machine. 2. A gaming machine having a game control computer, the game operation of which is controlled by the game control computer, wherein the control data used for controlling the game operation and an abnormality of the control data are determined. Storage means for storing data including a plurality of abnormality determination data to be used, and abnormality determination means for reading the plurality of abnormality determination data and determining whether or not the read data is abnormal data, An initialization unit that initializes the storage data of the storage unit when all the abnormality determination data of the plurality of abnormality determination data are determined to be abnormal by the abnormality determination unit. A gaming machine. 3. A game machine having a game control computer, the game operation being controlled by the game control computer, and being controlled to a specific game state advantageous to the player when a predetermined condition is satisfied. A storage means for storing data including control data used for controlling the game operation and a plurality of abnormality determination data used for determining an abnormality of the control data, and reading the plurality of abnormality determination data Abnormality determination means for determining whether or not the read data is abnormal data, and a specific one of the plurality of abnormality determination data in a state in which the gaming machine is not controlled to the specific gaming state. First initialization means for initializing the storage data of the storage means when the abnormality determination data determines that the abnormality determination data is abnormal; In the state where the gaming machine is controlled to the specific game state, when the abnormality determination means determines that a predetermined number of abnormality determination data in addition to the specific abnormality determination data is abnormal, A game machine comprising: a second initialization means for initializing stored data. 4. A gaming machine having a game control computer, the game operation being controlled by the game control computer, and being controlled to a specific game state advantageous to a player when a predetermined condition is satisfied. In the plurality of storage areas, there is a plurality of storage areas in which control data used for controlling the gaming machine are stored, and specific game control data indicating whether or not to control the particular gaming state And a discriminating means for discriminating whether or not the plurality of specific game control data stored dispersedly in a plurality of storage areas of the storing means are read and the read data coincide with each other. And an initialization unit that initializes the storage data of the storage unit when the match determination unit determines that the plurality of specific game control data do not match. A gaming machine characterized by.