JPH0989992A - System for automatically detecting approximate shortest connecting order in shift resistor type scanning circuit generation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system for automatically detecting an approximate shortest connecting order in shift resistor type scanning circuit generation by which the connecting order for realizing the shortest scan chain of a large scale logic circuit can be determined in a short computing time which arises no problem in practice. SOLUTION: A rectangular area in which a large scale logic circuit is formed is divided into n- and m-pieces of areas by means 1, 2, target vertical and horizontal divided areas are detected by means 3, 4, the rectangular area is divided into four areas by a means 5 by the cross area formed by these detected areas, and the number of connecting points in each divided rectangular area is counted by a means 7. When the number of connecting points is 1 as the result of counting, the connecting point is connected by a means 8, and when it is 2 or more, a temporary connecting point detected by a means 6 within the divided rectangular area where the two or more connecting points are present is connected, and a series of processing for dividing the area into four areas is repeated until one connecting point is present in one divided rectangular area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of automatically detecting an approximate shortest connection order in generating a shift register type scan circuit.

This system is based on a flip-flop (hereinafter, referred to as a storage element in a large-scale logic LSI (semiconductor integrated circuit)).
In order to automatically generate a shift register type scan circuit (hereinafter referred to as a scan chain) in which a plurality of FFs are connected in series, the total distance connecting all of the many points arranged by the straight line is the shortest. This is an application of an approximate solution of the “traveling salesman problem”, which is a problem of finding the connection order.

In recent years, due to the rapid progress of semiconductor technology, the logical scale of each LSI used in a computer or the like is ever increasing. In order to facilitate generation of a test pattern for performing a test after manufacturing such an LSI, shorten the time of the test itself (reduce the number of test patterns), and further facilitate the device test by a device tester, A technique for forming a scan chain is already widely used in order to controllability of externally changing the state of the FF in the logic circuit to an arbitrary value or observability of reading.

However, although all the FFs may be incorporated in the scan chain, only some of the FFs may be incorporated in the scan chain due to the chip size limitation. It does not matter which it is.

When constructing a scan chain, the order in which the FFs included in the scan chain are connected is usually not significant as a logical function and can be said to be arbitrary. However, in the packaging design (layout design), the shorter the total line length of the scan chain, the higher the probability of successful automatic wiring, and the standard cell type LSI.
Can reduce the chip area.

Further, connecting the wiring load of a long scan chain to the data output of the FF adversely affects the operation performance. That is, from the two aspects of mounting design and performance of logical operation, it is desirable that the connection order of the FFs as a scan chain is such that the connection distance between each FF and the total connection line length are as short as possible.

Therefore, there is a demand for a method of automatically finding the connection order satisfying such a demand in a short calculation processing time after the FFs are arranged.

[0008]

2. Description of the Related Art Generally, the above-mentioned method of reducing the connection order of FFs as a scan chain so that the connection distance between each FF and the total connection line length are as short as "traveling salesman's problem". It is almost the same as the known one, and various solution methods have been conventionally proposed as "combinatorial optimization problem".

For example, a simulated annealing method, a method in which a learning function is added to the simulated annealing method, and a method called a gene algorithm are used.

[0010]

By the way, the above-mentioned method focuses on obtaining an exact solution, and realizes the shortest scan chain of a large-scale logic circuit including more than 10,000 FFs. When it is applied to the task of obtaining the connection order, the calculation processing time becomes enormous, and there is a problem that it is practically impossible to use.

The present invention has been made in view of the above point, and the connection order for realizing the shortest scan chain of a large-scale logic circuit can be obtained in a short calculation processing time that does not pose a problem in practical use. An object of the present invention is to provide an automatic detection method of approximate shortest connection order in shift register type scan circuit generation.

[0012]

FIG. 1 shows the principle of the present invention. The automatic detection method of the approximate shortest connection order in the shift register type scan circuit generation shown in FIG. 1 is performed by automatically generating a shift register type scan circuit in which a large number of elements of a large-scale logic circuit are connected in series. The connection order is such that the total length of connection is the shortest.

The feature of the present invention resides in a vertical dividing means 1 for vertically dividing a rectangular area into n, a horizontal dividing means 2 for horizontally dividing a rectangular area into m, and each vertical divided area obtained by n division. Vertical division area detection means 3 for detecting a target vertical division area that is closest to the center of the n divisions and does not include the connection point that is the element described above, and is connected in each horizontal division area obtained by the m division. A rectangular area is divided into four areas by a horizontal divided area detection unit 4 that detects a target horizontal divided area that does not include a point and is closest to the center of the m-divided area, and a cross area formed by the target vertical and horizontal divided areas. 4 area dividing means 5, temporary connection point detecting means 6 that uses intersections of cross areas as temporary connection points, counting means 7 that counts the number of connection points in the rectangular area, and the number of connection points in the rectangular area is 1. Connect the connection points in two cases, and the connection points Is connected to the connecting means 8 for connecting the temporary connection points in the case of two or more, the rectangular area in which the large-scale logic circuit is formed is divided into n and m by the vertical and horizontal dividing means 1 and 2, The target vertical and horizontal division areas are detected by the horizontal division area detection means 3 and 4, and the rectangular area is divided into four areas by the four-area division means 5 by the cross area formed by the detection areas. The number of connecting points in the rectangular area is counted by the counting means 7, and if the number of connecting points of the counting result is 1, the connecting points are connected by the connecting means 8, and if there are two or more, the two or more connecting points are A series of processes for connecting the temporary connection points detected by the temporary connection point detection means 6 in the existing divided rectangular area and further dividing into four areas
It is configured to repeat until there is one connection point in one divided rectangular area.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of the present invention whose configuration has already been described in the above-mentioned “Means for Solving the Problems”. Referring to FIG. 1, a shift register type scan circuit generation according to an embodiment of the present invention is performed. The automatic detection method of the approximate shortest connection order in will be described.

FIG. 2 shows a rectangular area 10 in which a large scale logic circuit is formed. In this rectangular area 10, reference numeral 1
Reference numerals 1, 12, 13, 14 are a large number of FFs (flip-flops) that form a large-scale logic circuit. However, although the FF is shown by □, the reference numeral is attached to an arbitrary one.

When obtaining the approximate shortest connection order of the FFs 11 to 14, first, the rectangular area 10 is n and m (for example, 20 and 15) by the vertical and horizontal dividing means 1 and 2 shown in FIG.
After the division, the vertical and horizontal divided area detecting means 3 and 4 detect the target vertical divided area 16 and the target horizontal divided area 17.

In this detection, a vertical division area which does not include the FFs 11 to 14 in each vertical division area obtained by the n division and is closest to the center of the n division is detected as the target vertical division area 16, The target horizontal division region 17 is a horizontal division region that does not include the FFs 11 to 14 in each of the horizontal division regions obtained by the m division and is closest to the center of the m division.
Is detected as

However, n and m are numerical values manually specified, or numerical values that are equal to or less than the specified value of the average density of strip-shaped divided areas divided vertically and horizontally. Next, the four-region dividing means 5 divides the rectangular region 10 into four regions 19 by the cross region formed by the target vertical and horizontal divided regions 16 and 17.
Divide into 20, 21, 22.

Each of the divided rectangular areas 19 to 2
The number of the two FFs 11 to 14 is counted by the counting means 7. As a result of this counting, if the number of FFs is one of the FFs 14 as shown in the divided rectangular area 22, for example, the F by the connecting means 8.
F14 is connected to another FF or temporary connection point.

If there are two or more FFs, the divided rectangular area in which two or more FFs exist, for example, the divided rectangular area 20 in which three FFs 11 to 13 exist, is used to obtain the cross area described above. After performing a series of processing, the temporary connection point detected by the temporary connection point detection unit 6 is connected to the FF or another temporary connection point, and the area 20 is further divided into four areas.

The above series of processing is repeated until there is one connection point in one divided rectangular area (for example, divided rectangular area 22). According to such a series of processing, when a large number of FFs in a large-scale logic circuit are connected in series, the FFs are connected.
It is possible to obtain a connection order in which the total length of connecting the lines is close to the shortest.

Further, when the target vertical division area 16 and the target horizontal division area 17 are detected by the above-mentioned vertical and horizontal division area detecting means 3 and 4, the condition that no FF is included in the vertical or horizontal division area, It is assumed that the FF is replaced with a condition that a certain number of FFs are not included.

In this case, when the FF density of the large-scale logic circuit is high, the target vertical division area 16 and the target horizontal division area 1
It is effective for detecting 7. Further, when the number of divisions n and m is determined when dividing into n and m by the vertical and horizontal dividing means 1 and 2, the distribution density of the FFs to be connected in each of the vertical and horizontal directions is obtained, and the obtained distribution density number is obtained. Accordingly, the number is determined so that there is a high probability that the vertical and horizontal divided regions where the most connected FF does not exist can be found.

An FF indicated by a broken line □ around the rectangular area 10 in FIG. 2 is a division processing into vertical and horizontal division areas by the vertical and horizontal division means 1 and 2, and vertical and horizontal division area detection means 3,
In step 4, the target vertical division area 16 and the target horizontal division area 17 are ignored in the processing conditions.

This is a rectangular area 2 as shown in FIG.
5, that is, FFs indicated by broken lines □ all over the inside of the chip are evenly arranged, and are similarly ignored.
This is an FF in a large-scale logic circuit (LSI) in recent years.
The input / output circuits in which are embedded are uniformly arranged around the chip as shown by the broken line □ in FIG. 2 or inside the chip as shown by the broken line □ in FIG. This is because it must be configured.

In the rectangular area in which a large-scale logic circuit is formed, which is shown by reference numeral 26 in FIG. 4, or a divided rectangular area of this rectangular area, a large number of FFs are arranged in a certain range as shown by □. In this case, an area surrounded by a rectangular line 27 that covers all the FFs and has the FFs existing at the outermost corners of the FF group is set as the divided rectangular area.

Next, a method of correcting the connection order of FFs or temporary connection points will be described with reference to FIGS. However, FIG.
29, the same symbols are attached to the same portions. As described above, while repeating the four divisions, the connection order of the FFs or the temporary connection points at each division stage is evaluated and determined in comparison with all combinations. However, when determining the connection order from one of the four divided areas to the next divided area of the same level, the level of fineness of the division is different. Therefore, the division is advanced after that and the connection order is similarly set. There is a possibility that the connection order will be adversely affected when making the decision.

In order to eliminate such a situation at a rapid stage, the connection order correction process described below is performed. The connecting means 8 shown in FIG. 1 normally detects a start point, an end point, and an intermediate point between them from a connection point or a temporary connection point in each area of a four-divided area, and connects these points sequentially. However, the shortest connection may not be performed for the above-mentioned reason.

The first connection order correction process (2 point replacement improvement process within 4 points) performed by the connecting means 8 takes 4 points from the start point in the order of connection after the connection after the 4 divisions is completed. Switch the connection order of the middle two points, determine whether the line length connecting the four switched points is shorter than before replacement, and if it is shorter than before replacement, adopt that replacement process from the start point. One point is sequentially applied to all points until the end point.

In the second connection order correction process (adjacent point replacement improvement process), when the first intermediate point connected to the start point is not the closest point to the start point, the second intermediate point closest to the start point is obtained. A process of connecting to the first intermediate point via a point, determining whether the total line length after this replacement is shorter than that before replacement, and adopting the replacement if shorter than before replacement Is sequentially applied to all points from the start point to the end point one by one.

Further, the comparative evaluation of the line lengths before and after the first and second connection order correction processes are performed is performed by the total line length of the straight lines connecting the connection points, and further, the number of intersections of the straight lines. A constant weight is added to the increase / decrease in the evaluation.

Application of the first and second connection order correction processing is as follows.
It can be applied alone or in any order. First, as shown in FIG. 5, in the first division, the rectangular area 30 in which the large-scale logic circuit is formed is divided into four, and in each of the four divided areas, as described with reference to FIG. Further, rectangular areas 31, 32, 33, 34 surrounding the portion where FFs are densely located are obtained.

Since there is only one FF in the rectangular area 31, the FF serves as the connection point 35, and a large number of FFs exist in the rectangular area 32. Therefore, the temporary connection point detecting means 6 is provided.
The temporary connection point 36 is detected in (FIG. 1), and since a large number of FFs similarly exist in the rectangular area 33, the temporary connection point 37 is formed.
Is detected and a plurality of FFs are present in the rectangular area 34, so it is assumed that the temporary connection point 38 is detected.

At this time, the connecting means 8 makes the shortest connection connecting these four points with the connection point 35 as the start point, the temporary connection point 36 as the end point, and the other temporary connection points 37 and 38 as the intermediate points.
That is, the starting point 31 and the intermediate point 38 are connected, and the intermediate point 38
And 37 are connected, and the intermediate point 37 and the end point 36 are connected.

Next, as shown in FIG. 6, in the second division, the rectangular area 32 shown in FIG.
44, 45, and 46, the rectangular area 33 is divided into four areas 47, 48, 49, and 50, and the rectangular area 34 is divided into areas 51, 52, 53, and 54. Will be divided.

A temporary connection point 55 is detected in the area 43, a temporary connection point 56 in the area 44, a connection point 57 in the area 45, a temporary connection point 58 in the area 46, and a temporary connection point 59 in the area 47. 48 indicates a temporary connection point 60, region 49 indicates a temporary connection point 61, region 5 indicates
It is assumed that the temporary connection point 62 is detected at 0, the temporary connection point 63 is detected at the region 51, the connection point 64 is detected at the region 52, the connection point 65 is detected at the region 53, and the temporary connection point 54 is detected at the region 54.

At this time, the connecting means 8 makes the shortest connection to connect them, with the connection point 35 as the start point, the temporary connection point 56 as the end point, and the other intermediate points. It is assumed that, after this connection, the connection unit 8 applies the above-described second connection order correction process (adjacent point replacement improvement process). An example of this case is shown in FIG. As can be seen from the comparison with FIG. 6, in FIG. 7, the temporary connection points 60 and 61 are connected, and the temporary connection points 61 and 59 are 5
9 and 62, 62 and 66, FF 65 and temporary connection point 6
3 are connected, which is shorter than the connection length in the case of FIG.

After that, it is assumed that the connection means 8 further applies the above-mentioned first connection order correction processing (two-point replacement improvement processing within four points). An example of this case is shown in FIG. As can be seen from a comparison with FIG. 7, in FIG. 8, the temporary connection points 55 and 57 are connected, the temporary connection points 58 and 60, 60 and 59, 59 and 61, 61 and 62. And are connected, which is shorter than the connection length in the case of FIG.

Thereafter, the four-division processing and the normal connection processing, the first
And by repeating the second connection order correction process, all the FFs are finally connected in the approximate shortest connection order as shown in FIG.

Next, as shown in FIG. 9, after all the FFs are finally connected, the processing when the distance between the FFs (connection points) is a predetermined distance or more will be described with reference to FIGS. It will be described with reference to FIG.

First, the first process will be described with reference to FIG. As shown in FIG. 10, when the distance between the FFs 67 and 68 in the chip 66 is more than a predetermined distance, the electric resistance is large and the signal does not propagate properly.

Therefore, it is necessary to insert a gate for the buffer, but a relay point for automatically inserting the gate is obtained. Therefore, the first means for calculating the placement position of the gate so that the mounting design is appropriately performed, and the second means for propagating the relay point information obtained by the first means to the placement design processing means for performing the mounting design. Was provided in the connecting means 8.

As for the arrangement position of the gate, since the middle between FF 67 and 68 is suitable as shown by reference numeral 69 in the figure, it is calculated by the first means and then 69 by the second means.
A gate (relay point placement candidate) is placed at the position indicated by.

However, in the standard cell type LSI, the gate may be arranged between the mounting units, which are called layout blocks denoted by reference numerals 70 and 71. It is not allowed to arrange the gate in such a position because it is out of the packaging design rule.

Therefore, the connecting means 8 has a third means for rearranging the gate in the layout block 71 closest to the relay point 69 obtained first and at the position 72 where the signal can be properly propagated.

That is, if the position 72 where the buffer gate is inserted and connected between the FFs 67 and 68 which are connected to each other and are separated from each other by a predetermined distance or more is obtained by the control of the third means, the electric resistance is reduced and the signal is properly propagated. You can

Further, as shown in FIG. 11, in the chip 66, an FF 74 having an output terminal Q and an inverting output terminal XQ.
From the output terminal Q of the FF75 by lines 77 and 78.
And 76, the distance between the connections is such that the electrical resistance is large and the signal does not propagate properly.

In this case, the connecting means 8 is provided with a fourth means for changing the scan chain connection from the unused inverting output terminal XQ of the connection source FF 74 to one FF 76 via the inverter 79 as shown in FIG.

By changing the connection as shown in FIG. 12 under the control of the fourth means, the electric resistance can be reduced and the signal can be properly propagated. In the connection change of FIG. 12,
As described with reference to FIG. 10, when the inverter 79 is arranged between the mounting units called layout blocks, the fourth means causes the inverter 79 to operate.
It is assumed that control is performed so that the signal is rearranged in a layout block closest to 9 and at a position where signals can be properly propagated.

Next, as shown in FIG. 13, the detour wiring when a huge macro circuit 80 such as a RAM or a register file exists between the FFs 81 and 82 connected to each other will be described.

In such a case, the FFs 81 and 82 are connected by bypassing the upper side or the lower side of the macro circuit 80, and the connecting means 8 is provided with a fifth means for wiring the shorter one. That is, as shown in the figure, if the shorter one of the first bypass wiring 83 and the second bypass wiring 84 is obtained by the fifth means and the shorter one, for example, the first bypass wiring 83 is adopted, the entire wiring It can contribute to shortening the length.

Next, as shown in FIG. 14, a case will be described in which the giant macro circuit 86 whose scan data input / output terminals SDI and SDO are far apart is regarded as one connection point.
A huge macro circuit 86 including an FF that is much larger than a normal FF, such as a RAM or a register file, and is connected to a scan chain built in them.
In that case, SDI and SDO are far apart, and SDI
Some data is input from SDO and is output from SDO.

Since such SDI and SDO form a pair, it is not appropriate to regard each as one connection point. Therefore, in such a huge macro circuit 86, the connecting means 8 is provided with a sixth means for recognizing the center thereof as one connecting point 87.

In addition, as shown in FIG.
Even when the connection order of 9, 90, 91, 92 is predetermined, it is not appropriate to regard each as one connection point. Therefore, in such a case, the connecting means 8 is provided with the seventh means for determining the rectangular area 93 surrounding the plurality of FFs 89 to 92 and recognizing the center of the rectangular area 93 as one connecting point 94.

Next, as shown in FIG. 16, FF indicated by □
A description will be given of the connection in the case where are distributed in a plurality of independent areas 96, 97, 98, 99. In this case, all the FFs are connected in each of the areas 96 to 99, and then the connecting means 8 is provided with an eighth means for connecting the areas 96 to 99 in a predetermined order indicated by. Moreover, each area 96-9
The connection order of 9 can be manually specified.

In such a connection method, in the case of a standard cell type LSI, it is desired to mount and design a circuit having a functional cohesion as one layout block, and to access the scan chain in a functional cohesive unit for the convenience of device testing. This is effective for suppressing the generation of wiring that goes in and out of the layout block in the mounting wiring design.

[0057]

As described above, according to the present invention,
There is an effect that the connection order that realizes the shortest scan chain of a large-scale logic circuit can be obtained in a short calculation processing time that does not pose a practical problem.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a first diagram showing a rectangular area in which a large-scale logic circuit is formed.

FIG. 3 is a second diagram showing a rectangular area in which a large-scale logic circuit is formed.

FIG. 4 is an explanatory diagram of a rectangular area determination process.

FIG. 5 is a first diagram illustrating a connection order correction process.

FIG. 6 is a second diagram illustrating a connection order correction process.

FIG. 7 is a third diagram illustrating a connection order correction process.

FIG. 8 is a fourth diagram illustrating a connection order correction process.

FIG. 9 is a connection completion diagram.

FIG. 10 is a first process explanatory diagram when the distance between connection points is a predetermined distance or more.

FIG. 11 is a diagram showing a state in which a distance between connection points is a predetermined distance or more.

FIG. 12 is a second process explanatory diagram when the connection point distance is a predetermined distance or more.

FIG. 13 is an explanatory diagram of a case where a huge macro circuit is routed around.

FIG. 14 is an explanatory diagram of a case where a huge macro circuit having separate scan data input / output terminals is regarded as one connection point.

FIG. 15 is an explanatory diagram of a case where a rectangular area surrounding all connection points whose connection order is designated is regarded as one connection point.

FIG. 16 is a connection explanatory diagram when connection points are dispersed in a plurality of independent areas.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 vertical division means 2 horizontal division means 3 vertical division area detection means 4 horizontal division area detection means 5 4 area division means 6 temporary connection point detection means 7 counting means 8 connection means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisataka Fukase 2-15-16 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Computer Technology Limited

Claims (19)

[Claims] 1. A shift register type scan circuit for automatically generating a shift register type scan circuit in which a large number of elements of a large-scale logic circuit are connected to each other in a chain. In the automatic detection method of the approximate shortest connection order in generation, vertical division means for vertically dividing a rectangular area into n, horizontal division means for horizontally dividing a rectangular area with each vertical division area obtained by the n division And a vertical division area detecting means for detecting a target vertical division area which does not include the connection point which is the element and is closest to the center of the n divisions, and each of the horizontal division areas obtained by the m divisions. A horizontal division area detecting means for detecting a target horizontal division area that does not include the connection point and is closest to the center of the m division, and a cross area formed by the target vertical and horizontal division areas. A four-area dividing means for dividing the rectangular area into four areas, a temporary connection point detecting means for using a crossing point of the cross area as a temporary connection point, a counting means for counting the number of the connection points in the rectangular area, and a rectangle Connection means for connecting the connection points when the number of connection points in the area is one and connecting the temporary connection points when the number of connection points is two or more, and the large-scale logic circuit is formed. After dividing the rectangular area into n and m by the vertical and horizontal dividing means, the target vertical and horizontal divided areas are detected by the vertical and horizontal divided area detecting means, and the target area is divided by the cross area formed by the detection area. The rectangular area is divided into four areas by the four area dividing means, and the number of the connecting points of each of the divided rectangular areas is counted by the counting means. If the result of the counting is 1 the connecting points are connected. Connect the connection points by means of two If the above,
A series of processes for connecting the temporary connection points detected by the temporary connection point detection means in the divided rectangular area in which the two or more connection points exist and further dividing the connection into four areas
An automatic shortest connection order detection method in shift register type scan circuit generation, characterized in that it is repeated until the number of connection points becomes one in one divided rectangular area. 2. The condition of not including the connection points when the vertical / horizontal divided area detection unit detects the target vertical / horizontal divided areas is defined as a condition of not including a predetermined number or more of the connection points. The automatic detection method of the approximate shortest connection order in the shift register type scan circuit generation according to claim 1, which is replaced. 3. When dividing the number of divisions n and m by the vertical and horizontal dividing means to determine the number of divisions n and m, the distribution density of the connection points is obtained, and according to the obtained distribution density number, 3. The approximate shortest connection order in the shift register type scan circuit generation according to claim 1 or 2, wherein the number of vertical and horizontal divided regions where the connection point to be most connected does not exist is set to a high probability. Automatic detection method. 4. When the connection points are uniformly present around the rectangular area with a specific character, the vertical and horizontal dividing means performs division processing into the vertical and horizontal divided areas, and the vertical division. And an approximate shortest in the shift register type scan circuit generation according to any one of claims 1 to 3, characterized in that the condition is neglected from the condition in the detection processing of the target vertical and horizontal divided areas by the horizontal divided area detecting means. Automatic detection method of connection order. 5. When the connection points are uniformly present in the entire rectangular area with a specific character, the vertical and horizontal dividing means divides the vertical and horizontal divided areas, and the vertical division. And an approximate shortest in the shift register type scan circuit generation according to any one of claims 1 to 3, characterized in that the condition is neglected from the condition in the detection processing of the target vertical and horizontal divided areas by the horizontal divided area detecting means. Automatic detection method of connection order. 6. In the rectangular area, when the connecting points are arranged in a certain range, the connecting points existing at the outermost portion of the connecting point group come to the corners and cover all the connecting points. 6. The automatic detection method of approximate shortest connection order in shift register type scan circuit generation according to claim 1, wherein the area surrounded by the rectangular line is a divided rectangular area. 7. The connection means, after the connection of the connection points or the temporary connection points after the processing of dividing into the four regions is completed,
4 points are taken from the starting point of the connection in the order of connection, and the connection order of 2 points in the middle of these 4 points is exchanged. If the line length connecting these 4 exchanged points becomes shorter than before the exchange, the exchange is adopted. 2. The connection order correction process No. 1 is sequentially performed one by one for all points from the start point to the end point.
7. An automatic detection method of the approximate shortest connection order in the generation of the shift register type scan circuit according to any one of 1 to 6. 8. The connection means, after the connection of the connection point or the temporary connection point after the processing of dividing into the four regions is completed,
If the first point connected to the start point of the connection is not the closest point to the start point, the replacement is performed by connecting from the start point to the first point via the second point closest to the start point, and after this replacement If the total line length of is shorter than that before replacement, the replacement is adopted.
7. The approximate shortest connection order in the shift register type scan circuit generation according to claim 1, wherein the connection order correction process is sequentially performed one by one for all points from the start point to the end point. Automatic detection method. 9. The total sum of straight lines connecting the connection points or the temporary connection points for the comparative evaluation of the line lengths before and after the connection means performs the first and second connection order correction processes. 9. The approximate shortest connection in the shift register type scan circuit generation according to claim 7 or 8, characterized in that the evaluation is performed with a long length and a constant weight is added to the increase and decrease of the number of intersecting straight lines. Sequential automatic detection method. 10. The shift register type scan circuit generating method according to claim 7, wherein the connecting means applies the first and second connection order correction processing independently or in both of them in no particular order. Automatic detection method of approximate shortest connection order. 11. An element for enabling proper signal propagation when the connection means are connected after the connection of all of the connection points with a distance greater than a distance at which a signal cannot be properly propagated. 11. The shift register type scan circuit according to claim 1, further comprising: first means for calculating a relay point for intervening connection between the connection points by calculating an intermediate position between the connection points. Automatic detection method of approximate shortest connection order in generation. 12. The connecting means comprises second means for transmitting the relay point information to the layout design processing means after the relay point is calculated by the first means. Automatic detection method of approximate shortest connection order in shift register type scan circuit generation. 13. If the relay point calculated by the first means is an improper position in the layout design by the layout design processing means, the relay point is added to the connecting means other than the improper position. 11. An automatic detection method of an approximate shortest connection order in shift register type scan circuit generation according to claim 1, further comprising a third means for performing a correction for arranging. 14. An element, which is a connection point having two transmission connection terminals on the output side after all the connection points are connected to the connection means, for one transmission in a state where a signal cannot be properly propagated. When a connection terminal is connected to a plurality of other connection points, the connection of any of the other plurality of connection points is changed through a relay element that adapts the logic of a signal from the other unconnected transmission connection terminal. The automatic detection of the approximate shortest connection order in the shift register type scan circuit generation according to any one of claims 1 to 10, further comprising a fourth means for appropriately propagating a signal. method. 15. The fourth means arranges the relay element at a position other than the incorrect position when the relay element is in the incorrect position in the layout design when the connection is changed. 15. The automatic detection method of the approximate shortest connection order in shift register type scan circuit generation according to claim 14, wherein the correction is performed as described above. 16. The connection means according to claim 1, further comprising a fifth means for connecting the circuit by detouring the circuit at the shortest distance when a circuit exists between the connection points. An automatic detection method of the approximate shortest connection order in the generation of the shift register type scan circuit described in (1). 17. The connecting means comprises a sixth means for recognizing the center of the circuit as one connection point when a circuit having a pair of input / output terminals separated by a predetermined distance is detected. An approximate shortest connection order automatic detection method in the shift register type scan circuit generation according to claim 1. 18. The connecting means includes a seventh means for recognizing a center of a rectangular area surrounding the plurality of connection points as one connection point when a plurality of connection points having a predetermined connection order are detected. The automatic detection method of the approximate shortest connection order in the shift register type scan circuit generation according to any one of claims 1 to 10, which is provided. 19. The connecting means comprises, when the connecting points are dispersed in a plurality of independent areas, connecting the connecting points for each area and then connecting the areas in a predetermined order. The automatic detection method of the approximate shortest connection order in the shift register type scan circuit generation according to any one of claims 1 to 10, which is provided.