CN118504513A

CN118504513A - Method, apparatus, device, medium and program product for checking layout design

Info

Publication number: CN118504513A
Application number: CN202310140666.6A
Authority: CN
Inventors: 程中明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-02-15
Filing date: 2023-02-15
Publication date: 2024-08-16

Abstract

Embodiments of the present disclosure relate to methods, apparatuses, devices, media, and program products for inspecting layout designs. The method comprises the following steps: a plurality of patterns in a circuit layout are first inserted into a grid to determine a pattern distribution of the patterns in a grid array. The patterns in the same grid are then determined as the target pattern group based on the pattern distribution. According to the scheme, patterns close in distance can be rapidly determined by utilizing the grid screening patterns, algorithm steps and performance cost are reduced, and pattern extraction speed is increased.

Description

Method, apparatus, device, medium and program product for checking layout design

Technical Field

The present disclosure relates generally to the field of chip design tools, and more particularly to methods, apparatus, devices, media, and program products for inspecting layout designs.

Background

Electronic design automation (electronic design automation, EDA) software is widely used in the design of chips. With the aid of various EDA software, engineers can easily perform chip designs such as architectural design and Register Transfer Level (RTL) code design, synthesis, design for test (DFT), physical implementation (physical development), signature (signaff), and the like.

In EDA software, design Rule checking (Design Rule Check, DRC) and Mask Rule Checking (MRC) are important links in layout graphics processing. In the above inspection, it is often necessary to extract the patterns with the distances smaller than a specific value from the circuit layout, however, the number of the patterns in the layout is very large, and the scale of the patterns can reach hundreds of millions, so how to extract the patterns with the distances smaller than the specific value quickly is a technical problem to be solved in the industry.

Disclosure of Invention

In view of the above, embodiments of the present disclosure aim to provide a solution for inspecting layout designs.

According to a first aspect of the present disclosure, there is provided a method for inspecting a layout design, the method comprising: determining pattern distribution of the plurality of patterns in the grid array based on the plurality of patterns in the circuit layout; and determining at least one target pattern group of the plurality of patterns based on the pattern distribution in the grid array, the patterns in each of the at least one target pattern group being located in a same grid in the grid array. According to the method disclosed by the invention, the pattern distribution is determined by utilizing the constructed grid, so that the patterns in the same grid are determined, and the speed of determining the potential violation pattern is increased while the calculation cost is reduced.

In some implementations, determining a pattern distribution of the plurality of patterns in the grid array based on the plurality of patterns in the circuit layout includes: scanning the plurality of patterns column by column along a row direction of the grid array to allocate a plurality of pattern marks corresponding to the plurality of patterns to a plurality of sub-storage areas in a grid storage area corresponding to the grid array; and determining a pattern distribution of the plurality of patterns in the grid array based on the pattern flags stored in the grid storage area. In this way, the pattern flags are stored by means of a one-dimensional data structure in the grid storage area, i.e. the pattern flags stored in each grid storage area, whereby the data storage amount is significantly reduced, which is particularly advantageous for hundreds of millions of patterns. In addition, one-dimensional data structures have faster speeds in data access, which reduces computational overhead.

In some implementations, determining a pattern distribution of the plurality of patterns in the grid array based on the plurality of patterns in the circuit layout includes: scanning the plurality of patterns column by column along a row direction of the grid array to allocate a plurality of pattern flags corresponding to the plurality of patterns to a plurality of sub-banks in a column bank corresponding to columns in the grid array; and determining a pattern distribution of the plurality of patterns in the grid array based on the pattern flags stored in the column store. In this way, by introducing the column memory area on the basis of the grid memory area and performing pattern distribution determination from the column memory area, it is possible to further reduce the space required to store data and to accelerate the pattern distribution determination speed.

In some implementations, the method further comprises: the first pattern flag is deleted from the grid storage area in response to the first pattern flag corresponding to a first pattern of the plurality of patterns being stored in a first sub-storage area in the grid storage area and not being stored in a second sub-area adjacent to the first sub-area that is scanned successively. In this way, the pattern marks are dynamically deleted in the grid storage area when the pattern is no longer possible to be scanned by the scanning grid, thereby saving storage space.

In some implementations, the method further comprises: the deleted first pattern flag is assigned to the pattern of the subsequent scan. In this way, the pattern mark is given to a subsequently scanned pattern when the pattern is no longer possible to be scanned by the scanning grid. Thus, hundreds of millions of patterns in a circuit layout can be represented using a small number of pattern flags. This can significantly reduce the amount of memory and enable more rapid determination of the target pattern group.

In some implementations, determining at least one target pattern group of the plurality of patterns based on the pattern distribution in the grid array includes: in response to a plurality of sub-memory areas in the grid memory area corresponding to the same column storing the same plurality of pattern marks, the plurality of pattern marks stored in the plurality of sub-memory areas are determined to be the same target pattern group. In this way, the pattern mark is given to a subsequently scanned pattern when the pattern is no longer possible to be scanned by the scanning grid. Thus, hundreds of millions of patterns in a circuit layout can be represented using a small number of pattern flags. This can significantly reduce the amount of memory and enable more rapid determination of the target pattern group.

In some implementations, the method further comprises: amplifying at least one pattern of the plurality of patterns by a predetermined factor, the predetermined factor being associated with a design constraint of the circuit layout, prior to determining the pattern distribution; determining a pattern distribution of the plurality of patterns in the grid array includes: the expanded pattern is used to determine a pattern distribution of the plurality of patterns in the grid array. In this way, the pattern method is subjected to pattern processing before the pattern distribution is determined, so that the potential violation pattern which does not accord with the design constraint can be flexibly determined according to different layout design constraints

In some implementations, the method further comprises: determining a distance between a plurality of patterns in a first target pattern group of the at least one target pattern group; and in response to the distance being less than the threshold distance, determining a plurality of patterns in the first set of target patterns as offending patterns. In this way, the distance between patterns is determined using a specific algorithm after the preliminary screening of the potentially offending patterns, which can be further accurately determined.

According to a second aspect of the present disclosure, there is provided an apparatus for inspecting a layout design, characterized in that the apparatus comprises: a pattern distribution determination module configured to determine a pattern distribution of a plurality of patterns in the grid array based on the plurality of patterns in the circuit layout; and a pattern group determination module configured to determine at least one target pattern group of the plurality of patterns based on a pattern distribution in the grid array, the patterns in each of the at least one target pattern group being located in a same grid in the grid array.

In a third aspect of the present disclosure, an electronic device is provided. The electronic device includes: at least one computing unit; at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit cause the apparatus to perform the method of the first aspect or any one of the implementations of the first aspect.

In a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores one or more computer instructions, where the one or more computer instructions are executable by a processor to implement the first aspect or any of the implementations of the first aspect.

In a fifth aspect of the present disclosure, a computer program product is provided. The computer program product comprises computer executable instructions which, when executed by a processor, cause the computer to perform some or all of the steps of the method of the first aspect or any implementation of the first aspect.

It will be appreciated that the apparatus for splitting a circuit design of the second aspect, the electronic device of the third aspect, the computer storage medium of the fourth aspect or the computer program product of the fifth aspect provided above are all for implementing the method provided by the first aspect. Accordingly, the explanation or explanation regarding the first aspect is equally applicable to the second aspect, the third aspect, the fourth aspect, and the fifth aspect. The advantages achieved by the second, third, fourth and fifth aspects are referred to as advantages in the corresponding methods, and are not described here.

The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to be used to limit the scope of the disclosure.

It should be understood that the description in this summary is not intended to limit the critical or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above, as well as additional purposes, features, and advantages of embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not by way of limitation.

FIG. 1 shows a flow chart of a design fabrication process of a chip;

FIG. 2 illustrates a block diagram of an example environment, according to some embodiments of the disclosure;

FIG. 3 illustrates a flow chart for inspecting a layout design, according to some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of a circuit layout according to some embodiments of the present disclosure;

FIG. 5 illustrates a schematic diagram for inspecting a circuit layout, according to some embodiments of the present disclosure;

FIG. 6 shows a schematic diagram for inspecting a circuit layout according to further embodiments of the present disclosure

FIG. 7 illustrates a block diagram of an example apparatus for inspecting a layout design, in accordance with some embodiments of the present disclosure; and

Fig. 8 illustrates a schematic block diagram of an example device that may be used to implement some embodiments of the present disclosure.

Detailed Description

The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the drawings. It should be understood that these specific embodiments are described merely to enable those skilled in the art to better understand and practice the present disclosure and are not intended to limit the scope of the present disclosure in any way. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "upper," "lower," "front," "rear," and the like, as used herein, refer to a place or position relationship based on the orientation or position relationship shown in the drawings, and are merely for convenience in describing the principles of the present disclosure, and do not refer to or imply that the elements referred to must have a particular orientation, be configured or operated in a particular orientation, and thus should not be construed as limiting the present disclosure.

As described above, a solution is needed for quickly extracting patterns in a circuit layout that have distances less than a particular value. In some related schemes for inspecting a layout, non-vertical edges of a pattern are first ordered to generate an endpoint sequence of edges. Scanning then begins from left to right in an endpoint sequence. For the pattern side entering the scan line, it is checked in the y-direction with the side of the adjacent pattern and the data is stored in the worksheet. The newly entered pattern edges are then checked in the x-direction with the edges recorded in the worksheet. Pattern edges are removed from queues in the worksheet after leaving the scan line.

The above solution has at least the following drawbacks: (1) The algorithm flow has more steps and complex calculation, so that the required calculation cost is larger, the time consumption is more, and the method is further reflected in the experimental data given later; (2) The need to perform x-direction inspection and y-direction inspection for each pattern, resulting in repetitive computation that reduces performance and makes the underlying code implementation more complex; (3) There are some situations that cannot be handled, for example, vertical edges are not compared, edges that are not adjacent in the y direction are not compared, and the like, and the comparison is imperfect, so that more calculation results are wrong.

In various embodiments of the present disclosure, a method of inspecting a layout design is presented, first of all, a plurality of patterns in a circuit layout are mapped into a grid, thereby determining a pattern distribution of the patterns in a grid array. The patterns in the same grid are then determined as the target pattern group based on the pattern distribution. According to the scheme of the present disclosure, patterns close to each other in distance can be rapidly determined by using the mesh screening pattern. This can avoid a comparison between each of all patterns, thereby reducing algorithm steps and performance overhead and speeding up pattern extraction.

The scenario to which the scheme of the present disclosure is applied is first introduced below. It will be appreciated that the following scenarios are merely exemplary, which are not intended to limit the scope of the present disclosure, and that the aspects of the present disclosure may also be applied to other scenarios in which graphics are filtered according to distance. Fig. 1 shows a flow chart of a chip design fabrication process 100. The design fabrication process 100 begins with specification 110. At the stage of specification 110, the functional and performance requirements that the integrated circuit needs to meet are determined. At the stage of chip design 120, the circuit design is performed by means of EDA software to obtain, for example, a layout file for chip manufacturing. Design 120 may include different design elements based on the difference in circuitry (e.g., digital circuitry or analog circuitry). In the stage of fabrication 140, integrated circuits are formed on the wafer by photolithography, etching, ion implantation, thin film deposition, polishing, and the like. At the stage of packaging 150, the wafer is cut to obtain a die, and the die is packaged by technologies such as adhesion, welding, and mold sealing to obtain a chip. The resulting chips are tested in a stage of testing 160 to ensure that the performance of the finished chips meets the requirements determined in specification 110. The chips 170 that pass the test may be delivered to the customer. It will be appreciated that the above described process is merely illustrative and is not intended to limit the scope of the present disclosure. In some cases, the design and fabrication process of the chip may be different. For example, a tape-out (tape-out) may be performed prior to manufacturing 140. The resulting small number of chips from the die may be used to perform tests to verify that the chip design is expected. If the expectation is not reached, this indicates a die failure and may require chip design adjustments or chip redesign.

In some embodiments, the design 120 of the digital circuit may illustratively include an architectural design 121, an RTL design 123, a functional simulation 125, a synthesis 127, a timing analysis 129, a DFT 131, a verification check 133, a place and route 135, a design rule check (design rule check, DRC) 137, and a generate layout 139. Architecture design 121 includes, for example, designing the architecture of a chip. For example, EDA software may be used to determine the type and number of components or sub-circuits included in a chip system, as well as the function, connection, and interaction of the individual components or sub-circuits. At the stage of RTL design 123, the determined chip architecture may be code described at the RTL level using a hardware programming language such as Verilog or VHDL. The functional simulation 125 is also referred to as an RTL level behavioral simulation or a front-end simulation. The purpose of functional simulation is to analyze the correctness of the logic relationship of the design circuit. Synthesis 127 may convert the RTL into a gate-level netlist (gate-LEVEL NETLIST). The synthesis 127 may include, for example, transformation (transformation), optimization (optimization), and mapping (mapping). In one embodiment, EDA software for synthesis may first convert RTL code into a generic Boolean equation and compile it. The netlist can be optimized according to the delay, area, etc. constraints imposed by the designer, and then the RTL netlist is mapped to a process library to generate a gate level netlist.

Timing analysis 129 is typically a static timing analysis that primarily involves timing calculations and predictions for digital circuits. Whether timing convergence is achieved is determined by timing analysis of paths in the digital circuit, thereby ensuring that the timing of the various circuits meets various timing requirements. Verification of such digital circuits is typically accomplished statically and does not require analog of digital logic. At the stage of DFT 131, various hardware logic for improving chip testability (including controllability and observability) may be embedded in the design. By using this part of logic, test vectors can be generated for the purpose of testing large-scale digital circuits. The DFT may include, for example, a scan chain (SCAN CHAIN) based test method or a built-in self-test (BIST). At the stage of verification check 133, the circuit may be subjected to form verification and/or equivalence checking. Formal verification may use mathematical methods to prove its correctness or incorrectness based on some form specification or attribute. Formal verification may include, for example, abstract interpretation (abstract interpretation), formal model checking (formal model checking, also known as feature checking), and theorem proving (theory prover). The equivalence check may be used to verify that there is agreement between the register transfer level design and the gate level netlist, between the gate level netlist and the gate level netlist.

At the stage of laying out the wiring 135, a chip circuit may be laid out (placement) and wired (routing). The layout may arrange the gate-level netlist generated by the logic synthesis 127 reasonably in a rectangular region corresponding to the chip based on factors such as area, critical path delay length, power consumption, etc. After this, the laid-out individual components or sub-circuits may be routed to connect them. Routing is generally expected to be short overall routing, with routing delays meeting timing requirements, conforming to routing rules in the process (e.g., routing density). Although the layout and wiring are described separately herein, this is merely illustrative and not limiting of the scope of the present disclosure. In some cases, placement and routing may be performed simultaneously or alternately to achieve optimization of placement and routing.

At the stage of DRC 137, it may be checked whether the layout is potentially open, shorted, or otherwise ill-conditioned by violating design rules. After passing through the DRC, a file representing the layout, such as a GDSII file, may be generated 139 by EDA software. It should be understood that the above links are merely exemplary and are not intended to limit the scope of the present disclosure, and that the above links may be added, deleted or modified according to design needs during actual design. In addition, some of the above links may be implemented by different EDA software, or may be implemented integrated in one or more EDA software. The present disclosure is not limited in this regard.

The scheme of checking layout design of the present disclosure may be applied to the stage of DRC137, and patterns in the circuit layout that may violate design rules (e.g., distances less than a particular value) may be quickly prescreened according to the algorithms of the present disclosure. And then accurately calculating according to an algorithm for calculating the graph distance. It will be appreciated that the schemes of the present disclosure may also be applied to other scenarios where patterns are filtered based on distance, such as screening offending patterns in MRC, intersection of patterns in OPC, boolean operations, and so forth. The technical scheme of the present disclosure will be described in detail below.

It will be appreciated that although operations are described above in a particular order, this should be understood as not being limited to requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Fig. 2 illustrates a block diagram of an example environment 200, according to some embodiments of the disclosure. As shown in fig. 2, the example environment 200 may generally include an electronic device 230. In some embodiments, electronic device 230 may be a computing-enabled device such as a personal computer, workstation, server, or the like. The processes described in this disclosure may be implemented by EDA tool software in an electronic device having computing capabilities, such as a personal computer, workstation, server, or the like. The electronic device 230 may be installed with EDA software, which may be input with a configuration by a user (not shown) during EDA design of the chip, to automatically generate a logic circuit by the EDA software. EDA software includes, but is not limited to, chip design assistance software, programmable chip assistance design software, and system design assistance software. The scope of the present disclosure is not limited in this respect.

Electronic device 230 may obtain as inputs layout file 210 for implementing the circuit and netlist file 220 characterizing the circuit to determine a plurality of patterns in the circuit layout. In some embodiments, the layout file 210 may be provided to the electronic device 230, for example, in the form of a layout design interchange format (GRAPHIC DESIGN SYSTEM, GDS) file. The electronic device 230 may derive a circuit layout 410 as shown in fig. 4 from the GDS file, wherein the rectangular pattern shown by the four shadows in the circuit layout 410 may represent devices in the circuit. The rectangular shape is merely exemplary, and aspects of the present disclosure are applicable to other polygonal, circular, or other irregularly shaped patterns.

In some embodiments, computing device 230 may also insert the circuit layout into the grid to determine a pattern distribution of the pattern in the grid, and then determine a target pattern group of the plurality of patterns from the pattern distribution. In some embodiments, electronic device 230 may determine whether a pattern in the target pattern group is an offending pattern based on design constraints of the circuit layout. This will be described in further detail below in connection with fig. 3-6.

FIG. 3 illustrates a flow chart for inspecting a layout design, according to some embodiments of the present disclosure. In some embodiments, the method 300 may be performed by the electronic device 230 as shown in fig. 2. It should be understood that method 300 may also include additional blocks not shown and/or that the blocks shown may be omitted, the scope of the disclosure being not limited in this respect.

At block 302, the electronic device 230 determines a pattern distribution of a plurality of patterns in the grid array based on the plurality of patterns in the circuit layout 410. In this disclosure, pattern distribution may refer to a visual graphical representation of a pattern in a grid array. For example, the distribution of the 4 patterns 1-4 from left to right in the circuit layout 410 in the grid. For example, the electronic device 230 scans the pattern with the grid to determine a pattern distribution of the plurality of patterns in the grid array.

In some embodiments, computing device 230 may first scan a plurality of patterns column-by-column along a row direction of the grid array to assign a plurality of pattern flags corresponding to the plurality of patterns to a plurality of sub-banks in a grid bank corresponding to the grid array. A pattern distribution of the plurality of patterns in the grid array is then determined based on the pattern flags stored in the grid storage area. Computing device 230 may allocate a memory area for each of the grids in the grid array of fig. 4, and when a grid "overlaps" a pattern as the pattern in the circuit layout is scanned by column, computing device 230 may store a pattern flag for the pattern that overlaps the grid in the corresponding memory area. The computing device 230 may then visually present the pattern flags in a corresponding grid, as shown in fig. 4, where the corresponding pattern flags are present, which means that the corresponding patterns appear in the same grid array, i.e. the distances between the patterns may not meet the design constraints of the circuit layout.

In some embodiments, the size of each grid in the grid array may be determined based on the average size of the patterns in the circuit layout. For example, it may be provided that the pattern with the largest area covers no more than 3 grids in the row or column direction of the grids. It will be appreciated that the smaller the grid division, the finer the calculation result may be, but the greater the computational overhead required, and the larger the grid division, the coarser the calculation result may be, but the smaller the computational overhead required, the size of the grid needs to be determined according to the scene to which it is applied.

At block 304, the electronic device 230 determines at least one target pattern group of a plurality of patterns based on the pattern distribution in the grid array, the patterns in each of the at least one target pattern group being located in the same grid in the grid array. As described above, the computing device 230 has determined a pattern distribution in block 302, and then the computing device 230 may determine a set of target patterns that may be closer to (i.e., less than a threshold distance from) the pattern distribution, it being understood that patterns located in the same grid may be closer to each other in the pattern distribution. For example, as shown in fig. 4, the computing device 230 may determine (1, 2) as the target pattern group if the second column in the grid array has pattern flags 1 and 2 appearing in the same grid, and the computing device 230 may determine (2, 3, 4) as the target pattern group if the fourth column in the grid array has pattern flags 2,3, and 4 appearing in the same grid.

In some embodiments, after the computing device 230 determines the target pattern groups, distances between the plurality of patterns in the first target pattern group of the at least one target pattern group may be determined. If the determined distance is less than the threshold distance, then the plurality of patterns in the first target pattern group are determined to be offending patterns. Computing device 230 may determine a minimum distance between patterns based on design constraints of the circuit layout, such as layout rules and routing rules of the circuit layout, and take the minimum distance as a threshold distance. If the actual distance between the patterns is less than the threshold distance, the patterns are determined to be non-conforming to the design constraints of the circuit layout, also referred to as offending patterns.

For example, referring to FIG. 4, if the design constraints dictate that patterns cannot intersect, i.e., the minimum distance is 0, the computing device may calculate that the distance between pattern 1 and pattern 2 in the target pattern group (1, 2) is less than 0, i.e., it intersects, according to a specific distance algorithm, and may determine pattern 1 and pattern 2 as offending patterns. For another example, for the target pattern group (2, 3, 4), computing device 230 may determine that pattern 3 and pattern 4 are offending patterns if the distance between pattern 2 and pattern 3, pattern 2 and pattern 4 is greater than 0, and the distance between pattern 3 and pattern 4 is less than 0. Note that the minimum distance 0 described above is merely exemplary, and that other distances may exist. In addition, the solution of the present disclosure is to perform preliminary screening of illegal patterns, and the screened target pattern group may perform distance detection according to any suitable pattern distance algorithm, which is not limited herein.

It will be appreciated that the pattern may be magnified for distance detection at the time of scanning, in addition to setting different thresholds at the time of distance detection. Alternatively, in some embodiments, the computing device 230 may magnify at least one pattern of the plurality of patterns by a predetermined factor associated with a design constraint of the circuit layout prior to determining the pattern distribution. The computing device 230 then uses the expanded pattern to determine a pattern distribution of the plurality of patterns in the grid array.

The computing device 230 may expand the original pattern by a distance δ around according to the required inspection distance value δ, and add δ to the values of the right end points of all patterns in the lateral direction according to the required inspection distance value δ, so that the pattern with the lateral distance δ may be included in the contrast range during scanning. In the vertical direction, the contrast range can be expanded by delta when the pattern is read, namely, if the range of the pattern in the vertical direction is y ₀ to y ₁, the range after expansion is y ₀ -delta to y ₁ +delta. Patterns with vertical distance delta can be included in the contrast range after expansion. For example, as shown in fig. 6, patterns 2 and 4 may be expanded by a check distance value δ, if pattern 2 and pattern 4 are not expanded, they belong to different grids, no distance comparison is performed, and after expansion, pattern 4 covers a larger range 610, so that pattern mark 4 appears in more grids in the pattern distribution, where one grid is present and pattern 2 and pattern 4 are recorded at the same time, and pattern 2 and pattern 4 are compared.

In some embodiments, computing device 230 determines the plurality of pattern marks stored by the plurality of sub-storage areas as the same target pattern group in response to the plurality of sub-storage areas of the grid storage area corresponding to the same column storing the same plurality of pattern marks. For example, as shown in FIG. 4, for the second column grid in the grid array, where the same plurality of pattern flags (1, 2) are stored in two sub-storage areas, the computing device 230 may perform a deduplication operation, i.e., determine only one target pattern group (1, 2). Thus, pattern 1 and pattern 2 are compared only 1 time in the subsequent distance detection, which reduces the subsequent calculation overhead.

According to the embodiment of the disclosure, the built grid is utilized to scan the patterns in columns, so that the scanning speed is increased. Each grid storage area stores pattern flags according to a one-dimensional data structure, i.e. the pattern flags stored in each grid storage area, whereby the data storage amount is significantly reduced, which is particularly advantageous for hundreds of millions of patterns. In addition, one-dimensional data structures have faster speeds in data access, which reduces computational overhead.

As mentioned above, there may be a grid of a large order of magnitude in the grid array, so that there is a storage area of the same order of magnitude, and furthermore the number of pattern marks is also staggering, which still has a large impact on the performance of data storage and subsequent target pattern groups. In the following, the scheme of further reducing data storage and increasing scanning speed through the scanning queue will be further described.

Fig. 5 illustrates a schematic diagram for inspecting a circuit layout according to some embodiments of the present disclosure. As shown in fig. 5, there are a plurality of sub-banks in the column bank 420 corresponding to the columns 510, 520, 530, 540 in the grid array in addition to the grid bank. In some embodiments, computing device 230 scans each pattern column-wise along the row direction of the grid array to assign a plurality of pattern flags corresponding to the plurality of patterns to a plurality of sub-memory areas in a column memory area corresponding to columns in the grid array, based on the pattern flags stored in the column memory area, to determine a pattern distribution of the plurality of patterns in the grid array.

For example, as shown in fig. 5, the computing device 230 records the start and end points of projection of the pattern in the lateral direction (in the row direction of the grid array) into each of the column memory areas. The left edge (left end point) and the right edge (right end point) of the pattern are stored separately into each of the column storage areas. For example, the column corresponding to the first sub-memory area in the column memory area 420 covers the left edge of the pattern 1, and thus the pattern flag 1 is stored in this sub-memory area. The column corresponding to the second sub-memory area in the column memory area 420 covers the right edge of pattern 1 and the left edge of pattern 2, and thus the pattern marks (1, 2) are stored in this sub-memory area. The column corresponding to the third sub-memory area in column memory area 420 covers the left edge of pattern 3, so pattern flag 3 … is stored in this sub-memory area, and so on. The pattern scanning scheme discussed in fig. 3 may be further optimized based on the pattern flags stored in the column store.

In some embodiments, the computing device 230 deletes the first pattern flag from the grid storage area in response to the first pattern flag corresponding to the first pattern of the plurality of patterns being stored in a first sub-storage area in the grid storage area and not being stored in a second sub-area adjacent to the first sub-area that is scanned sequentially. For example, referring to fig. 5, the pattern is scanned column by a column grid 510 to 540, and the first column grid is scanned and then stored 111 in the grid storage area, at which time the pattern flag 1 is stored in the column storage area 420. After the first column grid scan, (1, 2) 1 is stored in the grid storage area, and at this time, the pattern flag (1, 2) is stored in the column storage area 420. 1 has been stored 2 times in column store 420, indicating that pattern 1 is about to leave the scan grid, pattern flag 1 may be deleted from the grid store to free up storage space. Therefore, the mark pattern marks in the grid storage area can be dynamically written in and deleted along with the scanning of the column-by-column grid, so that the storage space is saved, and the calculation cost is saved.

Alternatively, in some embodiments, the deleted first pattern flag is assigned to the subsequently scanned pattern. As discussed above, pattern 1 has left the scanning grid while pattern 3 has just entered the scanning grid when multiple patterns are scanned according to the third column grid 530, at which point pattern flag 1 of pattern 1 may be assigned to pattern 3. Thus, 2, (2, 1), 1 are stored in the grid storage area of the third column grid. Upon scanning multiple patterns with subsequent columns of grids, the computing device 120 may assign pattern flags that have occurred 2 times (i.e., pattern flags that are about to leave the scanning grid) to patterns that newly enter the scanning grid, based on the pattern identifications stored in the column store 420. Thus, hundreds of millions of patterns in a circuit layout can be represented using a small number of pattern flags. This can significantly reduce the amount of memory and enable more rapid determination of the target pattern group.

The inventors have surprisingly found that according to the grid scanning scheme of the present disclosure, the pattern identifications stored in the grid storage area are updated with further pattern identifications stored in the column storage area while scanning. The method can save the storage space, reduce the calculation cost and simultaneously rapidly screen out the patterns to be subjected to the subsequent distance detection. Experimental data are shown in table 1 below, and it can be seen that the greater the number of patterns processed, the less time consuming it is compared to the prior art scheme.

TABLE 1

Example implementations of methods according to the present disclosure have been described in detail above with reference to fig. 1 to 6, and implementations of corresponding apparatuses will be described below.

FIG. 7 illustrates a block diagram of an example apparatus for inspecting a layout design, according to some embodiments of the present disclosure. The apparatus 700 may be used, for example, to implement an electronic device such as that of fig. 2. The device 700 has EDA software installed thereon, or the device 700 may be referred to in essence as an EDA software device, with each module in the device 700 being capable of implementing different chip design and test functions with EDA software. As shown in fig. 7, the apparatus 700 includes: a pattern distribution determination module 702 configured to determine a pattern distribution of a plurality of patterns in the grid array based on the plurality of patterns in the circuit layout; and a pattern group determination module 704 configured to determine at least one target pattern group of the plurality of patterns based on the pattern distribution in the grid array, the patterns in each of the at least one target pattern group being located in the same grid in the grid array.

In some embodiments, the pattern distribution determination module 702 may include: a first grid scanning module configured to scan a plurality of patterns column by column in a row direction of the grid array to allocate a plurality of pattern marks corresponding to the plurality of patterns to a plurality of sub-storage areas in a grid storage area corresponding to the grid array; and a first distribution determination module configured to determine a pattern distribution of the plurality of patterns in the grid array based on the pattern flags stored in the grid storage area.

In some embodiments, the pattern distribution determination module 702 may include: a second grid scanning module configured to scan the plurality of patterns column by column in a row direction of the grid array to allocate a plurality of pattern marks corresponding to the plurality of patterns to a plurality of sub-storage areas in a column storage area corresponding to columns in the grid array; and a second distribution determining module configured to determine a pattern distribution of the plurality of patterns in the grid array based on the pattern flags stored in the column storage area.

In some embodiments, the pattern distribution determination module 702 may further include: a first pattern-flag updating module configured to delete a first pattern flag from the grid storage area in response to the first pattern flag corresponding to a first pattern of the plurality of patterns being stored in a first sub-storage area in the grid storage area and not being stored in a second sub-area adjacent to the first sub-area that is scanned successively.

In some embodiments, the apparatus 700 may further comprise: a second pattern-flag updating module configured to assign the deleted first pattern flag to the subsequently scanned pattern.

In some embodiments, pattern group determination module 704 may include: and the pattern group deduplication module is configured to determine a plurality of pattern marks stored in the plurality of sub-storage areas as the same target pattern group in response to the plurality of sub-storage areas corresponding to the same column in the grid storage area storing the same plurality of pattern marks.

In some embodiments, the apparatus 700 may further comprise: a pattern method module configured to magnify at least one pattern of the plurality of patterns by a predetermined factor, the predetermined factor associated with a design constraint of the circuit layout, prior to determining the pattern distribution; the pattern distribution determination module includes: a third distribution determination module configured to determine a pattern distribution of the plurality of patterns in the grid array using the expanded pattern.

In some embodiments, the apparatus 700 may further comprise: a distance determination module configured to determine distances between a plurality of patterns in a first target pattern group of the at least one target pattern group; and a violation pattern determination module configured to determine a plurality of patterns in the first target pattern group as violation patterns in response to the distance being less than a threshold distance.

Fig. 8 illustrates a schematic block diagram of an example device that may be used to implement some embodiments of the present disclosure. Device 800 may be used to implement an electronic device. The device 800 may include a simulation system with EDA software installed thereon, with which the device 800 may implement the processes described in this disclosure.

Fig. 8 illustrates a schematic block diagram of an example device 800 that may be used to implement some embodiments of the present disclosure. Device 800 may be used to implement an electronic device. As shown in fig. 8, the apparatus 800 includes a Central Processing Unit (CPU) 801 that can perform various appropriate actions and processes according to computer program instructions stored in a Read Only Memory (ROM) 802 or computer program instructions loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The CPU 801, ROM 802, and RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The processing unit 801 performs the various methods and processes described above, such as method 300. For example, in some embodiments, the method 300 may be implemented as a computer software program, in particular an EDA program, tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 800 via ROM 802 and/or communication unit 809. When a computer program is loaded into RAM 803 and executed by CPU 801, one or more steps of method 400 described above may be performed. Alternatively, in other embodiments, CPU 801 may be configured to perform method 400 by any other suitable means (e.g., by means of firmware).

The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), etc.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Claims

1. A method for inspecting a layout design, the method comprising:

Determining pattern distribution of a plurality of patterns in a grid array based on the plurality of patterns in the circuit layout; and

At least one target pattern group of the plurality of patterns is determined based on a pattern distribution in the grid array, the patterns in each of the at least one target pattern group being located in the same grid in the grid array.

2. The method of claim 1, wherein determining a pattern distribution of a plurality of patterns in a grid array based on the plurality of patterns in the circuit layout comprises:

Scanning the plurality of patterns column by column along a row direction of the grid array to allocate a plurality of pattern marks corresponding to the plurality of patterns to a plurality of sub-storage areas in a grid storage area corresponding to the grid array; and

A pattern distribution of the plurality of patterns in the grid array is determined based on the pattern flags stored in the grid storage area.

3. The method of claim 1 or 2, wherein determining a pattern distribution of a plurality of patterns in a grid array based on the plurality of patterns in the circuit layout comprises:

Scanning the plurality of patterns column by column along a row direction of the grid array to allocate a plurality of pattern flags corresponding to the plurality of patterns to a plurality of sub-banks in a column bank corresponding to columns in the grid array; and

A pattern distribution of the plurality of patterns in the grid array is determined based on the pattern flags stored in the column store.

4. The method as recited in claim 2, further comprising:

The first pattern flag is deleted from the grid storage area in response to the first pattern flag corresponding to a first pattern of the plurality of patterns being stored in a first sub-storage area in the grid storage area and not being stored in a second sub-area adjacent to the first sub-area that is scanned successively.

5. The method as recited in claim 4, further comprising:

The deleted first pattern flag is assigned to the pattern of the subsequent scan.

6. The method of claim 2, wherein determining at least one target pattern group of the plurality of patterns based on a pattern distribution in the grid array comprises:

And determining a plurality of pattern marks stored in a plurality of sub-storage areas corresponding to the same column as the same target pattern group in response to the plurality of sub-storage areas corresponding to the same column in the grid storage area storing the same plurality of pattern marks.

7. The method according to any one of claims 1-6, further comprising:

Amplifying at least one pattern of the plurality of patterns by a predetermined multiple prior to determining the pattern distribution, the predetermined multiple being associated with a design constraint of the circuit layout;

determining a pattern distribution of the plurality of patterns in the grid array includes: the expanded pattern is used to determine a pattern distribution of the plurality of patterns in the grid array.

8. The method as recited in claim 1, further comprising:

Determining distances between a plurality of patterns in a first target pattern group of the at least one target pattern group; and

In response to the distance being less than a threshold distance, a plurality of patterns in the first set of target patterns are determined to be offending patterns.

9. An apparatus for inspecting a layout design, the apparatus comprising:

A pattern distribution determination module configured to determine a pattern distribution of a plurality of patterns in a grid array based on the plurality of patterns in the circuit layout; and

A pattern group determination module configured to determine at least one target pattern group of the plurality of patterns based on a pattern distribution in the grid array, the patterns in each of the at least one target pattern group being located in a same grid in the grid array.

10. The apparatus of claim 9, wherein the pattern distribution determination module comprises:

A first grid scanning module configured to scan the plurality of patterns column by column in a row direction of the grid array to allocate a plurality of pattern marks corresponding to the plurality of patterns to a plurality of sub-storage areas in a grid storage area corresponding to the grid array; and

A first distribution determination module configured to determine a pattern distribution of the plurality of patterns in the grid array based on the pattern flags stored in the grid storage area.

11. The apparatus according to claim 9 or 10, wherein the pattern distribution determination module comprises:

A second grid scanning module configured to scan the plurality of patterns column by column in a row direction of the grid array to allocate a plurality of pattern flags corresponding to the plurality of patterns to a plurality of sub-memory areas in a column memory area corresponding to columns in the grid array; and

A second distribution determination module configured to determine a pattern distribution of the plurality of patterns in the grid array based on the pattern flags stored in the column store.

12. The apparatus of claim 11, wherein the pattern distribution determination module further comprises:

A first pattern-flag updating module configured to delete a first pattern flag corresponding to a first pattern of the plurality of patterns from the grid storage area in response to the first pattern flag being stored in a first sub-storage area in the grid storage area and not being stored in a second sub-area adjacent to the first sub-area that is scanned successively.

13. The apparatus of claim 12, wherein the apparatus further comprises:

a second pattern-flag updating module configured to assign the deleted first pattern flag to the subsequently scanned pattern.

14. The apparatus of claim 9, wherein the pattern group determination module comprises:

And the pattern group deduplication module is configured to determine a plurality of pattern marks stored in a plurality of sub-storage areas corresponding to the same column as the same target pattern group in response to the plurality of sub-storage areas corresponding to the same column in the grid storage area storing the same plurality of pattern marks.

15. The apparatus according to any one of claims 9-14, wherein the apparatus further comprises:

A pattern method module configured to magnify at least one pattern of the plurality of patterns by a predetermined multiple, the predetermined multiple associated with a design constraint of the circuit layout, prior to determining the pattern distribution;

The pattern distribution determination module includes: a third distribution determination module configured to determine a pattern distribution of the plurality of patterns in the grid array using the expanded pattern.

16. The apparatus of claim 9, wherein the apparatus further comprises:

A distance determination module configured to determine distances between a plurality of patterns in a first target pattern group of the at least one target pattern group; and

The violation pattern determination module is configured to determine a plurality of patterns in the first target pattern group as violation patterns in response to the distance being less than a threshold distance.

17. An electronic device, the electronic device comprising:

At least one processor; and

At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions when executed by the at least one processor cause the electronic device to perform the method of any one of claims 1-8.

18. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 8.

19. A computer program product comprising computer executable instructions which, when executed by a processor, cause a computer to implement the method according to any one of claims 1 to 8.